WO2023077517A1 - 显示装置 - Google Patents

显示装置 Download PDF

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Publication number
WO2023077517A1
WO2023077517A1 PCT/CN2021/129347 CN2021129347W WO2023077517A1 WO 2023077517 A1 WO2023077517 A1 WO 2023077517A1 CN 2021129347 W CN2021129347 W CN 2021129347W WO 2023077517 A1 WO2023077517 A1 WO 2023077517A1
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
disposed
display device
groove
Prior art date
Application number
PCT/CN2021/129347
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English (en)
French (fr)
Inventor
丁玎
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/614,507 priority Critical patent/US20230146219A1/en
Publication of WO2023077517A1 publication Critical patent/WO2023077517A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present application relates to the field of display technology, in particular to a display device.
  • the organic light-emitting display device utilizes the self-luminescence of organic light-emitting diodes to realize display, and has the advantages of low power consumption, fast response, and large viewing angle.
  • low temperature polysilicon (LTPS) thin film transistors and metal oxide (metal oxide) thin film transistors are integrated on the same backplane. Therefore, the advantages of high mobility of low-temperature polysilicon thin film transistors, fast charging speed of pixel capacitors, and low leakage of thin film transistors with metal oxides can be combined at the same time.
  • the metal oxides of thin film transistors are very sensitive to hydrogen. When hydrogen invades metal oxides, device characteristics will deteriorate, thereby affecting product quality.
  • the upper and lower layers adjacent to the metal oxide are usually set as silicon oxide layers.
  • silicon oxide has poor barrier ability to water and oxygen in the atmospheric environment, and water and oxygen will also affect the properties of metal oxides.
  • TFE thin film encapsulation
  • AMOLED active matrix organic light emitting diode
  • TFE thin film encapsulation
  • the TFE layer is generally not covered with the 2nd Cutting Line (2nd Cutting Line), but is designed to be a certain distance away from the 2nd Cutting Line to reduce cutting cracks. and extended risks.
  • such a design may make it easy for water vapor, oxygen, etc. to invade the metal oxide, that is, water vapor, oxygen, etc. invade the metal oxide along the inorganic insulating layer made of silicon oxide, resulting in deterioration of the characteristics of the thin film transistor device, which in turn leads to product failure. abnormal.
  • the present application uses the source and drain layers extending toward the substrate to reduce the influence of ambient water and oxygen on the metal oxide devices of thin film transistors, and prevent the diffusion of water vapor and oxygen in the environment into the display device, thus Improve display device stability.
  • the present application provides a display device.
  • a display area and a non-display area are defined on the display device.
  • the display device includes: a substrate; an inorganic insulating layer arranged on one side of the substrate, and a first groove is arranged in a corresponding non-display area, the opening of the first groove is far away from the substrate, and a metal retaining wall is arranged in the first groove; a light emitting layer , arranged on the side of the inorganic insulating layer away from the substrate; the encapsulation layer, arranged on the side of the light emitting layer away from the substrate, and extending from the display area to the non-display area.
  • the encapsulation layer is overlapped with the first groove in the non-display area, and there is a first gap between the edge of the encapsulation layer and the edge of the inorganic insulating layer.
  • the display device further includes: a first metal layer disposed on a side of the inorganic insulating layer away from the substrate, the first metal layer includes a plurality of peripheral traces disposed in the non-display area, the second A metal retaining wall is arranged in the groove to be electrically connected with at least one peripheral wiring.
  • the metal retaining wall in the first groove is electrically connected to the peripheral trace farthest from the display area.
  • the display device further includes: a driving circuit layer including a plurality of transistors arranged in the inorganic insulating layer; the first metal layer also includes source and drain wires arranged in the display area, the source The electrode-drain traces are electrically connected to the corresponding transistors.
  • the driving circuit layer includes: a first semiconductor layer; a first gate layer disposed on the side of the semiconductor layer away from the substrate; a second gate layer disposed on the side of the first gate layer away from the substrate
  • the second semiconductor layer is arranged on the side of the second gate layer away from the substrate
  • the third gate layer is arranged on the side of the second semiconductor layer away from the substrate
  • the source drain layer is arranged on the second
  • the gate layer is on a side away from the substrate, and is electrically connected to the first semiconductor layer and the second semiconductor layer respectively.
  • the inorganic insulating layer includes: a buffer layer disposed on one side of the substrate, wherein the first semiconductor layer is disposed on the side of the buffer layer away from the substrate; a first gate insulating layer disposed between the semiconductor layer and the first gate layer ; The second gate insulating layer is arranged between the first gate layer and the second gate layer; the third gate insulating layer is arranged between the second gate layer and the second semiconductor layer; the fourth gate The insulating layer is arranged between the second semiconductor layer and the third gate layer; the interlayer insulating layer is arranged between the third gate layer and the source drain layer; wherein, the first groove is separated from the interlayer insulating layer extending to the second gate insulating layer.
  • the third gate insulating layer further includes a first interlayer insulating film layer and a second interlayer insulating film layer, the first interlayer insulating film layer is disposed on the second gate insulating layer, The second interlayer insulating film layer is disposed between the first interlayer insulating film layer and the fourth gate insulating layer.
  • the display device further includes: a flat layer disposed on the side of the first metal layer away from the substrate, the flat layer is disposed on the display area and extends to the non-display area, the edge of the flat layer is connected to the inorganic insulating layer There is a second gap between the edges, the second gap being larger than the first gap.
  • the display device further includes a second metal layer arranged on the side of the flat layer away from the substrate, the second metal layer includes a jumper wire arranged in the anode of the display area and the non-display area, the jumper wire Electrically connected to the metal retaining wall.
  • the display device further includes a cathode disposed on a side of the light-emitting layer away from the substrate, wherein the cathode is electrically connected to the jumper in the non-display area.
  • the planar layer includes a first planar layer and a second planar layer, the first planar layer is disposed on the inorganic insulating layer, and the second planar layer is disposed on the first planar layer.
  • the second groove is defined in the non-display area and located in the first planar layer, and part of the second metal layer fills the second groove and connects with the first metal layer.
  • a plurality of third grooves are defined in the second flat layer, an anode is disposed on the flat layer, fills the third grooves, and is connected to the second metal layer.
  • the fourth groove extends from the interlayer insulating layer to the second semiconductor layer, and the first metal layer fills the fourth groove and is connected to the second semiconductor layer.
  • the display device further includes a pixel definition layer disposed on the anode.
  • the sixth groove is defined on the pixel definition layer, the light emitting layer is filled in the sixth groove, and the cathode covers the light emitting layer.
  • the substrate includes a first substrate layer, a first barrier layer, a second substrate layer and a second barrier layer, the first barrier layer is disposed on the first substrate layer, and the second substrate layer is disposed on the second substrate layer. On the first barrier layer, the second barrier layer is disposed on the second substrate layer.
  • the seventh groove extends from the interlayer insulating layer to the second substrate layer, and part of the first planar layer is filled in the seventh groove.
  • the first metal layer includes a first source-drain layer and a second source-drain layer
  • the second source-drain layer is disposed on the first source-drain layer and connected to the first source-drain layer polarity electrical connection.
  • the first source-drain layer and the second source-drain layer include a plurality of source-drain film layers.
  • the first groove is arranged around the display area.
  • the source and drain layers extending toward the substrate can reduce the influence of ambient water and oxygen on the metal oxide devices of thin film transistors, thus preventing the diffusion of water vapor and oxygen in the environment into the display device, thus improving the display performance.
  • the beneficial effect of the stability of the device can reduce the influence of ambient water and oxygen on the metal oxide devices of thin film transistors, thus preventing the diffusion of water vapor and oxygen in the environment into the display device, thus improving the display performance.
  • FIG. 1 is a top view of a display device of the present application.
  • FIG. 2 is a first schematic diagram of the display device of the present application.
  • FIG. 3 is a second schematic diagram of the display device of the present application.
  • FIG. 4 is a third schematic diagram of the display device of the present application.
  • FIG. 5 is a fourth schematic diagram of the display device of the present application.
  • FIG. 6 is a fifth schematic diagram of the display device of the present application.
  • FIG. 7 is a sixth schematic diagram of the display device of the present application.
  • FIG. 8 is a seventh schematic diagram of the display device of the present application.
  • FIG. 9 is a seventh schematic diagram of the display device of the present application.
  • FIG. 10 is a schematic diagram of the first metal layer of the present application.
  • FIG. 11 is a schematic diagram of the second metal layer of the present application.
  • FIG. 12 is a circuit diagram of the display device of the present application.
  • the present application provides a display device 10 .
  • the display device 10 has a display area AA and a non-display area.
  • the display area AA is the area where the cathode 500 is disposed; the non-display area includes the first wiring area VSS, the second wiring area GOA and the third wiring area VI.
  • the display area AA is an area where the cathode 500 is disposed.
  • the cathode signal is provided by the first wiring area VSS, the second wiring area GOA is the area where the driving circuit is set, and the third wiring area VI is the area where the reset wiring is set.
  • the display device 10 includes a substrate, an inorganic insulating layer, a pixel definition layer 300 , a light emitting layer 400 and an encapsulation layer.
  • the display device 10 can be a mobile phone screen, a computer screen, etc. with a display function.
  • the outermost edge of the device 10 shown in FIG. 1 may be a secondary cutting line. 2 to 9 are cross-sectional views along the dashed line AA' of FIG. 1 .
  • the substrate may include a first substrate layer 101 , a first barrier layer 102 , a second substrate layer 103 and a second barrier layer 104 .
  • the first barrier layer 102 is disposed on the first substrate layer 101
  • the second substrate layer 103 is disposed on the first barrier layer 102
  • the second barrier layer 104 is disposed on the second substrate layer 103 .
  • the first substrate layer 101 and the second substrate layer 103 may be flexible substrates.
  • the first substrate layer 101 and the second substrate layer 103 can be made of polyimide.
  • the inorganic insulating layer may be provided on one side of the substrate.
  • a first groove 201 is provided corresponding to the non-display area, the opening of the first groove 201 is away from the substrate, and the first groove 201 is filled with a metal barrier to block moisture, oxygen and the like.
  • the first groove 201 may be disposed around the display area AA.
  • the first groove 201 can be arranged in the second wiring area GOA, and surround the display area AA along the second wiring area GOA, so that moisture can be prevented from entering the display from the direction of the substrate. device 10.
  • the light emitting layer 400 may be disposed on a side of the inorganic insulating layer away from the substrate.
  • the light emitting layer 400 may include a plurality of organic light emitting transistors.
  • the encapsulation layer may be disposed on a side of the light emitting layer 400 away from the substrate, and extend from the display area AA to the non-display area.
  • the display device 10 of the present application is encapsulated by thin film encapsulation technology, and the encapsulation layer includes a first encapsulation layer 601 and a second encapsulation layer 602 .
  • the encapsulation layer is overlapped with the first groove 201 in the non-display area, and there is a first gap between the edge of the encapsulation layer and the edge of the inorganic insulating layer.
  • the first gap corresponds to the position of the 2nd Cutting Line, so setting a metal retaining wall in the first groove 201 corresponding to the first gap can prevent water vapor, oxygen, etc. from easily intruding into the metal oxide, that is, water vapor, oxygen Invasion of the metal oxide along the inorganic insulating layer made of silicon oxide will cause the deterioration of the characteristics of the thin film transistor device, which will lead to product abnormalities.
  • the display device 10 further includes a first metal layer.
  • the first metal layer is disposed on a side of the inorganic insulating layer away from the substrate.
  • the first metal layer includes a plurality of peripheral traces, such as source and drain traces, arranged in the non-display area.
  • the metal retaining wall in the first groove 201 is electrically connected with at least one peripheral wiring.
  • the metal retaining wall filled in the first groove 201 is electrically connected to the peripheral trace farthest from the display area AA. As shown in FIG. 2 to FIG. 9 , the metal barrier filled in the first groove 201 can be electrically connected to the peripheral traces of the first metal layer.
  • the display device 10 further includes a driving circuit layer.
  • the driving circuit layer includes a plurality of transistors arranged in the inorganic insulating layer, and the transistors may be thin film transistors.
  • the first metal layer further includes source and drain lines arranged in the display area, and the source and drain lines are electrically connected to corresponding transistors.
  • the source and drain traces can be made by filling the metal barriers in the first groove 201 .
  • the driving circuit layer includes a first semiconductor layer 107; a first gate layer 109 disposed on the side of the first semiconductor layer 107 away from the substrate; a second gate layer 111 disposed on the side of the first gate layer 109 away from the substrate
  • the second semiconductor layer 114 is arranged on the side of the second gate layer 111 away from the substrate; the third gate layer 116 is arranged on the side of the second semiconductor layer 114 away from the substrate; the source and drain layers are arranged On the side of the second gate layer 111 away from the substrate, it is electrically connected to the first semiconductor layer 107 and the second semiconductor layer 114 respectively.
  • the first semiconductor layer 107 includes amorphous silicon.
  • the polysilicon can be laser annealed (excimer Laser annealing) is formed in the first semiconductor layer 107 to provide a semiconductor channel with high mobility for electrons and holes.
  • the thin film transistor having the first semiconductor layer 107 may be a low temperature polysilicon thin film transistor (low temperature poly-silicon thin film transistor, LTPS TFT).
  • the second semiconductor layer 114 may include InGaZnO.
  • the thin film transistor with the second semiconductor layer 114 can be an indium gallium zinc oxide thin film transistor (indium gallium zinc oxide thin film transistor, IGZO TFT). Leakage current can be reduced by using IGZO TFT thin film transistors.
  • the first metal layer may include a first source-drain layer 119 and a second source-drain layer 120 .
  • the second source-drain layer 120 is disposed on the first source-drain layer 119 and is electrically connected to the first source-drain layer 119 .
  • the source and drain layers are a multilayer structure formed of metals with high corrosion resistance and high acid resistance.
  • the first source-drain layer 119 may include a first source-drain film layer 1191 , a second source-drain film layer 1192 and a third source-drain film layer 1193 .
  • the first source-drain film layer 1191 and the third source-drain film layer 1193 can be made of titanium, and the second source-drain film layer 1192 can be made of aluminum, but not limited thereto.
  • the first source-drain layer 119 can also be a single-layer structure, or the first source-drain film layer 1191, the second source-drain film layer 1192 and the third source-drain film layer 1193 can be made of other materials according to requirements. .
  • the second source-drain layer 120 may include a multilayer structure formed of a metal having high corrosion resistance and high acid resistance.
  • the second source-drain layer 120 may include a fourth source-drain film layer 1201 , a fifth source-drain film layer 1202 and a sixth source-drain film layer 1203 .
  • the fourth source-drain film layer 1201 and the sixth source-drain film layer 1203 can be made of titanium, and the fifth source-drain film layer 1202 can be made of aluminum, but not limited thereto.
  • the second source-drain layer 120 can also be a single-layer structure, or the fourth source-drain film layer 1201, the fifth source-drain film layer 1202 and the sixth source-drain film layer 1203 can be made of other materials according to requirements. .
  • the above-mentioned inorganic insulating layer includes: a buffer layer disposed on one side of the substrate, wherein the first semiconductor layer 107 is disposed on the side of the buffer layer away from the substrate; a first gate insulating layer 108 disposed on the first semiconductor layer 107 and the first gate layer 109; the second gate insulating layer 110 is arranged between the first gate layer 109 and the second gate layer 111; the third gate insulating layer is arranged on the second gate layer 111 and the second semiconductor layer 114; the fourth gate insulating layer 115 is arranged between the second semiconductor layer 114 and the third gate layer 116; the interlayer insulating layer 121 is arranged between the third gate layer 116 and between the source and drain layers; wherein, the first groove 201 extends from the interlayer insulating layer 121 to the second gate insulating layer 110 .
  • the buffer layer is disposed on the substrate.
  • the buffer layer includes a first buffer film layer 105 and a second buffer film layer 106 .
  • the first buffer film layer 105 is disposed on the substrate, and the second buffer film layer 106 is disposed on the first buffer film layer 105 .
  • the first buffer film layer 105 includes silicon nitride, and the second buffer film layer 106 includes silicon oxide.
  • the first semiconductor layer 107 is disposed on the buffer layer.
  • the first gate insulating layer 108 is disposed on the buffer layer and covers the first semiconductor layer 107 .
  • the first gate layer 109 is disposed on the first gate insulating layer 108 .
  • the second gate insulating layer 110 is disposed on the first gate insulating layer 108 .
  • the display device 10 further includes a planar layer, and the planar layer is disposed on a side of the first metal layer away from the substrate.
  • the flat layer may include a first flat layer 117 and a second flat layer 118 .
  • the first planar layer 117 is disposed on the interlayer insulating layer 121
  • the second planar layer 118 is disposed on the first planar layer 117 .
  • the flat layer is arranged in the display area and extends to the non-display area, and there is a second gap between the edge of the flat layer and the edge of the inorganic insulating layer, and the second gap is larger than the first gap.
  • the first metal layer can be disposed on the interlayer insulating layer 121 and covered by the first planar layer 117 ; the second metal layer can be disposed on the first planar layer 117 and covered by the second planar layer 118 ;
  • the second groove 202 can be defined in the non-display area and located in the first flat layer 117; and part of the second metal layer can fill the second groove 202 and connect with the first metal layer.
  • the second metal layer is disposed on the side of the flat layer away from the substrate, the second metal layer includes the jumper wire 210 arranged in the anode 200 of the display area AA and the non-display area, and the jumper wire 210 is connected to the metal barrier electrical connection.
  • the anode 200 is disposed on the side of the flat layer away from the substrate.
  • the jumper wire 210 in the non-display area is electrically connected to the metal retaining wall.
  • the display device 10 further includes a pixel definition layer 300 , a cathode 500 and a color filter layer 700 .
  • the cathode 500 is disposed on the side of the light emitting layer 400 away from the substrate. Specifically, the cathode 500 is laid on the entire surface of the light emitting layer 400 away from the substrate, and is electrically connected to the jumper 210 in the non-display area.
  • the jumper 210 is a jumper 210 made of the same layer of metal as the anode 200 .
  • the pixel definition layer 300 is disposed on the anode 200 .
  • the light emitting layer 400 is disposed on the pixel definition layer 300 .
  • the cathode 500 is disposed on the pixel definition layer 300 and covers the light emitting layer 400 .
  • the packaging layer is disposed on the cathode 500 and covers the anode 200 , the pixel definition layer 300 , the light emitting layer 400 and the cathode 500 .
  • the color filter layer 700 can be disposed between the first encapsulation layer 601 and the second encapsulation layer 602 by inkjet printing.
  • the third gate insulating layer further includes a first interlayer insulating film layer 112 and a second interlayer insulating film layer 113, and the first interlayer insulating film layer 112 is set On the second gate insulating layer 110 , the second interlayer insulating film layer 113 is disposed between the first interlayer insulating film layer 112 and the fourth gate insulating film layer 115 .
  • the first interlayer insulating film layer 112 includes silicon nitride.
  • the second interlayer insulating film layer 113 includes silicon oxide.
  • the first groove 201 extends from the interlayer insulating layer 121 to the upper surface of the second interlayer insulating film layer 113, so as to prevent the diffusion of moisture, hydrogen, oxygen, etc. from the direction of the substrate. to the second semiconductor layer 114 .
  • the first groove 201 extends from the interlayer insulating layer 121 to between the upper surface and the lower surface of the second interlayer insulating film layer 113 to block moisture, hydrogen, and oxygen. etc. diffuse to the second semiconductor layer 114 from the substrate direction.
  • the first groove 201 extends from the interlayer insulating layer 121 to the lower surface of the second interlayer insulating film layer 113 to increase barriers to the diffusion of moisture, hydrogen, oxygen, etc. from the direction of the substrate. to the effect of the second semiconductor layer 114 .
  • the first groove 201 extends from the first functional layer to have the best effect of blocking moisture, hydrogen, oxygen, etc. from diffusing from the substrate direction to the second semiconductor layer 114 .
  • the third gate insulating layer only includes the first interlayer insulating film layer 112 .
  • the first interlayer insulating film layer 112 only includes silicon oxide. Since the barrier ability of silicon oxide to moisture, hydrogen, oxygen, etc. is not as good as that of silicon nitride, in other words, the barrier ability of this structure to moisture, hydrogen, oxygen, etc. 112 and the embodiment of the second interlayer insulating film layer 113. Therefore, as shown in FIGS. 6 to 9 , the first groove 201 is at least from the interlayer insulating layer 121 to the second gate insulating layer 110 .
  • the first groove 201 extends from the interlayer insulating layer 121 to the upper surface of the second gate insulating layer 110 to block moisture, hydrogen, oxygen, etc. from the substrate. Diffusion to the second semiconductor layer 114 in the direction.
  • the first groove 201 extends from the interlayer insulating layer 121 to between the upper surface and the lower surface of the second gate insulating layer 110 to block moisture, hydrogen, oxygen, etc. Diffuse from the substrate direction to the second semiconductor layer 114 .
  • the first groove 201 extends from the interlayer insulating layer 121 to between the lower surface of the second gate insulating layer 110 to prevent the diffusion of moisture, hydrogen, oxygen, etc. from the direction of the substrate. to the second semiconductor layer 114 .
  • the first groove 201 extends from the interlayer insulating layer 121 to the first gate insulating layer 108 , which can better block moisture than the structure shown in FIGS. 6 to 8 . , hydrogen, oxygen, etc. diffuse from the direction of the substrate to the effect of the second semiconductor layer 114 .
  • first groove 201 and second groove 202 In addition to the above-mentioned first groove 201 and second groove 202, as shown in FIG. 2 to FIG.
  • the sixth groove 206 and the seventh groove 207 In addition to the above-mentioned first groove 201 and second groove 202, as shown in FIG. 2 to FIG.
  • the sixth groove 206 and the seventh groove 207 In addition to the above-mentioned first groove 201 and second groove 202, as shown in FIG. 2 to FIG.
  • the sixth groove 206 and the seventh groove 207 In addition to the above-mentioned first groove 201 and second groove 202, as shown in FIG. 2 to FIG.
  • the sixth groove 206 and the seventh groove 207 In addition to the above-mentioned first groove 201 and second groove 202, as shown in FIG. 2 to FIG.
  • the sixth groove 206 and the seventh groove 207 In addition to the above-mentioned first groove 201 and second groove 202, as shown in FIG. 2 to FIG.
  • a plurality of third grooves 203 are defined in the second planar layer 118 , the anode 200 is disposed on the planar layer, fills the third grooves 203 , and is connected to the second metal layer.
  • the fourth groove 204 extends from the interlayer insulating layer 121 to the second semiconductor layer 114 , and the first metal layer fills the fourth groove 204 and is connected to the second semiconductor layer 114 .
  • the fifth groove 205 extends from the interlayer insulating layer 121 to the first semiconductor layer 107 , and the first metal layer fills the fifth groove 205 and is connected to the first semiconductor layer 107 .
  • the sixth groove 206 is defined on the pixel definition layer 300 .
  • the light emitting layer 400 is filled in the sixth groove 206 , and the cathode 500 covers the light emitting layer 400 .
  • the seventh groove 207 extends from the interlayer insulating layer 121 to the second substrate layer 103, and part of the first planar layer 117 is filled in the seventh groove 207 to prevent moisture, oxygen, etc. from intruding into the display structure 100. .
  • the display device 10 of the present application includes a circuit composed of 7 thin film transistors and 1 capacitor (7T1C).
  • the thin film transistor having the second semiconductor layer 114 can be the thin film transistor T3 or the thin film transistor T4 in FIG. thin film transistor.
  • the present application uses the source and drain layers extending toward the substrate to reduce the influence of ambient water and oxygen on the metal oxide devices of thin film transistors, and prevent the diffusion of water vapor and oxygen in the environment into the display device, especially Yes, it can prevent the active layer from being affected by water vapor, oxygen, etc., thus improving the stability of the display device.

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Abstract

一种显示装置（10），包括显示区（AA）和非显示区。显示装置（10）包括：基板；无机绝缘层，设置在基板的一侧，并在对应非显示区设置第一凹槽（201），第一凹槽（201）的开口远离基板，第一凹槽中设置金属挡墙；发光层（400），设置在无机绝缘层远离基板的一侧；封装层，设置在发光层（400）远离基板的一侧，并从显示区（AA）延伸至非显示区。其中，封装层在非显示区与第一凹槽（201）重叠设置，且封装层的边缘与无机绝缘层边缘之间存在第一间隙。

Description

显示装置 技术领域
本申请涉及显示技术领域，特别是一种显示装置。
 背景技术
有机发光显示装置利用有机发光二极管的自发光实现显示，具有功耗低、响应快、视角大等优点。为了提升产品画质、降低产品功耗，低温多晶硅（LTPS）薄膜晶体管和金属氧化物（metal oxide）薄膜晶体管集成在同一背板上。因而低温多晶硅薄膜晶体管的高迁移率、对像素电容的充电速度快的优点以及具有金属氧化物的薄膜晶体管漏电低的优势可同时兼备。然而，薄膜晶体管的金属氧化物对氢非常敏感。当氢侵入到金属氧化物后，器件特性将会恶化，从而影响产品品质。所以在制造时需尽量降低金属氧化物上下膜层中的氢含量，避免高氢含量的膜层直接接触金属氧化物器件的沟道区。故通常在紧邻金属氧化物上下层设置为氧化硅层。但是氧化硅对大气环境中水氧的阻隔能力较差，而水氧同样会影响金属氧化物的特性。
在目前有源矩阵有机发光晶体管(active matrix organic light emitting diode,AMOLED)背板设计中，通常采用薄膜封装（thin film encapsulation,TFE）技术。但切割无机绝缘层时，会产生裂纹并向有源区延伸导致产品不良，故一般不会将TFE层覆盖二切线（2nd Cutting Line），而是设计将其距二切线一定距离，降低切割裂纹及延伸风险。但是这样的设计可能会使得水汽、氧气等容易入侵到金属氧化物，即水汽、氧气等沿着氧化硅制成的无机绝缘层入侵到金属氧化物，造成薄膜晶体管器件特性发生恶化，进而导致产品异常。
 技术问题
在目前有源矩阵有机发光晶体管背板设计中，存在水汽、氧气等容易入侵金属氧化物的技术问题。
 技术解决方案
为解决上述技术问题，本申请利用向基板延伸的源极漏极层，以降低环境水氧对薄膜晶体管的金属氧化物器件的影响，防止环境中的水汽、氧气等向显示装置内扩散，因而提高显示装置的稳定性。
基于上述目的，本申请提供一种显示装置。显示装置上定义有显示区和非显示区。显示装置包括：基板；无机绝缘层，设置在基板的一侧，并在对应非显示区设置第一凹槽，第一凹槽的开口远离基板，第一凹槽中设置金属挡墙；发光层，设置在无机绝缘层远离基板的一侧；封装层，设置在发光层远离基板的一侧，并从显示区延伸至非显示区。其中，封装层在非显示区与第一凹槽重叠设置，且封装层的边缘与无机绝缘层边缘之间存在第一间隙。
在本申请的一实施例中，显示装置还包括：第一金属层，设置在无机绝缘层远离所述基板的一侧，第一金属层包括多条设置在非显示区的外围走线，第一凹槽中设置金属挡墙与至少一条外围走线电连接。
在本申请的一实施例中，第一凹槽中的金属挡墙与最远离显示区的外围走线电连接。
在本申请的一实施例中，显示装置还包括：驱动电路层，包括多个设置在无机绝缘层中的晶体管；第一金属层还包括设置在显示区中的源极漏极走线，源极漏极走线与对应的晶体管电连接。
在本申请的一实施例中，驱动电路层包括：第一半导体层；第一栅极层，设置在半导体层远离基板的一侧；第二栅极层，设置在第一栅极层远离基板的一侧；第二半导体层，设置在第二栅极层远离基板的一侧；第三栅极层，设置在第二半导体层远离基板的一侧；源极漏极层，设置在第二栅极层远离基板的一侧，且分别与第一半导体层和第二半导体层电连接。无机绝缘层包括：缓冲层，设置在基板的一侧，其中，第一半导体层设置在缓冲层远离基板的一侧；第一栅极绝缘层，设置在半导体层和第一栅极层之间；第二栅极绝缘层，设置在第一栅极层和第二栅极层之间；第三栅极绝缘层，设置在第二栅极层和第二半导体层之间；第四栅极绝缘层，设置在第二半导体层和第三栅极层之间；层间绝缘层，设置在第三栅极层和源极漏极层之间；其中，第一凹槽从层间绝缘层延伸至第二栅极绝缘层。
在本申请的一实施例中，第三栅极绝缘层更包括第一层间绝缘膜层及第二层间绝缘膜层，第一层间绝缘膜层设置在第二栅极绝缘层上，第二层间绝缘膜层设置在第一层间绝缘膜层及第四栅极绝缘层之间。
在本申请的一实施例中，显示装置还包括：平坦层，设置在第一金属层远离基板的一侧，平坦层设置在显示区并延伸至非显示区，平坦层的边缘与无机绝缘层边缘之间存在第二间隙，第二间隙大于第一间隙。
在本申请的一实施例中，显示装置还包括设置在平坦层远离基板的一侧的第二金属层，第二金属层包括设置在显示区的阳极和非显示区中的跨接线，跨接线与金属挡墙电连接。
在本申请的一实施例中，显示装置还包括阴极，设置在发光层远离所述基板的一侧，其中，阴极在非显示区与跨接线电连接。
在本申请的一实施例中，平坦层包括第一平坦层及第二平坦层，第一平坦层设置在无机绝缘层上，第二平坦层设置于第一平坦层上。
在本申请的一实施例中，第二凹槽定义在非显示区域中，且位于第一平坦层中，部份第二金属层填充第二凹槽且与第一金属层相连接。
在本申请的一实施例中，多个第三凹槽定义于第二平坦层中，阳极设置于平坦层上，填充第三凹槽，且与第二金属层相连接。
在本申请的一实施例中，第四凹槽自层间绝缘层延伸至第二半导体层，第一金属层填充第四凹槽且与第二半导体层相连接。
在本申请的一实施例中，显示装置更包括像素定义层，像素定义层设置在阳极上。
在本申请的一实施例中，第六凹槽定义于像素定义层上，发光层填充于第六凹槽中，阴极覆盖发光层。
在本申请的一实施例中，基板包括第一基板层、第一阻挡层、第二基板层及第二阻挡层，第一阻挡层设置于第一基板层上，第二基板层设置于第一阻挡层上，第二阻挡层设置于所述第二基板层上。
在本申请的一实施例中，第七凹槽自层间绝缘层延伸至第二基板层，部分第一平坦层填充于第七凹槽中。
在本申请的一实施例中，第一金属层包括第一源漏极层及第二源漏极层，第二源漏极层设置在第一源漏极层上，且与第一源漏极层电连接。
在本申请的一实施例中，第一源漏极层及第二源漏极层包括多个源漏极膜层。
在本申请的一实施例中，第一凹槽环绕显示区设置。
 有益效果
在本申请中，向基板延伸的源极漏极层，可以降低环境水氧对薄膜晶体管的金属氧化物器件的影响，因此防止环境中的水汽、氧气等向显示装置内扩散，因而具有提高显示装置的稳定性的有益效果。
 附图说明
图1为本申请的显示装置的俯视图。
图2为本申请的显示装置的第一示意图。
图3为本申请的显示装置的第二示意图。
图4为本申请的显示装置的第三示意图。
图5为本申请的显示装置的第四示意图。
图6为本申请的显示装置的第五示意图。
图7为本申请的显示装置的第六示意图。
图8为本申请的显示装置的第七示意图。
图9为本申请的显示装置的第七示意图。
图10为本申请的第一金属层的示意图。
图11为本申请的第二金属层的示意图。
图12为本申请的显示装置的电路图。
 本发明的最佳实施方式
为了让本申请的上述及其他目的、特征、优点能更明显易懂，下文将特举本申请优选实施例，并配合所附图式，作详细说明如下。再者，本申请所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
在图中，结构相似的单元是以相同标号表示。
如图1至图9所示，本申请提供了一种显示装置10。显示装置10有显示区AA和非显示区。显示区AA为阴极500设置的区域；非显示区包括第一走线区域VSS、第二走线区域GOA及第三走线区域VI。显示区AA为阴极500设置的区域。阴极信号由第一走线区域VSS所提供，第二走线区域GOA为驱动电路设置的区域，第三走线区域VI为复位走线设置的区域。
显示装置10包括基板、无机绝缘层、像素定义层300、发光层400以及封装层。显示装置10可为具有显示功能的手机屏幕、电脑屏幕等。图1中显示装置10的最外缘可为二次切割线。图2至图9为图1沿虚线AA’的剖视图。
进一步说明，如图2置图9所示，基板可包括第一基板层101、第一阻挡层102、第二基板层103及第二阻挡层104。第一阻挡层102设置于第一基板层101上，第二基板层103设置于第一阻挡层102上，第二阻挡层104设置于第二基板层103上。在一实施例中，第一基板层101及第二基板层103可为柔性基板。具体地，第一基板层101及第二基板层103可以聚酰亚胺制作。
无机绝缘层可设置在基板的一侧。在无机绝缘层中，对应所述非显示区设置有第一凹槽201，第一凹槽201的开口远离基板，第一凹槽201中填充有金属挡墙以阻挡水气、氧气等。
在一实施例中，第一凹槽201可环绕显示区AA设置。例如，参照图1至图2可知，第一凹槽201可设置在第二走线区域GOA中，而沿着第二走线区域GOA环绕显示区AA，因此可以阻挡水气由基板方向侵入显示装置10之中。
发光层400可设置在无机绝缘层远离基板的一侧。在一实施例中，发光层400可包括多个有机发光晶体管。
封装层可设置在发光层400远离基板的一侧，并从显示区AA延伸至非显示区。在一实施例中，本申请的显示装置10是以薄膜封装技术进行封装，而封装层包括第一封装层601及第二封装层602。另外，封装层在非显示区与第一凹槽201重叠设置，且封装层的边缘与无机绝缘层边缘之间存在第一间隙。
进一步说明，第一间隙对应二切线（2nd Cutting Line）的位置，因此在对应第一间隙的第一凹槽201设置金属挡墙可避免水汽、氧气等容易入侵到金属氧化物，即水汽、氧气等沿着氧化硅制成的无机绝缘层入侵到金属氧化物，造成薄膜晶体管器件特性发生恶化，进而导致产品异常。
在一实施例中，显示装置10的还包括第一金属层。第一金属层设置在无机绝缘层远离基板的一侧。如图2至图9所示，第一金属层包括多条设置在非显示区的外围走线，例如源漏极走线等。而第一凹槽201中的金属挡墙与至少一条外围走线电连接。
更进一步，第一凹槽201中填充的金属挡墙与最远离显示区AA的外围走线电连接。如图2至图9所示，填充在第一凹槽201的金属挡墙可与第一金属层外围走线电连接。
在一实施例中，显示装置10还包括驱动电路层。驱动电路层包括多个设置在无机绝缘层中的晶体管，晶体管可薄膜晶体管。第一金属层还包括设置在显示区中的源极漏极走线，源极漏极走线与对应的晶体管电连接。另外，源极漏极走线可以填充在第一凹槽201的金属挡墙制成。
进一步说明，驱动电路层包括第一半导体层107；第一栅极层109，设置在第一半导体层107远离基板的一侧；第二栅极层111，设置在第一栅极层109远离基板的一侧；第二半导体层114，设置在第二栅极层111远离基板的一侧；第三栅极层116，设置在第二半导体层114远离基板的一侧；源极漏极层设置在第二栅极层111远离基板的一侧，且分别与第一半导体层107和第二半导体层114电连接。
在一實施例中，第一半导体层107包括非晶硅。而在另一实施例中，多晶硅可以雷射退火(excimer laser annealing)的方式形成于第一半导体层107中，以提供对于电子及电洞具有高移动率的半导体沟道。换言之，具有第一半导体层107的薄膜晶体管可为低温多晶硅薄膜晶体管(low temperature poly-silicon thin film transistor,LTPS TFT)。
在一实施例中，第二半导体层114可包括氧化铟镓锌。换言之，具有第二半导体层114的薄膜晶体管可为铟镓锌氧薄膜晶体管(indium gallium zinc oxide thin film transistor,IGZO TFT)。使用IGZO TFT薄膜晶体管可降低漏电流。
进一步说明，在一实施例中，如图2至图9所示，第一金属层可包括第一源漏极层119及第二源漏极层120。第二源漏极层120设置在第一源漏极层119上，且与第一源漏极层119电连接。
在一实施例中，如图10所示，源极漏极层为具有高耐腐蚀性和高耐酸性的金属形成的多层结构。具体地，第一源漏极层119可包括第一源漏极膜层1191、第二源漏极膜层1192及第三源漏极膜层1193。其中，第一源漏极膜层1191及第三源漏极膜层1193可由钛所制成，第二源漏极膜层1192可由铝所制成，但不以此为限。第一源漏极层119亦可为单层结构，或是第一源漏极膜层1191、第二源漏极膜层1192及第三源漏极膜层1193可依据需求以其它材质制成。
在另一实施例中，如图11所示，第二源漏极层120可包括具有高耐腐蚀性和高耐酸性的金属形成的多层结构。具体地，第二源漏极层120可包括第四源漏极膜层1201、第五源漏极膜层1202及第六源漏极膜层1203。其中，第四源漏极膜层1201及第六源漏极膜层1203可由钛所制成，第五源漏极膜层1202可由铝所制成，但不以此为限。第二源漏极层120亦可为单层结构，或是第四源漏极膜层1201、第五源漏极膜层1202及第六源漏极膜层1203可依据需求以其它材质制成。
而上述的无机绝缘层包括：缓冲层，设置在基板的一侧，其中，第一半导体层107设置在缓冲层远离基板的一侧；第一栅极绝缘层108，设置在第一半导体层107和第一栅极层109之间；第二栅极绝缘层110，设置在第一栅极层109和第二栅极层111之间；第三栅极绝缘层，设置在第二栅极层111和第二半导体层114之间；第四栅极绝缘层115，设置在第二半导体层114和第三栅极层116之间；层间绝缘层121，设置在第三栅极层116和源极漏极层之间；其中，第一凹槽201从层间绝缘层121延伸至第二栅极绝缘层110。
进一步说明，缓冲层设置在基板上。在一实施例中，缓冲层包括第一缓冲膜层105及第二缓冲膜层106。第一缓冲膜层105设置于基板上，第二缓冲膜层106设置于第一缓冲膜层105上。第一缓冲膜层105包括氮化硅，第二缓冲膜层106包括氧化硅。第一半导体层107，设置于缓冲层上。第一栅极绝缘层108设置于缓冲层上，且覆盖第一半导体层107。第一栅极层109设置于第一栅极绝缘层108上。第二栅极绝缘层110，设置于第一栅极绝缘层108上。
除此之外，显示装置10还包括平坦层，平坦层设置在第一金属层远离基板的一侧。且在一实施例中，平坦层可包括第一平坦层117及第二平坦层118。第一平坦层117设置于层间绝缘层121上，第二平坦层118设置于第一平坦层117上。平坦层设置在显示区并延伸至非显示区，平坦层的边缘与无机绝缘层边缘之间存在第二间隙，第二间隙大于第一间隙。
进一步说明，第一金属层可设置在层间绝缘层121上，且由第一平坦层117所覆盖；第二金属层可设置在第一平坦层117上，且由第二平坦层118所覆盖；第二凹槽202可定义在非显示区域中，且位于第一平坦层117中；而部份第二金属层可填充第二凹槽202且与第一金属层相连接。
在一实施例中，第二金属层设置在平坦层远离基板的一侧，第二金属层包括设置在显示区AA的阳极200和非显示区中的跨接线210，跨接线210与金属挡墙电连接。阳极200设置在平坦层远离基板的一侧。在非显示区的跨接线210与金属挡墙电连接。
如图2至图9所示，显示装置10还包括像素定义层300、阴极500及彩膜层700。阴极500设置在发光层400远离基板的一侧。具体地，阴极500整面铺设在发光层400远离基板的一侧，并在非显示区与跨接线210电连接。且在一实施例中，跨接线210是阳极200同层金属制备的跨接线210。像素定义层300设置在阳极200上。发光层400设置于像素定义层300上。
另外，如图2至图9所示，阴极500设置在像素定义层300上覆盖发光层400。封装层设置在阴极500上并覆阳极200、像素定义层300、发光层400及阴极500。且在一实施例中，彩膜层700可以喷墨打印方式设置于第一封装层601及第二封装层602之间。
在一实施例中，如图2至图6所示，第三栅极绝缘层更包括第一层间绝缘膜层112及第二层间绝缘膜层113，第一层间绝缘膜层112设置在第二栅极绝缘层110上，第二层间绝缘膜层113设置在第一层间绝缘膜层112及第四栅极绝缘层115之间。第一层间绝缘膜层112包括氮化硅。第二层间绝缘膜层113包括氧化硅。
如图2所示，在一实施例中，第一凹槽201自层间绝缘层121延伸至第二层间绝缘膜层113的上表面，以阻挡水气、氢气、氧气等从基板方向扩散至第二半导体层114。
如图3所示，在一实施例中，第一凹槽201自层间绝缘层121延伸至第二层间绝缘膜层113的上表面及下表面之间，以阻挡水气、氢气、氧气等从基板方向扩散至第二半导体层114。
如图4所示，在一实施例中，第一凹槽201自层间绝缘层121延伸至第二层间绝缘膜层113的下表面以增加阻挡水气、氢气、氧气等从基板方向扩散至第二半导体层114的效果。
如图5所示，在一实施例中，第一凹槽201自延伸至第一功能层，以具有最佳的阻挡水气、氢气、氧气等从基板方向扩散至第二半导体层114的效果。
在另一实施例中，如图6至图9所示，第三栅极绝缘层仅包括第一层间绝缘膜层112。第一层间绝缘膜层112仅包括氧化硅。由于氧化硅对于水气、氢气、氧气等的阻挡能力不如氮化硅，换言之，此种结构对于水气、氢气、氧气等的阻挡能力不如第三栅极绝缘层包括第一层间绝缘膜层112及第二层间绝缘膜层113的实施例。因此如图6至图9所示第一凹槽201至少自层间绝缘层121至第二栅极绝缘层110上。
具体地，在一实施例中，如图6所示，第一凹槽201自层间绝缘层121延伸至第二栅极绝缘层110的上表面，以阻挡水气、氢气、氧气等从基板方向扩散至第二半导体层114。
在一实施例中，如图7所示，第一凹槽201自层间绝缘层121延伸至第二栅极绝缘层110的上表面及下表面之间，以阻挡水气、氢气、氧气等从基板方向扩散至第二半导体层114。
在一实施例中，如图8所示，第一凹槽201自层间绝缘层121延伸至第二栅极绝缘层110下表面之间，以阻挡水气、氢气、氧气等从基板方向扩散至第二半导体层114。
在一实施例中，如图9所示，第一凹槽201自层间绝缘层121延伸至第一栅极绝缘层108，可较图6至图8的结构中具有更佳的阻挡水气、氢气、氧气等从基板方向扩散至第二半导体层114的功效。
除了上述的第一凹槽201及第二凹槽202外，如图2至图9所示，显示装置10还定义有第三凹槽203、第四凹槽204、第五凹槽205、第六凹槽206及第七凹槽207。
在一实施例中，多个第三凹槽203定义于第二平坦层118中，阳极200设置于平坦层上，填充第三凹槽203，且与第二金属层相连接。
在一实施例中，第四凹槽204自层间绝缘层121延伸至第二半导体层114，第一金属层填充第四凹槽204与第二半导体层114相连接。
在一实施例中，第五凹槽205自层间绝缘层121延伸至第一半导体层107，第一金属层填充第五凹槽205与第一半导体层107相连接。
在一实施例中，第六凹槽206定义于像素定义层300上。发光层400填充于第六凹槽206中，阴极500覆盖发光层400。
在一实施例中，第七凹槽207自层间绝缘层121延伸至第二基板层103，部分第一平坦层117填充于第七凹槽207，以阻挡水气、氧气等侵入显示结构100。
在一实施例中，如图12所示，本申请显示装置10包括由7个薄膜晶体管及1个电容(7 thin film transistors and 1 capacitor,7T1C)构成的电路。具有第二半导体层114的薄膜晶体管可为图12中的薄膜晶体管T3或是薄膜晶体管T4，具有第一半导体层107的薄膜晶体管可为图12中除薄膜晶体管T3或是薄膜晶体管T4之外的薄膜晶体管。
因此，综上所述，本申请利用向基板延伸的源漏极层，以降低环境水氧对薄膜晶体管的金属氧化物器件的影响，防止环境中的水汽、氧气等向显示装置内扩散，特别是，可防止有源层被水汽、氧气等影响，因而提高显示装置的稳定性。
尽管已经相对于一个或多个实现方式示出并描述了本申请，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本申请包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本申请的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1.    一种显示装置，其中，所述显示装置上定义有显示区和非显示区且包括：
    基板；
    无机绝缘层，设置在所述基板的一侧，并在对应所述非显示区设置第一凹槽，所述第一凹槽的开口远离所述基板，所述第一凹槽中设置金属挡墙；
    发光层，设置在所述无机绝缘层远离所述基板的一侧；
    封装层，设置在所述发光层远离所述基板的一侧，并从所述显示区延伸至所述非显示区，
    其中，所述封装层在所述非显示区与所述第一凹槽重叠设置，且所述封装层的边缘与所述无机绝缘层边缘之间存在第一间隙。
  2.    根据权利要求1所述的显示装置，其中，所述显示装置还包括：
    第一金属层，设置在所述无机绝缘层远离所述基板的一侧，所述第一金属层包括多条设置在所述非显示区的外围走线，所述第一凹槽中设置金属挡墙与至少一条所述外围走线电连接。
  3.    根据权利要求2所述的显示装置，其中，所述第一凹槽中的金属挡墙与最远离所述显示区的所述外围走线电连接。
  4.    根据权利要求2所述的显示装置，其中，所述显示装置还包括：
    驱动电路层，包括多个设置在所述无机绝缘层中的晶体管；
    所述第一金属层还包括设置在所述显示区中的源极漏极走线，所述源极漏极走线与对应的晶体管电连接。
  5.    根据权利要求4所述的显示装置，其中，所述驱动电路层包括：
    第一半导体层；
    第一栅极层，设置在所述半导体层远离所述基板的一侧；
    第二栅极层，设置在所述第一栅极层远离所述基板的一侧；
    第二半导体层，设置在所述第二栅极层远离所述基板的一侧；
    第三栅极层，设置在所述第二半导体层远离所述基板的一侧；
    源极漏极层，设置在所述第二栅极层远离所述基板的一侧，且分别与所述第一半导体层和所述第二半导体层电连接；
    所述无机绝缘层包括：
    缓冲层，设置在所述基板的一侧，其中，所述第一半导体层设置在所述缓冲层远离所述基板的一侧；
    第一栅极绝缘层，设置在所述半导体层和所述第一栅极层之间；
    第二栅极绝缘层，设置在所述第一栅极层和所述第二栅极层之间；
    第三栅极绝缘层，设置在所述第二栅极层和所述第二半导体层之间；
    第四栅极绝缘层，设置在所述第二半导体层和所述第三栅极层之间；
    层间绝缘层，设置在所述第三栅极层和所述源极漏极层之间；
    其中，所述第一凹槽从所述层间绝缘层延伸至所述第二栅极绝缘层。
  6.    根据权利要求4所述的显示装置，其中，所述第三栅极绝缘层更包括第一层间绝缘膜层及第二层间绝缘膜层，所述第一层间绝缘膜层设置在所述第二栅极绝缘层上，所述第二层间绝缘膜层设置在所述第一层间绝缘膜层及所述第四栅极绝缘层之间。
  7.    根据权利要求2所述的显示装置，其中，所述显示装置还包括：
    平坦层，设置在所述第一金属层远离所述基板的一侧，所述平坦层设置在所述显示区并延伸至所述非显示区，所述平坦层的边缘与所述无机绝缘层边缘之间存在第二间隙，所述第二间隙大于所述第一间隙。
  8.    根据权利要求7所述的显示装置，其中，所述显示装置还包括：
    设置在所述平坦层远离所述基板的一侧的第二金属层，所述第二金属层包括设置在所述显示区的阳极和所述非显示区中的跨接线，所述跨接线与所述金属挡墙电连接。
  9.    根据权利要求8所述的显示装置，其中，所述显示装置还包括：
    阴极，设置在所述发光层远离所述基板的一侧，其中，所述阴极在所述非显示区与所述跨接线电连接。
  10. 根据权利要求7所述的显示装置，其中，所述平坦层包括第一平坦层及第二平坦层，所述第一平坦层设置在所述无机绝缘层上，所述第二平坦层设置于所述第一平坦层上。
  11. 根据权利要求10所述的显示装置，其中，第二凹槽定义在所述非显示区域中，且位于所述第一平坦层中，部份所述第二金属层填充所述第二凹槽且与第一金属层相连接。
  12. 根据权利要求10所述的显示装置，其中，多个第三凹槽定义于所述第二平坦层中，所述阳极设置于所述平坦层上，填充所述第三凹槽，且与所述第二金属层相连接。
  13. 根据权利要求5所述的显示装置，其中，第四凹槽自所述层间绝缘层延伸至所述第二半导体层，所述第一金属层填充所述第四凹槽且与所述第二半导体层相连接。
  14. 根据权利要求8所述的显示装置，其中，所述显示装置更包括像素定义层，所述像素定义层设置在所述阳极上。
  15. 根据权利要求14所述的显示装置，其中，所述第六凹槽定义于所述像素定义层上，所述发光层填充于所述第六凹槽中，所述阴极覆盖所述发光层。
  16. 根据权利要求5所述的显示装置，其中，所述基板包括第一基板层、第一阻挡层、第二基板层及第二阻挡层，所述第一阻挡层设置于所述第一基板层上，所述第二基板层设置于所述第一阻挡层上，所述第二阻挡层设置于所述第二基板层上。
  17. 根据权利要求16所述的显示装置，其中，第七凹槽自所述层间绝缘层延伸至所述第二基板层，部分第一平坦层填充于所述第七凹槽中。
  18. 根据权利要求2所述的显示装置，其中，所述第一金属层包括第一源漏极层及第二源漏极层，所述第二源漏极层设置在所述第一源漏极层上，且与所述第一源漏极层电连接。
  19. 根据权利要求18所述的显示装置，其中，所述第一源漏极层及所述第二源漏极层包括多个源漏极膜层。
  20. 根据权利要求1所述的显示装置，其中，所述第一凹槽环绕所述显示区设置。
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