WO2023071312A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023071312A1
WO2023071312A1 PCT/CN2022/106870 CN2022106870W WO2023071312A1 WO 2023071312 A1 WO2023071312 A1 WO 2023071312A1 CN 2022106870 W CN2022106870 W CN 2022106870W WO 2023071312 A1 WO2023071312 A1 WO 2023071312A1
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WO
WIPO (PCT)
Prior art keywords
light emitting
emitting device
light
reset
display panel
Prior art date
Application number
PCT/CN2022/106870
Other languages
English (en)
French (fr)
Inventor
黄耀
刘聪
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP22885215.8A priority Critical patent/EP4336543A4/en
Priority to CN202280002288.9A priority patent/CN117296473A/zh
Priority to US18/287,529 priority patent/US20240212610A1/en
Publication of WO2023071312A1 publication Critical patent/WO2023071312A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/128—Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • Embodiments of the disclosure relate to a display panel and a display device.
  • OLED Organic Light-Emitting Diode
  • Embodiments of the present disclosure provide a display panel and a display device to improve display uniformity.
  • An embodiment of the present disclosure provides a display panel, including a first display area and a second display area, the transmittance of the first display area is greater than the transmittance of the second display area;
  • the first display The region includes a plurality of built-in light emitting devices and at least one first driving circuit, the plurality of built-in light emitting devices includes a first light emitting device and a second light emitting device, the first driving circuit is connected to the first light emitting device, the The first driving circuit is configured to drive the first light emitting device to emit light;
  • the second display area includes at least one third light emitting device and a plurality of external driving circuits, and the plurality of external driving circuits include a second driving circuit and a third driving circuit, the second driving circuit is connected to the second light emitting device through wires, the second driving circuit is configured to drive the second light emitting device to emit light, the third driving circuit is connected to the second light emitting device The third light emitting device is connected, and the third driving circuit is configured to drive the third light emit
  • the number of the third light-emitting devices is multiple, and in the first direction, the external driving circuit and the third light-emitting devices are arranged periodically, and the arrangement period of the external driving circuit is less than the arrangement period of the third light emitting device.
  • the ratio between the arrangement period of the external driving circuit and the arrangement period of the third light emitting devices is greater than or equal to 1/2 and less than or equal to 9/10.
  • the first light-emitting device includes a first anode layer disposed on the base substrate
  • the third light-emitting device includes a second anode layer disposed on the base substrate;
  • the ratio between the area of the orthographic projection on the base substrate and the area of the orthographic projection of the first anode layer on the base substrate is smaller than the area of the orthographic projection of the third drive circuit on the base substrate
  • the orthographic projection of the first anode layer on the base substrate covers the orthographic projection of the first driving circuit on the base substrate.
  • the first display area is divided into two sub-areas, wherein the light-emitting devices in one sub-area are all first light-emitting devices, and the light-emitting devices in the other sub-area are all second light-emitting devices.
  • multiple first light emitting devices are provided, multiple second light emitting devices are provided, multiple first light emitting devices form multiple first light emitting device groups, and multiple second light emitting devices form multiple second light emitting device groups.
  • a light emitting device group, a plurality of first light emitting device groups and a plurality of second light emitting device groups are arranged alternately, the first light emitting device group includes at least one row of first light emitting devices, and the second light emitting device group includes at least one row of second light emitting device groups Light emitting devices.
  • the first light emitting device includes a green light emitting device and/or a blue light emitting device;
  • the second light emitting device includes at least one of the following: a green light emitting device, a blue light emitting device and a red light emitting device.
  • the first light emitting device includes a red light emitting device and/or a blue light emitting device;
  • the second light emitting device includes at least one of the following: a green light emitting device, a blue light emitting device and a red light emitting device.
  • the first light emitting device includes a green light emitting device and/or a red light emitting device
  • the second light emitting device includes at least one of the following: a green light emitting device, a blue light emitting device and a red light emitting device.
  • the number of the first light emitting devices is greater than or equal to the number of the second light emitting devices.
  • the second light-emitting device includes a first-color light-emitting device, a second-color light-emitting device, and a third-color light-emitting device
  • the wire connecting the first-color light-emitting device and the second driving circuit is the first A lead wire
  • the lead wire connecting the light-emitting device of the second color and the second driving circuit is the second lead wire
  • the lead wire connecting the light-emitting device of the third color and the second driving circuit is the third lead wire
  • the first light emitting device includes a first color light emitting device
  • the second light emitting device includes a second color light emitting device and a third color light emitting device
  • the first color light emitting device, the second color light emitting device The two-color light-emitting device and the third-color light-emitting device are configured to emit light of different colors.
  • the first light emitting device includes a green light emitting device
  • the second light emitting device includes a red light emitting device and a blue light emitting device.
  • the lead wires include a first conductive wire and a second conductive wire, the first conductive wire is connected to the light emitting device of the second color, and the second conductive wire is connected to the light emitting device of the third color.
  • the signal line connected to the first driving circuit includes a first line segment and a second line segment, the first line segment is connected to the second line segment, and the first line segment is located in the first display area Inside, the second line segment is located in the second display area, the material of the first line segment includes a transparent conductive material, and the material of the second line segment includes a metal material.
  • the material of the lead wire is a transparent conductive material, and the lead wire and the first line segment are respectively located in different film layers.
  • the display panel further includes a plurality of signal lines connected to the first driving circuit, wherein at least one signal line in the plurality of signal lines is arranged in segments.
  • the segmented signal lines include a plurality of signal portions located on different layers.
  • the segmented signal line includes a first signal portion and a second signal portion
  • the material of the first signal portion includes transparent conductive metal oxide
  • the material of the second signal portion includes metal
  • the first display area includes a driving circuit setting area and a wiring area
  • the first signal part is located in the driving circuit setting area
  • the second signal part is located in the wiring area.
  • the display panel further includes a light emission control signal line, a reset control signal line, and a reset signal line
  • the pixel circuit includes a driving module, a light emission control circuit, and a reset circuit
  • the pixel circuit includes the first driving circuit
  • the At least one of the second drive circuit and the third drive circuit the light emission control signal line is connected to the control terminal of the light emission control circuit
  • the reset control signal line is connected to the control terminal of the reset circuit
  • the reset signal line is connected to the first pole of the reset circuit
  • at least one of the light emission control signal line, the reset control signal line, and the reset signal line is arranged in sections in the first display area.
  • the reset circuit includes a first reset transistor and a second reset transistor, the first reset transistor is configured to reset the control terminal of the driving module, and the second reset transistor is configured to reset the control terminal of the light emitting device.
  • the first electrode is reset
  • the light emitting device includes at least one of the first light emitting device, the second light emitting device, and the third light emitting device, and in the same pixel circuit located in the first display area, The first reset transistor and the second reset transistor share the same reset signal line.
  • the layout of the second driving circuit and the third driving circuit are the same, and the layout of the first driving circuit is different from that of the second driving circuit or the third driving circuit.
  • the first drive circuit includes a drive transistor, a first reset transistor, a second reset transistor, a data writing transistor, and a threshold compensation transistor
  • the first pole of the first reset transistor is electrically connected to the first reset signal line
  • the second pole of the first reset transistor is electrically connected to the gate of the drive transistor
  • the first pole of the second reset transistor is electrically connected to the second reset signal line
  • the second pole of the second reset transistor The electrode is connected to the first light-emitting device
  • the first electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor
  • the second electrode of the data writing transistor is configured to be connected to the data line
  • the first pole of the threshold compensation transistor is electrically connected to the second pole of the driving transistor
  • the second pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor
  • the first reset signal line and the The second reset signal line is the same reset signal line.
  • the gate of the second reset transistor, the gate of the data writing transistor, and the gate of the threshold compensation transistor are all connected to the same gate signal line.
  • the pixel density of the first display area is less than or equal to the pixel density of the second display area.
  • the second display area surrounds the first display area.
  • the present disclosure provides a display device, comprising: a photosensitive element and any one of the above display panels, where the orthographic projection of the photosensitive element on the display panel overlaps with the first display area.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a third light emitting device and an external driving circuit in a display panel provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a third light emitting device and an external driving circuit in another display panel provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a plane structure comparing a first display area and a second display area provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic plan view of another comparison of the first display area and the second display area provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic cross-sectional structure diagram of a signal line in a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display panel adopting a fully built-in solution.
  • FIG. 10 is a schematic diagram of a display panel adopting an all-exterior solution.
  • FIG. 11 is a schematic diagram of lead wires in a display panel adopting an all-exterior solution.
  • Fig. 12 is a schematic diagram of a display panel using a compression scheme and a built-in scheme provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 16 is a layout diagram of a pixel circuit located in a second display area in a display panel provided by an embodiment of the present disclosure.
  • Fig. 17 is a layout diagram of a pixel circuit located in a first display area in a display panel provided by an embodiment of the present disclosure.
  • FIG. 18 is a layout diagram of pixel circuits located in the first display area and the second display area in the display panel provided by an embodiment of the present disclosure.
  • FIG. 19 is a cross-sectional view along line B1-B2 of FIG. 18 .
  • FIG. 20 is a plan view of the active layer in FIG. 16 .
  • FIG. 21 is a plan view of the first conductive layer in FIG. 16 .
  • FIG. 22 is a plan view of the second conductive layer in FIG. 16 .
  • FIG. 23 is a plan view of the third conductive layer in FIG. 16 .
  • FIG. 24 is a plan view of the fourth conductive layer in FIG. 16 .
  • FIG. 25 is a stacked plan view of the active layer and the first conductive layer in FIG. 16 .
  • FIG. 26 is a stacked plan view of the active layer, the first conductive layer, and the second conductive layer in FIG. 16 .
  • FIG. 27 is a stacked plan view of the third conductive layer and the fourth conductive layer in FIG. 16 .
  • FIG. 28 is a stacked plan view of via holes in the third conductive layer, the fourth conductive layer and the insulating layer therebetween in FIG. 16 .
  • FIG. 29 is a stacked plan view of the active layer, the third conductive layer, the fourth conductive layer, and the via hole in the insulating layer between the third conductive layer and the fourth conductive layer in FIG. 16 .
  • Figure 30 is the active layer, the third conductive layer, the fourth conductive layer, the via hole in the insulating layer between the active layer and the third conductive layer in Figure 16, and the via hole in the third conductive layer and the fourth conductive layer Stack-up plan view of a via in the insulating layer between layers.
  • FIG. 31 is a plan view of an active layer in a first display region of a display panel provided by an embodiment of the present disclosure.
  • FIG. 32 is a plan view of a first conductive layer in a first display region of a display panel provided by an embodiment of the present disclosure.
  • FIG. 33 is a plan view of the second conductive layer in the first display area of the display panel provided by an embodiment of the present disclosure.
  • FIG. 34 is a plan view of a third conductive layer in a first display area of a display panel provided by an embodiment of the present disclosure.
  • FIG. 35 is a plan view of the fourth conductive layer in the first display area of the display panel provided by an embodiment of the present disclosure.
  • Fig. 36 is a plan view of the transparent conductive layer in the first display area of the display panel provided by an embodiment of the present disclosure.
  • FIG. 37A is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 37B is a layout diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 38 is a plan view of an active layer LY0 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 39 is a plan view of a first conductive layer LY1 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 40 is a plan view of a second conductive layer LY2 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 41 is a plan view of a third conductive layer LY3 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 42 is a plan view of a fourth conductive layer LY4 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 43 is a plan view of a transparent conductive layer LYa in a display panel provided by an embodiment of the present disclosure.
  • FIG. 44 is a plan view of a transparent conductive layer LYb in a display panel provided by an embodiment of the present disclosure.
  • FIG. 45 is a stacked plan view of an active layer LY0 and a first conductive layer LY1 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 46 is a stacked plan view of an active layer LY0 , a first conductive layer LY1 , and a second conductive layer LY2 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 47 is a stacked plan view of the active layer LY0 , the first conductive layer LY1 , the second conductive layer LY2 , and the third conductive layer LY3 in the display panel provided by an embodiment of the present disclosure.
  • FIG. 48 is a stacked plan view of the active layer LY0 , the first conductive layer LY1 , the second conductive layer LY2 , the third conductive layer LY3 , and the fourth conductive layer LY4 in the display panel provided by an embodiment of the present disclosure.
  • the fourth conductive layer LY4 is a stack of the active layer LY0, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, the fourth conductive layer LY4, and the transparent conductive layer LYa in the display panel provided by the embodiment of the present disclosure. floor plan.
  • FIG. 50 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 51 is a schematic diagram of a partial planar structure of a display panel provided by an embodiment of the present disclosure.
  • FIG. 52 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 53 is a schematic diagram of a partial planar structure of a display panel provided by an embodiment of the present disclosure.
  • the driving signals for controlling the light-emitting devices to emit light are drawn out from parallel pixel circuits in the horizontal direction, and the leads for transmitting the driving signals are made of transparent conductive materials.
  • embodiments of the present disclosure provide a display panel and a display device including the display panel, which will be described in detail below.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display panel, as shown in FIG. 1 , including a first display area 11 and a second display area 12 , the transmittance of the first display area 11 is greater than that of the second display area 12 .
  • the second display area 12 is located on at least one side of the first display area 11 .
  • Embodiments of the present disclosure are described by taking the second display area 12 surrounding the first display area 11 as an example.
  • the first display area 11 includes a plurality of built-in light emitting devices 13 and at least one first driving circuit 14, the plurality of built-in light emitting devices 13 includes a first light emitting device 131 and a second light emitting device 132, and the first driving circuit 14 is connected to the first light emitting device 131, and the first driving circuit 14 is configured to drive the first light emitting device 131 to emit light.
  • the first driving circuit 14 may also be referred to as a built-in driving circuit.
  • the second display area 12 includes at least one third light emitting device 15 and a plurality of external drive circuits 16, and the plurality of external drive circuits 16 include a second drive circuit 161 and a third drive circuit 162.
  • the driving circuit 161 is connected to the second light-emitting device 132 through the wire 17, the second driving circuit 161 is configured to drive the second light-emitting device 132 to emit light, the third driving circuit 162 is connected to the third light-emitting device 15, and the third driving circuit 162 is configured to To drive the third light emitting device 15 to emit light.
  • built-in and external can be relative to the first display area 11, and the light-emitting device located in the first display area 11 can be called a built-in light-emitting device (the built-in light-emitting device as shown in FIG. 1 13)
  • the driving circuit located in the first display area 11 may be called a built-in driving circuit (the first driving circuit 14 shown in FIG. 1 ).
  • the driving circuit can be divided into an in-situ driving circuit and an ex-situ driving circuit.
  • the second driving circuit 161 and the second light emitting device 132 are disposed separately and located in the second display area 12 and the first display area 11 respectively, so the second driving circuit 161 can be called an ex-situ driving circuit.
  • both the third driving circuit 162 and the third light emitting device 15 are located in the second display area 12 , so the third driving circuit 162 can be called an in-situ driving circuit.
  • both the first light emitting device 131 and the first driving circuit 14 are located in the first display area 11 , so the first driving circuit 14 can be called an in-situ driving circuit.
  • the direction connecting the second light emitting device 132 and the second driving circuit 161 is defined as a first direction X, as shown in FIG. 1 .
  • the second display area 12 is located on at least one side of the first display area 11 along the first direction X. As shown in FIG. Optionally, the second display area 12 may surround the first display area 11 .
  • the first light emitting device 131 , the second light emitting device 132 and the third light emitting device 15 may all be organic light emitting devices or quantum dot light emitting devices, which are not limited in this embodiment of the present disclosure.
  • the shape of the first display area 11 may be a rectangle, a square, a circle or an ellipse, which is not limited in this embodiment of the present disclosure.
  • the display panel provided by the embodiments of the present disclosure, by disposing the first drive circuit 14 connected to the first light emitting device 131 in the first display area 11, the number of wires 17 connecting the built-in light emitting device 13 and the external drive circuit 16 can be reduced. Quantity, so as to reduce the diffraction effect caused by the lead wire 17, and improve the image quality; the length of the lead wire 17 can also be shortened, thereby reducing the coupling capacitance caused by the lead wire 17, and improving the display uniformity of the first display area 11.
  • the second driving circuit 161 connected to the second light emitting device 132 in the second display area 12 the transmittance of the first display area 11 can be improved.
  • the length of the lead wires 17 can be shortened by optimizing the design, the coupling capacitance is reduced, and the influence of the coupling capacitance on the turn-on voltage is reduced, thereby improving display uniformity.
  • reducing the number of leads 17 can also increase process stability.
  • the display panel and the display device provided by the embodiments of the present disclosure can reduce the number of leads connecting the built-in light-emitting device and the external drive circuit by arranging the first drive circuit connected to the first light-emitting device in the first display area, thereby reducing the The diffraction effect caused by the lead wires improves the picture quality; the length of the lead wires can also be shortened, thereby reducing the coupling capacitance caused by the lead wires and improving the display uniformity of the first display area; in addition, by setting the second drive circuit connected to the second light-emitting device In the second display area, the transmittance of the first display area can be improved.
  • the number of the third light emitting devices 15 may be multiple.
  • the external drive circuit 16 and the third light emitting device 15 may be arranged periodically.
  • the arrangement period of the external driving circuit 16 and the arrangement period of the third light emitting devices 15 may be the same or different.
  • FIG. 2 is a schematic structural diagram of a third light emitting device and an external driving circuit in a display panel provided by an embodiment of the present disclosure.
  • the arrangement period p2 of the external driving circuit 16 is the same as the arrangement period p1 of the third light emitting device 15 , for example, both are 31.6 ⁇ m.
  • the arrangement period p2 of the external driving circuit 16 is shorter than the arrangement period p1 of the third light emitting devices 15 .
  • FIG. 3 is a schematic structural diagram of a third light emitting device and an external driving circuit in another display panel provided by an embodiment of the present disclosure.
  • the arrangement periods of the external drive circuit 16 and the third light emitting devices 15 in the first direction X are different.
  • the arrangement period p2 of the external driving circuit 16 is, for example, 27.6 ⁇ m
  • the arrangement period p1 of the third light emitting device 15 is 31.6 ⁇ m.
  • the arrangement period p1 of the third light emitting devices 15 is 4 ⁇ m wider than the arrangement period p2 of the external driving circuit 16 in the first direction X.
  • the arrangement period p2 of the external driving circuit 16 and the arrangement period p1 of the third light emitting devices 15 are not limited to the above description.
  • the external drive circuit 16 can be greater than the number of third light-emitting devices 15, to ensure that each third light-emitting device 15 has a corresponding external drive circuit 16, that is, the third drive circuit 162 is connected to ensure the normal display of the second display area 12, and also There is an external drive circuit 16 not connected to any third light emitting device 15, that is, a second drive circuit 161, and the second drive circuit 161 can be connected to the second light emitting device 132 of the first display area 11 for driving the first display The second light emitting device 132 in the region 11.
  • the second driving circuit 161 connected to the second light-emitting device 132 can be arranged in the second display area 12, so that the transmittance of the first display area 11 can be improved, and at the same time, the second driving circuit 161 can be ensured.
  • a display area 11 has high display uniformity.
  • the arrangement period p1 of the third light-emitting devices 15 in the first direction X is 31.6 ⁇ m
  • the external drive circuit 16 is in the first direction X
  • the arrangement period p2 on X is 27.6 ⁇ m.
  • 48 redundant second driving circuits 161 need to be set in the second display area 12 to control these first light emitting devices.
  • the second light-emitting device 132 emits light. Therefore, a total space of 48*27.6 ⁇ m needs to be compressed to set up 48 redundant second drive circuits 161.
  • each third light-emitting device 15 can compress a space of 4 ⁇ m, a corresponding The number of the third light emitting devices 15 is 48*27.6 ⁇ m/4 ⁇ m, which is 332 after rounding. That is, 332 third driving circuits 162 and 48 second driving circuits 161 can be arranged in a space of 332*31.6 ⁇ m. Among them, 332 third driving circuits 162 are used to drive 332 third light emitting devices 15 in the second display area 12 to emit light, and 48 second driving circuits 161 are used to drive 48 second light emitting devices in the first display area 11. Device 132 emits light.
  • the ratio between the arrangement period p2 of the external drive circuit 16 and the arrangement period p1 of the third light-emitting devices 15 may be greater than or equal to 1/2 and less than or equal to 9/10. There is no limit to this.
  • the ratio may be 2/3, 3/4, 4/5, 5/6, 6/7, 7/8, 8/9, and so on. As shown in FIG. 3 , the ratio between the arrangement period p2 of the external driving circuit 16 and the arrangement period p1 of the third light emitting devices 15 is 4/5.
  • the arrangement period may refer to a pitch (Pitch).
  • the arrangement period p2 of the external driving circuits 16 refers to the pitch of the external driving circuits 16 .
  • the arrangement period p1 of the third light emitting devices 15 refers to the pitch of the arrangement period p1 of the third light emitting devices 15 .
  • the arrangement period p1 may be a fixed value, and the arrangement period p2 may be a fixed value.
  • the arrangement period p1 can be different values, and the arrangement period p2 can be different values.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present disclosure.
  • the first light-emitting device 131 may include a first anode layer 41 disposed on the base substrate 40 , and may also include a first light-emitting layer 42 disposed on the side of the first anode layer 41 away from the base substrate 40 and the first cathode layer 43 , the first light emitting layer 42 is disposed between the first anode layer 41 and the first cathode layer 43 .
  • the first driving circuit 14 may be disposed on a side of the first anode layer 41 close to the base substrate 40 , that is, disposed between the base substrate 40 and the first anode layer 41 .
  • the third light emitting device 15 may include a second anode layer 44 disposed on the base substrate 40 , and may also include a second light emitting layer 45 disposed on the side of the second anode layer 44 away from the base substrate 40 and the second cathode layer 46 , the second light emitting layer 45 is disposed between the second anode layer 44 and the second cathode layer 46 .
  • the third driving circuit 162 may be disposed on a side of the second anode layer 44 close to the base substrate 40 , that is, disposed between the base substrate 40 and the second anode layer 44 .
  • FIG. 5 is a schematic diagram of a plane structure comparing a first display area and a second display area provided by an embodiment of the present disclosure.
  • the area between the orthographic projection area of the first drive circuit 14 on the base substrate 40 and the orthographic projection area of the first anode layer 41 on the base substrate 40 The ratio of is smaller than the ratio between the area of the orthographic projection of the third driving circuit 162 on the base substrate 40 and the area of the orthographic projection of the second anode layer 44 on the base substrate 40 .
  • Orthographic projection areas of the second driving circuit 161 and the third driving circuit 162 on the base substrate 40 may be the same.
  • the first drive circuit 14 when the area of the orthographic projection of the first anode layer 41 on the base substrate 40 is equal to the area of the orthographic projection of the second anode layer 44 on the base substrate 40 , the first drive circuit 14 The area of the orthographic projection on the base substrate 40 is smaller than the area of the orthographic projection of the third driving circuit 162 on the base substrate 40 .
  • the driving circuit in the first display area 11 that is, the compression ratio of the first driving circuit 14 relative to the first anode layer 41 is larger. Since the driving circuit usually includes multiple metal layers, the transmittance is relatively poor. In this implementation, by rationally designing the positional relationship between the first anode layer 41 and the first driving circuit 14, the impact of the first driving circuit 14 on the The influence of the aperture ratio of the first display region 11 increases the aperture ratio of the first display region 11 .
  • FIG. 6 is a schematic plan view of another comparison of the first display area and the second display area provided by an embodiment of the present disclosure.
  • the orthographic projection of the first anode layer 41 on the base substrate 40 may cover the orthographic projection of the first driving circuit 14 on the base substrate 40 . Since the transmittance of the driving circuit is poor, the transmittance of the first display region 11 can be further improved by setting the first anode layer 41 to completely cover the first driving circuit 14 .
  • the first anode layer 41 may also be referred to as a first electrode of the first light emitting device 131
  • the first cathode layer 43 may also be referred to as a second electrode of the first light emitting device 131
  • the second anode layer 44 can also be called the first electrode of the third light emitting device 15
  • the second cathode layer 46 can also be called the second electrode of the third light emitting device 15 .
  • the first light-emitting device 131 may include one or more of green light-emitting devices, blue light-emitting devices, red light-emitting devices, and white light-emitting devices, which are not discussed in this embodiment of the present disclosure. limited.
  • the built-in light emitting devices 13 in the first display area 11 except the first light emitting device 131 may all be the second light emitting devices 132 .
  • the second light emitting device 132 may include one or more of a green light emitting device, a blue light emitting device, a red light emitting device and a white light emitting device, which are not limited in this embodiment of the present disclosure.
  • the first light emitting device 131 includes a green light emitting device and/or a blue light emitting device.
  • the first light emitting device 131 may include a green light emitting device, or a blue light emitting device, or a green light emitting device and a blue light emitting device.
  • the first light emitting device 131 includes a red light emitting device and/or a blue light emitting device.
  • the first light emitting device 131 may include a red light emitting device, or a blue light emitting device, or a red light emitting device and a blue light emitting device.
  • the first light emitting device 131 includes a green light emitting device and/or a red light emitting device.
  • the first light emitting device 131 may include a green light emitting device, or a red light emitting device, or a red light emitting device and a green light emitting device.
  • the uniformity of the display image can be further improved.
  • the anode area in the blue light emitting device is relatively large, when the first light emitting device 131 includes a blue light emitting device, the influence of the first driving circuit 14 connected to the blue light emitting device on the aperture ratio can be reduced, which helps to improve the first display. Transmittance in zone 11.
  • the number of first light emitting devices 131 may be greater than or equal to the number of second light emitting devices 132 .
  • the ratio between the number of first light-emitting devices 131 and the number of second light-emitting devices 132 can be greater than or equal to 1, that is, the built-in light-emitting devices that set the driving circuit in the first display area 11
  • the ratio of the device 13 is relatively high, which can further reduce the number of leads and improve the picture quality.
  • the ratio between the number of the first light-emitting devices 131 and the number of the second light-emitting devices 132 can be, for example, 2:1, 3:1, etc. The requirements are set, which is not limited in the embodiments of the present disclosure.
  • all may be first light emitting devices 131 ; all may be second light emitting devices 132 ;
  • the number of first light emitting devices 131 may be greater than or equal to the number of second light emitting devices 132, which can further reduce the number of leads and improve picture quality.
  • the ratio between the number of first light emitting devices 131 and the number of second light emitting devices 132 can be, for example, 2:1, 3:1, etc., and the specific value can be based on The actual requirements are set, which is not limited in the embodiments of the present disclosure.
  • the second light emitting device 132 includes a green light emitting device, a blue light emitting device and a red light emitting device
  • the lead 17 connecting the green light emitting device and the second driving circuit 161 is a first lead, connected to The lead 17 connecting the red light emitting device and the second driving circuit 161 is the second lead
  • the lead 17 connecting the blue light emitting device and the second driving circuit 161 is the third lead.
  • a green light emitting device may be referred to as a first color light emitting device
  • a red light emitting device may be referred to as a second color light emitting device
  • a blue light emitting device may be referred to as a third color light emitting device.
  • the light-emitting device of the first color is configured to emit light of the first color
  • the light-emitting device of the second color is configured to emit light of the second color
  • the light-emitting device of the third color is configured to emit light of the third color.
  • the first color light is green light
  • the second color light is red light
  • the third color light is blue light, but not limited thereto, and can be selected according to needs.
  • the first color light emitting device, the second color light emitting device and the third color light emitting device are configured to emit light of different colors.
  • the area of the first lead may be smaller than or equal to the area of the second lead, and the area of the second lead may be smaller than or equal to the area of the third lead.
  • the green light emitting device, the red light emitting device and the blue light emitting device are less sensitive to the coupling capacitance caused by the lead 17, by setting the area of the first lead to be smaller than or equal to the area of the second lead, the area of the second lead is smaller than Or equal to the area of the third lead, can reduce the influence of the coupling capacitance as a whole, further improve the display quality of the image, and improve the uniformity of the display image.
  • the length of the first lead can be set to be less than or equal to the length of the second lead, and the length of the second lead can be set to be less than or equal to the third lead. The length of the lead.
  • Fig. 7 is a schematic cross-sectional structure diagram of a signal line in a display panel provided by an embodiment of the present disclosure.
  • the signal line 18 connected to the first drive circuit 14 includes a first line segment 181 and a second line segment 182 , the first line segment 181 and the second line segment 182 The line segments 182 are connected, the first line segment 181 is located in the first display area 11 , and the second line segment 182 is located in the second display area 12 .
  • the first line segment 181 and the second line segment 182 may be disposed on different film layers, for example, an insulating layer may be disposed between the two, and the first line segment 181 and the second line segment 182 may be connected through vias disposed in the insulating layer, As shown in Figure 7.
  • the first line segment 181 and the second line segment 182 may also be disposed on the same film layer, or connected by overlapping, which is not limited in this embodiment of the present disclosure.
  • the signal line 18 can be, for example, a gate signal line (such as the first scanning signal line Ga1 or the second scanning signal line Ga2 in FIG. 8 ), an emission control signal line (such as the first emission control signal line EM1 or the second scanning signal line in FIG. Two light emission control signal lines EM2), data signal lines (such as the data line Vd in Figure 8), reset control signal lines (such as the first reset control signal line Rst1 or the second reset control signal line Rst2 in Figure 8), power supply Signal line, reset signal line, etc.
  • a gate signal line such as the first scanning signal line Ga1 or the second scanning signal line Ga2 in FIG. 8
  • an emission control signal line such as the first emission control signal line EM1 or the second scanning signal line in FIG. Two light emission control signal lines EM2
  • data signal lines such as the data line Vd in Figure 8
  • reset control signal lines such as the first reset control signal line Rst1 or the second reset control signal line Rst2 in Figure 8
  • power supply Signal line reset signal line, etc.
  • the material of the first line segment 181 may be a transparent conductive material.
  • the material of the second line segment 182 may be a metal material.
  • the transparent conductive material can be metal, metal oxide, inorganic material, organic material or composite material, etc.
  • the transparent conductive material may be indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), carbon nanotubes, nano silver or graphene, etc., which are not limited in the embodiments of the present disclosure. .
  • the material of the lead 17 can be ITO.
  • the material of the first line segment 181 can be ITO or nano-silver. Since the square resistance of nano silver is low and the transmittance is high, when nano silver is used as the material of the first line segment 181, the resistance of the first line segment 181 can be reduced, and the transmittance of the first display area 11 can be improved. Rate.
  • the leads 17 and the first line segment 181 are respectively located in different film layers.
  • the wiring space can be increased, thereby helping to realize the first display area 11 with high pixel density.
  • an insulating material may be disposed between the lead wire 17 and the first line segment 181 .
  • FIG. 7 takes an example where the film layer where the lead wire 17 is located is closer to the substrate. However, it is not limited thereto. In other implementations, the film layer where the first line segment 181 is located may be closer to the film layer where the lead wire 17 is located. Substrate substrate.
  • the pixel density of the first display area 11 is less than or equal to the pixel density of the second display area 12.
  • pixel density refers to the number of light emitting devices disposed per inch.
  • the circuit structures of the first driving circuit 14 , the second driving circuit 161 and the third driving circuit 162 may be the same or different, which is not limited in the embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure.
  • at least one of the first driving circuit 14 , the second driving circuit 161 and the third driving circuit 162 is a pixel circuit 221 as shown in FIG. 8 .
  • the light emitting device 220 in FIG. 8 may be the first light emitting device 131 , the second light emitting device 132 or the third light emitting device 15 .
  • the light emitting device 220 may be an organic light emitting device, but is not limited thereto.
  • the pixel circuit 221 includes a first light emission control circuit 223 , a second light emission control circuit 224 and a driving module 222 .
  • the driving module 222 includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current for driving the light emitting device 220 to emit light.
  • the first lighting control circuit 223 is connected to the first terminal of the driving module 222 and the first voltage terminal VDD, and is configured to enable or disable the connection between the driving module 222 and the first voltage terminal VDD
  • the second The lighting control circuit 224 is electrically connected to the second terminal of the driving module 222 and the first electrode of the light emitting device 220 , and is configured to realize the connection between the driving module 222 and the light emitting device 220 to be turned on or off.
  • the pixel circuit 221 further includes a data writing circuit 226 , a storage circuit 227 , a threshold compensation circuit 228 and a reset circuit 229 .
  • the data writing circuit 226 is electrically connected to the first end of the driving module 222, and is configured to write the data signal into the storage circuit 227 under the control of the scan signal; the storage circuit 227 is connected to the control terminal of the driving module 222 and the first voltage respectively.
  • the terminal VDD is electrically connected, and is configured to store data signals;
  • the threshold compensation circuit 228 is electrically connected to the control terminal and the second end of the driving module 222, and is configured to perform threshold compensation on the driving module 222;
  • the reset circuit 229 and the driving module 222 The control terminal of the drive module 222 is electrically connected to the first electrode of the light emitting device 220, and is configured to reset the control terminal of the driving module 222 and the first electrode of the light emitting device 220 under the control of the reset control signal.
  • the driving module 222 includes a driving transistor T1
  • the control terminal of the driving module 222 includes the gate of the driving transistor T1
  • the first end of the driving module 222 includes the first pole of the driving transistor T1
  • the driving module 222 The second end includes a second pole of the driving transistor T1.
  • the data writing circuit 226 includes a data writing transistor T2
  • the storage circuit 227 includes a capacitor C
  • the threshold compensation circuit 228 includes a threshold compensation transistor T3
  • the first light emission control circuit 223 includes a first light emission control transistor T4.
  • the second light emission control circuit 224 includes a second light emission control transistor T5
  • the reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7
  • the reset control signal may include a first reset control signal and a second reset control signal.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1, and the second pole of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data signal
  • the gate of the data writing transistor T2 is configured to be electrically connected to the first scanning signal line Ga1 to receive the scanning signal; the first electrode Cb of the capacitor C is electrically connected to the first power supply terminal VDD, and the second electrode Ca of the capacitor C is electrically connected to the first power supply terminal VDD.
  • the gate of the driving transistor T1 is electrically connected; the first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the driving transistor T1, the second pole of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the threshold compensation transistor T3
  • the gate of the first reset transistor T6 is configured to be electrically connected to the second scanning signal line Ga2 to receive the compensation control signal; the first pole of the first reset transistor T6 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal.
  • the second pole of a reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the first reset control signal line Rst1 to receive the first reset control signal; the second reset The first pole of the transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive the second reset signal, the second pole of the second reset transistor T7 is electrically connected to the first electrode of the light emitting device 220, and the second reset transistor T7
  • the gate of the first light emission control transistor T4 is electrically connected to the first power supply terminal VDD, and the first electrode of the first light emission control transistor T4 is electrically connected to the second reset control signal line Rst2 to receive the second reset control signal.
  • the second pole is electrically connected to the first pole of the driving transistor T1, and the gate of the first light emission control transistor T4 is configured to be electrically connected to the first light emission control signal line EM1 to receive the first light emission control signal; the second light emission control transistor T5
  • the first pole of the second light emission control transistor T1 is electrically connected to the second pole of the driving transistor T1
  • the second pole of the second light emission control transistor T5 is electrically connected to the first electrode of the light emitting device 220
  • the gate of the second light emission control transistor T5 is configured to be connected to the first electrode of the second light emission control transistor T5.
  • the two light emission control signal lines EM2 are electrically connected to receive the second light emission control signal
  • the second electrode of the light emitting device 220 is electrically connected to the second power supply terminal VSS.
  • the light emitting device 220 includes an organic light emitting element, but is not limited thereto, and the type of the light emitting device 220 can be determined according to needs.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power supply terminal VSS can be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the scan signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 can be electrically connected to the same signal line, such as the first scan signal line Ga1 to receive the same signal (for example, a scan signal), at this time, the display panel (display substrate) may not be provided with the second scan signal line Ga2, reducing the number of signal lines.
  • the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1, and the threshold The gate of the compensation transistor T3 is electrically connected to the second scanning signal line Ga2, and the signals transmitted by the first scanning signal line Ga1 and the second scanning signal line Ga2 are the same.
  • the scanning signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the first light emission control signal and the second light emission control signal may be the same, that is, the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may be electrically connected to the same signal Lines, for example, are electrically connected to the first light emission control signal line EM1 to receive the same signal (for example, the first light emission control signal), at this time, the display panel (display substrate) may not be provided with the second light emission control signal line EM2, Reduce the number of signal lines.
  • the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may also be electrically connected to different signal lines, that is, the gate of the first light emission control transistor T4 is electrically connected to the first light emission control transistor T5.
  • the control signal line EM1 the gate of the second light emission control transistor T5 is electrically connected to the second light emission control signal line EM2, and the signals transmitted by the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same.
  • first light emission control transistor T4 and the second light emission control transistor T5 are transistors of different types, for example, the first light emission control transistor T4 is a P-type transistor, and the second light emission control transistor T5 is an N-type transistor.
  • the first light emission control signal and the second light emission control signal may also be different, which is not limited in this embodiment of the present disclosure.
  • the first reset control signal and the second reset control signal can be the same, that is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 can be electrically connected to the same signal line, such as the first reset control signal Line Rst1 to receive the same signal (for example, the first reset control signal), at this time, the display panel (display substrate) may not be provided with the second reset control signal line Rst2, reducing the number of signal lines.
  • the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1 , the gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the signals transmitted by the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same. It should be noted that the first reset control signal and the second reset control signal may also be different.
  • the second reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the first scan signal line Ga1 to receive the scan signal as the second reset control signal.
  • the first pole of the first reset transistor T6 and the first pole of the second reset transistor T7 are respectively connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2, and the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be a DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same, for example, the first pole of the first reset transistor T6 and the first pole of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide the first reset signal and the second reset signal to drive the gate of the transistor T1 and the light-emitting device 220. It only needs to reset the first electrode, which is not limited in the embodiments of the present disclosure.
  • the specific structures of circuits such as 226 , storage circuit 227 , threshold compensation circuit 228 , and reset circuit 229 may be set according to actual application requirements, and are not specifically limited in this embodiment of the present disclosure.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to illustrate the details of the present disclosure in detail.
  • the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6 and the second Both the reset transistor T7 and the like can be P-type transistors.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can use N-type transistors (for example, N-type MOS transistors) to realize the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, etc. .
  • the source and drain of the transistor can be symmetrical in structure, so there can be no difference in the physical structure of the source and drain.
  • the transistors except for the gate as the control electrode, it is directly described that one of them is the first electrode and the other is the second electrode, so the first electrode of all or part of the transistors in the embodiments of the present disclosure
  • the first and second poles are interchangeable as desired.
  • the pixel circuit of the sub-pixel can also be a structure including other numbers of transistors , such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, which is not limited in embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of a display panel adopting a fully built-in solution.
  • FIG. 10 is a schematic diagram of a display panel adopting an all-exterior solution.
  • FIG. 11 is a schematic diagram of lead wires in a display panel adopting an all-exterior solution.
  • Fig. 12 is a schematic diagram of a display panel using a compression scheme and a built-in scheme provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the light emitting device 600 includes a first color light emitting device 601 , a second color light emitting device 602 and a third color light emitting device 603 .
  • the pixel circuits PXC connected to the light emitting devices 600 in the first display area 11 are all built-in, that is, the pixel circuits PXC connected to the light emitting devices 600 in the first display area 11 are all located in the first display area 11.
  • Display area 11 The all-built-in solution does not need to set the lead wires connecting the light-emitting device 600 and the pixel circuit PXC, and can achieve a large aperture, but the transmittance of the first display area 11 is low, for example, the transmittance is 12%, and it has glare diffraction. question.
  • the pixel circuits PXC connected to the light-emitting devices 600 in the first display area 11 are all externally placed, that is, the pixel circuits PXC connected to the light-emitting devices 600 in the first display area 11 are all located in the first display area 11.
  • Two display areas 12 The light emitting device 600 and the pixel circuit PXC in the first display area 11 are arranged separately.
  • the light-emitting device 600 in the first display area 11 is connected to the pixel circuit PXC located in the second display area 12 through lead wires 17.
  • the number of lead wires 17 is relatively large, and the length of the lead wires 17 is relatively long.
  • the load on the leads is relatively large, and the lengths of the leads 17 vary greatly, which easily causes the problem of non-uniform display.
  • FIG. 11 shows a schematic diagram of some leads in the display panel. As shown in FIG. 11 , the lengths of the lead wires 17 are large, and the lengths of the lead wires 17 vary greatly.
  • the display panel provided by the embodiment of the present disclosure adopts a combination of a compression scheme and a built-in scheme, so that the first display area 11 can have a larger aperture and lower glare diffraction,
  • the number of lead wires 17 in the display panel shown in FIG. 12 is about half less than the number of lead wires 17 in the display panel shown in FIG. 10 or FIG. Therefore, the length of the lead wires 17 is relatively small, and the length difference of the lead wires 17 is small, which is beneficial to improve display uniformity.
  • the first light emitting device 131 includes a first color light emitting device 601
  • the second light emitting device 132 includes a second color light emitting device 602 and a third color light emitting device 603, and the first color light emits light
  • the device 601 , the second color light emitting device 602 and the third color light emitting device 603 are configured to emit light of different colors.
  • the first light emitting device 131 includes a green light emitting device
  • the second light emitting device 132 includes a red light emitting device and a blue light emitting device.
  • G in FIG. 13 represents a green light emitting device (the first color light emitting device 601)
  • R represents a red light emitting device (the second color light emitting device 602)
  • B represents a blue light emitting device (the third color light emitting device 603) .
  • the leads 17 include a first conductive wire 1701 and a second conductive wire 1702, the first conductive wire 1701 is connected to the light emitting device 602 of the second color, and the second conductive wire 1702 is connected to the light emitting device of the third color. 603 connected.
  • the first conductive line 1701 is located on the first transparent conductive layer LYa, and the second conductive line 1702 is located on the second transparent conductive layer LYb.
  • the first conductive lines 1701 and the second conductive lines 1702 are alternately arranged, but not limited thereto.
  • the green light emitting device (first color light emitting device 601) is built in, that is, located in the first display area 11, the green light emitting device (first color light emitting device 601) is not provided Lead 17.
  • the capacitance of the leads varies greatly. Due to the different lengths of the lead wires connecting the various light emitting devices located in the first display area 11, the capacitance difference of the light emitting devices emitting light of different colors changes differently. Compared with the capacitance difference between the lead wires connected to the red light emitting device and the capacitance difference of the lead wires connected to the blue light emitting device, the capacitance difference of the lead wires connected to the green light emitting device is larger. Because the capacitance difference of the leads connected to the green light emitting device is relatively large, the luminous time of the green light emitting device is reduced, so that the brightness of the display panel is different, resulting in poor display.
  • the defect degree of the green light emitting device is greater than that of the red light emitting device, and the defect degree of the red light emitting device is greater than that of the blue light emitting device.
  • the driving current for driving the blue light emitting device is greater than the driving current for driving the red light emitting device, and the driving current for driving the red light emitting device is greater than the driving current for driving the green light emitting device.
  • the second driving circuit 161 is connected to the second light-emitting device 132 through wires 17 , and the area where the second driving circuit 161 is disposed can be called an auxiliary area 12 a (as shown in FIG. 14 ).
  • an auxiliary area 12 a (as shown in FIG. 14 )
  • a dummy pixel circuit DPXC not connected to the built-in light emitting device 13 and not connected to the third light emitting device 15 can be provided.
  • the scheme of combining external and compression is illustrated.
  • part of them is external to achieve high transparency and compatibility with display design.
  • Some display panels for example, display panels with distance sensors need to have: large aperture, high transmittance, and less glare and diffraction problems.
  • the pure external (full external) solution cannot solve the problem of large aperture in the first display area, reducing the number of film layers and the number of reticles.
  • a large aperture is realized, which not only meets the requirements of transmittance but also meets the requirements of diffraction.
  • the number of lead wires required is relatively large.
  • 40 lead wires may need to be provided, thus three transparent conductive layers need to be provided.
  • 20 lead wires need to be provided.
  • two transparent conductive layers are provided.
  • the lead wire arrangement is then completed, and the length of the lead wire is reduced by half.
  • the pixel circuit connected to the green light emitting device is built in (placed in the first display area 11). area 11), and the pixel circuit connected to the red light emitting device and the blue light emitting device is externally placed (placed in the second display area 12), and the red sub-pixel and the blue sub-pixel are externally placed, that is, the pixel of the green sub-pixel Circuits are built in to improve display uniformity.
  • FIG. 15 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the size of the light-emitting device 600 located in the first display area 11 is smaller than the size of the light-emitting device 600 located in the second display area 12, so as to improve the quality of the first display area 11. the transmittance.
  • the transmittance of the first display area 11 can also be improved.
  • a region between adjacent light emitting devices 600 includes a light-transmitting region R0. That is, in the first display region 11 , the pixel circuit, the light-transmitting region R0 is located in the region between adjacent light-emitting devices 600 .
  • FIG. 15 shows the light emitting device 600 with a first electrode E1 of the light emitting device.
  • a closed line frame within the first electrode E1 represents the light emitting region EMR of the light emitting device 600, and the light emitting region EMR corresponds to the opening OPN of the pixel definition layer.
  • FIG. 16 is a layout diagram of a pixel circuit located in a second display area in a display panel provided by an embodiment of the present disclosure.
  • FIG. 17 is a layout diagram of a pixel circuit located in a first display area in a display panel provided by an embodiment of the present disclosure.
  • FIG. 18 is a layout diagram of pixel circuits located in the first display area and the second display area in the display panel provided by an embodiment of the present disclosure.
  • 16 to 18 show the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, the second light emission control transistor T5 included in the pixel circuit PXC.
  • the transistor T7, the first pole Cb of the capacitor C, and the second pole Ca of the capacitor C are reset.
  • the first scanning signal line Ga1 and the second scanning signal line Ga2 are the same signal line, that is, both are the gate signal line GA; the first reset control signal line Rst1 and the second reset control signal line Rst1
  • the signal line Rst2 is the same signal line, that is, both the reset control signal line RST; the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same signal line, that is, the same light emission control signal line EML.
  • the display panel further includes a plurality of signal lines connected to the pixel circuit PXC (first driving circuit 14 ), at least one signal line in the plurality of signal lines is arranged in segments.
  • FIG. 18 is illustrated by taking the first power line Vdd, the light emission control signal line EML, the reset control signal line RST, and the reset signal line INT2 all adopting segmented arrangement as an example.
  • the reset signal line INT1 is connected to the first reset power supply terminal Vinit1, and the reset signal line INT2 is connected to the second reset power supply terminal Vinit2.
  • the reset signal line INT2 is connected to the first reset power supply terminal Vinit1 or the second reset power supply terminal Vinit2 .
  • the emission control signal line EML includes an emission control signal portion EMLa, an emission control signal portion EMLb, and an emission control signal portion EMLc.
  • the light emission control signal part EMLa is located in the second display area 12
  • the light emission control signal part EMLb and the light emission control signal part EMLc are located in the first display area
  • the adjacent light emission control signal parts EMLc are connected through the light emission control signal part EMLb
  • the light emission control signal part EMLa It is connected to the adjacent emission control signal portion EMLc via the emission control signal portion EMLb.
  • the reset control signal line RST includes a reset control signal portion RSTa, a reset control signal portion RSTb, and a reset control signal portion RSTc.
  • the reset control signal part RSTa is located in the second display area 12
  • the reset control signal part RSTb and the reset control signal part RSTc are located in the first display area, and the adjacent reset control signal parts RSTc are connected through the reset control signal part RSTb, and the reset control signal part RSTa It is connected to the adjacent reset control signal part RSTc through the reset control signal part RSTb.
  • the reset signal line INT2 includes a reset signal portion INTa, a reset signal portion INTb, and a reset signal portion INTc.
  • the reset signal part INTa is located in the second display area 12
  • the reset signal part INTb and the reset signal part INTc are located in the first display area, and the adjacent reset signal part INTc is connected through the reset signal part INTb, and the reset signal part INTa and the reset signal part INTa adjacent thereto are connected.
  • the signal unit INTc is connected through the reset signal unit INTb.
  • the segmented signal line includes a plurality of signal parts located in different layers.
  • the segmented signal line includes a first signal portion and a second signal portion
  • the material of the first signal portion includes transparent conductive metal oxide
  • the material of the second signal portion includes metal .
  • the reset signal portion INTc, the reset control signal portion RSTc, and the light emission control signal portion EMLc can be referred to as the first signal portion P1, the reset signal portion INTa, the reset signal portion INTb, the reset control signal portion RSTa, the reset control signal portion
  • the signal part RSTb, the light emission control signal part EMLa, and the light emission control signal part EMLb may be referred to as a second signal part P2.
  • the first signal part P1 and the second signal part P2 are not limited to the above description, and can be set as required.
  • the first display area 11 includes a driving circuit setting area 1101 and a wiring area 1102 , the first signal part P1 is located in the driving circuit setting area 1101 , and the second signal part P2 is located in the wiring area 1102 .
  • the display panel further includes an emission control signal line EML, a reset control signal line RST, and a reset signal line INT2
  • the pixel circuit PXC includes a driving module 222, an emission control Circuit 223, light emission control circuit 224, and reset circuit 229
  • the pixel circuit PXC includes at least one of the first drive circuit 14, the second drive circuit 161, and the third drive circuit 162
  • the light emission control signal line EML and the light emission control circuit 223 The control terminal is connected to at least one of the control terminals of the light-emitting control circuit 224
  • the reset control signal line RST is connected to the control terminal of the reset circuit 229
  • the reset signal line INT2 is connected to the first pole of the reset circuit 229
  • reset At least one of the control signal line RST and the reset signal line INT2 is arranged in segments in the first display area 11 .
  • the reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7, and the first reset transistor T6 is configured to control the control terminal of the drive module 222 Reset, the second reset transistor T7 is configured to reset the first electrode of the light emitting device 600, and the light emitting device 600 includes at least one of the first light emitting device 131, the second light emitting device 132, and the third light emitting device.
  • the first reset transistor T6 and the second reset transistor T7 share the same reset signal line INT2 to be configured to provide the same reset signal.
  • the light emitting device 600 is the light emitting device 220 in FIG. 8 .
  • FIG. 17 shows the connection electrode CE1 , the connection electrode CE2 , and the connection electrode CE3 .
  • one end of the connection electrode CE1 is connected to the reset signal line INT2
  • the other end of the connection electrode CE1 is connected to the first pole of the second reset transistor T7
  • one end of the connection electrode CE2 is connected to the second pole of the second reset transistor T7.
  • the other end of the connection electrode CE2 is connected to the second electrode of the second light emission control transistor T5.
  • one end of the connecting electrode CE3 is connected to the second electrode of the first reset transistor T6
  • the other end of the connecting electrode CE3 is connected to the gate of the driving transistor T1 .
  • the layout of the second driving circuit 161 and the third driving circuit 162 are the same, and the layout of the first driving circuit 14 is different from that of the second driving circuit 161 or the third driving circuit 162 .
  • the layout of the first driving circuit 14 is adjusted to improve the transmittance of the first display area.
  • FIG. 16 to 18 show the reset signal line INT1 and the reset signal line INT2.
  • the reset signal line INT1 is connected to the first reset power terminal Vinit1
  • the reset signal line INT2 is connected to the second reset power terminal Vinit2.
  • FIG. 16 to FIG. 18 take the reset signal line INT as an example to illustrate the reset signal line INT1 and reset signal line INT2.
  • FIG. 19 is a cross-sectional view along line B1-B2 of FIG. 18 .
  • FIG. 20 is a plan view of the active layer in FIG. 16 .
  • FIG. 21 is a plan view of the first conductive layer in FIG. 16 .
  • FIG. 22 is a plan view of the second conductive layer in FIG. 16 .
  • FIG. 23 is a plan view of the third conductive layer in FIG. 16 .
  • FIG. 24 is a plan view of the fourth conductive layer in FIG. 16 .
  • FIG. 25 is a stacked plan view of the active layer and the first conductive layer in FIG. 16 .
  • FIG. 26 is a stacked plan view of the active layer, the first conductive layer, and the second conductive layer in FIG. 16 .
  • FIG. 20 is a plan view of the active layer in FIG. 16 .
  • FIG. 21 is a plan view of the first conductive layer in FIG. 16 .
  • FIG. 22 is a plan view of the second conductive layer in
  • FIG. 27 is a stacked plan view of the third conductive layer and the fourth conductive layer in FIG. 16 .
  • FIG. 28 is a stacked plan view of via holes in the third conductive layer, the fourth conductive layer and the insulating layer therebetween in FIG. 16 .
  • FIG. 29 is a stacked plan view of the active layer, the third conductive layer, the fourth conductive layer, and the via hole in the insulating layer between the third conductive layer and the fourth conductive layer in FIG. 16 .
  • Figure 30 is the active layer, the third conductive layer, the fourth conductive layer, the via hole VH1 in the insulating layer between the active layer and the third conductive layer in Figure 16, and the via hole VH1 in the third conductive layer and the fourth conductive layer.
  • FIG. 31 is a plan view of an active layer in a first display region of a display panel provided by an embodiment of the present disclosure.
  • FIG. 32 is a plan view of a first conductive layer in a first display region of a display panel provided by an embodiment of the present disclosure.
  • FIG. 33 is a plan view of the second conductive layer in the first display area of the display panel provided by an embodiment of the present disclosure.
  • FIG. 34 is a plan view of a third conductive layer in a first display area of a display panel provided by an embodiment of the present disclosure.
  • FIG. 35 is a plan view of the fourth conductive layer in the first display area of the display panel provided by an embodiment of the present disclosure.
  • FIG. 36 is a plan view of a transparent conductive layer in a first display area of a display panel provided by an embodiment of the present disclosure.
  • 20 and 31 show the active layer LY0.
  • 21 and 32 illustrate the first conductive layer LY1.
  • 22 and 33 illustrate the second conductive layer LY2.
  • 23 and 34 illustrate the third conductive layer LY3.
  • 24 and 35 illustrate the fourth conductive layer LY4.
  • FIG. 36 shows the transparent conductive layer LYx.
  • the display panel includes a base substrate BS, a barrier layer BR is located on the base substrate BS, a buffer layer BF is located on the barrier layer BR, and an active layer LY0 is located on the buffer layer BF.
  • the active layer LY0 includes a channel T7c of the second reset transistor T7, a first pole T71 and a second pole T72 located on both sides of the channel T7c, a channel T5c of the second light emission control transistor T5, And the first pole T51 and the second pole T52 located on both sides of the channel T5c.
  • the insulating layer 801 is located on the active layer LY0
  • the first conductive layer LY1 is located on the insulating layer 801
  • FIG. 19 shows the reset control signal part RSTb, the gate signal line GA, and the light emission control signal part EMLb in the first conductive layer LY1.
  • the insulating layer 802 is located on the first conductive layer LY1
  • the second conductive layer LY2 is located on the insulating layer 802 .
  • FIG. 19 shows the reset signal part INTb in the second conductive layer LY2. As shown in FIG.
  • FIG. 19 shows the connection electrode CE1 and the connection electrode CE2 in the third conductive layer LY3.
  • one end of the connection electrode CE1 is connected to the reset signal part INTb
  • the other end of the connection electrode CE1 is connected to the first pole T71 of the second reset transistor T7
  • one end of the connection electrode CE2 is connected to the first electrode T7 of the second reset transistor T7.
  • the two electrodes T72 are connected, and the other end of the connection electrode CE2 is connected to the second electrode T52 of the second light emission control transistor T5.
  • FIG. 19 shows the connection electrode CE1 and the connection electrode CE2 in the third conductive layer LY3.
  • FIG. 19 shows the connection electrode CE11 and the connection electrode CE12 in the fourth conductive layer LY4. As shown in FIG. 19, the connection electrode CE11 is connected to the connection electrode CE1, and the connection electrode CE12 is connected to the connection electrode CE2. As shown in FIG. 19 , the insulating layer 805 is located on the fourth conductive layer LY4 , and the transparent conductive layer LYx is located on the insulating layer 805 .
  • FIG. 19 shows the reset signal portion INTc and the connection electrode CEx in the transparent conductive layer LYx. The connection electrode CEx is connected to the connection electrode CE12, and the reset signal part INTc is connected to the connection electrode CE11.
  • the insulating layer 804 may include at least one insulating layer.
  • FIG. 19 is illustrated by taking the insulating layer 804 including the passivation layer PVX and the planarization layer PLN as an example.
  • the insulating layer 801 may also be called a gate insulating layer GI1
  • the insulating layer 802 may also be called a gate insulating layer GI2
  • the insulating layer 803 may also be called an interlayer insulating layer ILD.
  • the first conductive layer LY1 includes a reset control signal line RST, a gate signal line GA, a second electrode Ca of a capacitor C, and an emission control signal line EML.
  • the second conductive layer LY2 includes a reset signal line INT2 , a block BK, and a first pole Cb of a capacitor C. As shown in FIG. 22 , the second conductive layer LY2 includes a reset signal line INT2 , a block BK, and a first pole Cb of a capacitor C. As shown in FIG. 22 , the reset signal line INT2 , a block BK, and a first pole Cb of a capacitor C. As shown in FIG.
  • the block BK is connected to the first power line Vdd through the via hole V5.
  • the block BK functions to stabilize the voltage at the intermediate node between the two channels of the threshold compensation transistor T3.
  • the first power line Vdd is connected to the first voltage terminal VDD.
  • the first pole Cb of the capacitor C has an opening Cb0 for connecting the connecting electrode CEd to the second pole Ca of the capacitor C.
  • the third conductive layer LY3 includes a data line Vd, a first power line Vdd, a reset signal line INT1 , a connection electrode CEa, a connection electrode CEb, a connection electrode CEc, and a connection electrode CEd.
  • the fourth conductive layer LY4 includes a connection electrode CEe, a connection electrode CEf, and a shield electrode CEg.
  • Figure 25 shows each transistor, the part of the active layer LY0 covered by the first conductive layer LY1 is the channel of the transistor, the two sides of the channel are respectively the first pole and the second pole of the transistor, and the second pole of the capacitor C Ca also serves as the gate of the driving transistor T1, a part of the gate signal line GA serves as the gate of the data writing transistor T2, a part of the gate signal line GA serves as the gate of the threshold compensation transistor T3, and a part of the light emission control signal line EML As the gate of the first light emission control transistor T4, a part of the light emission control signal line EML is used as the gate of the second light emission control transistor T5, and a part of the reset control signal line RST is used as the gate of the first reset transistor T6. A part of RST serves as the gate of the second reset transistor T7.
  • connection electrode CEe is connected to the connection electrode CEb through the via hole V12
  • the other end of the connection electrode CEe is connected to the connection electrode CEc through the via hole V13
  • the connection electrode CEf Connected to the first power line Vdd through the via hole V15
  • the orthographic projection of the shielding electrode CEg on the base substrate covers the orthographic projection of the connecting electrode CEd on the base substrate, so as to stabilize the voltage on the gate of the driving transistor.
  • connection electrode CEa one end of the connection electrode CEa is connected to the reset signal line INT (reset signal line INT2) through the via hole V1, and the other end of the connection electrode CEa is connected to the second reset transistor T7.
  • One pole is connected through the via hole V2.
  • connection electrode CEb is connected to the second pole of the second reset transistor T7 through the via hole V3 .
  • connection electrode CEc is connected to the second pole of the second light emission control transistor T5 through the via hole V11 .
  • connection electrode CEd is connected to the second pole of the first reset transistor T6 through the via hole V7, and the other end of the connection electrode CEd is connected to the gate of the drive transistor T1 through the via hole V7. Hole V8 is connected.
  • the first power line Vdd is connected to the first pole Cb of the capacitor C through the via hole V9.
  • the first power line Vdd is connected to the first electrode of the first light emitting control transistor T4 through the via hole V10.
  • the data line Vd is connected to the second pole of the data writing transistor T2 through the via hole V6 .
  • the reset signal line INT1 is connected to the first pole of the first reset transistor T6 through the via hole V4 .
  • connection electrode CE01 located on the transparent conductive layer LYx is connected to the connection electrode CEc through the via hole V14 .
  • the reset signal line INT1 and the reset signal line INT2 are located in different layers, for example, the reset signal line INT1 is located in the third conductive layer LY3, and the reset signal line INT2 is located in the second conductive layer.
  • Layer LY2 the reset signal line INT1 is located in the third conductive layer LY3
  • the reset signal line INT2 is located in the second conductive layer.
  • the reset signal line INT1 intersects with the reset signal line INT2 .
  • the reset signal line INT1 is perpendicular to the reset signal line INT2.
  • the via hole VH1 located in the insulating layer between the active layer and the third conductive layer includes via holes V1 to V11, and the via holes located in the insulating layer between the third conductive layer and the fourth conductive layer
  • the hole VH2 includes a via V12, a via V13, and a via V15.
  • the insulating layer 801, the insulating layer 802, the insulating layer 803, the insulating layer 804, and the insulating layer 805 can all be made of insulating materials.
  • the base substrate may be a flexible base substrate, and the material includes polyimide, but is not limited thereto.
  • FIG. 18 shows the pixel circuits of some sub-pixels, and the rest of the pixel circuits can refer to the structure of the pixel circuits shown in FIG. 18 according to their positions.
  • 31 to 36 show plan views of a single film layer located in the first display area 11 in the display panel provided by the embodiments of the present disclosure.
  • the structure of the pixel circuit PXC (first driving circuit 14 ) located in the first display area 11 will be described below with reference to FIGS. 17 , 18 , and 31 to 36 .
  • 31 to 36 show three pixel circuits PXC (first drive circuit 14 ).
  • FIG. 31 shows the active layer LY0.
  • the portion of the active layer LY0 shown in FIG. 20 located in the second display area has a different structure from the portion of the active layer LY0 shown in FIG. 31 located in the first display area. Therefore, referring to FIGS. 16 and 17 , the structure of the first drive circuit 14 is different from that of the external drive circuit 16 .
  • FIG. 17 shows vias Va to vias Vk.
  • connection electrode CE1 is connected to the reset signal line INT2 through the via hole Va, and the other end of the connection electrode CE1 is connected to the first pole of the second reset transistor T7 through the via hole Vb.
  • One end of the electrode CE2 is connected to the second pole of the second reset transistor T7 through the via hole Vc, and the other end of the connection electrode CE2 is connected to the second pole of the second light emission control transistor T5 through the via hole Vd.
  • connection electrode CE3 is connected to the second pole of the first reset transistor T6 through the via hole Ve, and the other end of the connection electrode CE3 is connected to the gate of the driving transistor T1 through the via hole Vf. .
  • the first power line Vdd is connected to the first pole Cb of the capacitor C through the via hole Vg.
  • connection electrode CE4 is connected to the first pole of the first light emission control transistor T4 through the via hole Vh, and the other end of the connection electrode CE4 is connected to the first power line Vdd through the via hole Vi. .
  • the data line Vd is connected to the second pole of the data writing transistor T2 through the via hole Vj.
  • the first power line Vdd includes: connecting electrode CE10 (power supply part Vddc), power supply part Vdda, and power supply part Vddb, and connecting electrode CE10 (power supply part Vddc) and power supply part Vdda pass through The via hole Vk is connected, and the connection electrode CE10 (power supply part Vddc) is connected to the power supply part Vddb through the via hole Vi.
  • the first power line Vdd is made of different materials located in different layers, which is beneficial to improve the transmittance of the first display area. Certainly, in other embodiments, the first power line Vdd may not be arranged in segments.
  • the reset signal part INTc is connected to the reset signal part INTb through the via hole Vaa.
  • FIG. 34 also shows connection electrode CE5 , connection electrode CE6 , connection electrode CE7 , connection electrode CE8 , and connection electrode CE9 .
  • the connection electrodes CE5 , CE6 , CE7 , CE8 , and CE9 are all used as intermediate elements for connecting with corresponding elements in the fourth conductive layer LY4 .
  • FIG. 35 also shows connection electrodes CE11 , connection electrodes CE12 , connection electrodes CE15 , connection electrodes CE16 , connection electrodes CE17 , connection electrodes CE18 , and connection electrodes CE19 .
  • connection electrode CE11 is connected to the connection electrode CE1, for example, connected to the upper end of the connection electrode CE1; the connection electrode CE12 is connected to the connection electrode CE2, for example, connected to the lower end of the connection electrode CE2; CE15 is connected to connection electrode CE5, connection electrode CE16 is connected to connection electrode CE6, connection electrode CE17 is connected to connection electrode CE7, connection electrode CE18 is connected to connection electrode CE8, and connection electrode CE19 is connected to connection electrode CE9.
  • the elements located in the fourth conductive layer LY4 and the elements located in the third conductive layer LY3 are connected through vias penetrating the insulating layer between the third conductive layer LY3 and the fourth conductive layer LY4 .
  • the reset control signal part RSTb is connected to the connection electrode CE18 through a via hole
  • the connection electrode CE18 is connected to the connection electrode CE8 through a via hole
  • the connection electrode CE8 is connected to the reset control signal part RSTc through a via hole.
  • Both the connecting electrode CE18 and the connecting electrode CE8 serve as intermediate connecting pieces.
  • This arrangement enables the reset control signal line to include at least two materials with different materials, so as to improve the transmittance of the first display area.
  • the reset control signal lines may also be formed of the same material on the same layer, instead of being formed in a segmented manner.
  • the connection electrode CE6 and the connection electrode CE16 serve as an intermediate connection member at the other end of the reset control signal portion RSTb, which will not be repeated here.
  • the reset signal part INTb is connected to the connection electrode CE1 through the via hole
  • the connection electrode CE1 is connected to the connection electrode CE11 through the via hole
  • the connection electrode CE11 is connected to the reset signal part INTc through the via hole.
  • Both the connecting electrode CE1 and the connecting electrode CE11 serve as intermediate connecting pieces.
  • This arrangement enables the reset control signal line to include at least two materials with different materials, so as to improve the transmittance of the first display area.
  • the reset signal line can also be formed of the same material on the same layer, instead of being formed in a segmented manner.
  • the connection electrode CE7 and the connection electrode CE17 serve as an intermediate connection member at the other end of the reset signal portion INTb, which will not be repeated here.
  • the light emission control signal portion EMLb is connected to the connection electrode CE9 through a via hole
  • the connection electrode CE9 is connected to the connection electrode CE19 through a via hole
  • the connection electrode CE19 is connected to the light emission control signal portion EMLc through a via hole.
  • Both the connecting electrode CE9 and the connecting electrode CE19 serve as intermediate connecting pieces.
  • This arrangement enables the reset control signal line to include at least two materials with different materials, so as to improve the transmittance of the first display area.
  • the reset signal line can also be formed of the same material on the same layer, instead of being formed in a segmented manner.
  • the connection electrode CE5 and the connection electrode CE15 are used as the intermediate connection member of the other end of the light emission control signal part EMLb, which will not be repeated here.
  • connection electrode CE2 is connected to the connection electrode CE12 through the via hole, and the connection electrode CE12 is connected to the connection electrode CE20 through the via hole.
  • the connection electrode CE20 may be connected to the first electrode of the light emitting device.
  • the transparent conductive layer where each signal line is located can be compared to the lead wire.
  • the transparent conductive layer where 17 is located is closer to the base substrate.
  • the control lines of the second reset transistor T7 , the data writing transistor T2 and the threshold compensation transistor T3 are gate signal lines GA.
  • the gates of the second reset transistor T7, the data writing transistor T2, and the threshold compensation transistor T3 are all connected to the gate signal line GA.
  • the gates of the first reset transistor T6 and the gates of the second reset transistor T7 are not connected, and signals can be input separately.
  • the control lines of the first reset transistor T6 and the second reset transistor T7 are reset control signal lines RST. That is, the gate of the first reset transistor T6 is connected to the gate of the second reset transistor T7.
  • the reset signal line INT2 extends from the second display area 12 to the first display area 11 and serves as a reset signal for the first reset transistor T6 and the second reset transistor T7 of the pixel circuit located in the first display area 11 Wire. That is, the first reset transistor T6 and the second reset transistor T7 of the pixel circuit located in the first display area 11 share the same reset signal line, so as to be configured to provide the same reset signal.
  • the same reset signal line can provide the same reset signal.
  • the same reset signal line can be arranged in sections, and the sections located in different layers are connected through via holes.
  • a pixel circuit located in the second display area 12 has two reset signal lines (reset signal line INT2 and reset signal line INT1), and the reset signal line INT2 extending along the first direction X extends from the second
  • the display area 12 extends to the first display area 11 and serves as a reset signal line for the first reset transistor T6 and the second reset transistor T7 of the pixel circuit located in the first display area 11 .
  • FIG. 37A is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 37B is a layout diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 38 is a plan view of an active layer LY0 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 39 is a plan view of a first conductive layer LY1 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 40 is a plan view of a second conductive layer LY2 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 41 is a plan view of a third conductive layer LY3 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 42 is a plan view of a fourth conductive layer LY4 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 43 is a plan view of a transparent conductive layer LYa in a display panel provided by an embodiment of the present disclosure.
  • FIG. 44 is a plan view of a transparent conductive layer LYb in a display panel provided by an embodiment of the present disclosure.
  • FIG. 45 is a stacked plan view of an active layer LY0 and a first conductive layer LY1 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 46 is a stacked plan view of an active layer LY0 , a first conductive layer LY1 , and a second conductive layer LY2 in a display panel provided by an embodiment of the present disclosure.
  • FIG. 47 is a stacked plan view of the active layer LY0 , the first conductive layer LY1 , the second conductive layer LY2 , and the third conductive layer LY3 in the display panel provided by an embodiment of the present disclosure.
  • FIG. 48 is a stacked plan view of the active layer LY0 , the first conductive layer LY1 , the second conductive layer LY2 , the third conductive layer LY3 , and the fourth conductive layer LY4 in the display panel provided by an embodiment of the present disclosure.
  • the fourth conductive layer LY4 is a stack of the active layer LY0, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, the fourth conductive layer LY4, and the transparent conductive layer LYa in the display panel provided by the embodiment of the present disclosure. floor plan.
  • FIG. 37B is an example of an active layer LY0, a first conductive layer LY1, a second conductive layer LY2, a third conductive layer LY3, a fourth conductive layer LY4, a transparent conductive layer LYa, and a display panel provided by an embodiment of the present disclosure.
  • a stacked plan view of the bright conductive layer LYb. 49 is a stacked plan view of the active layer LY0, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, the fourth conductive layer LY4, and the transparent conductive layer LYa in FIG. 37B.
  • the display panel includes a first driving circuit 14 , a first light emitting device 131 connected to the first driving circuit 14 , and a second light emitting device 132 .
  • FIG. 37A shows the first electrode E1 of the light emitting device with an oval dotted line frame, and the first electrode E1 represents the light emitting device.
  • the shape of the first electrode E1 is not limited to what is shown in the figure, and the size of the first electrode E1 is not limited to what is shown in the figure, and can be determined according to requirements.
  • FIG. 37A shows a part of the first display area 11 .
  • FIG. 37A shows that a region between adjacent light emitting devices includes a light-transmitting region R0.
  • FIG. 37B is a layout diagram of the pixel circuit in FIG. 37A. Refer to FIG. 8 for the pixel circuit diagram shown in FIG. 37B .
  • FIG. 38 shows the active layer LY0.
  • FIG. 39 shows the first conductive layer LY1.
  • FIG. 40 shows the second conductive layer LY2.
  • FIG. 41 shows the third conductive layer LY3.
  • FIG. 42 shows the fourth conductive layer LY4.
  • FIG. 43 shows the transparent conductive layer LYa.
  • FIG. 44 shows the transparent conductive layer LYb.
  • connection between components located in different layers in the active layer LY0 , the first conductive layer LY1 , and the second conductive layer LY2 is realized through components located in the third conductive layer LY3 .
  • Components in the fourth conductive layer LY4 and components in the third conductive layer LY3 are connected through via holes penetrating the insulating layer between the third conductive layer LY3 and the fourth conductive layer LY4 .
  • Components in the transparent conductive layer LYa and components in the fourth conductive layer LY4 are connected through via holes penetrating the insulating layer between the transparent conductive layer LYa and the fourth conductive layer LY4 .
  • Components in the transparent conductive layer LYa and components in the transparent conductive layer LYb are connected through via holes penetrating the insulating layer between the transparent conductive layer LYa and the transparent conductive layer LYb.
  • the first conductive layer LY1 includes a reset control signal line RST (reset control signal line RST1 and reset control signal line RST2), a gate signal line GA, a second electrode Ca of a capacitor C, and a light emission control signal line. EML.
  • the reset control signal line RST is connected to the gate signal line GA.
  • the second conductive layer LY2 includes a reset signal line INT1 , a reset signal line INT2 , a block BK, and a first pole Cb of a capacitor C.
  • a reset signal line INT1 As shown in FIG. 40 , the second conductive layer LY2 includes a reset signal line INT1 , a reset signal line INT2 , a block BK, and a first pole Cb of a capacitor C.
  • Both the reset signal line INT1 and the reset signal line INT2 may be referred to as a reset signal line INT.
  • the first pole Cb of the capacitor C has an opening Cb0.
  • the block BK is connected to the first power line Vdd through a via hole.
  • the block BK functions to stabilize the voltage at the intermediate node between the two channels of the threshold compensation transistor T3.
  • the first power line Vdd is connected to the first voltage terminal VDD.
  • the first pole Cb of the capacitor C has an opening Cb0 for connecting the connecting electrode EC1 to the second pole Ca of the capacitor C.
  • the third conductive layer LY3 includes signal lines SL1 , signal lines SL2 , connection electrodes EC1 , connection electrodes EC2 , connection electrodes EC3 , connection electrodes EC4 , connection electrodes EC5 , connection electrodes EC6 , and connection electrodes EC7 .
  • the fourth conductive layer LY4 includes a data line Vd, a first power line Vdd, and a connecting electrode ECO.
  • the orthographic projection of the first power line Vdd on the base substrate and the orthographic projection of the connecting electrode EC1 on the substrate substrate overlap to stabilize the gate of the driving transistor. voltage on the pole.
  • FIG. 45 shows individual transistors.
  • FIG. 45 shows a drive transistor T1, a data write transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7.
  • the part of the active layer LY0 covered by the first conductive layer LY1 is the channel (semiconductor) of the transistor, and the two sides of the channel are respectively the first pole (conductor part) and the second pole (body) of the transistor.
  • the second pole Ca of the capacitor C is used as the gate of the driving transistor T1
  • a part of the gate signal line GA is used as the gate of the data writing transistor T2
  • a part of the gate signal line GA is used as the gate of the threshold compensation transistor T3
  • a part of the light emission control signal line EML serves as the gate of the first light emission control transistor T4
  • a part of the light emission control signal line EML serves as the gate of the second light emission control transistor T5
  • a part of the reset control signal line RST serves as the first reset transistor
  • the gate of T6 and a part of the reset control signal line RST serve as the gate of the second reset transistor T7.
  • connection electrode EC1 is connected to the gate of the drive transistor T1 through a via hole, and the other end of the connection electrode EC1 is connected to the second pole of the first reset transistor T6 through a via hole .
  • connection electrode EC2 is connected to the block BK through a via hole, and the other end of the connection electrode EC2 is connected to the first power line Vdd through a via hole.
  • connection electrode EC3 is connected to the second pole of the data writing transistor T2 through a via hole, and the other end of the connection electrode EC3 is connected to the data line Vd through a via hole .
  • connection electrode EC4 is connected to the second pole of the second light emission control transistor T5 through a via hole, and the other end of the connection electrode EC4 is connected to the connection electrode ECO.
  • connection electrode EC5 is connected to the first pole of the first light emission control transistor T4 through a via hole, and the other end of the connection electrode EC5 is connected to the first power line Vdd through the via hole.
  • the holes are connected.
  • connection electrode EC6 is connected to the first pole of the second reset transistor T7 through a via hole, and the other end of the connection electrode EC6 is connected to the reset signal line INT2 through a via hole.
  • connection electrode EC7 is connected to the first pole of the first reset transistor T6 through a via hole, and the other end of the connection electrode EC7 is connected to the reset signal line INT1 through a via hole.
  • the signal line SL2 is connected to the light emission control signal line EML through via holes.
  • the connecting electrode ECa is connected to the connecting electrode ECO through a via hole, and the connecting electrode ECa can be used to be connected to the connecting electrode ECb, and then connected to the first light emitting device 131 .
  • the transparent conductive layer LYa includes a plurality of leads 17 .
  • the plurality of leads 17 include a lead 17a, a lead 17b, and a lead 17c.
  • the lead wire 17a shows both left and right ends. Referring to FIG. 1 and FIG. 43 , the left end of the lead wire 17 a is used to connect to the second driving circuit 161 , and the right end of the lead wire 17 a is used to connect to the second light emitting device 132 .
  • the lead wire 17b shows its right end
  • the lead wire 17c shows its middle part, and its left and right ends are not shown.
  • connection electrode ECb is connected to the connection electrode ECa through a via hole.
  • the lead wire 17c in FIG. 44 shows its middle part, and its left and right ends are not shown.
  • FIG. 50 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 51 is a schematic diagram of a partial planar structure of a display panel provided by an embodiment of the present disclosure.
  • FIG. 52 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 53 is a schematic diagram of a partial planar structure of a display panel provided by an embodiment of the present disclosure.
  • the first display area 11 includes a plurality of built-in light emitting devices 13 and at least one first driving circuit 14, and the plurality of built-in light emitting devices 13 includes a first light emitting device 131 and a second light emitting device 132.
  • a driving circuit 14 is connected to the first light emitting device 131, and the first driving circuit 14 is configured to drive the first light emitting device 131 to emit light.
  • the second display area 12 includes at least one third light emitting device 15 and a plurality of external drive circuits 16, and the plurality of external drive circuits 16 include a second drive circuit 161 and a third drive circuit 162 , the second driving circuit 161 is connected to the second light emitting device 132 through a wire 17, the second driving circuit 161 is configured to drive the second light emitting device 132 to emit light, the third driving circuit 162 is connected to the third light emitting device 15, the third driving circuit 162 is configured to drive the third light emitting device 15 to emit light.
  • the first display area 11 has a symmetry axis X1 , for example, the symmetry axis X1 extends along the second direction Y.
  • the first display area 11 may also have a symmetry axis X2, and the symmetry axis X2 extends along the first direction X.
  • the light-emitting devices located on one side of the symmetry axis X1 are all connected by wires (external pixel circuits, compression scheme), that is, the light-emitting devices and pixel circuits Separately arranged, and the light-emitting devices located on the other side of the symmetry axis X1 all adopt the method of built-in pixel circuits (built-in solution).
  • the light-emitting devices located on the left side of the symmetry axis X1 all use external pixel circuits, while the light-emitting devices located on the right side of the symmetry axis X1 use built-in pixel circuits. But not limited to this. It can also be divided according to the axis of symmetry X2.
  • the light-emitting devices on one side of the symmetry axis X2 are all connected by wires (external pixel circuits, compression scheme), that is, the light-emitting devices and pixel circuits are separately arranged, while the light-emitting devices on the other side of the symmetry axis X2 All light-emitting devices are built in pixel circuits (built-in solution). That is, the first display area 11 is divided into two sub-areas, one of which adopts the built-in scheme, and the other adopts the compression scheme.
  • the built-in light-emitting device 13 includes a plurality of first light-emitting device groups G1 and a plurality of second light-emitting device groups G2, and a plurality of first light-emitting device groups G1 and a plurality of light-emitting device groups G2
  • Two second light-emitting device groups G2 are arranged alternately, the light-emitting devices (first light-emitting devices 131) in the first light-emitting device group G1 adopt the method of built-in pixel circuits, and the light-emitting devices (second light-emitting devices 131) in multiple second light-emitting device groups G2
  • the device 132) adopts a method in which the pixel circuit and the light emitting device are arranged separately.
  • FIG. 52 and FIG. 53 illustrate by taking the example that the first light emitting device group G1 includes two columns of light emitting devices, and the second light emitting device group G2 includes two columns of light emitting devices.
  • the first light-emitting device group G1 one column of light-emitting devices is green light-emitting devices, and the other column is alternately arranged red light-emitting devices and blue light-emitting devices.
  • the second light-emitting device group G2 one column of light-emitting devices is green light-emitting devices, and the other column is alternately arranged red light-emitting devices and blue light-emitting devices.
  • the first light emitting device group G1 includes at least one column of first light emitting devices 131
  • the second light emitting device group G2 includes at least one column of second light emitting devices 132 .
  • Fig. 50 is illustrated by setting up a column of second drive circuits 161 every four columns of third drive circuits 162 as an example
  • Fig. 52 is an example of setting up a column of second drive circuits 161 every two columns of third drive circuits 162, and it needs to be explained It is noted that the number of columns of the third driving circuits 162 disposed between two adjacent columns of the second driving circuits 161 can be set as required, and is not limited to what is shown in the figure.
  • FIG. 50 and FIG. 52 do not show all structures in the second display area 21 .
  • An embodiment of the present disclosure provides a display device, including: a photosensitive element and any display panel as described above.
  • the orthographic projection of the photosensitive element on the display panel overlaps with the first display area.
  • the photosensitive element may include a sensing module, and the sensing module may include, for example, an infrared sensing module; a specific pattern (such as a fingerprint pattern, an iris pattern, etc.) is recognized from an infrared image.
  • the sensing module may perform facial recognition.
  • the photosensitive element may include an optical member, and the optical member may include an illuminance sensor.
  • the illuminance sensor may measure illuminance around the display device, and the display device may adjust the brightness of the screen based on the measured illuminance.
  • a photosensitive element may include a sensor, which may be an electronic component that utilizes light or sound.
  • the sensor may be a sensor for receiving and utilizing light (such as an infrared sensor), a sensor for measuring distance or recognizing a fingerprint by outputting and detecting light or sound, a small lamp for outputting light, a sensor for outputting sound, etc.
  • the number of sensor devices may be provided as plural.
  • the sensors include infrared sensors, ultrasonic sensors, LIDAR (Light Detection and Ranging, LIDAR) sensors, radar (Radar) sensors, and camera sensors.
  • LIDAR Light Detection and Ranging
  • radar Radar
  • the photosensitive element includes an under-screen camera or a distance sensor, but is not limited thereto.
  • distance sensors include (Time of Flight, TOF) sensors.
  • TOF stands for Time of Flight, which is a technology that uses the time of flight of light to measure distance. It has been widely used in facial recognition of smartphones and other fields.
  • the display device has all the features and advantages of the above-mentioned display panel.
  • the specific types of the display device include but not limited to mobile phones, notebooks, iPads, kindles, televisions and other display devices with display and camera functions.
  • the display device can also include structures or components necessary for conventional display devices.
  • the display device in addition to the above-mentioned display panel, it also includes a glass cover , battery back cover, middle frame, motherboard, touch module, audio module, camera module and other necessary structures or components.
  • the first direction X is a direction parallel to the main surface of the base substrate 40 .
  • the second direction Y is a direction parallel to the main surface of the base substrate 40 .
  • the first direction X intersects the second direction Y.
  • Embodiments of the present disclosure are described by taking the first direction X perpendicular to the second direction Y as an example.
  • the third direction Z is a direction perpendicular to the main surface of the base substrate 40 .
  • the main surface of the base substrate 40 is the surface used to fabricate various film layers.
  • the upper surface of the base substrate 40 in FIG. 4 is its main surface.
  • elements arranged in the same layer are formed by the same film layer using the same patterning process.
  • elements arranged in the same layer are located on the surface of the same element away from the base substrate, but not limited thereto.
  • Components arranged in the same layer may have different heights relative to the base substrate.
  • the patterning or patterning process may only include a photolithography process, or include a photolithography process and an etching step, or may include printing, inkjet and other processes for forming a predetermined pattern.
  • the photolithography process refers to the process including film formation, exposure, development, etc., using photoresist, mask plate, exposure machine, etc. to form graphics.
  • a corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

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Abstract

提供一种显示面板及显示装置。显示面板包括第一显示区(11)和第二显示区(12)。第一显示区(11)包括多个内置发光器件(13)和至少一个第一驱动电路(14)，多个内置发光器件(13)包括第一发光器件(131)和第二发光器件(132)，第一驱动电路(14)与第一发光器件(131)连接；第二显示区(12)包括至少一个第三发光器件(15)和多个外置驱动电路(16)，多个外置驱动电路(16)包括第二驱动电路(161)和第三驱动电路(162)，第二驱动电路(161)与第二发光器件(132)通过引线(17)连接，第三驱动电路(162)与第三发光器件(15)连接。该技术方案可提高显示画面质量和显示均一性。

Description

显示面板及显示装置
相关申请的交叉引用
本专利申请要求于2021年10月28日递交的中国专利申请第202111265004.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示面板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器与传统的液晶显示器相比，具有自发光、广色域、高对比度、轻薄等优点。由于OLED显示面板具有超高的屏占比，因此逐渐成为移动装置例如移动手机的主流形态。
随着技术的不断进步，屏下摄像头是未来全面屏的发展趋势之一。但是相关技术中，设置有屏下摄像头的显示产品仍具有许多问题有待改进。
发明内容
本公开的实施例提供一种显示面板及显示装置，以提高显示均一性。
本公开的实施例提供了一种显示面板，包括第一显示区和第二显示区，所述第一显示区的透过率大于所述第二显示区的透过率；所述第一显示区包括多个内置发光器件和至少一个第一驱动电路，所述多个内置发光器件包括第一发光器件和第二发光器件，所述第一驱动电路与所述第一发光器件连接，所述第一驱动电路被配置为驱动所述第一发光器件发光；所述第二显示区包括至少一个第三发光器件和多个外置驱动电路，所述多个外置驱动电路包括第二驱动电路和第三驱动电路，所述第二驱动电路与所述第二发光器件通过引线连接，所述第二驱动电路被配置为驱动所述第二发光器件发光，所述第三驱动电路与所述第三发光器件连接，所述第三驱动电路被配置为驱动所述第三发光器件发光。
例如，所述第三发光器件的数量为多个，在第一方向上，所述外置驱动 电路和所述第三发光器件均呈周期性排布，所述外置驱动电路的排布周期小于所述第三发光器件的排布周期。
例如，所述外置驱动电路的排布周期与所述第三发光器件的排布周期之间的比值大于或等于1/2，且小于或等于9/10。
例如，所述第一发光器件包括设置在衬底基板上的第一阳极层，所述第三发光器件包括设置在所述衬底基板上的第二阳极层；所述第一驱动电路在所述衬底基板上的正投影面积与所述第一阳极层在所述衬底基板上的正投影面积之间的比值，小于所述第三驱动电路在所述衬底基板上的正投影面积与所述第二阳极层在所述衬底基板上的正投影面积之间的比值。
例如，所述第一阳极层在所述衬底基板上的正投影覆盖所述第一驱动电路在所述衬底基板上的正投影。
例如，所述第一显示区被划分为两个子区，其中一个子区内的发光器件均为第一发光器件，另一个子区内的发光器件均为第二发光器件。
例如，所述第一发光器件设置为多个，所述第二发光器件设置为多个，多个第一发光器件构成多个第一发光器件组，多个第二发光器件构成多个第二发光器件组，多个第一发光器件组和多个第二发光器件组交替排布，所述第一发光器件组包括至少一列第一发光器件，所述第二发光器件组包括至少一列第二发光器件。
例如，所述第一发光器件包括绿光发光器件和/或蓝光发光器件；所述第二发光器件包括以下至少之一：绿光发光器件，蓝光发光器件和红光发光器件。
例如，所述第一发光器件包括红光发光器件和/或蓝光发光器件；所述第二发光器件包括以下至少之一：绿光发光器件，蓝光发光器件和红光发光器件。
例如，所述第一发光器件包括绿光发光器件和/或红光发光器件；所述第二发光器件包括以下至少之一：绿光发光器件，蓝光发光器件和红光发光器件。
例如，所述第一发光器件的数量大于或等于所述第二发光器件的数量。
例如，所述第二发光器件包括第一颜色光发光器件、第二颜色光发光器件和第三颜色光发光器件，连接所述第一颜色光发光器件与所述第二驱动 电路的引线为第一引线，连接所述第二颜色光发光器件与所述第二驱动电路的引线为第二引线，连接所述第三颜色光发光器件与所述第二驱动电路的引线为第三引线，所述第一引线的面积小于或等于所述第二引线的面积，所述第二引线的面积小于或等于第三引线的面积。
例如，所述第一发光器件包括第一颜色光发光器件，所述第二发光器件包括第二颜色光发光器件和第三颜色光发光器件，并且所述第一颜色光发光器件、所述第二颜色光发光器件和所述第三颜色光发光器件被配置为发不同颜色的光。
例如，所述第一发光器件包括绿光发光器件，所述第二发光器件包括红光发光器件和蓝光发光器件。
例如，所述引线包括第一导电线和第二导电线，所述第一导电线与所述第二颜色光发光器件相连，所述第二导电线与所述第三颜色光发光器件相连。
例如，与所述第一驱动电路连接的信号线包括第一线段和第二线段，所述第一线段与所述第二线段连接，所述第一线段位于所述第一显示区内，所述第二线段位于所述第二显示区内，所述第一线段的材料包括透明导电材料，所述第二线段的材料包括金属材料。
例如，所述引线的材料为透明导电材料，且所述引线与所述第一线段分别位于不同的膜层。
例如，显示面板还包括与所述第一驱动电路连接的多条信号线，其中，所述多条信号线中的至少一条信号线分段设置。
在一种可选的实现方式中，所述分段设置的信号线包括位于不同层的多个信号部。
例如，所述分段设置的信号线包括第一信号部和第二信号部，所述第一信号部的材料包括透明的导电金属氧化物，所述第二信号部的材料包括金属。
例如，所述第一显示区包括驱动电路设置区和走线区，所述第一信号部位于所述驱动电路设置区，所述第二信号部位于所述走线区。
例如，显示面板还包括发光控制信号线、复位控制信号线、以及复位信号线、其中，像素电路包括驱动模块、发光控制电路、以及复位电路，所述 像素电路包括所述第一驱动电路、所述第二驱动电路、以及所述第三驱动电路中至少一个，所述发光控制信号线与所述发光控制电路的控制端相连，所述复位控制信号线与所述复位电路的控制端相连，所述复位信号线与所述复位电路的第一极相连，所述发光控制信号线、所述复位控制信号线、以及所述复位信号线中至少之一在所述第一显示区分段设置。
例如，所述复位电路包括第一复位晶体管和第二复位晶体管，所述第一复位晶体管被配置为对所述驱动模块的控制端进行复位，所述第二复位晶体管被配置为对发光器件的第一电极进行复位，所述发光器件包括所述第一发光器件、第二发光器件、以及所述第三发光器件中至少之一，在位于所述第一显示区的同一个像素电路中，所述第一复位晶体管和所述第二复位晶体管共用同一条复位信号线。
例如，所述第二驱动电路和所述第三驱动电路的布局相同，所述第一驱动电路的布局与所述第二驱动电路或所述第三驱动电路的布局不同。
例如，所述第一驱动电路包括驱动晶体管、第一复位晶体管、第二复位晶体管、数据写入晶体管、以及阈值补偿晶体管，所述第一复位晶体管的第一极与第一复位信号线电连接，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连接，所述第二复位晶体管的第一极与第二复位信号线电连接，所述第二复位晶体管的第二极与所述第一发光器件相连，所述数据写入晶体管的第一极与所述驱动晶体管的第一极电连接，所述数据写入晶体管的第二极被配置为与数据线相连，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极电连接，所述第一复位信号线和所述第二复位信号线为同一条复位信号线。
例如，所述第二复位晶体管的栅极、所述数据写入晶体管的栅极、以及所述阈值补偿晶体管的栅极均与同一条栅极信号线相连。
例如，所述第一显示区的像素密度小于或等于所述第二显示区的像素密度。
例如，所述第二显示区包围所述第一显示区。
本公开提供了一种显示装置，包括：感光元件以及上述任一显示面板，所述感光元件在所述显示面板上的正投影与第一显示区有交叠。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开的实施例提供的一种显示面板的平面结构示意图。
图2为本公开的实施例提供的一种显示面板中的第三发光器件和外置驱动电路的结构示意图。
图3为本公开的实施例提供的另一种显示面板中的第三发光器件和外置驱动电路的结构示意图。
图4为本公开的实施例提供的一种显示面板的剖面结构示意图。
图5为本公开的实施例提供的一种对比第一显示区和第二显示区的平面结构示意图。
图6为本公开的实施例提供的另一种对比第一显示区和第二显示区的平面结构示意图。
图7为本公开的实施例提供的一种显示面板中的一种信号线的剖面结构示意图。
图8为本公开的实施例提供的一种显示面板中的一种像素电路的结构示意图。
图9为一种采用全内置方案的显示面板的示意图。
图10为一种采用全外置方案的显示面板的示意图。
图11为一种采用全外置方案的显示面板中的引线的示意图。
图12为本公开实施例提供的一种采用压缩方案和内置方案的显示面板的示意图。
图13为本公开实施例提供的一种显示面板的示意图。
图14为本公开实施例提供的一种显示面板的示意图。
图15为本公开的实施例提供的显示面板的示意图。
图16为本公开的实施例提供的显示面板中的位于第二显示区的像素电路的布局图。
图17为本公开的实施例提供的显示面板中的位于第一显示区的像素电 路的布局图。
图18为本公开的实施例提供的显示面板中的位于第一显示区和第二显示区的像素电路的布局图。
图19为图18的沿线B1-B2的截面图。
图20为图16中的有源层的平面图。
图21为图16中的第一导电层的平面图。
图22为图16中的第二导电层的平面图。
图23为图16中的第三导电层的平面图。
图24为图16中的第四导电层的平面图。
图25为图16中的有源层和第一导电层的叠层平面图。
图26为图16中的有源层、第一导电层、以及第二导电层的叠层平面图。
图27为图16中的第三导电层和第四导电层的叠层平面图。
图28为图16中的第三导电层、第四导电层以及其间的绝缘层中的过孔的叠层平面图。
图29为图16中的有源层、第三导电层、第四导电层以及位于第三导电层和第四导电层之间的绝缘层中的过孔的叠层平面图。
图30为图16中的有源层、第三导电层、第四导电层、位于有源层和第三导电层之间的绝缘层中的过孔、以及位于第三导电层和第四导电层之间的绝缘层中的过孔的叠层平面图。
图31为本公开的实施例提供的显示面板的第一显示区内的有源层的平面图。
图32为本公开的实施例提供的显示面板的第一显示区内的第一导电层的平面图。
图33为本公开的实施例提供的显示面板的第一显示区内的第二导电层的平面图。
图34为本公开的实施例提供的显示面板的第一显示区内的第三导电层的平面图。
图35为本公开的实施例提供的显示面板的第一显示区内的第四导电层的平面图。
图36为本公开的实施例提供的显示面板的第一显示区内的透明导电层 的平面图。
图37A为本公开的实施例提供的一种显示面板的示意图。
图37B为本公开的实施例提供的一种显示面板的布局图。
图38为本公开的实施例提供的显示面板中的有源层LY0的平面图。
图39为本公开的实施例提供的显示面板中的第一导电层LY1的平面图。
图40为本公开的实施例提供的显示面板中的第二导电层LY2的平面图。
图41为本公开的实施例提供的显示面板中的第三导电层LY3的平面图。
图42为本公开的实施例提供的显示面板中的第四导电层LY4的平面图。
图43为本公开的实施例提供的显示面板中的透明导电层LYa的平面图。
图44为本公开的实施例提供的显示面板中的透明导电层LYb的平面图。
图45为本公开的实施例提供的显示面板中的有源层LY0和第一导电层LY1的叠层平面图。
图46为本公开的实施例提供的显示面板中的有源层LY0、第一导电层LY1、以及第二导电层LY2的叠层平面图。
图47为本公开的实施例提供的显示面板中的有源层LY0、第一导电层LY1、第二导电层LY2、以及第三导电层LY3的叠层平面图。
图48为本公开的实施例提供的显示面板中的有源层LY0、第一导电层LY1、第二导电层LY2、第三导电层LY3、以及第四导电层LY4的叠层平面图。
图49为本公开的实施例提供的显示面板中的有源层LY0、第一导电层LY1、第二导电层LY2、第三导电层LY3、第四导电层LY4、以及透明导电层LYa的叠层平面图。
图50为本公开的实施例提供的一种显示面板的平面结构示意图。
图51为本公开的实施例提供的一种显示面板的局部平面结构示意图。
图52为本公开的实施例提供的一种显示面板的平面结构示意图。
图53为本公开的实施例提供的一种显示面板的局部平面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述， 显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
相关技术中的显示面板在摄像头区域仅设置发光器件，控制发光器件发光的驱动信号由横向的同行像素电路引出，传输驱动信号的引线采用透明导电材料。发明人发现，由于引线的长短不一，导致引线引起的耦合电容差异较大，进而导致显示面板的显示均一性较差。
为了解决上述问题，本公开的实施例提供一种显示面板和包含该显示面板的显示装置，以下进行详细说明。
图1为本公开的实施例提供的一种显示面板的平面结构示意图。本公开的实施例提供一种显示面板，如图1所示，包括第一显示区11和第二显示区12，第一显示区11的透过率大于第二显示区12的透过率。如图1所示，第二显示区12位于第一显示区11的至少一侧。本公开的实施例以第二显示区12围绕第一显示区11为例进行说明。
如图1所示，第一显示区11包括多个内置发光器件13和至少一个第一驱动电路14，多个内置发光器件13包括第一发光器件131和第二发光器件132，第一驱动电路14与第一发光器件131连接，第一驱动电路14被配置为驱动第一发光器件131发光。第一驱动电路14也可称作内置驱动电路。
如图1所示，第二显示区12包括至少一个第三发光器件15和多个外置驱动电路16，多个外置驱动电路16包括第二驱动电路161和第三驱动电路162，第二驱动电路161与第二发光器件132通过引线17连接，第二驱动电 路161被配置为驱动第二发光器件132发光，第三驱动电路162与第三发光器件15连接，第三驱动电路162被配置为驱动第三发光器件15发光。
例如，在本公开的实施例中，内置和外置可相对于第一显示区11而言，位于第一显示区11的发光器件可称作内置发光器件(如图1所示的内置发光器件13)，位于第一显示区11的驱动电路可称作内置驱动电路(如图1所示的第一驱动电路14)。
例如，在本公开的实施例中，根据发光器件和驱动电路是否分离设置，即是否位于同一个显示区，可将驱动电路分为原位驱动电路和非原位驱动电路。如图1所示，第二驱动电路161和第二发光器件132分离设置，分别位于第二显示区12和第一显示区11，则第二驱动电路161可称作非原位驱动电路。如图1所示，第三驱动电路162和第三发光器件15均位于第二显示区12，则第三驱动电路162可称作原位驱动电路。如图1所示，第一发光器件131和第一驱动电路14均位于第一显示区11，则第一驱动电路14可称作原位驱动电路。
本公开的实施例中，将连接第二发光器件132与第二驱动电路161的方向定义为第一方向X，如图1所示。
如图1所示，第二显示区12位于第一显示区11沿第一方向X的至少一侧。可选地，第二显示区12可以包围第一显示区11。
第一发光器件131、第二发光器件132以及第三发光器件15可以均为有机发光器件或量子点发光器件，本公开的实施例对此不作限定。
第一显示区11的形状可以为长方形、正方形、圆形或者椭圆形等形状，本公开的实施例对此不作限定。
本公开的实施例提供的显示面板，通过将与第一发光器件131连接的第一驱动电路14设置在第一显示区11，可以减少连接内置发光器件13与外置驱动电路16的引线17的数量，从而降低引线17引起的衍射效应，提升画面质量；还可以缩短引线17长度，从而降低引线17引起的耦合电容，提高第一显示区11的显示均一性。另外，通过将与第二发光器件132连接的第二驱动电路161设置在第二显示区12，可以提高第一显示区11的透过率。
由于引线17的数量减少，通过优化设计可以使得引线17的长度变短，耦合电容降低，进而耦合电容对启亮电压的影响减小，从而可以提高显示均 一性。另外，引线17的数量减少还可以增加工艺稳定性。
本公开的实施例提供的显示面板及显示装置，通过将与第一发光器件连接的第一驱动电路设置在第一显示区，可以减少连接内置发光器件与外置驱动电路的引线数量，从而降低引线引起的衍射效应，提升画面质量；还可以缩短引线长度，从而降低引线引起的耦合电容，提高第一显示区的显示均一性；另外，通过将与第二发光器件连接的第二驱动电路设置在第二显示区，可以提高第一显示区的透过率。
在具体实现中，第三发光器件15的数量可以为多个。在第一方向X上，外置驱动电路16和第三发光器件15可以均呈周期性排布。外置驱动电路16的排布周期与第三发光器件15的排布周期可以相同或不同。
图2为本公开的实施例提供的一种显示面板中的第三发光器件和外置驱动电路的结构示意图。如图2所示，在第一方向X上，外置驱动电路16的排布周期p2与第三发光器件15的排布周期p1相同，例如均为31.6μm。
在一种可选的实现方式中，如图3所示，外置驱动电路16的排布周期p2小于第三发光器件15的排布周期p1。
图3为本公开的实施例提供的另一种显示面板中的第三发光器件和外置驱动电路的结构示意图。本实现方式中，如图3所示，外置驱动电路16与第三发光器件15在第一方向X上的排布周期不同。外置驱动电路16的排布周期p2例如为27.6μm，第三发光器件15的排布周期p1为31.6μm。例如，第三发光器件15的排布周期p1在第一方向X上比外置驱动电路16的排布周期p2宽4μm。外置驱动电路16的排布周期p2和第三发光器件15的排布周期p1不限于上述描述。
本实现方式中，如图3所示，通过在第二显示区12设置较小的外置驱动电路16的排布周期，使得在第二显示区12的第一方向X上，外置驱动电路16的数量能够大于第三发光器件15的数量，确保每个第三发光器件15都有对应的外置驱动电路16即第三驱动电路162连接，保证第二显示区12的正常显示，另外还具有未与任何第三发光器件15连接的外置驱动电路16，即第二驱动电路161，第二驱动电路161可以与第一显示区11的第二发光器件132连接，用于驱动第一显示区11内的第二发光器件132。
这样，在不牺牲像素密度的前提下，实现将与第二发光器件132连接的 第二驱动电路161设置在第二显示区12，从而可以提高第一显示区11的透过率，同时确保第一显示区11具有较高的显示均一性。
下面进行举例说明，参照图1，假设第一显示区11为一个圆形区域，第三发光器件15在第一方向X上的排布周期p1为31.6μm，外置驱动电路16在第一方向X上的排布周期p2为27.6μm。假设在第一显示区11内沿第一方向X的某一行上共有48个第二发光器件132，所以需要在第二显示区12内设置48个冗余的第二驱动电路161来控制这些第二发光器件132发光，因此，总共需要压缩出48*27.6μm的空间来设置48个冗余的第二驱动电路161，由于每个第三发光器件15可以压缩出4μm的空间，因此需要对应的第三发光器件15的数量为48*27.6μm/4μm，取整后为332个。也就是在332*31.6μm的空间内可以设置332个第三驱动电路162和48个第二驱动电路161。其中，332个第三驱动电路162用于驱动第二显示区12内的332个第三发光器件15发光，48个第二驱动电路161用于驱动第一显示区11内的48个第二发光器件132发光。
可选地，外置驱动电路16的排布周期p2与第三发光器件15的排布周期p1之间的比值可以大于或等于1/2，且小于或等于9/10，本公开的实施例对此不作限定。例如，该比值可以为2/3、3/4、4/5、5/6、6/7、7/8、8/9等等。如图3所示，外置驱动电路16的排布周期p2与第三发光器件15的排布周期p1之间的比值为4/5。
例如，排布周期可指间距(Pitch)。外置驱动电路16的排布周期p2是指外置驱动电路16的间距。第三发光器件15的排布周期p1是指第三发光器件15的排布周期p1的间距。例如，排布周期p1可以为定值，排布周期p2可以为定值。当然，在不同的实施例中，排布周期p1可以为不同的数值，排布周期p2可以为不同的数值。
图4为本公开的实施例提供的一种显示面板的剖面结构示意图。如图4所示，第一发光器件131可以包括设置在衬底基板40上的第一阳极层41，还可以包括设置在第一阳极层41背离衬底基板40一侧的第一发光层42和第一阴极层43，第一发光层42设置在第一阳极层41和第一阴极层43之间。第一驱动电路14可以设置在第一阳极层41靠近衬底基板40的一侧，即设置在衬底基板40与第一阳极层41之间。
如图4所示，第三发光器件15可以包括设置在衬底基板40上的第二阳极层44，还可以包括设置在第二阳极层44背离衬底基板40一侧的第二发光层45和第二阴极层46，第二发光层45设置在第二阳极层44和第二阴极层46之间。第三驱动电路162可以设置在第二阳极层44靠近衬底基板40的一侧，即设置在衬底基板40与第二阳极层44之间。
图5为本公开的实施例提供的一种对比第一显示区和第二显示区的平面结构示意图。在一种可选的实现方式中，参照图4和图5，第一驱动电路14在衬底基板40上的正投影面积与第一阳极层41在衬底基板40上的正投影面积之间的比值，小于第三驱动电路162在衬底基板40上的正投影面积与第二阳极层44在衬底基板40上的正投影面积之间的比值。
第二驱动电路161与第三驱动电路162分别在衬底基板40上的正投影面积可以相同。
如图4和图5所示，当第一阳极层41在衬底基板40上的正投影面积与第二阳极层44在衬底基板40上的正投影面积相等时，第一驱动电路14在衬底基板40上的正投影面积小于第三驱动电路162在衬底基板40上的正投影面积。
本实现方式中，与外置驱动电路16相比，第一显示区11内的驱动电路即第一驱动电路14相对于第一阳极层41的压缩比例较大。由于驱动电路通常包括多个金属层，透过率较差，在本实现方式中，通过合理设计第一阳极层41与第一驱动电路14之间的位置关系，可以降低第一驱动电路14对第一显示区11开口率的影响，提高第一显示区11的开口率。
图6为本公开的实施例提供的另一种对比第一显示区和第二显示区的平面结构示意图。可选地，如图4和图6所示，第一阳极层41在衬底基板40上的正投影可以覆盖第一驱动电路14在衬底基板40上的正投影。由于驱动电路的透过率较差，通过设置第一阳极层41完全覆盖住第一驱动电路14，可以进一步提高第一显示区11的透过率。
例如，第一阳极层41也可称为第一发光器件131的第一电极，第一阴极层43也可称为第一发光器件131的第二电极。例如，第二阳极层44也可称为第三发光器件15的第一电极，第二阴极层46也可称为第三发光器件15的第二电极。
本公开的实施例中，第一发光器件131可以包括绿光发光器件，蓝光发光器件、红光发光器件以及白光发光器件等发光器件中的一种或多种，本公开的实施例对此不作限定。
第一显示区11内除第一发光器件131之外的内置发光器件13可以均为第二发光器件132。第二发光器件132可以包括绿光发光器件，蓝光发光器件、红光发光器件以及白光发光器件等发光器件中的一种或多种，本公开的实施例对此不作限定。
在第一种可选的实现方式中，第一发光器件131包括绿光发光器件和/或蓝光发光器件。本实现方式中，第一发光器件131可以包括绿光发光器件，或者蓝光发光器件，或者绿光发光器件和蓝光发光器件。
在第二种可选的实现方式中，第一发光器件131包括红光发光器件和/或蓝光发光器件。本实现方式中，第一发光器件131可以包括红光发光器件，或者蓝光发光器件，或者红光发光器件和蓝光发光器件。
在第二种可选的实现方式中，第一发光器件131包括绿光发光器件和/或红光发光器件。本实现方式中，第一发光器件131可以包括绿光发光器件，或者红光发光器件，或者红光发光器件和绿光发光器件。
由于绿光发光器件对引线17引起的电容较为敏感，当第一发光器件131包括绿光发光器件时，可以进一步提升显示画面的均一性。
由于蓝光发光器件中的阳极面积较大，当第一发光器件131包括蓝光发光器件时，可以降低与该蓝光发光器件连接的第一驱动电路14对开口率的影响，有助于提高第一显示区11的透过率。
在一种可选的实现方式中，第一发光器件131的数量可以大于或等于第二发光器件132的数量。
对于所有颜色的内置发光器件13，第一发光器件131的数量与第二发光器件132的数量之间的比值可以大于或等于1，也就是将驱动电路设置在第一显示区11内的内置发光器件13的比例较高，这样可以进一步减少引线数量，提升画面质量。在具体实现中，所有颜色的内置发光器件13中，第一发光器件131的数量与第二发光器件132的数量之间的比值例如可以为2:1，3:1等，具体数值可以根据实际需求进行设定，本公开的实施例对此不作限定。
对于同一种颜色的内置发光器件13，可以全部为第一发光器件131；也可以全部为第二发光器件132；还可以其中一部分为第一发光器件131，其余部分为第二发光器件132。
可选地，同一种颜色的内置发光器件13中，第一发光器件131的数量可以大于或等于第二发光器件132的数量，这样可以进一步减少引线数量，提升画面质量。在具体实现中，同一种颜色的内置发光器件13中，第一发光器件131的数量与第二发光器件132的数量之间的比值例如可以为2:1，3:1等，具体数值可以根据实际需求进行设定，本公开的实施例对此不作限定。
在一种可选的实现方式中，第二发光器件132包括绿光发光器件、蓝光发光器件和红光发光器件，连接绿光发光器件与第二驱动电路161的引线17为第一引线，连接红光发光器件与第二驱动电路161的引线17为第二引线，连接蓝光发光器件与第二驱动电路161的引线17为第三引线。
例如，绿光发光器件可称作第一颜色光发光器件，红光发光器件可称作第二颜色光发光器件，蓝光发光器件可称作第三颜色光发光器件。
例如，第一颜色光发光器件被配置为发第一颜色光，第二颜色光发光器件被配置为发第二颜色光，第三颜色光发光器件被配置为发第三颜色光。例如，第一颜色光为绿光，第二颜色光为红光，第三颜色光为蓝光，但不限于此，可根据需要选择。
例如，第一颜色光发光器件、第二颜色光发光器件和第三颜色光发光器件被配置为发不同颜色的光。
例如，第一引线的面积可以小于或等于第二引线的面积，第二引线的面积小于或等于第三引线的面积。
由于绿光发光器件、红光发光器件和蓝光发光器件对引线17引起的耦合电容的敏感度依次降低，因此通过设置第一引线的面积小于或等于第二引线的面积，第二引线的面积小于或等于第三引线的面积，可以整体降低耦合电容的影响，进一步提升画面显示质量，提高显示画面的均一性。
当第一引线、第二引线和第三引线在垂直于各自延伸方向上的宽度相同时，可以设置第一引线的长度小于或等于第二引线的长度，第二引线的长度小于或等于第三引线的长度。
图7为本公开的实施例提供的一种显示面板中的一种信号线的剖面结构 示意图。在一种可选的实现方式中，如图1和图7所示，与第一驱动电路14连接的信号线18包括第一线段181和第二线段182，第一线段181与第二线段182连接，第一线段181位于第一显示区11内，第二线段182位于第二显示区12内。
第一线段181与第二线段182可以设置在不同膜层，例如二者之间可以设置有绝缘层，第一线段181与第二线段182可以通过设置在绝缘层中的过孔连接，如图7所示。第一线段181与第二线段182还可以设置在同一膜层，或者通过搭接的方式连接，本公开的实施例对此不作限定。
信号线18例如可以为栅极信号线(如图8中的第一扫描信号线Ga1或第二扫描信号线Ga2)、发光控制信号线(如图8中的第一发光控制信号线EM1或第二发光控制信号线EM2)、数据信号线(如图8中的数据线Vd)、复位控制信号线(如图8中的第一复位控制信号线Rst1或第二复位控制信号线Rst2)、电源信号线、复位信号线等。
例如，第一线段181的材料可以为透明导电材料。
例如，第二线段182的材料可以为金属材料。
例如，透明导电材料可以为金属、金属氧化物、无机材料、有机材料或复合材料等。具体地，透明导电材料可以为氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)、碳纳米管、纳米银或石墨烯等，本公开的实施例对此不作限定。
例如，引线17的材料可以选用ITO。第一线段181的材料可以选用ITO或纳米银。由于纳米银的方阻较低，透过率较高，因此当采用纳米银作为第一线段181的材料时，可以降低第一线段181的电阻，并且提高第一显示区11的透过率。
可选地，如图7所示，引线17与第一线段181分别位于不同的膜层。通过在两个膜层上分别设置引线17和第一线段181，可以增大布线空间，从而有助于实现高像素密度的第一显示区11。如图7所示，引线17与第一线段181之间可以设置有绝缘材料。图7以引线17所在的膜层更靠近衬底基板为例，然而，并不限于此，在其他的实施欧中，第一线段181所在的膜层可以比引线17所在的膜层更靠近衬底基板。
在一种可选的实现方式中，第一显示区11的像素密度小于或等于第二显 示区12的像素密度。例如，像素密度指的是每英寸所设置的发光器件的数量。当第一显示区11的像素密度小于第二显示区12的像素密度时，可以进一步提高第一显示区11的透过率。
本公开的实施例中，第一驱动电路14、第二驱动电路161和第三驱动电路162的电路结构可以相同或不同，本公开的实施例对此不作限定。
图8为本公开的实施例提供的一种显示面板中的一种像素电路的结构示意图。可选地，第一驱动电路14、第二驱动电路161和第三驱动电路162中的至少一个为如图8所示的像素电路221。图8中的发光器件220可以为第一发光器件131、第二发光器件132或第三发光器件15。发光器件220可以为有机发光器件，但不限于此。
如图8所示，像素电路221包括第一发光控制电路223、第二发光控制电路224和驱动模块222。
例如，如图8所示，驱动模块222包括控制端、第一端和第二端，且被配置为提供驱动发光器件220发光的驱动电流。例如，第一发光控制电路223与驱动模块222的第一端和第一电压端VDD连接，且被配置为实现驱动模块222和第一电压端VDD之间的连接导通或断开，第二发光控制电路224与驱动模块222的第二端和发光器件220的第一电极电连接，且被配置为实现驱动模块222和发光器件220之间的连接导通或断开。
例如，如图8所示，像素电路221还包括数据写入电路226、存储电路227、阈值补偿电路228和复位电路229。数据写入电路226与驱动模块222的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路227；存储电路227分别与驱动模块222的控制端和第一电压端VDD电连接，且被配置为存储数据信号；阈值补偿电路228与驱动模块222的控制端和第二端电连接，且被配置为对驱动模块222进行阈值补偿；复位电路229与驱动模块222的控制端和发光器件220的第一电极电连接，且配置为在复位控制信号的控制下对驱动模块222的控制端和发光器件220的第一电极进行复位。
例如，如图8所示，驱动模块222包括驱动晶体管T1，驱动模块222的控制端包括驱动晶体管T1的栅极，驱动模块222的第一端包括驱动晶体管T1的第一极，驱动模块222的第二端包括驱动晶体管T1的第二极。
例如，如图8所示，数据写入电路226包括数据写入晶体管T2，存储电路227包括电容C，阈值补偿电路228包括阈值补偿晶体管T3，第一发光控制电路223包括第一发光控制晶体管T4，第二发光控制电路224包括第二发光控制晶体管T5，复位电路229包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一复位控制信号和第二复位控制信号。
例如，如图8所示，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；电容C的第一极Cb与第一电源端VDD电连接，电容C的第二极Ca与驱动晶体管T1的栅极电连接；阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T6的第一极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一复位控制信号；第二复位晶体管T7的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T7的第二极与发光器件220的第一电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二复位控制信号；第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与发光器件220的第一电极电连接，第二发光控制晶体管T5的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；发光器件220的第二电极与第二电源端VSS电连接。
例如，发光器件220包括有机发光元件，但不限于此，发光器件220的类型可根据需要而定。
例如，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低 压端。例如，如图8所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
例如，如图8所示，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极可以电连接到同一条信号线，例如第一扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示面板(显示基板)可以不设置第二扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T2的栅极电连接到第一扫描信号线Ga1，阈值补偿晶体管T3的栅极电连接到第二扫描信号线Ga2，而第一扫描信号线Ga1和第二扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T2的栅极和阈值补偿晶体管T3可以被分开单独控制，增加控制像素电路的灵活性。
例如，如图8所示，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线，例如均电连接至第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示面板(显示基板)可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T4的栅极电连接到第一发光控制信号线EM1，第二发光控制晶体管T5的栅极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T4和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T4为P型晶体管，而第二发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。
例如，第一复位控制信号和第二复位控制信号可以相同，即，第一复位 晶体管T6的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一复位控制信号)，此时，显示面板(显示基板)可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T6的栅极电连接到第一复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到第二复位控制信号线Rst2，而第一复位控制信号线Rst1和第二复位控制信号线Rst2传输的信号相同。需要说明的是，第一复位控制信号和第二复位控制信号也可以不相同。
例如，在一些示例中，第二复位控制信号可以与扫描信号相同，即第二复位晶体管T7的栅极可以电连接到第一扫描信号线Ga1以接收扫描信号作为第二复位控制信号。
例如，第一复位晶体管T6的第一极和第二复位晶体管T7的第一极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如，第一复位晶体管T6的第一极和第二复位晶体管T7的第一极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T1的栅极和发光器件220的第一电极进行复位即可，本公开的实施例对此不作限制。
需要说明的是，图8所示的像素电路中的驱动模块222、数据写入电路226、存储电路227、阈值补偿电路228和复位电路229仅为示意性的，驱动模块222、数据写入电路226、存储电路227、阈值补偿电路228和复位电路229等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶 体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
需要说明的是，在本公开的实施例中，子像素的像素电路除了可以为图8所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开的实施例对此不作限定。
图9为一种采用全内置方案的显示面板的示意图。图10为一种采用全外置方案的显示面板的示意图。图11为一种采用全外置方案的显示面板中的引线的示意图。图12为本公开实施例提供的一种采用压缩方案和内置方案的显示面板的示意图。图13为本公开实施例提供的一种显示面板的示意图。图14为本公开实施例提供的一种显示面板的示意图。
如图9至图12所示，发光器件600包括第一颜色光发光器件601、第二颜色光发光器件602和第三颜色光发光器件603。
如图9所示，位于第一显示区11内的发光器件600相连的像素电路PXC均采用内置方式，即，与位于第一显示区11内的发光器件600相连的像素电路PXC均位于第一显示区11。采用全内置方案可不必设置连接发光器件600和像素电路PXC的引线，可实现大孔径，但第一显示区11的透过率较低，例如，透过率为12％，并且具有炫光衍射问题。
如图10所示，位于第一显示区11内的发光器件600相连的像素电路PXC均采用外置方式，即，与位于第一显示区11内的发光器件600相连的像素电路PXC均位于第二显示区12。第一显示区11内的发光器件600和 像素电路PXC采用分离设置的方式。第一显示区11内的发光器件600和位于第二显示区12的像素电路PXC采用引线17相连，采用全外置方案的显示面板中，引线17的数量较多，引线17的长度较长，造成引线上的负载较大，且引线17的长度差异较大，容易引起显示不均一的问题。
图11示出了显示面板中的部分引线的示意图。如图11所示，引线17的长度较大，并且引线17的长度差异较大。
如图12所示，本公开的实施例提供的显示面板，采用压缩方案和内置方案的结合，从而，可以使得第一显示区11具有较大的孔径，并且具有较低的炫光衍射情况，同时，因在第一显示区11具有同样的孔径的情况下，图12所示的显示面板中的引线17的数量比图10或图11所示的显示面板中的引线17的数量少约一半，从而，引线17的长度较小，且引线17的长度差异较小，利于提高显示均一性。
例如，如图13所示，第一发光器件131包括第一颜色光发光器件601，第二发光器件132包括第二颜色光发光器件602和第三颜色光发光器件603，并且第一颜色光发光器件601、第二颜色光发光器件602和第三颜色光发光器件603被配置为发不同颜色的光。例如，第一发光器件131包括绿光发光器件，第二发光器件132包括红光发光器件和蓝光发光器件。图13中的G表示绿光发光器件(第一颜色光发光器件601)、R表示红光发光器件(第二颜色光发光器件602)、B表示蓝光发光器件(第三颜色光发光器件603)。
例如，如图13所示，引线17包括第一导电线1701和第二导电线1702，第一导电线1701与第二颜色光发光器件602相连，第二导电线1702与第三颜色光发光器件603相连。第一导电线1701位于第一透明导电层LYa，第二导电线1702位于第二透明导电层LYb。
例如，如图13所示，在第二方向Y上，第一导电线1701和第二导电线1702交替设置，但不限于此。
如图13所示，因绿光发光器件(第一颜色光发光器件601)的像素电路PXC内置，即，位于第一显示区11，绿光发光器件(第一颜色光发光器件601)不设置引线17。
在显示面板中，引线的电容量差异较大。因连接位于第一显示区11的 各个发光器件的引线的长度不同，从而导致发不同颜色光的发光器件的电容量差异变化不同。与红光发光器件相连的引线的电容量差异和与蓝光发光器件相连的引线的电容量差异相比，与绿光发光器件相连的引线的电容量差异较大。因为与绿光发光器件相连的引线的电容量差异较大，造成绿光发光器件的发光时间减少，从而显示面板出现亮度差异，造成显示不良。在低灰阶下，绿光发光器件的不良程度大于红光发光器件的不良程度，且红光发光器件的不良程度大于蓝光发光器件的不良程度。例如，在相同灰阶下，驱动蓝光发光器件的驱动电流大于驱动红光发光器件的驱动电流，且驱动红光发光器件的驱动电流大于驱动绿光发光器件的驱动电流。
参考图12至图14，第二驱动电路161与第二发光器件132通过引线17相连，设置第二驱动电路161的区域可称为辅助区12a(如图14所示)。在第二显示区12的除了辅助区12a之外的区域12d(如图14所示)，可设置不与内置发光器件13，并且也不与第三发光器件15相连的虚设像素电路DPXC。
如图12和图14所示为外置和压缩结合的方案说明，通过将第一显示区域11内的发光器件相连的像素电路一部分内置，一部分外置来实现高透与显示设计兼容。一些显示面板，例如，含有距离传感器的显示面板需要具备：大孔径、高透过率、以及较轻的炫光衍射问题。通常，纯外置(全外置)方案无法解决第一显示区的大孔径，减少膜层数量和掩模版数量的问题。通过内置与外置方案结合方式，实现大孔径，即满足透过率需求又能满足衍射需求。
对于纯外置方案，需要的引线数量较大，例如，在一些显示面板中，对于第一显示区的左上部分来说，可能需要设置40条的引线，从而，需要设置三个透明导电层，而对于外置和内置结合的方案，只需要设置大约一半的引线即可，即，对于第一显示区的左上部分来说，需要设置20条的引线，该情况下，设置两个透明导电层即可完成引线布置，而且，引线的长度缩减一半。以上以第一显示区的左上部分需要设置40条的引线为例进行说明，引线的设置数量可根据需要调整为其他数值。
如图13所示，由于引线的长度对绿光发光器件的影响最大，从而，对于位于第一显示区11内的各个发光器件，与绿光发光器件相连的像素电路 内置(置于第一显示区11)，而与红光发光器件和蓝光发光器件相连的像素电路外置(置于第二显示区12)，红色子像素和蓝色子像素采用外置方式，即，绿色子像素的像素电路内置，以提升显示均一性。
对于图14所示的显示面板的其他结构，可参考图1的描述，在此不再赘述。
图15为本公开的实施例提供的显示面板的示意图。如图15所示，对于同一颜色光的发光器件，位于第一显示区11内的发光器件600的尺寸小于位于第二显示区12内的发光器件600的尺寸，以利于提高第一显示区11的透过率。同时，因为像素电路一部分内置，一部分外置，也可以提高第一显示区11的透过率。在图15的第一显示区11中，相邻的发光器件600之间的区域包括透光区域R0。即，在第一显示区11中，像素电路，透光区域R0位于相邻的发光器件600之间的区域。
图15以发光器件的第一电极E1示出该发光器件600。第一电极E1内的封闭线框表示发光器件600的发光区域EMR，发光区域EMR对应于像素定义层的开口OPN。
图16为本公开的实施例提供的显示面板中的位于第二显示区的像素电路的布局图。图17为本公开的实施例提供的显示面板中的位于第一显示区的像素电路的布局图。图18为本公开的实施例提供的显示面板中的位于第一显示区和第二显示区的像素电路的布局图。
图16至图18示出了像素电路PXC包括的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7、电容C的第一极Cb、以及电容C的第二极Ca。
参考图8、图16和图17，第一扫描信号线Ga1和第二扫描信号线Ga2为同一条信号线，即同为栅极信号线GA；第一复位控制信号线Rst1和第二复位控制信号线Rst2为同一条信号线，即同为复位控制信号线RST；第一发光控制信号线EM1和第二发光控制信号线EM2为同一条信号线，即同为发光控制信号线EML。
例如，如图16至图18所示，显示面板还包括与像素电路PXC(第一驱动电路14)连接的多条信号线，多条信号线中的至少一条信号线分段设 置。
如图16至图18所示，第一电源线Vdd、发光控制信号线EML、复位控制信号线RST、以及复位信号线INT2中的至少一个采用分段设置。图18以第一电源线Vdd、发光控制信号线EML、复位控制信号线RST、以及复位信号线INT2均采用分段设置为例进行说明。
例如，复位信号线INT1与第一复位电源端Vinit1相连，复位信号线INT2与第二复位电源端Vinit2相连。例如，在本公开的一些实施例中，复位信号线INT2与第一复位电源端Vinit1或第二复位电源端Vinit2相连。
如图18所示，发光控制信号线EML包括发光控制信号部EMLa、发光控制信号部EMLb、以及发光控制信号部EMLc。发光控制信号部EMLa位于第二显示区12，发光控制信号部EMLb以及发光控制信号部EMLc位于第一显示区，相邻的发光控制信号部EMLc通过发光控制信号部EMLb相连，发光控制信号部EMLa和与其相邻的发光控制信号部EMLc通过发光控制信号部EMLb相连。
如图18所示，复位控制信号线RST包括复位控制信号部RSTa、复位控制信号部RSTb、以及复位控制信号部RSTc。复位控制信号部RSTa位于第二显示区12，复位控制信号部RSTb以及复位控制信号部RSTc位于第一显示区，相邻的复位控制信号部RSTc通过复位控制信号部RSTb相连，复位控制信号部RSTa和与其相邻的复位控制信号部RSTc通过复位控制信号部RSTb相连。
如图18所示，复位信号线INT2包括复位信号部INTa、复位信号部INTb、以及复位信号部INTc。复位信号部INTa位于第二显示区12，复位信号部INTb以及复位信号部INTc位于第一显示区，相邻的复位信号部INTc通过复位信号部INTb相连，复位信号部INTa和与其相邻的复位信号部INTc通过复位信号部INTb相连。
例如，如图16至图18所示，分段设置的信号线包括位于不同层的多个信号部。
例如，如图16至图18所示，分段设置的信号线包括第一信号部和第二信号部，第一信号部的材料包括透明的导电金属氧化物，第二信号部的材料包括金属。例如，复位信号部INTc、复位控制信号部RSTc、以及发光 控制信号部EMLc中至少之一可称作第一信号部P1，复位信号部INTa、复位信号部INTb、复位控制信号部RSTa、复位控制信号部RSTb、发光控制信号部EMLa、以及发光控制信号部EMLb可称作第二信号部P2。当然，第一信号部P1和第二信号部P2不限于上述描述，可根据需要进行设置。
例如，如图18所示，第一显示区11包括驱动电路设置区1101和走线区1102，第一信号部P1位于驱动电路设置区1101，第二信号部P2位于走线区1102。
例如，参考图1、图8、图15、图16至图18，显示面板还包括发光控制信号线EML、复位控制信号线RST、以及复位信号线INT2，像素电路PXC包括驱动模块222、发光控制电路223、发光控制电路224、以及复位电路229，像素电路PXC包括第一驱动电路14、第二驱动电路161、以及第三驱动电路162中至少一个，发光控制信号线EML与发光控制电路223的控制端和发光控制电路224的控制端至少之一相连，复位控制信号线RST与复位电路229的控制端相连，复位信号线INT2与复位电路229的第一极相连，发光控制信号线EML、复位控制信号线RST、以及复位信号线INT2中至少之一在第一显示区11分段设置。
例如，参考图1、图8、图15、图16至图18，复位电路229包括第一复位晶体管T6和第二复位晶体管T7，第一复位晶体管T6被配置为对驱动模块222的控制端进行复位，第二复位晶体管T7被配置为对发光器件600的第一电极进行复位，发光器件600包括第一发光器件131、第二发光器件132、以及第三发光器件中至少之一。如图17和图18所示，在同一个像素电路中，第一复位晶体管T6和第二复位晶体管T7共用同一条复位信号线INT2，以被配置为提供同一复位信号。例如，发光器件600为图8中的发光器件220。
图17示出了连接电极CE1、连接电极CE2、以及连接电极CE3。如图17所示，连接电极CE1的一端与复位信号线INT2相连，连接电极CE1的另一端与第二复位晶体管T7的第一极相连，连接电极CE2的一端与第二复位晶体管T7的第二极相连，连接电极CE2的另一端与第二发光控制晶体管T5的第二极相连。如图17所示，连接电极CE3的一端与第一复位晶体管T6的第二极相连，连接电极CE3的另一端与驱动晶体管T1的栅极相连。
例如，参考图16至图18，第二驱动电路161和第三驱动电路162的布局相同，第一驱动电路14的布局与第二驱动电路161或第三驱动电路162的布局不同。调整第一驱动电路14的布局，以利于提升第一显示区的透过率。
图16至图18示出了复位信号线INT1和复位信号线INT2。复位信号线INT1与第一复位电源端Vinit1相连，复位信号线INT2与第二复位电源端Vinit2相连。图16至图18以复位信号线INT作为复位信号线INT1和复位信号线INT2为例进行说明。
图19为图18的沿线B1-B2的截面图。图20为图16中的有源层的平面图。图21为图16中的第一导电层的平面图。图22为图16中的第二导电层的平面图。图23为图16中的第三导电层的平面图。图24为图16中的第四导电层的平面图。图25为图16中的有源层和第一导电层的叠层平面图。图26为图16中的有源层、第一导电层、以及第二导电层的叠层平面图。图27为图16中的第三导电层和第四导电层的叠层平面图。图28为图16中的第三导电层、第四导电层以及其间的绝缘层中的过孔的叠层平面图。图29为图16中的有源层、第三导电层、第四导电层以及位于第三导电层和第四导电层之间的绝缘层中的过孔的叠层平面图。图30为图16中的有源层、第三导电层、第四导电层、位于有源层和第三导电层之间的绝缘层中的过孔VH1、以及位于第三导电层和第四导电层之间的绝缘层中的过孔VH2的叠层平面图。图31为本公开的实施例提供的显示面板的第一显示区内的有源层的平面图。图32为本公开的实施例提供的显示面板的第一显示区内的第一导电层的平面图。图33为本公开的实施例提供的显示面板的第一显示区内的第二导电层的平面图。图34为本公开的实施例提供的显示面板的第一显示区内的第三导电层的平面图。图35为本公开的实施例提供的显示面板的第一显示区内的第四导电层的平面图。图36为本公开的实施例提供的显示面板的第一显示区内的透明导电层的平面图。
图20和图31示出了有源层LY0。图21和图32示出了第一导电层LY1。图22和图33示出了第二导电层LY2。图23和图34示出了第三导电层LY3。图24和图35示出了第四导电层LY4。图36示出了透明导电层LYx。
如图19所示，显示面板包括衬底基板BS，阻隔层BR位于衬底基板BS 上，缓冲层BF位于阻隔层BR上，有源层LY0位于缓冲层BF上。如图19所示，有源层LY0包括第二复位晶体管T7的沟道T7c、位于沟道T7c的两侧的第一极T71和第二极T72、第二发光控制晶体管T5的沟道T5c、以及位于沟道T5c两侧的第一极T51和第二极T52。如图19所示，绝缘层801位于有源层LY0上，第一导电层LY1位于绝缘层801上。图19示出了第一导电层LY1中的复位控制信号部RSTb、栅极信号线GA、以及发光控制信号部EMLb。如图19所示，绝缘层802位于第一导电层LY1上，第二导电层LY2位于绝缘层802上。图19示出了第二导电层LY2中的复位信号部INTb。如图19所示，绝缘层803位于第二导电层LY2上，第三导电层LY3位于绝缘层803上。图19示出了第三导电层LY3中的连接电极CE1和连接电极CE2。如图19所示，连接电极CE1的一端与复位信号部INTb相连，连接电极CE1的另一端与第二复位晶体管T7的第一极T71相连，连接电极CE2的一端与第二复位晶体管T7的第二极T72相连，连接电极CE2的另一端与第二发光控制晶体管T5的第二极T52相连。如图19所示，绝缘层804位于第三导电层LY3上，第四导电层LY4位于绝缘层804上。图19示出了第四导电层LY4中的连接电极CE11和连接电极CE12。如图19所示，连接电极CE11与连接电极CE1相连，连接电极CE12与连接电极CE2相连。如图19所示，绝缘层805位于第四导电层LY4上，透明导电层LYx位于绝缘层805上。图19示出了透明导电层LYx中的复位信号部INTc和连接电极CEx。连接电极CEx与连接电极CE12相连，复位信号部INTc与连接电极CE11相连。
如图19所示，绝缘层804可以包括至少一个绝缘层。图19以绝缘层804包括钝化层PVX和平坦化层PLN为例进行说明。
如图19所示，绝缘层801也可称作栅绝缘层GI1，绝缘层802也可称作栅绝缘层GI2，绝缘层803也可称作层间绝缘层ILD。
如图21所示，第一导电层LY1包括复位控制信号线RST、栅极信号线GA、电容C的第二极Ca、以及发光控制信号线EML。
如图22所示，第二导电层LY2包括复位信号线INT2、挡块BK、以及电容C的第一极Cb。
如图16所示，挡块BK通过过孔V5与第一电源线Vdd相连。挡块BK 起到稳定阈值补偿晶体管T3的两个沟道之间的中间节点的电压的作用。
在本公开的实施例中，第一电源线Vdd与第一电压端VDD相连。
参照图16、图21至图23，电容C的第一极Cb具有开口Cb0，以便于连接电极CEd与电容C的第二极Ca相连。
如图23所示，第三导电层LY3包括数据线Vd、第一电源线Vdd、复位信号线INT1、连接电极CEa、连接电极CEb、连接电极CEc、以及连接电极CEd。
如图24所示，第四导电层LY4包括连接电极CEe、连接电极CEf、以及屏蔽电极CEg。
图25示出了各个晶体管，有源层LY0的被第一导电层LY1覆盖的部分为晶体管的沟道，沟道两侧分别为晶体管的第一极和第二极，电容C的第二极Ca同时作为驱动晶体管T1的栅极，栅极信号线GA的一部分作为数据写入晶体管T2的栅极，栅极信号线GA的一部分作为阈值补偿晶体管T3的栅极，发光控制信号线EML的一部分作为第一发光控制晶体管T4的栅极，发光控制信号线EML的一部分作为第二发光控制晶体管T5的栅极，复位控制信号线RST的一部分作为第一复位晶体管T6的栅极，复位控制信号线RST的一部分作为第二复位晶体管T7的栅极。
参考图16、图23、图24、图27至图30，连接电极CEe的一端与连接电极CEb通过过孔V12相连，连接电极CEe的另一端与连接电极CEc通过过孔V13相连，连接电极CEf与第一电源线Vdd通过过孔V15相连，屏蔽电极CEg在衬底基板上的正投影覆盖连接电极CEd在衬底基板上的正投影，以稳定驱动晶体管的栅极上的电压。
参考图16、图23、图24、以及图30，连接电极CEa的一端与复位信号线INT(复位信号线INT2)通过过孔V1相连，连接电极CEa的另一端与第二复位晶体管T7的第一极的通过过孔V2相连。
参考图16、图23、图24、以及图30，连接电极CEb的一端与第二复位晶体管T7的第二极通过过孔V3相连。
参考图16、图23、图24、以及图30，连接电极CEc的一端与第二发光控制晶体管T5的第二极通过过孔V11相连。
参考图16、图23、图24、以及图30，连接电极CEd的一端与第一复位 晶体管T6的第二极通过过孔V7相连，连接电极CEd的另一端与驱动晶体管T1的栅极通过过孔V8相连。
参考图16、图23、以及图30，第一电源线Vdd与电容C的第一极Cb通过过孔V9相连。第一电源线Vdd与第一发光控制晶体管T4的第一极通过过孔V10相连。
参考图16、图23、以及图30，数据线Vd与数据写入晶体管T2的第二极通过过孔V6相连。
参考图16、图23、图24、以及图30，复位信号线INT1与第一复位晶体管T6的第一极通过过孔V4相连。
如图16所示，位于透明导电层LYx的连接电极CE01通过过孔V14与连接电极CEc相连。
参考图16、图22、图23、图27至图30，复位信号线INT1与复位信号线INT2位于不同层，例如，复位信号线INT1位于第三导电层LY3，复位信号线INT2位于第二导电层LY2。
参考图16、图23、图24、图27至图30，复位信号线INT1与复位信号线INT2相交。例如，复位信号线INT1与复位信号线INT2垂直。
如图30所示，位于有源层和第三导电层之间的绝缘层中的过孔VH1包括过孔V1至V11，位于第三导电层和第四导电层之间的绝缘层中的过孔VH2包括过孔V12、过孔V13、以及过孔V15。
例如，绝缘层801、绝缘层802、绝缘层803、绝缘层804、绝缘层805均可采用绝缘材料制作。在本公开的实施例中，衬底基板可采用柔性衬底基板，材料包括聚酰亚胺，但不限于此。
图18中的“Normal”表示像素电路位于第二显示区12，图中的“R”表示与红光发光器件相连的像素电路，“B”表示与蓝光发光器件相连的像素电路。图18示出了部分子像素的像素电路，其余的像素电路可根据其位置对应参照图18所示的像素电路的结构。
图31至图36示出了本公开的实施例提供的显示面板中的位于第一显示区11中的单个膜层的平面图。以下参照图17、图18、图31至图36对位于第一显示区11中的像素电路PXC(第一驱动电路14)的结构进行描述。图31至图36示出了三个像素电路PXC(第一驱动电路14)。
图31示出了有源层LY0。参考图20和图31，图20所示的有源层LY0的位于第二显示区的部分与图31所示的有源层LY0的位于第一显示区的部分具有不同的结构。从而，参照图16和图17，第一驱动电路14的结构与外置驱动电路16的结构不同。
图17示出了过孔Va至过孔Vk。
参考图17、图33、以及图34，连接电极CE1的一端与复位信号线INT2通过过孔Va相连，连接电极CE1的另一端与第二复位晶体管T7的第一极通过过孔Vb相连，连接电极CE2的一端与第二复位晶体管T7的第二极通过过孔Vc相连，连接电极CE2的另一端与第二发光控制晶体管T5的第二极通过过孔Vd相连。
参考图17、图33、以及图34，连接电极CE3的一端与第一复位晶体管T6的第二极通过过孔Ve相连，连接电极CE3的另一端与驱动晶体管T1的栅极通过过孔Vf相连。
参考图17、图33、以及图34，第一电源线Vdd与电容C的第一极Cb通过过孔Vg相连。
参考图17、图33、以及图34，连接电极CE4的一端与第一发光控制晶体管T4的第一极通过过孔Vh相连，连接电极CE4的另一端与第一电源线Vdd通过过孔Vi相连。
参考图17、图33、以及图34，数据线Vd与数据写入晶体管T2的第二极通过过孔Vj相连。
参考图17、图35、以及图36，第一电源线Vdd包括：连接电极CE10(电源部Vddc)、电源部Vdda、以及电源部Vddb，且连接电极CE10(电源部Vddc)与电源部Vdda通过过孔Vk相连，连接电极CE10(电源部Vddc)与电源部Vddb通过过孔Vi相连。第一电源线Vdd采用位于不同层的不同材质的材料制作，利于提升第一显示区的透过率。当然，在其他的实施例中，第一电源线Vdd也可不分段设置。
参考图17、图33、以及图36，复位信号部INTc与复位信号部INTb通过过孔Vaa相连。
图34还示出了连接电极CE5、连接电极CE6、连接电极CE7、连接电极CE8、以及连接电极CE9。连接电极CE5、连接电极CE6、连接电极CE7、 连接电极CE8、以及连接电极CE9均作为中间元件，用于与对应位置的位于第四导电层LY4中的元件相连。
图35还示出了连接电极CE11、连接电极CE12、连接电极CE15、连接电极CE16、连接电极CE17、连接电极CE18、连接电极CE19。
参考图18、图34、以及图35，连接电极CE11与连接电极CE1相连，例如与连接电极CE1的上端相连；连接电极CE12与连接电极CE2相连，例如，与连接电极CE2的下端相连；连接电极CE15与连接电极CE5相连，连接电极CE16与连接电极CE6相连，连接电极CE17与连接电极CE7相连，连接电极CE18与连接电极CE8相连，连接电极CE19与连接电极CE9相连。位于第四导电层LY4中的元件和位于第三导电层LY3中的元件通过贯穿第三导电层LY3和第四导电层LY4之间的绝缘层的过孔相连。
参考图18、图34至图36，复位控制信号部RSTb与连接电极CE18通过过孔相连，连接电极CE18与连接电极CE8通过过孔相连，连接电极CE8通过过孔与复位控制信号部RSTc相连。连接电极CE18和连接电极CE8均作为中间连接件。该设置方式使得复位控制信号线可以包括材质不同的至少两种材料，以便于提升第一显示区的透过率。当然，在其他的实施例中，复位控制信号线也可以由位于同一层的相同材料形成，而不采用分段方式形成。同样的，连接电极CE6和连接电极CE16作为复位控制信号部RSTb的另一端的中间连接件，在此不再赘述。
参考图18、图34至图36，复位信号部INTb与连接电极CE1通过过孔相连，连接电极CE1与连接电极CE11通过过孔相连，连接电极CE11通过过孔与复位信号部INTc相连。连接电极CE1和连接电极CE11均作为中间连接件。该设置方式使得复位控制信号线可以包括材质不同的至少两种材料，以便于提升第一显示区的透过率。当然，在其他的实施例中，复位信号线也可以由位于同一层的相同材料形成，而不采用分段方式形成。同样的，连接电极CE7和连接电极CE17作为复位信号部INTb的另一端的中间连接件，在此不再赘述。
参考图18、图34至图36，发光控制信号部EMLb与连接电极CE9通过过孔相连，连接电极CE9与连接电极CE19通过过孔相连，连接电极CE19通过过孔与发光控制信号部EMLc相连。连接电极CE9和连接电极CE19 均作为中间连接件。该设置方式使得复位控制信号线可以包括材质不同的至少两种材料，以便于提升第一显示区的透过率。当然，在其他的实施例中，复位信号线也可以由位于同一层的相同材料形成，而不采用分段方式形成。同样的，连接电极CE5和连接电极CE15作为发光控制信号部EMLb的另一端的中间连接件，在此不再赘述。
参考图18、图34至图36，连接电极CE2通过过孔与连接电极CE12相连，连接电极CE12通过过孔与连接电极CE20相连。连接电极CE20可与发光器件的第一电极相连。
在信号线例如第一电源线Vdd、发光控制信号线EML、复位控制信号线RST、以及复位信号线INT2中的至少一个采用分段设置的情况下，各条信号线所在的透明导电层可比引线17所在的透明导电层更靠近衬底基板。
如图17和图18所示，对于位于第一显示区11的像素电路，第二复位晶体管T7、数据写入晶体管T2、阈值补偿晶体管T3的控制线均为栅极信号线GA。第二复位晶体管T7、数据写入晶体管T2、阈值补偿晶体管T3的栅极均与栅极信号线GA相连。如图17和图18所示，对于位于第一显示区11的像素电路，第一复位晶体管T6栅极和第二复位晶体管T7的栅极不相连，可被分别输入信号。
如图16和图18所示，对于位于第二显示区12的像素电路，第一复位晶体管T6和第二复位晶体管T7的控制线均为复位控制信号线RST。即，第一复位晶体管T6栅极和第二复位晶体管T7的栅极相连。
参考图16至图18，复位信号线INT2从第二显示区12延伸至第一显示区11并作为位于第一显示区11的像素电路的第一复位晶体管T6和第二复位晶体管T7的复位信号线。即，位于第一显示区11的像素电路的第一复位晶体管T6和第二复位晶体管T7共用同一条复位信号线，以被配置为提供同一复位信号。该同一条复位信号线可提供同一复位信号即可。该同一条复位信号线可分段设置，由位于不同层的部分通过过孔相连。参考图16至图18，位于第二显示区12的一个像素电路具有两条复位信号线(复位信号线INT2和复位信号线INT1)，而沿第一方向X延伸的复位信号线INT2从第二显示区12延伸至第一显示区11并作为位于第一显示区11的像素电路的第一复位晶体管T6和第二复位晶体管T7的复位信号线。
图37A为本公开的实施例提供的一种显示面板的示意图。图37B为本公开的实施例提供的一种显示面板的布局图。图38为本公开的实施例提供的显示面板中的有源层LY0的平面图。图39为本公开的实施例提供的显示面板中的第一导电层LY1的平面图。图40为本公开的实施例提供的显示面板中的第二导电层LY2的平面图。图41为本公开的实施例提供的显示面板中的第三导电层LY3的平面图。图42为本公开的实施例提供的显示面板中的第四导电层LY4的平面图。图43为本公开的实施例提供的显示面板中的透明导电层LYa的平面图。图44为本公开的实施例提供的显示面板中的透明导电层LYb的平面图。图45为本公开的实施例提供的显示面板中的有源层LY0和第一导电层LY1的叠层平面图。图46为本公开的实施例提供的显示面板中的有源层LY0、第一导电层LY1、以及第二导电层LY2的叠层平面图。图47为本公开的实施例提供的显示面板中的有源层LY0、第一导电层LY1、第二导电层LY2、以及第三导电层LY3的叠层平面图。图48为本公开的实施例提供的显示面板中的有源层LY0、第一导电层LY1、第二导电层LY2、第三导电层LY3、以及第四导电层LY4的叠层平面图。图49为本公开的实施例提供的显示面板中的有源层LY0、第一导电层LY1、第二导电层LY2、第三导电层LY3、第四导电层LY4、以及透明导电层LYa的叠层平面图。
图37B为本公开的实施例提供的一种显示面板中的有源层LY0、第一导电层LY1、第二导电层LY2、第三导电层LY3、第四导电层LY4、透明导电层LYa、以及明导电层LYb的叠层平面图。图49为图37B中的有源层LY0、第一导电层LY1、第二导电层LY2、第三导电层LY3、第四导电层LY4、以及透明导电层LYa的叠层平面图。
如图1和图37A所示，显示面板包括第一驱动电路14、与第一驱动电路14相连的第一发光器件131、以及第二发光器件132。图37A以椭圆形的虚线框示出发光器件的第一电极E1，并以该第一电极E1表示发光器件。第一电极E1的形状不限于图中所示，第一电极E1的尺寸也不限于图中所示，可根据需要而定。图37A示出了第一显示区11的一部分。图37A示出了相邻的发光器件之间的区域包括透光区域R0。
图37B为图37A的像素电路的布局图。图37B所示的像素电路图可参照图8。
图38示出了有源层LY0。图39示出了第一导电层LY1。图40示出了第二导电层LY2。图41示出了第三导电层LY3。图42示出了第四导电层LY4。图43示出了透明导电层LYa。图44示出了透明导电层LYb。
图37A、图37B、图47至图49示出了连接不同层的部件的过孔。
在本公开的实施例中，有源层LY0、第一导电层LY1、第二导电层LY2中位于不同层的部件之间的连接通过位于第三导电层LY3中的部件来实现。第四导电层LY4中的部件与第三导电层LY3中的部件通过贯穿位于第三导电层LY3和第四导电层LY4之间的绝缘层的过孔来连接。透明导电层LYa中的部件与第四导电层LY4中的部件通过贯穿位于透明导电层LYa和第四导电层LY4之间的绝缘层的过孔来连接。透明导电层LYa中的部件与透明导电层LYb中的部件通过贯穿位于透明导电层LYa和透明导电层LYb之间的绝缘层的过孔来连接。
如图39所示，第一导电层LY1包括复位控制信号线RST(复位控制信号线RST1和复位控制信号线RST2)、栅极信号线GA、电容C的第二极Ca、以及发光控制信号线EML。在同一行子像素中，复位控制信号线RST与栅极信号线GA相连。
如图40所示，第二导电层LY2包括复位信号线INT1、复位信号线INT2、挡块BK、以及电容C的第一极Cb。复位信号线INT1和复位信号线INT2均可称作复位信号线INT。电容C的第一极Cb具有开口Cb0。
如图48所示，挡块BK通过过孔与第一电源线Vdd相连。挡块BK起到稳定阈值补偿晶体管T3的两个沟道之间的中间节点的电压的作用。在本公开的实施例中，第一电源线Vdd与第一电压端VDD相连。
参照图37B、图40、图41、图46至图49，电容C的第一极Cb具有开口Cb0，以便于连接电极EC1与电容C的第二极Ca相连。
如图41所示，第三导电层LY3包括信号线SL1、信号线SL2、连接电极EC1、连接电极EC2、连接电极EC3、连接电极EC4、连接电极EC5、连接电极EC6、以及连接电极EC7。
如图42所示，第四导电层LY4包括数据线Vd、第一电源线Vdd、连接电极EC0。
参照图37B、图40、图41、图46至图49，第一电源线Vdd在衬底基板 上的正投影与连接电极EC1在衬底基板上的正投影交叠，以稳定驱动晶体管的栅极上的电压。
图45示出了各个晶体管。图45示出了驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7。
如图45所示，有源层LY0的被第一导电层LY1覆盖的部分为晶体管的沟道(半导体)，沟道两侧分别为晶体管的第一极(导体部)和第二极(体部)，电容C的第二极Ca同时作为驱动晶体管T1的栅极，栅极信号线GA的一部分作为数据写入晶体管T2的栅极，栅极信号线GA的一部分作为阈值补偿晶体管T3的栅极，发光控制信号线EML的一部分作为第一发光控制晶体管T4的栅极，发光控制信号线EML的一部分作为第二发光控制晶体管T5的栅极，复位控制信号线RST的一部分作为第一复位晶体管T6的栅极，复位控制信号线RST的一部分作为第二复位晶体管T7的栅极。
参考图8、图41、图46至图49，连接电极EC1的一端与驱动晶体管T1的栅极通过过孔相连，连接电极EC1的另一端与第一复位晶体管T6的第二极通过过孔相连。
参考图8、图41、图42、图46至图49，连接电极EC2的一端与挡块BK通过过孔相连，连接电极EC2的另一端与第一电源线Vdd通过过孔相连。
参考图8、图41、图42、图46至图49，连接电极EC3的一端与数据写入晶体管T2的第二极通过过孔相连，连接电极EC3的另一端与数据线Vd通过过孔相连。
参考图8、图41、图42、图46至图49，连接电极EC4的一端与第二发光控制晶体管T5的第二极通过过孔相连，连接电极EC4的另一端与连接电极EC0相连。
参考图8、图41、图42、图46至图49，连接电极EC5的一端与第一发光控制晶体管T4的第一极通过过孔相连，连接电极EC5的另一端第一电源线Vdd通过过孔相连。
参考图8、图41、图46至图49，连接电极EC6的一端与第二复位晶体管T7的第一极通过过孔相连，连接电极EC6的另一端与复位信号线INT2通过过孔相连。
参考图8、图41、图46至图49，连接电极EC7的一端与第一复位晶体管T6的第一极通过过孔相连，连接电极EC7的另一端与复位信号线INT1通过过孔相连。
如图41、图46至图49所示，信号线SL2与发光控制信号线EML通过过孔相连。
如图43和图44所示，连接电极ECa与连接电极EC0通过过孔相连，连接电极ECa可用于与连接电极ECb相连，进而与第一发光器件131连接。
如图43所示，透明导电层LYa包括多条引线17。多条引线17包括引线17a、引线17b、以及引线17c。如图43所示，引线17a示出了左右两端。参考图1和图43，引线17a的左端用于与第二驱动电路161相连，引线17a的右端用于与第二发光器件132相连。如图43所示，引线17b示出了其右端，引线17c示出了其中间部分，未示出其左右两端。
如图43和图44所示，连接电极ECb与连接电极ECa通过过孔相连。图44中的引线17c示出了其中间部分，未示出其左右两端。
图50为本公开的实施例提供的一种显示面板的平面结构示意图。图51为本公开的实施例提供的一种显示面板的局部平面结构示意图。图52为本公开的实施例提供的一种显示面板的平面结构示意图。图53为本公开的实施例提供的一种显示面板的局部平面结构示意图。
如图50至图52所示，第一显示区11包括多个内置发光器件13和至少一个第一驱动电路14，多个内置发光器件13包括第一发光器件131和第二发光器件132，第一驱动电路14与第一发光器件131连接，第一驱动电路14被配置为驱动第一发光器件131发光。
如图50至图52所示，第二显示区12包括至少一个第三发光器件15和多个外置驱动电路16，多个外置驱动电路16包括第二驱动电路161和第三驱动电路162，第二驱动电路161与第二发光器件132通过引线17连接，第二驱动电路161被配置为驱动第二发光器件132发光，第三驱动电路162与第三发光器件15连接，第三驱动电路162被配置为驱动第三发光器件15发光。
如图50至图53所示，第一显示区11具有对称轴X1，例如，对称轴X1沿第二方向Y延伸。第一显示区11还可以具有对称轴X2，对称轴X2沿第 一方向X延伸。
如图50和图51所示，在第一显示区11中，位于对称轴X1的一侧的发光器件全部采用引线连接的方式(像素电路外置，压缩方案)，即，发光器件和像素电路分离设置的方式，而位于对称轴X1的另一侧的发光器件全部采用像素电路内置(内置方案)的方式。即，在第一显示区11中，位于对称轴X1左侧的发光器件均采用像素电路外置的方式，而位于对称轴X1右侧的发光器件均采用像素电路内置的方式。但不限于此。也可以根据对称轴X2来进行划分。例如，位于对称轴X2的一侧的发光器件全部采用引线连接的方式(像素电路外置，压缩方案)，即，发光器件和像素电路分离设置的方式，而位于对称轴X2的另一侧的发光器件全部采用像素电路内置(内置方案)的方式。即，将第一显示区11划分为两个子区，其中一个子区采用内置方案，另一个子区采用压缩方案。
如图52和图53所示，在第一显示区11中，内置发光器件13包括多个第一发光器件组G1和多个第二发光器件组G2，多个第一发光器件组G1和多个第二发光器件组G2交替设置，第一发光器件组G1中的发光器件(第一发光器件131)采用像素电路内置的方式，多个第二发光器件组G2中的发光器件(第二发光器件132)采用像素电路和发光器件分离设置的方式。
图52和图53以第一发光器件组G1包括两列发光器件，第二发光器件组G2包括两列发光器件为例进行说明。例如，在第一发光器件组G1中，其中一列发光器件为绿光发光器件，另一列为交替设置的红光发光器件和蓝光发光器件。例如，在第二发光器件组G2中，其中一列发光器件为绿光发光器件，另一列为交替设置的红光发光器件和蓝光发光器件。
例如，第一发光器件组G1包括至少一列第一发光器件131，第二发光器件组G2包括至少一列第二发光器件132。
图50以每隔四列第三驱动电路162设置一列第二驱动电路161为例进行说明，图52以每隔两列第三驱动电路162设置一列第二驱动电路161为例进行说明，需要说明的是，相邻两列第二驱动电路161之间设置的第三驱动电路162的列数可根据需要设置，不限于图中所示。
为了清楚起见，图50和图52未示出第二显示区21内的全部结构。
本公开的实施例提供一种显示装置，包括：感光元件以及如上所述的任 一显示面板。
例如，感光元件在显示面板上的正投影与第一显示区有交叠。
例如，感光元件可以包括感测模块，感测模块可以包括例如红外线感测模块；从红外线图像识别特定的图案(例如，指纹图案、虹膜图案等)。在实施方式中，感测模块可以执行面部识别。
例如，感光元件可以包括光学构件，光学构件可以包括照度传感器。照度传感器可以测量显示设备周围的照度，并且显示设备可以基于所测量的照度来调节屏幕的亮度。
例如，感光元件可以包括传感器，传感器可以是利用光或声音的电子元件。例如，传感器可以是用于接收并利用光的传感器(例如红外传感器)、用于通过输出并检测光或声音来测量距离或识别指纹的传感器、用于输出光的小型灯、用于输出声音的扬声器和/或用于拍摄图像的相机。传感器设备的数量可以被提供为多个。
例如，传感器包括红外线传感器、超声波传感器、激光雷达(Light Detection and Ranging，LIDAR)传感器、雷达(Radar)传感器、摄像头传感器。
例如，感光元件包括屏下摄像头或距离传感器，但不限于此。
例如，距离传感器包括(Time of Flight，TOF)传感器。TOF即Time of flight，是利用光的飞行时间来测量距离的技术，目前已广泛应用在智能手机的面部识别等领域。
本领域技术人员可以理解，该显示装置具有前面所述显示面板的所有特征和优点。
在一些实施例中，该显示装置的具体种类包括但不限于手机、笔记本、iPad、kindle、电视等具有显示和拍照功能的显示装置。
本领域技术人员可以理解，该显示装置除了前面所述的显示面板，还可以包括常规显示装置所必备的结构或部件，以手机为例，除了前面所述的显示面板，还包括玻璃盖板、电池后盖、中框、主板、触控模组、音频模组、摄像模组等必备的结构或部件。
例如，第一方向X为平行于衬底基板40的主表面的方向。第二方向Y为平行于衬底基板40的主表面的方向。第一方向X与第二方向Y相交。本公开的实施例以第一方向X垂直于第二方向Y为例进行说明。第三方向Z 为垂直于衬底基板40的主表面的方向。衬底基板40的主表面为用于制作各个膜层的表面。例如，图4中的衬底基板40的上表面即为其主表面。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
需要说明的是，为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
本公开的实施例中，同层设置的元件由同一膜层采用同一构图工艺形成。例如，同层设置的元件位于同一元件的远离衬底基板的表面，但不限于此。同层设置的元件可相对于衬底基板具有不同的高度。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种显示面板，包括第一显示区和第二显示区，其中，所述第二显示区位于所述第一显示区的至少一侧，所述第一显示区的透过率大于所述第二显示区的透过率；
    所述第一显示区包括多个内置发光器件和至少一个第一驱动电路，所述多个内置发光器件包括第一发光器件和第二发光器件，所述第一驱动电路与所述第一发光器件连接，所述第一驱动电路被配置为驱动所述第一发光器件发光；
    所述第二显示区包括至少一个第三发光器件和多个外置驱动电路，所述多个外置驱动电路包括第二驱动电路和第三驱动电路，所述第二驱动电路与所述第二发光器件通过引线连接，所述第二驱动电路被配置为驱动所述第二发光器件发光，所述第三驱动电路与所述第三发光器件连接，所述第三驱动电路被配置为驱动所述第三发光器件发光。
  2. 根据权利要求1所述的显示面板，其中，所述第三发光器件的数量为多个，在第一方向上，所述外置驱动电路和所述第三发光器件均呈周期性排布，所述外置驱动电路的排布周期小于所述第三发光器件的排布周期。
  3. 根据权利要求2所述的显示面板，其中，所述外置驱动电路的排布周期与所述第三发光器件的排布周期之间的比值大于或等于1/2，且小于或等于9/10。
  4. 根据权利要求1至3任一项所述的显示面板，其中，所述第一发光器件包括设置在衬底基板上的第一阳极层，所述第三发光器件包括设置在所述衬底基板上的第二阳极层；
    其中，所述第一驱动电路在所述衬底基板上的正投影面积与所述第一阳极层在所述衬底基板上的正投影面积之间的比值，小于所述第三驱动电路在所述衬底基板上的正投影面积与所述第二阳极层在所述衬底基板上的正投影面积之间的比值。
  5. 根据权利要求4所述的显示面板，其中，所述第一阳极层在所述衬底基板上的正投影覆盖所述第一驱动电路在所述衬底基板上的正投影。
  6. 根据权利要求1至5任一项所述的显示面板，其中，所述第一显示 区被划分为两个子区，其中一个子区内的发光器件均为第一发光器件，另一个子区内的发光器件均为第二发光器件。
  7. 根据权利要求1至5任一项所述的显示面板，其中，所述第一发光器件设置为多个，所述第二发光器件设置为多个，多个第一发光器件构成多个第一发光器件组，多个第二发光器件构成多个第二发光器件组，多个第一发光器件组和多个第二发光器件组交替排布，所述第一发光器件组包括至少一列第一发光器件，所述第二发光器件组包括至少一列第二发光器件。
  8. 根据权利要求1至7任一项所述的显示面板，其中，所述第一发光器件包括绿光发光器件和/或蓝光发光器件；所述第二发光器件包括以下至少之一：绿光发光器件，蓝光发光器件和红光发光器件。
  9. 根据权利要求1至7任一项所述的显示面板，其中，所述第一发光器件包括红光发光器件和/或蓝光发光器件；所述第二发光器件包括以下至少之一：绿光发光器件，蓝光发光器件和红光发光器件。
  10. 根据权利要求1至7任一项所述的显示面板，其中，所述第一发光器件包括绿光发光器件和/或红光发光器件；所述第二发光器件包括以下至少之一：绿光发光器件，蓝光发光器件和红光发光器件。
  11. 根据权利要求1至7任一项所述的显示面板，其中，所述第一发光器件的数量大于或等于所述第二发光器件的数量。
  12. 根据权利要求1至7任一项所述的显示面板，其中，所述第二发光器件包括第一颜色光发光器件、第二颜色光发光器件和第三颜色光发光器件，连接所述第一颜色光发光器件与所述第二驱动电路的引线为第一引线，连接所述第二颜色光发光器件与所述第二驱动电路的引线为第二引线，连接所述第三颜色光发光器件与所述第二驱动电路的引线为第三引线，所述第一引线的面积小于或等于所述第二引线的面积，所述第二引线的面积小于或等于第三引线的面积。
  13. 根据权利要求1至7任一项所述的显示面板，其中，所述第一发光器件包括第一颜色光发光器件，所述第二发光器件包括第二颜色光发光器件和第三颜色光发光器件，并且所述第一颜色光发光器件、所述第二颜色光发光器件和所述第三颜色光发光器件被配置为发不同颜色的光。
  14. 根据权利要求13所述的显示面板，其中，所述第一发光器件包括绿光发光器件，所述第二发光器件包括红光发光器件和蓝光发光器件。
  15. 根据权利要求13或14所述的显示面板，其中，所述引线包括第一导电线和第二导电线，所述第一导电线与所述第二颜色光发光器件相连，所述第二导电线与所述第三颜色光发光器件相连。
  16. 根据权利要求1至15任一项所述的显示面板，其中，与所述第一驱动电路连接的信号线包括第一线段和第二线段，所述第一线段与所述第二线段连接，所述第一线段位于所述第一显示区内，所述第二线段位于所述第二显示区内，所述第一线段的材料包括透明导电材料，所述第二线段的材料包括金属材料。
  17. 根据权利要求16所述的显示面板，其中，所述引线的材料包括透明导电材料，且所述引线与所述第一线段分别位于不同的膜层。
  18. 根据权利要求1至17任一项所述的显示面板，还包括与所述第一驱动电路连接的多条信号线，其中，所述多条信号线中的至少一条信号线分段设置。
  19. 根据权利要求18所述的显示面板，其中，所述分段设置的信号线包括位于不同层的多个信号部。
  20. 根据权利要求18或19所述的显示面板，其中，所述分段设置的信号线包括第一信号部和第二信号部，所述第一信号部的材料包括透明的导电金属氧化物，所述第二信号部的材料包括金属。
  21. 根据权利要求19或20所述的显示面板，其中，所述第一显示区包括驱动电路设置区和走线区，所述第一信号部位于所述驱动电路设置区，所述第二信号部位于所述走线区。
  22. 根据权利要求1至17任一项所述的显示面板，还包括发光控制信号线、复位控制信号线、以及复位信号线、其中，像素电路包括驱动模块、发光控制电路、以及复位电路，所述像素电路包括所述第一驱动电路、所述第二驱动电路、以及所述第三驱动电路中至少一个，其中，
    所述发光控制信号线与所述发光控制电路的控制端相连，
    所述复位控制信号线与所述复位电路的控制端相连，
    所述复位信号线与所述复位电路的第一极相连，
    所述发光控制信号线、所述复位控制信号线、以及所述复位信号线中至少之一在所述第一显示区分段设置。
  23. 根据权利要求22所述的显示面板，其中，所述复位电路包括第一复位晶体管和第二复位晶体管，所述第一复位晶体管被配置为对所述驱动模块的控制端进行复位，所述第二复位晶体管被配置为对发光器件的第一电极进行复位，所述发光器件包括所述第一发光器件、第二发光器件、以及所述第三发光器件中至少之一，在位于所述第一显示区的同一个像素电路中，所述第一复位晶体管和所述第二复位晶体管共用同一条复位信号线。
  24. 根据权利要求1至22任一项所述的显示面板，其中，所述第二驱动电路和所述第三驱动电路的布局相同，所述第一驱动电路的布局与所述第二驱动电路或所述第三驱动电路的布局不同。
  25. 根据权利要求1至21任一项所述的显示面板，其中，所述第一驱动电路包括驱动晶体管、第一复位晶体管、第二复位晶体管、数据写入晶体管、以及阈值补偿晶体管，
    所述第一复位晶体管的第一极与第一复位信号线电连接，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连接，
    所述第二复位晶体管的第一极与第二复位信号线电连接，所述第二复位晶体管的第二极与所述第一发光器件相连，
    所述数据写入晶体管的第一极与所述驱动晶体管的第一极电连接，所述数据写入晶体管的第二极被配置为与数据线相连，
    所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极电连接，
    所述第一复位信号线和所述第二复位信号线为同一条复位信号线。
  26. 根据权利要求25所述的显示面板，其中，所述第二复位晶体管的栅极、所述数据写入晶体管的栅极、以及所述阈值补偿晶体管的栅极均与同一条栅极信号线相连。
  27. 一种显示装置，包括：感光元件以及根据权利要求1至26任一项所述的显示面板，所述感光元件在所述显示面板上的正投影与所述第一显示区交叠。
PCT/CN2022/106870 2021-10-28 2022-07-20 显示面板及显示装置 WO2023071312A1 (zh)

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