WO2023065878A1 - 开关电路及电子设备 - Google Patents

开关电路及电子设备 Download PDF

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Publication number
WO2023065878A1
WO2023065878A1 PCT/CN2022/117899 CN2022117899W WO2023065878A1 WO 2023065878 A1 WO2023065878 A1 WO 2023065878A1 CN 2022117899 W CN2022117899 W CN 2022117899W WO 2023065878 A1 WO2023065878 A1 WO 2023065878A1
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Prior art keywords
node
pin
coupled
common
enable
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PCT/CN2022/117899
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English (en)
French (fr)
Inventor
王朝
马波
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荣耀终端有限公司
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Publication of WO2023065878A1 publication Critical patent/WO2023065878A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching

Definitions

  • the present application relates to the technical field of electronic equipment, in particular to a switch circuit and electronic equipment.
  • the analog switch is a switch that uses the characteristics of an analog device (MOS tube) to realize the control signal path, and is mainly used to complete the switching function of connecting or disconnecting the signal link. Because of its low power consumption, fast speed, no mechanical contacts, small size and long service life, it is widely used in electronic devices such as mobile phones, tablets, and computers.
  • MOS tube analog device
  • analog switches they are generally divided into low-speed analog switches and high-speed analog switches.
  • the analog switch when the analog switch needs to transmit USB signals, the analog switch is a high-speed analog switch; when the analog switch needs to transmit audio analog signals, the analog switch can be a low-speed analog switch.
  • High-speed analog switches require higher switching speeds, so the design requirements are higher and the cost is higher.
  • electronic equipment such as mobile phones, tablets, and computers, the cost of electronic equipment will increase.
  • the present application provides a switch circuit and electronic equipment.
  • the cost of electronic equipment can be reduced.
  • the embodiment of the present application provides a switch circuit
  • the switch circuit includes: at least one analog switch, an input node, a power node, a ground node, an enable node, and a common node
  • the analog switch includes an input pin, a power pin , ground pins, enable pins, common pins
  • input pins are coupled to input nodes
  • power supply pins are coupled to power supply nodes
  • ground pins are coupled to ground nodes
  • enable pins are coupled to enable nodes
  • common pins The pin is coupled to the common node
  • the switch circuit also includes: at least one impedance device; wherein, the impedance device is coupled between the power pin and the power node, between the ground pin and the ground node, and between the enable pin and the enable node between at least one of the
  • Impedance devices are added to the pins of the analog switch to increase the impedance of the path and reduce signal leakage. Even if the analog switch used is a low-speed analog switch, high-speed signals can be transmitted through the low-speed analog switch to expand the use of low-speed analog switches. Scenes. In addition, since the cost of the low-speed analog switch is relatively low, when the switching circuit is applied to an electronic device, the cost of the electronic device can be reduced.
  • the number of analog switches is one
  • the number of input pins in the analog switch is two
  • the number of power supply pins, ground pins, enable pins and common pins is one
  • the second input pins include the first An input pin and a second input pin.
  • the number of input pins is four, that is, the input pins include a first input pin, a second input pin, a third input pin, and a fourth input pin
  • the number of common pins is two, that is, the common pins
  • the pins include the first common pin, the second common pin, and the number of enabled pins is two, even if the enabled pins include the first enabled pin, the second enabled pin, the power supply pin, and the ground pin. Quantity is one.
  • the input node includes a first input node and a second input node;
  • the common node includes a first common node and a second common node;
  • the enabling node includes a first enabling node and a second enabling node;
  • the first input node, the second input node, the first common node, the second common node, the first enable node and the second enable node are respectively coupled to different pins of the analog switch;
  • the first input node is used to receive positive differential signal;
  • the first enable node is used to receive the first enable voltage, and transmit the first enable voltage to the enable pin coupled with the first enable node, so that the common tube coupled with the first common node
  • the pin and the input pin coupled with the first input node are turned on; the common pin coupled with the first common node is used to transmit the positive differential signal to the first common node;
  • the second input node is used to receive the negative differential signal;
  • the second input node is used to receive the negative differential signal;
  • the first input node, the second input node, the first common node, the second common node, the first enabling node, and the second enabling node are respectively coupled to different pins of the analog switch and may be the first input node , the second input node, the first common node, the second common node, the first enabling node and the second enabling node are respectively coupled to different pins of the same analog switch. It may also be an analog switch corresponding to the pins coupled to the first input node, the first common node, and the first enable node, and an analog switch corresponding to the pins coupled to the second input node, the second common node, and the second enable node different.
  • the switch circuit includes: at least two analog switches, the at least two analog switches include a first analog switch and a second analog switch; the first input node is coupled to an input pin of the first analog switch, The first common node is coupled to the common pin of the first analog switch; the second input node is coupled to the input pin of the second analog switch, and the second common node is coupled to the common pin of the second analog switch.
  • the positive differential signal and the negative differential signal are respectively transmitted in the two analog switches, further reducing mutual coupling within the analog switches.
  • the number of impedance devices corresponding to the first analog switch is the same as the number of impedance devices corresponding to the second analog switch.
  • the impedance device corresponding to each analog switch has the same influence on the positive differential signal and the negative differential signal, thereby improving the reliability of the signal.
  • the position of the impedance device corresponding to the first analog switch is the same as the position of the impedance device corresponding to the second analog switch. Further, the impedance device corresponding to each analog switch has the same influence on the positive differential signal and the negative differential signal, thereby improving the reliability of the signal.
  • the pins and nodes coupled to the impedance device corresponding to the first analog switch are the same as the pins and nodes coupled to the impedance device corresponding to the second analog switch.
  • the switching speed of the analog switch is less than or equal to 100 MHz, that is, high-speed signals can be transmitted through the low-speed analog switch, and the cost of the electronic device can be reduced when the switch circuit is applied to the electronic device.
  • the impedance value of the impedance device is greater than 600 ohms, which further increases the impedance of the path and further prevents signal leakage.
  • the impedance device includes an inductor, a magnetic bead, or a combination of an inductor and a capacitor.
  • Some possible implementations include: at least three impedance devices; the three impedance devices are respectively coupled between the ground node and the ground pin, between the enable node and the enable pin, and between the power node and the power pin between. In this way, the transmission of the signal will not be affected, and the leakage of the signal can be better reduced.
  • an embodiment of the present application provides an electronic device, where the electronic device includes any one of the switching circuits described above. All the effects of the above switching circuit can be realized.
  • FIG. 1 is one of a schematic diagram of an application scenario of an electronic device provided in an embodiment of the present application
  • FIG. 2 is one of a schematic diagram of an application scenario of an electronic device provided in an embodiment of the present application
  • FIG. 3 is one of a schematic diagram of an application scenario of an electronic device provided in an embodiment of the present application.
  • FIG. 4 is one of a schematic diagram of an application scenario of an electronic device provided in an embodiment of the present application.
  • FIG. 5 is one of a schematic diagram of an application scenario of an electronic device provided in an embodiment of the present application.
  • FIG. 6 is one of a schematic diagram of an application scenario of an electronic device provided in an embodiment of the present application.
  • FIG. 7 is one of the schematic diagrams of an application scenario of an electronic device provided in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a switch circuit provided by an embodiment of the present application.
  • FIG. 9 is an equivalent circuit diagram of an analog switch provided in an embodiment of the present application.
  • FIG. 10 is a partial structural schematic diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 11 is a partial structural schematic diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 12 is a partial structural schematic diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 13 is a partial structural schematic diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • FIG. 24 is a schematic structural diagram of another switch circuit provided by the embodiment of the present application.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects.
  • first target object, the second target object, etc. are used to distinguish different target objects, rather than describing a specific order of the target objects.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
  • the embodiment of the present application provides an electronic device.
  • the electronic device provided in the embodiment of the present application may be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA for short), a vehicle-mounted computer, a TV, a smart wearable device, a smart For electronic devices with analog switches, such as household appliances, the embodiments of the present application do not specifically limit the specific forms of the above electronic devices.
  • PDA personal digital assistant
  • FIG. 1 shows a schematic diagram of an application scenario of an electronic device provided by an embodiment of the present application.
  • the electronic device 100 includes a control module 10, an audio module 20, an analog switch 30, an external interface 40, and the like.
  • the setting of the external interface 40 enables the electronic device 100 to be coupled with an external device.
  • the external interface 40 is, for example, a USB interface or the like.
  • External devices may include electronic devices such as chargers, earphones, mobile phones, and computers, for example.
  • the analog switch 30 can include, for example, a single pole double throw (Single Pole Double Throw, SPDT) switch, in conjunction with FIG. 2, FIG. 2 shows a functional block diagram of the analog switch, the analog switch 30 includes a first input pin 1, a ground Pin 2, second input pin 3, enable pin 4, power supply pin 5 and common pin 6.
  • the first input pin 1 is coupled to the control module 10
  • the second input pin 3 is coupled to the audio module 20
  • the ground pin 2 is grounded
  • the power pin 5 is used to receive the power signal
  • the enable pin 4 is used to receive the enable Enable voltage
  • control the common pin 6 to conduct with the first input pin 1 according to the enable voltage, or control the common pin 6 to conduct with the second input pin 3 .
  • FIG. 2 uses the analog switch 30 as an example of an SPDT switch, but this does not constitute a limitation to the present application. Those skilled in the art can select the type of the analog switch 30 according to the actual situation. The embodiment of the present application does not Make specific restrictions. Unless otherwise specified, the analog switch 30 is used as an example of an SPDT switch for illustration.
  • the control module 10 may be configured to output a high-speed USB signal, for example.
  • the enable pin 4 controls the common pin 6 to conduct with the first input pin 1 according to the received enable voltage, and the high-speed USB signal is transmitted to the computer 200 through the analog switch 30 and the external interface 40, thereby realizing the transmission of the USB signal.
  • the control module 10 may include, for example, a Microcontroller Unit (MCU).
  • MCU Microcontroller Unit
  • the control module 10 may be an independent device, or may be integrated on a system on chip (SoC), which is not limited in this embodiment of the present application. Referring to FIG.
  • the audio module 20 when the external device connected to the external interface 40 is an earphone 300 , the audio module 20 is used to output an audio analog signal, for example.
  • the enable pin 4 controls the common pin 6 to conduct with the second input pin 3 according to the received enable voltage, and the audio analog signal output by the audio module 20 is transmitted to the earphone 300 through the analog switch 30 and the external interface 40, so that the earphone 300 can hear the sound from the electronic device 100 .
  • the audio module 20 may be, for example, a chip for audio processing. Based on this situation, the embodiment of the present application does not limit the type of the chip.
  • FIG. 5 shows a schematic diagram of another application scenario of the electronic device provided by the embodiment of the present application.
  • the electronic device 100 includes a control module 10, an analog switch 30, an external interface 40, and the like.
  • the setting of the external interface 40 enables the electronic device 100 to be coupled with an external device.
  • the external interface 40 is, for example, a USB interface or the like.
  • External devices may include, for example, electronic devices such as chargers, earphones, mobile phones, computers, and test equipment.
  • the analog switch 30 includes a Single Pole Double Throw (Single Pole Double Throw, SPDT) switch as an example for illustration.
  • SPDT Single Pole Double Throw
  • the control module 10 can be used to output high-speed USB signals, for example.
  • the enable pin 4 controls the common pin 6 to conduct with the first input pin 1 according to the received enable voltage, and the high-speed USB signal is transmitted to the computer 200 through the analog switch 30 and the external interface 40, thereby realizing the transmission of the USB signal.
  • the external device connected to the external interface 40 is the testing device 400
  • the control module 10 outputs a low-speed debugging signal.
  • the enable pin 4 controls the conduction between the common pin 6 and the second input pin 3 according to the received enable voltage, and the low-speed debugging signal is transmitted to the testing device 400 through the analog switch 30 and the external interface 40 to debug the electronic device 100 .
  • the above example only uses the analog switch 30 to couple with the control module 10 and the audio module 20 respectively, and the high-speed USB signal output by the control module 10 and the audio analog signal output by the audio module 20 are transmitted through the analog switch 30;
  • the switch 30 is coupled with the control module 10 , and the high-speed USB signal and the low-speed debugging signal are transmitted through the analog switch 30 as an example for illustration.
  • the analog switch 30 can also be applied to other scenarios to realize the transmission of other signals.
  • the analog switch 30 may only transmit one kind of signal; it may also transmit different signals, which is not limited in this embodiment of the present application. Unless otherwise specified, the transmission of high-speed USB signals and audio analog signals through the analog switch 30 is taken as an example in the following text.
  • the analog switch 30 needs to be a high-speed analog switch. In this way, the link switching can be quickly realized and the transmission of the high-speed signal can be completed.
  • the cost of the electronic device 100 is relatively high.
  • an embodiment of the present application provides a switch circuit, which includes at least one analog switch and an impedance device located on a pin of the analog switch.
  • the impedance of the path can be increased and the signal leakage can be reduced.
  • the analog switch used is a low-speed analog switch
  • high-speed signals can be transmitted through the low-speed analog switch to expand the range of the low-speed analog switch. scenes to be used.
  • the cost of the low-speed analog switch is relatively low, when the switching circuit is applied to an electronic device, the cost of the electronic device can be reduced.
  • the switch circuit 50 includes an analog switch 30 , an enable node IN, a power node VCC, a common node COM, a ground node GND, and an input node N.
  • the input node N may include, for example, a first input node NO and a second input node NC.
  • the switching speed of the analog switch 30 may be relatively low, for example, the switching speed of the analog switch 30 may be less than or equal to 100 MHz, for example.
  • the first input node NO is coupled to the first input pin 1
  • the second input node NC is coupled to the second input pin 3
  • the ground node GND is coupled to the ground pin 2
  • the enabling node IN is coupled to the enabling pin 4
  • the power supply node VCC is coupled to the power supply pin 5
  • the common node COM is coupled to the common pin 6 .
  • the switch circuit 50 further includes impedance devices 60 , and the number of impedance devices 60 is, for example, three.
  • One of the impedance devices 60 is coupled between the ground node GND and the ground pin 2
  • one of the impedance devices 60 is coupled between the enable node IN and the enable pin 4
  • one of the impedance devices 60 is coupled between the power supply node VCC and the power supply between pin 5.
  • FIG. 9 is an equivalent circuit diagram of an analog switch 30.
  • the gate and source of the MOS transistor form a parasitic capacitance C gs
  • the gate and drain of the MOS transistor form a parasitic capacitance C gd
  • the source and drain of the MOS transistor form a parasitic capacitance C gs .
  • the pole forms a parasitic capacitance C sd
  • the first input node NO and the ground node GND form a parasitic capacitance C no
  • the second input node NC and the ground node GND form a parasitic capacitance C nc
  • the common node COM and the ground node GND form a parasitic capacitance C com .
  • the analog switch 30 includes a plurality of parasitic capacitances inside.
  • the magnitude of the parasitic capacitance affects the edge timing of the signal.
  • the main limitation of the low-speed analog switch is that the internal parasitic capacitance is too large, and the large parasitic capacitance makes the high-speed signal attenuation seriously, which affects the transmission of the high-speed signal.
  • an impedance device 60 is provided between the ground node GND and the ground pin 2 , between the enable node IN and the enable pin 4 , and between the power node VCC and the power pin 5 .
  • the impedance of the high-frequency path is increased through the impedance device 60, which can reduce the path between the high-speed signal passing through the ground node GND and the ground pin 2, the path between the enable node IN and the enable pin 4, and the path between the power supply node VCC and the power supply pin 5. In this way, even if the analog switch 30 used is a low-speed analog switch, high-speed signals can be transmitted through the low-speed analog switch.
  • the high-speed USB signal transmission can be completed through the switch circuit 50 including the low-speed analog switch 30 .
  • the transmission of audio analog signals can also be completed through a switch circuit 50 including a low-speed analog switch 30 .
  • the transmission of the low-speed debugging signal can also be completed through the switch circuit 50 including the low-speed analog switch 30 .
  • the switch circuit 50 when the switch circuit 50 is arranged in the electronic device 100, since the analog switch 30 of the switch circuit 50 can be a low-speed analog switch, that is to say, the electronic device 100 and the external device are completed through the switch circuit 50 including the low-speed analog switch. The transmission of high-speed signals between them, in this way, the cost of the electronic device 100 can be reduced.
  • analog switch 30 is not limited to being a low-speed analog switch, and the analog switch 30 can also be a high-speed analog switch.
  • the switch circuit 50 can also be applied to Higher frequency scenarios support the transmission of higher speed signals.
  • the embodiment of the present application does not limit the application scenarios of the switch circuit 50 .
  • the above example only shows one setting position of the impedance device 60, that is, as shown in FIG. 8, the impedance device 60 is set between the ground node GND and the ground pin 2, and the An impedance device 60 is provided between IN and the enable pin 4 , and an impedance device 60 is provided between the power supply node VCC and the power supply pin 5 .
  • the signal leakage can be reduced when the high-speed signal is transmitted through the analog switch 30 .
  • the impedance device 60 is only coupled between one of the pins and the node corresponding to the pin.
  • the impedance device 60 is coupled between the ground node GND and the ground pin 2 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the ground node GND and the ground pin 2 .
  • the impedance device 60 is coupled between the power node VCC and the power pin 5 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the power node VCC and the power pin 5 .
  • the impedance device 60 is coupled between the enable node IN and the enable pin 4 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the enabling node IN and the enabling pin 4 .
  • the impedance device 60 is coupled between one of the pins and the node corresponding to the pin; and, between the other pin and the node corresponding to the pin.
  • the impedance device 60 is coupled between the ground node GND and the ground pin 2
  • the impedance device 60 is coupled between the enable node IN and the enable pin 4 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the ground node GND and the ground pin 2 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the enabling node IN and the enabling pin 4 .
  • the impedance device 60 is coupled between the ground node GND and the ground pin 2
  • the impedance device 60 is coupled between the power node VCC and the power pin 5 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the ground node GND and the ground pin 2 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the power node VCC and the power pin 5 .
  • the impedance device 60 is coupled between the enable node IN and the enable pin 4
  • the impedance device 60 is coupled between the power node VCC and the power pin 5 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the enabling node IN and the enabling pin 4 .
  • the impedance of the high-frequency path is increased to avoid leakage of high-speed signals through the path between the power node VCC and the power pin 5 .
  • an impedance device 60 is provided between the ground node GND and the ground pin, an impedance device 60 is provided between the enable node IN and the enable pin, and an impedance device 60 is provided between the power node VCC and the power pin.
  • the impedance device 60 is provided as an example for description.
  • the embodiment of the present application does not limit the type of the impedance device 60 .
  • the impedance device 60 is, for example, an inductor. However, it does not constitute a limitation to the present application, as long as the devices that can increase the impedance on the path are within the protection scope of the present application. Exemplarily, the impedance device 60 may also be a combination of an inductor and a capacitor, or a magnetic bead, or the like.
  • the embodiment of the present application does not limit the impedance value of the impedance device 60 .
  • the impedance value of the impedance device 60 may be greater than 600 ohms, for example.
  • the impedance value of the impedance device 60 is greater than 600 ohms, it can better prevent the high-speed signal from leaking through the path between the ground node GND and the ground pin 2, prevent the high-speed signal from leaking through the path between the enable node IN and the enable pin 4, and , to prevent the high-speed signal from leaking through the path between the power supply node VCC and the power supply pin 5 .
  • the analog switch 30 includes one switch and the transmitted signal is a single-ended signal.
  • the analog switch 30 may further include a multi-way switch, and the signal transmitted through the analog switch 30 is a differential signal.
  • the analog switch 30 includes M switches inside, where M is a positive integer greater than or equal to 2. Then the analog switch 30 may include, for example, 2M input pins, M enable pins, and M common pins.
  • the analog switch 30 includes two switches inside.
  • the analog switch 30 includes a first input pin 1, a second input pin 2, a ground pin 3, a third input pin 4, a fourth input pin 5, a first enabling pin 6, and a first common pin 7.
  • the switch circuit 50 includes the analog switch 30 .
  • the switch circuit 50 also includes an enable node IN, a power node VCC, a common node COM, a ground node GND, and an input node N.
  • the input node N includes a first input node NO1 , a second input node NO2 , a third input node NC1 , and a fourth input node NC2 .
  • the enabling nodes IN include a first enabling node IN1 and a second enabling node IN2.
  • the common nodes COM include a first common node COM1 and a second common node COM2.
  • the first input pin 1 is coupled to the first input node NO1
  • the second input pin 2 is coupled to the third input node NC1
  • the ground pin 3 is coupled to the ground node GND
  • the third input pin 4 is coupled to the fourth input node NC2 Coupling
  • the fourth input pin 5 is coupled to the second input node NO2
  • the first enable pin 6 is coupled to the first enable node IN1
  • the first common pin 7 is coupled to the first common node COM1
  • the power supply pin 8 It is coupled with the power supply node VCC
  • the second enable pin 9 is coupled with the second enable node IN2
  • the second common pin 10 is coupled with the second common node COM2.
  • the external interface 40 is, for example, USB 2.0.
  • the USB signals include a positive differential signal USB_DP and a negative differential signal USB_DP.
  • the low speed analog signal includes a left channel signal L and a right channel signal R.
  • the transmitted signal is a positive differential signal USB_DP and a negative differential signal USB_DP
  • the first input node NO1 transmits the received positive differential signal USB_DP to the first input pin 1
  • the first enabling node IN1 transmits the received positive differential signal USB_DP
  • the first enable voltage is transmitted to the first enable pin 6 to control the conduction between the first common pin 7 and the first input pin 1
  • the positive differential signal USB_DP is transmitted to the first common node COM1 through the analog switch 30 to It is transmitted to an external device (such as a computer) through the first public node COM1.
  • the second input node NO2 transmits the received negative differential signal USB_DP to the fourth input pin 5, and the second enable node IN2 transmits the received second enable voltage to the second enable pin 9 to control the first
  • the second common pin 10 is connected to the fourth input pin 5 , and the negative differential signal USB_DP is transmitted to the second common node COM2 through the analog switch 30 , so as to be transmitted to an external device through the second common node COM2 .
  • USB signal In order to realize the transmission of USB signal.
  • the third input node NC1 transmits the received left channel signal L to the second input pin 2, and the first input pin received by the first enabling node IN1
  • the enable voltage is transmitted to the first enable pin 6 to control the conduction between the first common pin 7 and the second input pin 2, and the left channel signal L is transmitted to the first common node COM1 through the analog switch 30 to pass through
  • the first common node COM1 transmits to an external device (such as an earphone).
  • the fourth input node NC2 transmits the received right channel signal R to the third input pin 4, and the second enabling voltage received by the second enabling node IN2 is transmitted to the second enabling pin 9 to control the first
  • the second common pin 10 is connected to the third input pin 4 , and the right channel signal R is transmitted to the second common node COM2 through the analog switch 30 , so as to be transmitted to an external device through the second common node COM2 .
  • the switch circuit 50 when the switch circuit 50 is arranged in the electronic device 100, since the analog switch 30 of the switch circuit 50 can be a low-speed analog switch, that is to say, the high-speed differential signal in the electronic device 100 is completed by the switch circuit 50 including the low-speed analog switch. transmission, or complete the transmission of high-speed differential signals between the electronic device 100 and the external device, in this way, the cost of the electronic device 100 can be reduced.
  • the high-speed differential signal can also be respectively transmitted on two independent low-speed analog switches.
  • the two low-speed Analog switches can be in close proximity. That is to say, the switch circuit 50 may only include one analog switch 30, see, for example, FIG. 8 , but this does not constitute a limitation to the present application.
  • the switch circuit 50 may also include L analog switches, where L is a positive integer greater than or equal to 2 .
  • the switch circuit 50 includes two analog switches 30 .
  • the two analog switches 30 include a first analog switch 31 and a second analog switch 32 .
  • the structure of the first analog switch 31 and the second analog switch 32 is, for example, the same as that of the analog switch 30 in the embodiment corresponding to FIG. 2 .
  • the switch circuit 50 also includes an enable node IN, a power node VCC, a common node COM, a ground node GND, and an input node N.
  • the input node N includes a first input node NO1 , a second input node NO2 , a third input node NC1 , and a fourth input node NC2 .
  • the enabling nodes IN include a first enabling node IN1 and a second enabling node IN2.
  • the common nodes COM include a first common node COM1 and a second common node COM2.
  • the ground node GND includes a first ground node GND1 and a second ground node GND2.
  • the power supply node VCC includes a first power supply node VCC1 and a second power supply node VCC2.
  • the first input pin 1 corresponding to the first analog switch 31 is coupled to the first input node NO1
  • the ground pin 2 corresponding to the first analog switch 31 is coupled to the first ground node GND1
  • the second input pin corresponding to the first analog switch 31 Pin 2 is coupled to the third input node NC1
  • the enable pin 4 corresponding to the first analog switch 31 is coupled to the first enable node IN1
  • the power supply pin 5 corresponding to the first analog switch 31 is coupled to the first power supply node VCC1
  • the common pin 6 corresponding to the first analog switch 31 is coupled to the first common node COM1.
  • the first input pin 1 corresponding to the second analog switch 32 is coupled to the fourth input node NC2, the ground pin 2 corresponding to the second analog switch 32 is coupled to the second ground node GND2, and the second input pin 1 corresponding to the second analog switch 32
  • the pin 3 is coupled to the second input node NO2
  • the enable pin 4 corresponding to the second analog switch 32 is coupled to the second enable node IN2
  • the power supply pin 5 corresponding to the second analog switch 32 is coupled to the second power supply node VCC2
  • the common pin 6 corresponding to the second analog switch 32 is coupled to the second common node COM2.
  • the external interface 40 is, for example, USB 2.0.
  • the USB signals include a positive differential signal USB_DP and a negative differential signal USB_DP.
  • the low speed analog signal includes a left channel signal L and a right channel signal R.
  • the transmitted signal is a positive differential signal USB_DP and a negative differential signal USB_DP
  • the first input node NO1 transmits the received positive differential signal USB_DP to the first input pin 1 of the first analog switch 31, and the first enable
  • the first enable voltage received by the enable node IN1 is transmitted to the enable pin 4 of the first analog switch 31 to control the conduction between the common pin 6 of the first analog switch 31 and the first input pin 1, and the positive differential signal USB_DP It is transmitted to the first common node COM1 through the analog switch 30, so as to be transmitted to an external device (such as a computer) through the first common node COM1.
  • the second input node NO2 transmits the received negative differential signal USB_DP to the second input pin 3 of the second analog switch 32, and the second enable voltage received by the second enable node IN2 is transmitted to the second analog switch 32.
  • the pin 4 is enabled to control the conduction between the common pin 6 of the second analog switch 32 and the second input pin 3 of the second analog switch 32, and the negative differential signal USB_DP is transmitted to the second common node COM2 through the analog switch 30, to be transmitted to an external device through the second public node COM2. In order to realize the transmission of USB signal.
  • the third input node NC1 transmits the received left channel signal L to the second input pin 3 of the first analog switch 31, and the first enable
  • the first enable voltage received by the node IN1 is transmitted to the enable pin 4 of the first analog switch 31 to control the conduction between the common pin 6 of the first analog switch 31 and the second input pin 3, and the left channel signal L It is transmitted to the first common node COM1 through the analog switch 30, so as to be transmitted to an external device (such as an earphone) through the first common node COM1.
  • the fourth input node NC2 transmits the received right channel signal R to the first input pin 1 of the second analog switch 32, and the second enable voltage received by the second enable node IN2 is transmitted to the second analog switch 32
  • the enabling pin 4 of the second analog switch 32 is used to control the conduction between the common pin 6 of the second analog switch 32 and the first input pin 1, and the right channel signal R is transmitted to the second common node COM2 through the analog switch 30 to pass through the second
  • the public node COM2 is transmitted to the external device.
  • the impedance device 60 is coupled between the first ground node GND1 and the ground pin 2 of the first analog switch 31, and the impedance device 60 is coupled to Between the first enable node IN1 and the enable pin 4 of the first analog switch 31, the impedance device 60 is coupled between the first power supply node VCC1 and the power supply pin 5 of the first analog switch 31, and the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32, the impedance device 60 is coupled between the second enable node IN2 and the enable pin 4 of the second analog switch 32, the impedance device 60 is coupled between the second power node VCC2 and the power pin 5 of the second analog switch 32 as an example for illustration.
  • the impedance device 60 can also be coupled only between one of the pins and the node corresponding to the pin; or, the impedance device 60 is coupled between one of the pins and the node corresponding to the pin; And, between another pin and the node corresponding to that pin.
  • the number of impedance devices 60 corresponding to the first analog switch 31 and the second analog switch 32 are the same, the types of the impedance devices 60 are the same, and the positions of the impedance devices 60 are the same, that is, the impedance The corresponding pins and nodes of device 60 are the same.
  • the impedance device 60 when the impedance device 60 is only coupled between one of the pins and the node corresponding to the pin, the impedance device 60 is coupled to the first ground node GND1 and the ground pin 2 of the first analog switch 31. , and the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32 .
  • the impedance device 60 when the impedance device 60 is coupled between one of the pins and the node corresponding to the pin; and, when the impedance device 60 is coupled between another pin and the node corresponding to the pin , the impedance device 60 is coupled between the first ground node GND1 and the ground pin 2 of the first analog switch 31, and the impedance device 60 is coupled between the first enable node IN1 and the enable pin 4 of the first analog switch 31 , and, the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32, and the impedance device 60 is coupled between the second enable node IN2 and the enable pin 4 of the second analog switch 32 between.
  • This setting is because the impedance device 60 corresponding to each analog switch 30 has the same influence on the differential signal (positive differential signal USB_DP and negative differential signal USB_DP) (to prevent signal leakage), which improves the reliability of the signal.

Abstract

本申请提供了一种开关电路及电子设备，涉及电子设备技术领域，可以降低电子设备的成本。该开关电路，包括：至少一个模拟开关、输入节点、电源节点、接地节点、使能节点、公共节点；模拟开关包括输入管脚、电源管脚、接地管脚、使能管脚、公共管脚；输入管脚与输入节点耦合，电源管脚与电源节点耦合，接地管脚与接地节点耦合，使能管脚与使能节点耦合，公共管脚与公共节点耦合；开关电路还包括：至少一个阻抗器件；其中，阻抗器件耦合于电源管脚与电源节点之间、接地管脚与接地节点之间以及使能管脚与使能节点之间中的至少一个之间。

Description

开关电路及电子设备
本申请要求于2021年10月22日提交中国国家知识产权局、申请号为202111235596.X、申请名称为“开关电路及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子设备技术领域，尤其涉及一种开关电路及电子设备。
背景技术
模拟开关是利用模拟器件(MOS管)的特性实现控制信号通路的开关，主要用于完成信号链路连接或断开的切换功能。由于其具有功耗低、速度快、无机械触点、体积小和使用寿命长等特点，因而，在手机、平板、电脑等电子设备中得到广泛应用。
根据模拟开关的应用场景，一般分为低速模拟开关和高速模拟开关。例如，手机中，当需要通过模拟开关传输USB信号时，此模拟开关为高速模拟开关；当需要通过模拟开关传输音频模拟信号时，此模拟开关可以为低速模拟开关。
高速模拟开关由于需要更高的开关速度，所以其设计的要求更高，成本更高。当高速模拟开关应用到手机、平板、电脑等电子设备时，使得电子设备的成本提高。
发明内容
为了解决上述技术问题，本申请提供一种开关电路及电子设备。可以降低电子设备的成本。
第一方面，本申请实施例提供一种开关电路，该开关电路包括：至少一个模拟开关、输入节点、电源节点、接地节点、使能节点、公共节点；模拟开关包括输入管脚、电源管脚、接地管脚、使能管脚、公共管脚；输入管脚与输入节点耦合，电源管脚与电源节点耦合，接地管脚与接地节点耦合，使能管脚与使能节点耦合，公共管脚与公共节点耦合；开关电路还包括：至少一个阻抗器件；其中，阻抗器件耦合于电源管脚与电源节点之间、接地管脚与接地节点之间以及使能管脚与使能节点之间中的至少一个之间。
在模拟开关的管脚上增加阻抗器件，实现通路的阻抗增大，减少信号泄露，即便使用的模拟开关为低速模拟开关，也可以通过该低速模拟开关传输高速信号，扩宽低速模拟开关的使用场景。此外，由于低速模拟开关的成本较低，因此，当该开关电路应用到电子设备时，可以降低电子设备的成本。
示例性的，模拟开关的数量为一，模拟开关中输入管脚的数量为二，电源管脚、接地管脚、使能管脚以及公共管脚的数量为一，二个输入管脚包括第一输入管脚和第二输入管脚。或者，输入管脚的数量为四，即输入管脚包括第一输入管脚，第二输入管脚、第三输入管脚和第四输入管脚，公共管脚的数量为二，即公共管脚包括第一公共管脚， 第二公共管脚，使能管脚的数量为二，即使能管脚包括第一使能管脚，第二使能管脚，电源管脚、接地管脚的数量为一。
在一些可能实现的方式中，输入节点包括第一输入节点和第二输入节点；公共节点包括第一公共节点和第二公共节点；使能节点包括第一使能节点和第二使能节点；第一输入节点、第二输入节点、第一公共节点、第二公共节点、第一使能节点和第二使能节点分别与模拟开关的不同管脚耦合；第一输入节点用于接收正差分信号；第一使能节点用于接收第一使能电压，并将第一使能电压传输至与第一使能节点耦合的使能管脚处，以使与第一公共节点耦合的公共管脚和与第一输入节点耦合的输入管脚导通；与第一公共节点耦合的公共管脚用于将正差分信号传输至第一公共节点；第二输入节点用于接收负差分信号；第二使能节点用于接收第二使能电压，并将第二使能电压传输至与第二使能节点耦合的使能管脚处，以使与第二公共节点耦合的公共管脚和与第二输入节点耦合的输入管脚导通；与第二公共节点耦合的公共管脚用于将负差分信号传输至第二公共节点，使得该开关电路可以应用于传输差分信号中。
示例性的，第一输入节点、第二输入节点、第一公共节点、第二公共节点、第一使能节点和第二使能节点分别与模拟开关的不同管脚耦合可以是第一输入节点、第二输入节点、第一公共节点、第二公共节点、第一使能节点和第二使能节点分别与同一个模拟开关的不同管脚耦合。还可以是第一输入节点、第一公共节点、第一使能节点耦合的管脚对应的模拟开关与第二输入节点、第二公共节点和第二使能节点耦合的管脚对应的模拟开关不同。
在一些可能实现的方式中，开关电路包括：至少两个模拟开关，至少两个模拟开关包括第一模拟开关和第二模拟开关；第一输入节点与第一模拟开关中的输入管脚耦合，第一公共节点与第一模拟开关中的公共管脚耦合；第二输入节点和第二模拟开关的输入管脚耦合，第二公共节点与第二模拟开关中的公共管脚耦合。如此，正差分信号和负差分信号分别在两个模拟开关中传输，进一步减少模拟开关内的相互耦合。
在一些可能实现的方式中，第一模拟开关对应的阻抗器件的数量和第二模拟开关对应的阻抗器件的数量相同。使得每个模拟开关对应的阻抗器件对正差分信号和负差分信号的影响相同，提高信号的可靠性。
在一些可能实现的方式中，第一模拟开关对应的阻抗器件的位置和第二模拟开关对应的阻抗器件的位置相同。进一步使得每个模拟开关对应的阻抗器件对正差分信号和负差分信号的影响相同，提高信号的可靠性。
示例性的，第一模拟开关对应的阻抗器件耦合的管脚和节点与第二模拟开关对应的阻抗器件耦合的管脚和节点相同。
在一些可能实现的方式中，模拟开关的开关速度小于或等于100兆赫兹，即可以通 过低速模拟开关传输高速信号，当该开关电路应用到电子设备中时降低电子设备的成本。
在一些可能实现的方式中，阻抗器件的阻抗值大于600欧姆，进一步增大通路的阻抗，进一步防止信号泄露。
在一些可能实现的方式中，阻抗器件包括电感、磁珠或电感和电容的组合等。
在一些可能实现的方式中，包括：至少三个阻抗器件；三个阻抗器件分别耦合于接地节点与接地管脚之间、使能节点与使能管脚之间以及电源节点与电源管脚之间。如此，既不会影响信号的传输，同时还可以更好的减少信号的泄露。
第二方面，本申请实施例提供一种电子设备，该电子设备包括上述任一项的开关电路。能够实现上述开关电路的所有效果。
附图说明
图1为本申请实施例提供的电子设备的一种应用场景示意图之一；
图2为本申请实施例提供的电子设备的一种应用场景示意图之一；
图3为本申请实施例提供的电子设备的一种应用场景示意图之一；
图4为本申请实施例提供的电子设备的一种应用场景示意图之一；
图5为本申请实施例提供的电子设备的一种应用场景示意图之一；
图6为本申请实施例提供的电子设备的一种应用场景示意图之一；
图7为本申请实施例提供的电子设备的一种应用场景示意图之一；
图8为本申请实施例提供的一种开关电路的结构示意图；
图9为本申请实施例提供的一种模拟开关的等效电路图；
图10为本申请实施例提供的电子设备的部分结构示意图；
图11为本申请实施例提供的电子设备的部分结构示意图；
图12为本申请实施例提供的电子设备的部分结构示意图；
图13为本申请实施例提供的电子设备的部分结构示意图；
图14为本申请实施例提供的又一种开关电路的结构示意图；
图15为本申请实施例提供的又一种开关电路的结构示意图；
图16为本申请实施例提供的又一种开关电路的结构示意图；
图17为本申请实施例提供的又一种开关电路的结构示意图；
图18为本申请实施例提供的又一种开关电路的结构示意图；
图19为本申请实施例提供的又一种开关电路的结构示意图；
图20为本申请实施例提供的又一种开关电路的结构示意图；
图21为本申请实施例提供的又一种开关电路的结构示意图；
图22为本申请实施例提供的又一种开关电路的结构示意图；
图23为本申请实施例提供的又一种开关电路的结构示意图；
图24为本申请实施例提供的又一种开关电路的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个系统是指两个或两个以上的系统。
本申请实施例提供一种电子设备，本申请实施例提供的电子设备可以是手机、电脑、平板电脑、个人数字助理(personal digital assistant，简称PDA)、车载电脑、电视、智能穿戴式设备、智能家居设备等具有模拟开关的电子设备，本申请实施例对上述电子设备的具体形式不作特殊限定。
以下对本申请实施例提供的电子设备的具体结构和用途进行说明。
如图1所示，图1示出了本申请实施例提供的电子设备的一种应用场景示意图，电子设备100包括控制模块10、音频模块20、模拟开关30和对外接口40等。对外接口40的设置使得电子设备100可以与外接设备耦合。其中，对外接口40例如为USB接口等。外接设备例如可以包括充电器、耳机、手机、电脑等电子设备。
示例性的，模拟开关30例如可以包括单刀双掷(Single Pole Double Throw，SPDT)开关，结合图2，图2示出了模拟开关的功能框图，模拟开关30包括第一输入管脚1、接地管脚2、第二输入管脚3、使能管脚4、电源管脚5和公共管脚6。第一输入管脚1与控制模块10耦合，第二输入管脚3与音频模块20耦合，接地管脚2接地设置，电源管脚5用于接收电源信号，使能管脚4用于接收使能电压，并根据使能电压控制公共管脚6与第一输入管脚1导通，或者，控制公共管脚6与第二输入管脚3导通。
此处需要说明的是，图2以模拟开关30为SPDT开关为例进行的说明，但不构成对本申请的限定，本领域技术人员可以根据实际情况选择模拟开关30的类型，本申请 实施例不进行具体限定。下文中除另有说明外，下文中均以模拟开关30为SPDT开关举例说明。
在此情况下，示例性的，参见图3，当对外接口40接入的外接设备为电脑200时，控制模块10例如可以用于输出高速USB信号。使能管脚4根据接收的使能电压控制公共管脚6与第一输入管脚1导通，高速USB信号通过模拟开关30以及对外接口40传输至电脑200，从而实现USB信号的传输。其中，控制模块10例如可以包括微控制单元(Microcontroller Unit，MCU)。控制模块10可以是独立的器件，也可以集成在系统级芯片(system on chip SoC)上，本申请实施例不作限定。参见图4，当对外接口40接入的外接设备为耳机300时，音频模块20例如用于输出音频模拟信号。使能管脚4根据接收的使能电压控制公共管脚6与第二输入管脚3导通，音频模块20输出的音频模拟信号通过模拟开关30以及对外接口40传输至耳机300，从而使得耳机300能够听到电子设备100发出的声音。其中，音频模块20例如可以为进行音频处理的芯片，在此情况的基础上，本申请实施例不对该芯片的类型进行限定。
如图5所示，图5示出了本申请实施例提供的电子设备的又一种应用场景示意图，电子设备100包括控制模块10、模拟开关30和对外接口40等。对外接口40的设置使得电子设备100可以与外接设备耦合。其中，对外接口40例如为USB接口等。外接设备例如可以包括充电器、耳机、手机、电脑、测试设备等电子设备。
同样以模拟开关30包括单刀双掷(Single Pole Double Throw，SPDT)开关为例进行说明。参见图6，当对外接口40接入的外接设备为电脑200时，控制模块10例如可以用于输出高速USB信号。使能管脚4根据接收的使能电压控制公共管脚6与第一输入管脚1导通，高速USB信号通过模拟开关30以及对外接口40传输至电脑200，从而实现USB信号的传输。参见图7，当需要对电子设备100进行调试时，对外接口40接入的外接设备为测试设备400，控制模块10输出低速调试信号。使能管脚4根据接收的使能电压控制公共管脚6与第二输入管脚3导通，低速调试信号通过模拟开关30以及对外接口40传输至测试设备400，以对电子设备100进行调试。
需要说明的是，上述示例仅以模拟开关30分别与控制模块10以及音频模块20耦合，且通过模拟开关30传输控制模块10输出的高速USB信号和音频模块20输出的音频模拟信号；以及，模拟开关30与控制模块10耦合，且通过模拟开关30传输高速USB信号和低速调试信号作为示例进行的说明。当然，模拟开关30还可应用到其他场景，实现其他信号的传输。此外，模拟开关30可以仅传输一种信号；也可以传输不同的信号，本申请实施例对此不作限定。下文中除另有说明外，均以通过模拟开关30传输高速USB信号和音频模拟信号作为示例。
由于USB信号为高速信号，因此，模拟开关30需要为高速模拟开关，如此，可以快速实现链路切换，完成高速信号的传输。但是因为高速模拟开关设计的要求高，所以其成本较高，这样一来，导致电子设备100的成本较高。
为了解决上述技术问题，本申请实施例提供了一种开关电路，该开关电路包括至少一个模拟开关，还包括位于模拟开关管脚上的阻抗器件。通过在模拟开关的管脚上增加阻抗器件，实现通路的阻抗增大，减少信号泄露，即便使用的模拟开关为低速模拟开 关，也可以通过该低速模拟开关传输高速信号，扩宽低速模拟开关的使用场景。此外，由于低速模拟开关的成本较低，因此，当该开关电路应用到电子设备时，可以降低电子设备的成本。
以下结合电子设备对上述开关电路进行具体说明。
如图8所示，开关电路50包括模拟开关30、使能节点IN、电源节点VCC、公共节点COM、接地节点GND、输入节点N。其中，输入节点N例如可以包括第一输入节点NO和第二输入节点NC。模拟开关30的开关速度可以较低，例如，模拟开关30的开关速度例如可以小于或等于100兆赫兹。第一输入节点NO与第一输入管脚1耦合，第二输入节点NC与第二输入管脚3耦合，接地节点GND与接地管脚2耦合，使能节点IN与使能管脚4耦合，电源节点VCC与电源管脚5耦合，公共节点COM与公共管脚6耦合。
继续参见图8，开关电路50还包括阻抗器件60，阻抗器件60的数量例如为3个。其中一个阻抗器件60耦合于接地节点GND与接地管脚2之间，其中一个阻抗器件60耦合于使能节点IN与使能管脚4之间，其中一个阻抗器件60耦合于电源节点VCC与电源管脚5之间。
具体的，模拟开关30的开关功能例如是通过MOS管实现的。图9是模拟开关30的等效电路图，参见图9，MOS管的栅极与源极形成寄生电容C gs，MOS管的栅极与漏极形成寄生电容C gd，MOS管的源极与漏极形成寄生电容C sd，第一输入节点NO与接地节点GND形成寄生电容C no，第二输入节点NC与接地节点GND形成寄生电容C nc，公共节点COM与接地节点GND形成寄生电容C com。也就是说，模拟开关30内部包括多个寄生电容。寄生电容的大小影响信号的边沿时间。低速模拟开关的主要限制是内部的寄生容值偏大，较大的寄生电容使得高速信号衰减严重，影响高速信号的传输。本申请实施例中通过在接地节点GND与接地管脚2、使能节点IN与使能管脚4之间以及电源节点VCC与电源管脚5之间均设置阻抗器件60。通过阻抗器件60使得高频通路阻抗增大，可以减少高速信号通过接地节点GND与接地管脚2的通路、使能节点IN与使能管脚4的通路以及电源节点VCC与电源管脚5的通路泄露，如此，即便使用的模拟开关30为低速模拟开关，也可以通过该低速模拟开关传输高速信号。
在此基础上，示例性的，参见图10和图11，当对外接口40接入的外接设备为电脑200时，可以通过包括低速的模拟开关30的开关电路50完成高速USB信号的传输。参见图12，当对外接口40接入的外接设备为耳机300时，也可以通过包括低速的模拟开关30的开关电路50完成音频模拟信号的传输。以及，参见图13，当对外接口40接入的外接设备为测试设备400时，也可以通过包括低速的模拟开关30的开关电路50完成低速调试信号的传输。
本申请中，当开关电路50设置于电子设备100中时，由于开关电路50的模拟开关30可以为低速模拟开关，也就是说，通过包括低速模拟开关的开关电路50完成电子设备100与外接设备之间高速信号的传输，这样一来，可以降低电子设备100的成本。
需要说明的是，上述模拟开关30并不限于为低速模拟开关，模拟开关30还可以为高速模拟开关，当开关电路50中的模拟开关30为高速模拟开关时，该开关电路50还 可以应用到更高频率的场景，支撑更高速度信号的传输。
需要说明的是，不仅可以通过包括低速模拟开关的开关电路50完成电子设备100与外接设备之间高速信号的传输，还可以通过包括低速模拟开关的开关电路50完成电子设备100内高速信号的传输等，本申请实施例不对开关电路50的应用场景进行限定。
此外，对于阻抗器件60的设置位置，上述示例仅示出阻抗器件60的一种设置位置，即如图8所示，接地节点GND与接地管脚2之间设置有阻抗器件60，使能节点IN与使能管脚4之间设置有阻抗器件60，电源节点VCC与电源管脚5之间设置有阻抗器件60。但不构成对本申请的限定，当高速信号通过模拟开关30进行传输时，只要可以减少信号泄露即可。
在一些可能实现的方式中，阻抗器件60仅耦合于其中一个管脚和与该管脚对应的节点之间。
一个示例中，参见图14，阻抗器件60耦合于接地节点GND与接地管脚2之间。通过接地节点GND与接地管脚2之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过接地节点GND与接地管脚2的通路泄露。
又一个示例中，参见图15，阻抗器件60耦合于电源节点VCC与电源管脚5之间。通过电源节点VCC与电源管脚5之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过电源节点VCC与电源管脚5的通路泄露。
再一个示例中，参见图16，阻抗器件60耦合于使能节点IN与使能管脚4之间。通过使能节点IN与使能管脚4之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过使能节点IN与使能管脚4的通路泄露。
又一些可能实现的方式中，阻抗器件60耦合于其中一个管脚和与该管脚对应的节点之间；以及，另一个管脚和与该管脚对应的节点之间。
一个示例中，参见图17，阻抗器件60耦合于接地节点GND与接地管脚2之间，以及，阻抗器件60耦合于使能节点IN与使能管脚4之间。通过接地节点GND与接地管脚2之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过接地节点GND与接地管脚2的通路泄露。通过使能节点IN与使能管脚4之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过使能节点IN与使能管脚4的通路泄露。
又一个示例中，参见图18，阻抗器件60耦合于接地节点GND与接地管脚2之间，以及，阻抗器件60耦合于电源节点VCC与电源管脚5之间。通过接地节点GND与接地管脚2之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过接地节点GND与接地管脚2的通路泄露。通过电源节点VCC与电源管脚5之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过电源节点VCC与电源管脚5的通路泄露。
再一个示例中，参见图19，阻抗器件60耦合于使能节点IN与使能管脚4之间，以及，阻抗器件60耦合于电源节点VCC与电源管脚5之间。通过使能节点IN与使能管脚4之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过使能节点IN与使能管脚4的通路泄露。通过电源节点VCC与电源管脚5之间的阻抗器件60使得高频通路阻抗增大，避免高速信号通过电源节点VCC与电源管脚5的通路泄露。
需要说明的是，下述示例均以接地节点GND与接地管脚之间设置有阻抗器件60，使能节点IN与使能管脚之间设置有阻抗器件60，电源节点VCC与电源管脚之间设置有阻抗器件60为例进行的说明。
此外，对于阻抗器件60的类型，本申请实施例不对阻抗器件60的类型进行限定。
在一些可能实现的方式中，参见图20，阻抗器件60例如为电感。但是不构成对本申请的限定，只要可以增大通路上的阻抗的器件均位于本申请的保护范围内。示例性的，阻抗器件60还可以是电感和电容的组合或磁珠等。
此外，对于阻抗器件60的阻抗值，本申请实施例不对阻抗器件60的阻抗值进行限定。在一些可能实现的方式中，阻抗器件60的阻抗值例如可以大于600欧姆。当阻抗器件60的阻抗值大于600欧姆时，可以更好防止高速信号通过接地节点GND与接地管脚2的通路泄露，防止高速信号通过使能节点IN与使能管脚4的通路泄露，以及，防止高速信号通过电源节点VCC与电源管脚5的通路泄露。
需要说明的是，上述示例仅以模拟开关30内部包含一路开关，且传输的信号为单端信号为例进行的说明。可选的，模拟开关30内部还可以包括多路开关，且通过该模拟开关30传输的信号为差分信号。例如，模拟开关30内部包括M路开关，其中，M为大于或等于2的正整数。则模拟开关30例如可以包括2M个输入管脚，M个使能管脚，M个公共管脚。
在一些可能实现的方式中，参见图21，示例性的，模拟开关30内部包括两路开关。模拟开关30包括第一输入管脚1、第二输入管脚2、接地管脚3、第三输入管脚4、第四输入管脚5、第一使能管脚6、第一公共管脚7、电源管脚8、第二使能管脚9和第二公共管脚10。开关电路50包括该模拟开关30。此外，开关电路50还包括使能节点IN、电源节点VCC、公共节点COM、接地节点GND、输入节点N。其中，输入节点N包括第一输入节点NO1、第二输入节点NO2、第三输入节点NC1、第四输入节点NC2。使能节点IN包括第一使能节点IN1和第二使能节点IN2。公共节点COM包括第一公共节点COM1和第二公共节点COM2。第一输入管脚1与第一输入节点NO1耦合，第二输入管脚2与第三输入节点NC1耦合，接地管脚3与接地节点GND耦合，第三输入管脚4与第四输入节点NC2耦合，第四输入管脚5与第二输入节点NO2耦合，第一使能管脚6与第一使能节点IN1耦合，第一公共管脚7与第一公共节点COM1耦合，电源管脚8与电源节点VCC耦合，第二使能管脚9与第二使能节点IN2耦合，第二公共管脚10与第二公共节点COM2耦合。
示例性的，对外接口40例如为USB 2.0。USB信号包括正差分信号USB_DP和负差分信号USB_DP。低速模拟模拟信号包括左声道信号L和右声道信号R。
示例性的，当传输的信号为正差分信号USB_DP和负差分信号USB_DP时，第一输入节点NO1将接收的正差分信号USB_DP传输至第一输入管脚1，第一使能节点IN1将接收的第一使能电压传输至第一使能管脚6，以控制第一公共管脚7与第一输入管脚1导通，正差分信号USB_DP通过模拟开关30传输至第一公共节点COM1，以通过第一公共节点COM1传输至外接设备(例如为电脑)。同时，第二输入节点NO2将接收的负差分信号USB_DP传输至第四输入管脚5，第二使能节点IN2将接收的第二使能电压 传输至第二使能管脚9，以控制第二公共管脚10与第四输入管脚5导通，负差分信号USB_DP通过模拟开关30传输至第二公共节点COM2，以通过第二公共节点COM2传输至外接设备。从而实现USB信号的传输。
当传输的信号为左声道信号L和右声道信号R时，第三输入节点NC1将接收的左声道信号L传输至第二输入管脚2，第一使能节点IN1接收的第一使能电压传输至第一使能管脚6，以控制第一公共管脚7与第二输入管脚2导通，左声道信号L通过模拟开关30传输至第一公共节点COM1，以通过第一公共节点COM1传输至外接设备(例如为耳机)。同时，第四输入节点NC2将接收的右声道信号R传输至第三输入管脚4，第二使能节点IN2接收的第二使能电压传输至第二使能管脚9，以控制第二公共管脚10与第三输入管脚4导通，右声道信号R通过模拟开关30传输至第二公共节点COM2，以通过第二公共节点COM2传输至外接设备。从而实现音频模拟信号的传输。
如此，当开关电路50设置于电子设备100中时，由于开关电路50的模拟开关30可以为低速模拟开关，也就是说，通过包括低速模拟开关的开关电路50完成电子设备100内高速差分信号的传输，或者，完成电子设备100与外接设备之间高速差分信号的传输，这样一来，可以降低电子设备100的成本。
此外，当模拟开关30传输的信号为差分信号时，为了减少模拟开关30内部的相互耦合，还可以将高速差分信号分别传输在两个独立的低速模拟开关上，可选的，该两个低速模拟开关可以紧邻。也就是说，开关电路50可以仅包括一个模拟开关30，例如参见图8，但不构成对本申请的限定，开关电路50还可以包括L个模拟开关，其中，L为大于或等于2的正整数。
在一些可能实现的方式中，参见图22，开关电路50包括两个模拟开关30。两个模拟开关30包括第一模拟开关31和第二模拟开关32。第一模拟开关31和第二模拟开关32例如与图2对应实施例中模拟开关30的结构相同，具体可以参见图2中对模拟开关30各管脚的描述，此处不再赘述。开关电路50还包括使能节点IN、电源节点VCC、公共节点COM、接地节点GND、输入节点N。其中，输入节点N包括第一输入节点NO1、第二输入节点NO2、第三输入节点NC1、第四输入节点NC2。使能节点IN包括第一使能节点IN1和第二使能节点IN2。公共节点COM包括第一公共节点COM1和第二公共节点COM2。接地节点GND包括第一接地节点GND1和第二接地节点GND2。电源节点VCC包括第一电源节点VCC1和第二电源节点VCC2。第一模拟开关31对应的第一输入管脚1与第一输入节点NO1耦合，第一模拟开关31对应的接地管脚2与第一接地节点GND1耦合，第一模拟开关31对应的第二输入管脚2与第三输入节点NC1耦合，第一模拟开关31对应的使能管脚4与第一使能节点IN1耦合，第一模拟开关31对应的电源管脚5与第一电源节点VCC1耦合，第一模拟开关31对应的公共管脚6与第一公共节点COM1耦合。第二模拟开关32对应的第一输入管脚1与第四输入节点NC2耦合，第二模拟开关32对应的接地管脚2与第二接地节点GND2耦合，第二模拟开关32对应的第二输入管脚3与第二输入节点NO2耦合，第二模拟开关32对应的使能管脚4与第二使能节点IN2耦合，第二模拟开关32对应的电源管脚5与第二电源节点VCC2耦合，第二模拟开关32对应的公共管脚6与第二公共节点COM2耦合。
示例性的，对外接口40例如为USB 2.0。USB信号包括正差分信号USB_DP和负差分信号USB_DP。低速模拟模拟信号包括左声道信号L和右声道信号R。
示例性的，当传输的信号为正差分信号USB_DP和负差分信号USB_DP时，第一输入节点NO1将接收的正差分信号USB_DP传输至第一模拟开关31的第一输入管脚1，第一使能节点IN1接收的第一使能电压传输至第一模拟开关31的使能管脚4，以控制第一模拟开关31的公共管脚6与第一输入管脚1导通，正差分信号USB_DP通过模拟开关30传输至第一公共节点COM1，以通过第一公共节点COM1传输至外接设备(例如为电脑)。同时，第二输入节点NO2将接收的负差分信号USB_DP传输至第二模拟开关32的第二输入管脚3，第二使能节点IN2接收的第二使能电压传输至第二模拟开关32的使能管脚4，以控制第二模拟开关32的公共管脚6与第二模拟开关32的第二输入管脚3导通，负差分信号USB_DP通过模拟开关30传输至第二公共节点COM2，以通过第二公共节点COM2传输至外接设备。从而实现USB信号的传输。
当传输的信号为左声道信号L和右声道信号R时，第三输入节点NC1将接收的左声道信号L传输至第一模拟开关31的第二输入管脚3，第一使能节点IN1接收的第一使能电压传输至第一模拟开关31的使能管脚4，以控制第一模拟开关31的公共管脚6与第二输入管脚3导通，左声道信号L通过模拟开关30传输至第一公共节点COM1，以通过第一公共节点COM1传输至外接设备(例如为耳机)。同时，第四输入节点NC2将接收的右声道信号R传输至第二模拟开关32的第一输入管脚1，第二使能节点IN2接收的第二使能电压传输至第二模拟开关32的使能管脚4，以控制第二模拟开关32的公共管脚6与第一输入管脚1导通，右声道信号R通过模拟开关30传输至第二公共节点COM2，以通过第二公共节点COM2传输至外接设备。从而实现音频模拟信号的传输。
此外，当模拟开关30传输的信号为差分信号时，上述示例(参见图22)以阻抗器件60耦合于第一接地节点GND1与第一模拟开关31的接地管脚2之间，阻抗器件60耦合于第一使能节点IN1与第一模拟开关31的使能管脚4之间，阻抗器件60耦合于第一电源节点VCC1与第一模拟开关31的电源管脚5之间，以及，阻抗器件60耦合于第二接地节点GND2与第二模拟开关32的接地管脚2之间，阻抗器件60耦合于第二使能节点IN2与第二模拟开关32的使能管脚4之间，阻抗器件60耦合于第二电源节点VCC2与第二模拟开关32的电源管脚5之间为例进行的说明。由前述内容可知，阻抗器件60还可以仅耦合于其中一个管脚和与该管脚对应的节点之间；或者，阻抗器件60耦合于其中一个管脚和与该管脚对应的节点之间；以及，另一个管脚和与该管脚对应的节点之间。在此情况下，可选的，第一模拟开关31和第二模拟开关32对应的阻抗器件60的数量相同，阻抗器件60的类型相同，且该阻抗器件60的位置相同，也就是说，阻抗器件60对应的管脚和节点相同。
例如，参见图23，当阻抗器件60仅耦合于其中一个管脚和与该管脚对应的节点之间时，阻抗器件60耦合于第一接地节点GND1和第一模拟开关31的接地管脚2之间，以及，阻抗器件60耦合于第二接地节点GND2和第二模拟开关32的接地管脚2之间。
再如，参见图24，当阻抗器件60耦合于其中一个管脚和与该管脚对应的节点之 间；以及，阻抗器件60耦合于另一个管脚和与该管脚对应的节点之间时，阻抗器件60耦合于第一接地节点GND1和第一模拟开关31的接地管脚2之间，阻抗器件60耦合于第一使能节点IN1和第一模拟开关31的使能管脚4之间，以及，阻抗器件60耦合于第二接地节点GND2和第二模拟开关32的接地管脚2之间，阻抗器件60耦合于第二使能节点IN2和第二模拟开关32的使能管脚4之间。
这样设置是由于，每个模拟开关30对应的阻抗器件60对差分信号(正差分信号USB_DP和负差分信号USB_DP)的影响(防止信号泄露)相同，提高信号的可靠性。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (18)

  1. 一种开关电路，其特征在于，包括：至少一个模拟开关、输入节点、电源节点、接地节点、使能节点、公共节点；
    所述模拟开关包括输入管脚、电源管脚、接地管脚、使能管脚、公共管脚；所述输入管脚与所述输入节点耦合，所述电源管脚与所述电源节点耦合，所述接地管脚与所述接地节点耦合，所述使能管脚与所述使能节点耦合，所述公共管脚与所述公共节点耦合；
    所述开关电路还包括：至少一个阻抗器件；其中，所述阻抗器件耦合于所述电源管脚与所述电源节点之间、所述接地管脚与所述接地节点之间以及所述使能管脚与所述使能节点之间中的至少一个之间。
  2. 根据权利要求1所述的开关电路，其特征在于，所述输入节点包括第一输入节点和第二输入节点；所述公共节点包括第一公共节点和第二公共节点；所述使能节点包括第一使能节点和第二使能节点；
    所述第一输入节点、所述第二输入节点、所述第一公共节点、所述第二公共节点、所述第一使能节点和所述第二使能节点分别与所述模拟开关的不同管脚耦合；
    所述第一输入节点用于接收正差分信号；所述第一使能节点用于接收第一使能电压，并将所述第一使能电压传输至与所述第一使能节点耦合的使能管脚处，以使与第一公共节点耦合的公共管脚和与所述第一输入节点耦合的输入管脚导通；与所述第一公共节点耦合的公共管脚用于将所述正差分信号传输至所述第一公共节点；
    所述第二输入节点用于接收负差分信号；所述第二使能节点用于接收第二使能电压，并将所述第二使能电压传输至与所述第二使能节点耦合的使能管脚处，以使与第二公共节点耦合的公共管脚和与所述第二输入节点耦合的输入管脚导通；与所述第二公共节点耦合的公共管脚用于将所述负差分信号传输至所述第二公共节点。
  3. 根据权利要求2所述的开关电路，其特征在于，包括：至少两个模拟开关，至少两个模拟开关包括第一模拟开关和第二模拟开关；
    所述第一输入节点与所述第一模拟开关中的输入管脚耦合，所述第一公共节点与所述第一模拟开关中的公共管脚耦合；
    所述第二输入节点和所述第二模拟开关中的输入管脚耦合，所述第二公共节点与所述第二模拟开关中的公共管脚耦合。
  4. 根据权利要求3所述的开关电路，其特征在于，所述第一模拟开关对应的所述阻抗器件的数量和所述第二模拟开关对应的所述阻抗器件的数量相同。
  5. 根据权利要求3或4所述的开关电路，其特征在于，所述第一模拟开关对应的所述阻抗器件的位置和所述第二模拟开关对应的所述阻抗器件的位置相同。
  6. 根据权利要求1-5任一项所述的开关电路，其特征在于，所述模拟开关的开关速度小于或等于100兆赫兹。
  7. 根据权利要求1-6任一项所述的开关电路，其特征在于，所述阻抗器件的阻抗值大于600欧姆。
  8. 根据权利要求1-7任一项所述的开关电路，其特征在于，所述阻抗器件包括电感、磁珠或电感和电容的组合。
  9. 根据权利要求1-8任一项所述的开关电路，其特征在于，包括：至少三个所述阻抗器件；三个所述阻抗器件分别耦合于所述接地节点与所述接地管脚之间、所述使能节点与所述使能管脚之间以及所述电源节点与所述电源管脚之间。
  10. 一种开关电路，其特征在于，包括：至少一个模拟开关、输入节点、电源节点、接地节点、使能节点、公共节点；
    所述模拟开关包括输入管脚、电源管脚、接地管脚、使能管脚、公共管脚；所述输入管脚与所述输入节点耦合，所述电源管脚与所述电源节点耦合，所述接地管脚与所述接地节点耦合，所述使能管脚与所述使能节点耦合，所述公共管脚与所述公共节点耦合；
    所述开关电路还包括：至少一个阻抗器件；其中，所述阻抗器件耦合于所述电源管脚与所述电源节点之间、所述接地管脚与所述接地节点之间以及所述使能管脚与所述使能节点之间中的至少一个之间；
    其中，所述阻抗器件包括电感、磁珠或电感和电容的组合；
    当所述模拟开关为低速模拟开关时，所述开关电路用于传输高速信号；
    当所述模拟开关为高速模拟开关时，所述开关电路用于传输更高速信号。
  11. 根据权利要求10所述的开关电路，其特征在于，所述输入节点包括第一输入节点和第二输入节点；所述公共节点包括第一公共节点和第二公共节点；所述使能节点包括第一使能节点和第二使能节点；
    所述第一输入节点、所述第二输入节点、所述第一公共节点、所述第二公共节点、所述第一使能节点和所述第二使能节点分别与所述模拟开关的不同管脚耦合；
    所述第一输入节点用于接收正差分信号；所述第一使能节点用于接收第一使能电压，并将所述第一使能电压传输至与所述第一使能节点耦合的使能管脚处，以使与第一公共节点耦合的公共管脚和与所述第一输入节点耦合的输入管脚导通；与所述第一公共节点耦合的公共管脚用于将所述正差分信号传输至所述第一公共节点；
    所述第二输入节点用于接收负差分信号；所述第二使能节点用于接收第二使能电压，并将所述第二使能电压传输至与所述第二使能节点耦合的使能管脚处，以使与第二 公共节点耦合的公共管脚和与所述第二输入节点耦合的输入管脚导通；与所述第二公共节点耦合的公共管脚用于将所述负差分信号传输至所述第二公共节点。
  12. 根据权利要求11所述的开关电路，其特征在于，包括：至少两个模拟开关，至少两个模拟开关包括第一模拟开关和第二模拟开关；
    所述第一输入节点与所述第一模拟开关中的输入管脚耦合，所述第一公共节点与所述第一模拟开关中的公共管脚耦合；
    所述第二输入节点和所述第二模拟开关中的输入管脚耦合，所述第二公共节点与所述第二模拟开关中的公共管脚耦合。
  13. 根据权利要求12所述的开关电路，其特征在于，所述第一模拟开关对应的所述阻抗器件的数量和所述第二模拟开关对应的所述阻抗器件的数量相同。
  14. 根据权利要求12或13所述的开关电路，其特征在于，所述第一模拟开关对应的所述阻抗器件的位置和所述第二模拟开关对应的所述阻抗器件的位置相同。
  15. 根据权利要求10-13任一项所述的开关电路，其特征在于，所述模拟开关的开关速度小于或等于100兆赫兹。
  16. 根据权利要求10-13任一项所述的开关电路，其特征在于，所述阻抗器件的阻抗值大于600欧姆。
  17. 根据权利要求10-13任一项所述的开关电路，其特征在于，包括：至少三个所述阻抗器件；三个所述阻抗器件分别耦合于所述接地节点与所述接地管脚之间、所述使能节点与所述使能管脚之间以及所述电源节点与所述电源管脚之间。
  18. 一种电子设备，其特征在于，包括权利要求1-17任一项所述的开关电路。
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