WO2023060595A9 - 阵列基板及制作方法、显示面板、显示装置 - Google Patents

阵列基板及制作方法、显示面板、显示装置 Download PDF

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Publication number
WO2023060595A9
WO2023060595A9 PCT/CN2021/124215 CN2021124215W WO2023060595A9 WO 2023060595 A9 WO2023060595 A9 WO 2023060595A9 CN 2021124215 W CN2021124215 W CN 2021124215W WO 2023060595 A9 WO2023060595 A9 WO 2023060595A9
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WIPO (PCT)
Prior art keywords
layer
base substrate
metal
touch
common electrode
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PCT/CN2021/124215
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English (en)
French (fr)
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WO2023060595A1 (zh
Inventor
吕凤珍
谢勇贤
邹志翔
唐川江
曲峰
杨通
马小叶
张然
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/124215 priority Critical patent/WO2023060595A1/zh
Priority to CN202180002929.6A priority patent/CN116964521A/zh
Publication of WO2023060595A1 publication Critical patent/WO2023060595A1/zh
Publication of WO2023060595A9 publication Critical patent/WO2023060595A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method, a display panel, and a display device.
  • a liquid crystal display panel (Liquid Crystal Display, LCD) is usually formed by combining an array substrate and a color filter substrate and injecting liquid crystal between the two substrates.
  • the purpose of the present disclosure is to provide an array substrate and a manufacturing method, a display panel, and a display device.
  • the array substrate helps to adjust the flatness at the crossing positions of data lines and scan lines.
  • a display panel comprising:
  • a base substrate including a display area and a peripheral area located on the periphery of the display area;
  • the driving circuit layer is arranged on one side of the base substrate and is located in the display area, and includes a plurality of data lines and a plurality of scanning lines, and the plurality of data lines extend along the first direction and are arranged at intervals along the second direction
  • the plurality of scanning lines extend along the second direction and are arranged at intervals along the first direction, the second direction intersects with the first direction, and the data lines intersect with the scanning lines defining a plurality of sub-pixel regions;
  • the metal layer is arranged on the side of the driving circuit layer away from the base substrate and is located in the display area, the metal layer includes a plurality of metal blocks arranged at intervals, and the metal blocks are located between the data lines and the the intersection of the scanlines.
  • the metal layer further includes a plurality of touch signal lines, and the orthographic projection of the touch signal lines on the base substrate is located in the sub-pixel area on the In addition to the orthographic projection on the base substrate, and the orthographic projection of the touch signal line on the base substrate and the orthographic projection of the data line on the base substrate at least partially overlap;
  • the metal block includes a touch connection metal block and a metal spacer block, the touch connection metal block is connected to the touch signal line, and there is a gap between the metal spacer block and the touch signal line. spacing.
  • the array substrate further includes:
  • the common electrode is arranged on the side of the driving circuit layer away from the base substrate, the common electrode includes a plurality of touch units distributed at intervals, and the touch unit includes a plurality of interconnected common electrode blocks;
  • the metal layer is disposed between the driving circuit layer and the common electrode, or on a side of the common electrode away from the base substrate;
  • the touch connection metal block includes a first touch metal block and a second touch metal block, and the touch signal line passes through the first touch metal block and one of the common electrodes in the touch unit block connection, the second touch metal block is not connected to the common electrode block; the metal spacer block is connected to the common electrode block through a via hole.
  • the touch control unit includes a plurality of common electrode blocks arranged in an array, wherein at least two of the common electrode blocks are arranged in a row along the first direction, and at least The two common electrode blocks are arranged along the second direction to form a row;
  • the common electrode blocks in two adjacent rows are connected through a row connection part, and the common electrode blocks in two adjacent columns are connected through a column connection part;
  • the column connection part includes an upper connection part connected to the upper area of the common electrode block and a lower connection part connected to the lower area of the common electrode block.
  • the sub-pixel area includes a red sub-pixel area, a green sub-pixel area and a blue sub-pixel area, at least one of the red sub-pixel area, at least one green sub-pixel area and At least one blue sub-pixel area is arranged and combined along the second direction to form a pixel unit area, and one pixel unit area corresponds to one common electrode block;
  • the orthographic projection of the row connecting portion on the base substrate is located between the orthographic projections of two adjacent sub-pixel regions corresponding to the common electrode block on the base substrate.
  • the common electrode block includes a main body and a first protruding portion and a second protruding portion connected to one side of the main body, the first protruding portion is connected to the The middle part of one side of the main body, and the orthographic projection of the first protrusion on the base substrate is located between the orthographic projections of the two adjacent sub-pixel regions corresponding to the common electrode block on the base substrate Between, the second protruding part is connected to the corner of the main body;
  • the metal spacer includes a first spacer, the orthographic projection of the first spacer on the base substrate at least partially overlaps with the first protrusion, and the first spacer passes through the via hole connected with the first protrusion;
  • the number of the first protrusions is multiple, and when two adjacent rows of the common electrode blocks are connected, part of the first protrusions are reused as the row connection parts;
  • the orthographic projection of the first touch metal block on the base substrate and the orthographic projection of the second protrusion of one of the common electrode blocks in the touch unit on the base substrate are at least at least partially overlapped, and the first touch metal block is connected to the second protruding part through a via hole.
  • the orthographic projection of part of the data lines on the base substrate is located at the position of the touch signal line on the base substrate. within the orthographic projection.
  • the width of the touch signal line is 5.2-6.2 ⁇ m, and the width of the data line is 2.5-3.5 ⁇ m.
  • the metal spacer block includes a first side, a second side and a third side connected in sequence, and the second side and the third side are along the first direction Located on one side of the first side and parallel to the first side, the distance between the second side and the first side is greater than the distance between the third side and the first side, The orthographic projection of the connecting via hole between the metal spacer block and the common electrode block on the base substrate is located between the orthographic projections of the first side and the second side on the base substrate .
  • the size of the metal spacer block in the second direction is 16-17 ⁇ m, and the distance between the first side and the second side is 11.6- 12.6 ⁇ m, the distance between the first side and the third side is 9.2-10.2 ⁇ m.
  • the orthographic projection of the touch signal line on the base substrate is located in the red sub-pixel region and the blue sub-pixel region on the base substrate between the orthographic projections of .
  • the driving circuit layer further includes:
  • a gate layer is provided on one side of the base substrate, the scan line is provided on the same layer as the gate layer, the gate layer includes a gate, and the scan line is connected to the gate;
  • a gate insulating layer disposed on a side of the gate layer away from the base substrate, the gate insulating layer covering the surface of the gate layer;
  • the source-drain layer includes a source electrode covering one end of the active layer and a drain electrode covering the other end of the active layer, the data line is set on the same layer as the source-drain layer line, and the data line and the drain connection.
  • the orthographic projection of the metal block on the substrate covers the gap between the orthographic projections of the source and the drain on the substrate .
  • the array substrate further includes:
  • Signal wires arranged on one side of the base substrate and located in the peripheral area, include data wires and scan wires, the data wires are connected to the data wires and arranged on the same layer, and the scan wires are connected to the scan wires line same layer setting;
  • the touch lead is arranged on one side of the base substrate and located in the peripheral area, the touch lead is connected to the touch signal line and arranged on the same layer;
  • the orthographic projections of the data wires, the scan wires and the touch wires on the base substrate are at least partially overlapped.
  • the peripheral area includes a binding area; the array substrate further includes:
  • pads provided on one side of the base substrate and located in the binding area, the pads include a first pad, a second pad, and a third pad;
  • the first pad is connected to the data lead wire, the first pad includes a first conductive layer and a second conductive layer, the first conductive layer is set on the same layer as the data line, and the first pad includes a first conductive layer and a second conductive layer.
  • the second conductive layer is arranged on the same layer as the pixel electrode, and the second conductive layer is connected to the first conductive layer through a via hole;
  • the second pad is connected to the scan wire, the second pad includes a third conductive layer and a fourth conductive layer, the third conductive layer is set on the same layer as the scan line, and the fourth conductive layer The layer is set on the same layer as the pixel electrode, and the fourth conductive layer is connected to the third conductive layer through a via hole;
  • the third pad is connected to the touch lead, the third pad includes a fifth conductive layer and a sixth conductive layer, the fifth conductive layer is set on the same layer as the touch signal line, the The sixth conductive layer is disposed on the same layer as the pixel electrode, and the sixth conductive layer is connected to the fifth conductive layer through a via hole.
  • a method for manufacturing an array substrate including:
  • the base substrate including a display area and a peripheral area located on the periphery of the display area;
  • a driving circuit layer is formed on one side of the base substrate.
  • the driving circuit layer is located in the display area and includes a plurality of data lines and a plurality of scanning lines.
  • the plurality of data lines extend along the first direction and extend along the second direction.
  • the two directions are arranged at intervals, the plurality of scanning lines extend along the second direction, and are arranged at intervals along the first direction, the second direction intersects with the first direction, and the data lines and the The scanning lines cross each other to define a plurality of sub-pixel regions;
  • a metal layer is formed on the side of the driving circuit layer away from the base substrate, the metal layer is located in the display area, the metal layer includes a plurality of metal blocks arranged at intervals, and the metal blocks are located in the the intersection of the data line and the scan line.
  • a display panel including:
  • a color filter substrate disposed on one side of the array substrate
  • a plurality of spacers are arranged between the array substrate and the color filter substrate, the spacers are in one-to-one correspondence with the metal blocks, and the tops of the spacers are on the base substrate at least half of the orthographic projection lies within the orthographic projection of the metal block on the substrate substrate;
  • the liquid crystal layer is arranged between the array substrate and the color filter substrate.
  • the sub-pixel area includes a red sub-pixel area, a blue sub-pixel area, and a green sub-pixel area
  • the spacer includes a main spacer, and the main spacer
  • the orthographic projection of the object on the base substrate is located between the red sub-pixel area and the orthographic projection of the blue sub-pixel area on the base substrate.
  • the distance between the orthographic projection of the spacer on the substrate and the orthographic projection of the source and the drain on the substrate is The gaps partially overlap.
  • a display device including the display panel as described in the third aspect.
  • the array substrate provided in the present disclosure includes a base substrate, a driving circuit layer and a metal layer, wherein the metal layer includes a plurality of metal blocks arranged at intervals, and the metal blocks are located at intersections of data lines and scan lines.
  • the metal block helps to adjust the flatness at the crossing position of the data line and the scanning line, so that when other structures are formed at the position of the metal block, the height uniformity of the structure and the stability of the distribution position are maintained .
  • FIG. 1 is a schematic cross-sectional view of a display panel in an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a display panel in another exemplary embodiment of the present disclosure.
  • Fig. 3 is a schematic diagram of the structure of a substrate in an exemplary embodiment of the present disclosure.
  • Fig. 4 is a schematic diagram of the planar structure of an array substrate in an exemplary embodiment of the present disclosure
  • FIG. 5 is a schematic plan view of a display panel in an exemplary embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a common electrode structure in an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a partial planar structure of an array substrate in an exemplary embodiment of the present disclosure.
  • Fig. 8 is a sectional view in the direction of A-A in Fig. 7;
  • FIG. 9 is a schematic structural diagram of a common electrode block in an exemplary embodiment of the present disclosure.
  • Fig. 10 is a schematic diagram of the connection structure of the common electrode blocks in the touch control unit according to the exemplary embodiment of the present disclosure
  • Fig. 11 is a schematic structural diagram of a metal spacer block in an exemplary embodiment of the present disclosure.
  • Fig. 13 is a B-B direction sectional view in Fig. 12;
  • FIG. 14 is a schematic diagram of a pad plane structure in an exemplary embodiment of the present disclosure.
  • 16 is a cross-sectional view of a spacer on an array substrate in an exemplary embodiment of the present disclosure
  • FIG. 17 is a schematic flowchart of a method for preparing an array substrate in an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure.
  • a structure When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is “directly” placed on another structure, or that a structure is “indirectly” placed on another structure through another structure. other structures.
  • Various wirings such as scanning lines and data lines, are usually arranged in the array substrate of the liquid crystal display panel.
  • the width of the scanning lines and data lines is usually designed to be narrow, resulting in uneven heights of the spacers above them, and the stability is not good, thus affecting the liquid crystal display.
  • the thickness of the case of the display panel, etc. will cause adverse effects.
  • the present disclosure provides an array substrate, including a base substrate 1 , a driving circuit layer 2 and a metal layer 3 .
  • the base substrate 1 includes a display area 11 and a peripheral area 12 located on the periphery of the display area 11;
  • the driving circuit layer 2 is arranged on one side of the base substrate 1 and located in the display area 11, including a plurality of data lines 22 and a plurality of scanning Lines 21, data lines 22 and scan lines 21 intersect each other to define a plurality of sub-pixel regions 9;
  • the metal layer 3 is arranged on the side of the driving circuit layer 2 away from the base substrate 1 and is located in the display region 11, and the metal layer 3 includes a plurality of intervals
  • the metal blocks 31 are arranged, and the metal blocks 31 are located at intersections of the data lines 22 and the scan lines 21 .
  • the array substrate provided by the present disclosure includes a base substrate 1, a driving circuit layer 2 and a metal layer 3, wherein the metal layer 3 includes a plurality of metal blocks 31 arranged at intervals, and the metal blocks 31 are located on the data line 22 and the scan line 21 of the intersection.
  • the metal block 31 helps to adjust the flatness at the crossing position of the data line 22 and the scanning line 21, so that when other structures are formed at the position of the metal block 31, the uniformity of the height of the structure and the distribution position of the structure are maintained. on the stability.
  • An embodiment of the present disclosure provides an array substrate, which can be used to form a TFT-LCD (Thin Film Transistor Liquid Crystal Display, Thin Film Transistor Liquid Crystal Display) display panel.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, Thin Film Transistor Liquid Crystal Display
  • the base substrate 1 includes a display area 11 and a non-display area 11 located on the periphery of the display area 11 .
  • the base substrate 1 may be a base substrate of inorganic material, or a base substrate of organic material.
  • the material of the base substrate 1 can be glass materials such as soda-lime glass, quartz glass, sapphire glass, or can be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the base substrate 1 can be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyethersulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (Polycarbonate, PC), polyethylene terephthalate (Polyethylene terephthalate, PET), Polyethylene naphthalate (PEN) or a combination thereof.
  • the base substrate 1 may also be a flexible base substrate.
  • the material of the base substrate 1 may be polyimide (PI).
  • the base substrate 1 can also be a composite of multi-layer materials.
  • the base substrate 1 can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, A first polyimide layer and a second polyimide layer.
  • the driving circuit layer 2 is arranged on one side of the base substrate 1 and is located in the display area 11.
  • the driving circuit layer 2 includes a plurality of data lines 22 and a plurality of scanning lines 21.
  • the data lines 22 and the scanning lines 21 cross each other to define a plurality of sub-substrates.
  • the data line 22 is disposed on a side of the scan line 21 away from the base substrate 1 .
  • the extending direction and arrangement direction of the data lines 22 and the scanning lines 21 can have various designs.
  • a plurality of data lines 22 extend along the column direction and are arranged at intervals along the row direction
  • a plurality of scanning lines 21 extend along the row direction and are arranged at intervals along the column direction.
  • the row direction and the column direction are relative terms, and the intersection angle between the row direction and the column direction may be greater than 0° and less than or equal to 90°.
  • a plurality of data lines 22 extend along the first direction X and are arranged at intervals along the second direction Y, the first direction X and the second direction Y intersect, and the angle is greater than 0°. Less than or equal to 90°.
  • a plurality of scanning lines 21 extend along the second direction Y and are arranged at intervals along the first direction X.
  • the first direction X is perpendicular to the second direction Y.
  • the scan line 21 and the data line 22 can be a layer of conductive material, or a stack of multiple layers of conductive material.
  • the scan line 21 may include a first conductive material layer, a second conductive material layer and a first conductive material layer stacked in sequence, ie present a sandwich structure.
  • the first conductive material layer can be selected from corrosion-resistant metal or alloy, such as molybdenum;
  • the second conductive material layer can be selected from high-conductivity metal or alloy, such as copper, aluminum, silver, etc. can be selected.
  • the scan line 21 may include a layer of conductive material, for example, the material of the scan line 21 may be molybdenum.
  • the data lines 22 may include the same conductive material as the scan lines 21 .
  • the driving circuit layer 2 further includes a gate layer 24, which is arranged on one side of the base substrate 1, and the scanning lines 21 and the gate layer 24 Same level settings.
  • the gate layer includes a gate, and the scan line 21 is connected to the gate for providing a scan signal.
  • the gate layer 24 may include metal material or alloy material to ensure its good electrical conductivity.
  • the gate layer 24 can also be made of transparent conductive materials, such as ITO (indium tin oxide), IZO (indium zinc oxide) and the like.
  • the gate layer 24 and the scan line 21 can be formed by a photolithography process, and the scan line 21 and the gate layer 24 can be formed by the same photolithography process.
  • a layer of conductive material may be deposited on one side of the base substrate 1 first, and then the layer of conductive material may be patterned to obtain the required scan lines 21 and gate layer 24 .
  • the driving circuit layer 2 further includes a gate insulating layer 25 disposed on a side of the gate layer 24 away from the substrate 1 , and the gate insulating layer 25 covers the surface of the gate layer 24 .
  • the gate insulating layer 25 can be a single film layer such as silicon nitride, silicon oxide, aluminum oxide, etc. or a multi-film layer formed by a combination thereof.
  • the gate insulating layer 25 can be formed by a deposition method, for example, a silicon oxide layer can be formed by vapor phase chemical deposition as a gate insulating material layer, and the gate insulating layer 25 can be formed after the gate insulating material layer is patterned.
  • the driving circuit layer 2 further includes an active layer 26 disposed on a side of the gate insulating layer 25 away from the base substrate 1 .
  • the material of the active layer 26 can be polysilicon or IGZO (Indium Gallium Zinc Oxide), which can change the conductivity at different positions through processes such as doping.
  • the driving circuit layer 2 also includes a source-drain layer 23 , including a source 23S covering one end of the active layer 26 and a drain 23D covering the other end of the active layer 26 , and the data lines 22 and the source-drain layer 23 are arranged on the same layer.
  • the data line 22 is connected to the drain 23D.
  • the gate layer 24, the gate insulating layer 25, the active layer 26, and the source-drain layer 23 may be used to form a thin film transistor.
  • the thin film transistor is located in the sub-pixel area 9, and serves as a component structure of the pixel driving circuit to drive the liquid crystal pixel area.
  • the driving circuit/2 further includes a planarization layer 27 disposed on a side of the source-drain layer 23 away from the substrate 1 , and the planarization layer 27 covers the surface of the source-drain layer 23 .
  • the metal layer 3 is arranged on the side of the driving circuit layer 2 away from the base substrate 1 and located in the display area 11, and the metal layer 3 includes a plurality of metal blocks arranged at intervals. 31 , the metal block 31 is located at the intersection of the data line 22 and the scan line 21 . A plurality of metal blocks 31 may be arranged in a matrix array, and a metal block 31 is provided at each intersection of the data line 22 and the scan line 21 .
  • the orthographic projection of the metal block 31 on the base substrate 1 covers the gap between the orthographic projections of the source 23S and the drain 23D on the base substrate 1 . That is, there is a gap between the orthographic projections of the source 23S and the drain 23D on the base substrate 1 , and the orthographic projection of the metal block 31 on the base substrate 1 is located in the gap and covers the gap.
  • the metal layer 3 further includes a plurality of touch signal lines 32 . 1, and the orthographic projection of the touch signal line 32 on the base substrate 1 and the orthographic projection of the data line 22 on the base substrate 1 at least partially overlap, so as to reduce the pixel opening of the touch signal line 32 rate impact.
  • the metal block 31 includes a touch connection metal block 311 and a metal spacer block 312 , the touch connection metal block 311 is connected to the touch signal line 32 , and there is a distance between the metal spacer block 312 and the touch signal line 32 .
  • the touch connection metal block 311 is in direct contact with the touch signal line 32 .
  • the orthographic projection of part of the data lines 22 on the base substrate 1 is located within the orthographic projection of the touch signal line 32 on the base substrate 1 . That is, in the second direction Y, the width of the touch signal line 32 is greater than the width of the data line 22, so as to reduce the common electrode voltage disturbance (vcom ripple). In a specific embodiment, in the second direction Y, the width of the touch signal line 32 is 5.2-6.2 ⁇ m, and the width of the data line 22 is 2.5-3.5 ⁇ m.
  • the touch connection metal block 311 , the metal spacer block 312 and the touch signal line 32 can be formed using the same material and the same photolithography process.
  • a metal material layer can be deposited and formed on the side of the driving circuit layer 2 away from the base substrate 1, and then the metal material layer can be patterned to obtain the required touch connection metal block 311, metal spacer block 312 and touch control.
  • Signal line 32 can be formed using the same material and the same photolithography process.
  • the array substrate further includes a common electrode 5 and a plurality of pixel electrodes 6 .
  • the common electrode 5 is disposed on a side of the driving circuit layer 2 away from the base substrate 1
  • a plurality of pixel electrodes 6 is disposed on a side of the common electrode 5 away from the base substrate 1 .
  • a first passivation layer 501 or/and a second passivation layer 502 are formed between the common electrode 5 and the pixel electrode 6, and the pixel electrode 6 is connected to the source electrode in the source-drain layer 23 through a via hole. connect.
  • the common electrode 5 includes a plurality of touch units 51 distributed at intervals, and the touch unit 51 includes a plurality of interconnected common electrode blocks 511 .
  • a plurality of pixel electrodes 6 are disposed on a side of the common electrode 5 away from the base substrate 1 .
  • One pixel electrode 6 corresponds to one sub-pixel region 9 .
  • the common electrodes 5 are multiplexed as touch electrodes.
  • this principle can be used to form a touch and display driver integration (Touch and Display Driver Integration, TDDI) touch screen, integrate the touch sensor into the display, and integrate the touch chip and display chip into a single chip , making the screen thinner and meeting the design requirements for thinner display products.
  • TDDI Touch and Display Driver Integration
  • the array substrate is provided with a plurality of touch units 51 (self-capacitance electrodes) on the same layer and mutually insulated.
  • touch units 51 self-capacitance electrodes
  • the capacitance of each touch unit 51 is a fixed value
  • the capacitance of the corresponding touch unit 51 is the value obtained by superimposing the human body capacitance on the fixed value.
  • the touch detection chip determines the touch position by detecting the change of the capacitance value of each touch unit 51 during the touch time period.
  • the metal layer 3 is disposed on a side of the driving circuit layer 2 away from the base substrate 1 .
  • the metal layer 3 is disposed on the side of the common electrode 5 away from the base substrate 1 ( FIG. 1 ), and in another embodiment, the metal layer 3 may be disposed on a side of the common electrode 5 close to the base substrate 1. side ( Figure 2).
  • the metal block 31 includes a touch connection metal block 311 and a metal spacer block 312 .
  • the touch connection metal block 311 includes a first touch metal block 3111 and a second touch metal block 3112
  • the touch signal line 32 passes through the first touch metal block 3111 and a common electrode block 511 in the touch unit 51 connected so that the capacitance value of the touch unit 51 can be transmitted to the touch detection chip through the touch signal line 32, so that the touch detection chip can accurately determine the touched capacitor electrode and make a corresponding response.
  • the second touch metal block 3112 is not connected to the common electrode block 511 .
  • the metal spacer block 312 is connected to the common electrode block 511 at its corresponding position, so that the voltage of the metal spacer block 312 is equal to the voltage of the common electrode block 511, so as to prevent the metal spacer block 312 from causing adverse effects on the electric field due to floating (floating) .
  • the metal layer 3 When the metal layer 3 is arranged on the side of the common electrode 5 close to the base substrate 1, that is, between the driving circuit layer 2 and the common electrode 5, the metal layer can be formed on the side of the driving circuit layer 2 away from the base substrate 1 first. 3. Subsequently, a passivation layer is formed on the side of the metal layer 3 away from the base substrate 1, and a via hole is formed by etching at a specific position of the formed passivation layer to expose the metal layer 3 at the specific position, and then the passivation layer The common electrode 5 is formed on the side of the metallization layer away from the base substrate 1 , and some common electrode blocks 511 in the formed common electrode 5 can be connected to some metal blocks 31 in the metal layer 3 through via holes.
  • the area of the via hole can be set to 9-25 ⁇ m2, and the shape of the orthographic projection of the via hole on the base substrate 1 can be roughly circular, elliptical, irregular polygonal or regular polygonal, etc., which is not limited in this disclosure.
  • the metal layer 3 When the metal layer 3 is arranged on the side of the common electrode 5 away from the base substrate 1, such as between the common electrode 5 and the pixel electrode 6 (FIG. Form the common electrode 5, then form a passivation layer 501 on the side of the common electrode 5 away from the base substrate 1, and then etch a via hole at a specific position of the formed passivation layer 501 to expose the common electrode at the specific position. Electrode 5. Afterwards, a metal layer 3 is formed on the side of the passivation layer 501 away from the base substrate 1, and some metal blocks 31 in the formed metal layer 3 can be connected to some common electrode blocks 511 in the common electrode 5 through via holes. .
  • the area of the via hole can be set to 9-25 ⁇ m2, and the shape of the orthographic projection of the via hole on the base substrate 1 can be roughly circular, elliptical, irregular polygonal or regular polygonal, etc., which is not limited in this disclosure.
  • the metal spacer block 312 includes a first side 312a, a second side 312b and a third side 312c connected in sequence, and the second side 312b and the third side 312c Located on one side of the first side 312a along the first direction X and approximately parallel to the first side 312a, the distance between the second side 312b and the first side 312a is greater than the distance between the third side 312c and the first side 312a, The orthographic projection of the connection via hole between the metal spacer block 312 and the common electrode block 511 on the substrate 1 is located between the orthographic projections of the first side 312 a and the second side 312 b on the substrate 1 .
  • the first side 312a , the second side 312b and the third side 312c are substantially parallel to the second direction Y, and the lengths of the second side 312b and the third side 312c are smaller than the length of the first side 312a .
  • the metal spacer block 312 also includes a fourth side 312d and a fifth side 312e located at both ends of the first side 312a in the second direction Y, the fourth side 312d and the fifth side 312e are substantially perpendicular to the first side 312a .
  • the first side 312a, the fourth side 312d, the second side 312b, the third side 312c and the fifth side 312e are sequentially connected to form a closed figure.
  • the metal spacer block 312 by increasing the distance between the second side 312b and the first side 312a, the metal spacer block 312 includes the area of the second side 312b and the common area above it.
  • the electrode block 511 has a lamination area, so as to facilitate the connection between the metal spacer block 312 and the common electrode block 511 .
  • the shape design of the metal spacer block 312 is also applicable to the first touch metal block 3111 .
  • the shape can be the same as that of the metal spacer block 312 .
  • the second touch metal block 3112 does not need to be connected to the common electrode block, its shape can be set according to actual needs.
  • the second touch metal block 3112 is a regular polygon
  • its orthographic projection on the substrate 1 is an axisymmetric regular polygon, such as a left-right symmetrical regular hexagon or octagon.
  • the orthographic projection of the second touch metal block 3112 on the base substrate 1 may also be a regular polygon with central symmetry.
  • the second touch metal block is a symmetrical regular octagon, and the size of the second touch metal block 3112 in the second direction Y is 16-17 ⁇ m.
  • the size in the first direction X is 9.2-10.2 ⁇ m.
  • the size of the metal spacer block 312 in the second direction Y is 16-17 ⁇ m
  • the distance between the second side 312 b and the first side 312 a is 11.6-12.6 ⁇ m
  • the distance between the third side 312 c and the first side 312 a is 11.6-12.6 ⁇ m.
  • the distance between the sides 312a is 9.2-10.2 ⁇ m.
  • the touch unit 51 includes a plurality of common electrode blocks 511 arranged in an array, and at least two common electrode blocks 511 are arranged along the first direction.
  • X is arranged to form columns
  • at least two common electrode blocks are arranged along the second direction Y to form rows.
  • the touch control unit 51 two adjacent rows of common electrode blocks 511 are connected through a row connection portion 512
  • two adjacent columns of common electrode blocks 511 are connected through a column connection portion 513 .
  • the column connecting portion 513 includes an upper connecting portion 5111 connected to the upper area of the common electrode block 511 and a lower connecting portion 5112 connected to the lower area of the common electrode block.
  • the column connecting portion 513 between two adjacent common electrode blocks 511 includes an upper connecting portion 5131 and a lower connecting portion 5132 to ensure the stability and firmness when the common electrode blocks 511 are connected.
  • the row connecting portion 512 and the column connecting portion 513 are disposed on the same layer as the common electrode block 511 .
  • the size of the common electrode block 511 can be set according to actual conditions. For example, it is set according to the number of corresponding sub-pixel regions 9 or pixel electrodes 6 .
  • the sub-pixel area 9 includes a red sub-pixel area 91, a green sub-pixel area 92 and a blue sub-pixel area 93, at least one red sub-pixel area 91, at least one One green sub-pixel area 92 and at least one blue sub-pixel area 93 are arranged and combined to form a pixel unit area 90 , and one pixel unit area 90 corresponds to one common electrode block 511 .
  • the orthographic projection of the row connection portion 512 on the base substrate 1 is located between the orthographic projections of two adjacent sub-pixel regions corresponding to the common electrode block 511 on the base substrate 1 .
  • a red sub-pixel region 91, a green sub-pixel region 92 and a blue sub-pixel region 93 are arranged in sequence along the second direction Y to form a pixel unit region 90, and a common electrode block 511 corresponds to a Pixel unit area 90 .
  • the orthographic projection of the row connection portion 512 on the base substrate 1 is located between the orthographic projections of the green sub-pixel region 92 and the blue sub-pixel region 93 corresponding to the common electrode block 511 on the base substrate 1 .
  • the first touch metal block 3111 and the metal spacer block 312 can be respectively connected to the common electrode block 511 through different connection positions.
  • the common electrode block 511 includes a main body 511a and a first protruding portion 511b and a second protruding portion 511c connected to one side of the main body 511a, the first protruding portion 511b It is connected to the middle of one side of the main body 511a, and the orthographic projection of the first protrusion 511b on the base substrate 1 is located between the orthographic projections of the two adjacent sub-pixel regions 9 corresponding to the common electrode block 511 on the base substrate 1 In between, the second protruding portion 511c is connected to the corner of the main body 511a.
  • the number of the first protrusions 511b can be set according to the number of sub-pixel regions 9 corresponding to the common electrode block 511, for example, when the common electrode block 511 corresponds to three sub-pixel regions 9, the first protrusion
  • the number of parts 511b may be two, correspondingly located between two adjacent sub-pixel regions 9 .
  • the metal spacer block 312 includes a first spacer block 3121, and the orthographic projection of the first spacer block 3121 on the base substrate 1 at least partially overlaps with the first protrusion 511b, and The first pad 3121 is connected to the first protruding portion 511b through a via hole.
  • there are multiple first protrusions 511b and the shapes and dimensions of different first protrusions 511b may be the same or different.
  • the corresponding first protruding portion 511 b located between the green sub-pixel area 92 and the blue sub-pixel area 93 is multiplexed as the row connecting portion 512 .
  • the size of the first protruding portion 511b can be set according to the distance between two adjacent rows of common electrode blocks 511 .
  • the number of the second protruding parts 511b is more than one, wherein part of the second protruding part 511b is provided with a touch connection metal block 311 at the corresponding position, and a part of the second protruding part 511c is provided at the corresponding position There is a metal spacer block 312 .
  • the touch connection metal block 311 connected to the touch signal line 32 can be disposed at a position corresponding to the second protruding portion 511 c of the common electrode block 511 .
  • the touch signal line 32 needs to be connected to the common electrode block 511 through the first touch metal block 3111, the orthographic projection of the first touch metal block 3111 on the base substrate 1 and a common electrode in the touch unit 51
  • the orthographic projection of the second protruding portion 511c of the block 511 on the base substrate 1 at least partially overlaps, and the first touch metal block 3111 is connected to the second protruding portion 511c through a via hole.
  • a metal spacer block 312 can be provided at the corresponding position of the second protrusion 511c of the common electrode block 511, and the metal spacer block 312 also includes a second pad Block 3122 , the orthographic projection of the second spacer 3122 on the base substrate 1 at least partially overlaps the second protrusion 511c, and the second spacer 3122 is connected to the second protrusion 511c through a via hole.
  • the array substrate further includes signal wires and touch wires 03 located in the peripheral area 12 .
  • the signal leads are arranged on one side of the base substrate 1 and located in the peripheral area 12, including data leads 01 and scan leads 02, the data leads 01 are connected to the data lines 22 and arranged on the same layer, and the scan leads 02 and the scan lines 21 are arranged on the same layer;
  • the touch lead 03 is disposed on one side of the base substrate 1 and located in the peripheral area 12 , and the touch lead 03 is connected to the touch signal line 32 and disposed on the same layer.
  • the orthographic projections of the data wires 01 , the scan wires 02 and the touch wires 03 on the base substrate 1 are at least partially overlapped.
  • an insulating layer 001 is further disposed between the film layers of the data wire 01 , the scan wire 02 and the touch wire 03 .
  • the data wires 01 , the scan wires 02 and the touch wires 03 overlap in three layers, which is beneficial to reduce the width of the fan-shaped area and realize the narrow frame design of the array substrate in this area.
  • the three layers of lead wires are stacked and insulated from each other through the insulating layer 001, which can effectively reduce the risk of short circuit between the lead wires.
  • the line widths of the data wires 01 , the scan wires 02 and the touch wires 03 can be set according to actual conditions. In a specific embodiment, the line width of the data wire 01 , the scan wire 02 and the touch wire 03 may be 2.7 ⁇ m, and when the three layers are in the same layer, the line spacing may be 2.3 ⁇ m.
  • the peripheral area 12 further includes a binding area.
  • the peripheral leads are connected to the chip to realize the transmission of touch and display signals.
  • Each lead can be connected to the chip through the transition hole.
  • the array substrate also includes pads.
  • the pads are arranged on one side of the base substrate 1 and located in the bonding area.
  • the pads include a first pad 04, a second pad 05 and a third pad 06; the first pad 04 Connected to the data lead 01, the first pad 04 includes a first conductive layer 041 and a second conductive layer 042, the first conductive layer 041 is set on the same layer as the data line 22, and the second conductive layer 042 is set on the same layer as the pixel electrode 6,
  • the second conductive layer 042 is connected to the first conductive layer 041 through via holes.
  • the second pad 05 is connected to the scan wire 02, the second pad 05 includes a third conductive layer 051 and a fourth conductive layer 052, the third conductive layer 051 is set on the same layer as the scan line 21, and the fourth conductive layer 052 is connected to the pixel electrode 6 are arranged in the same layer, and the fourth conductive layer 052 is connected to the third conductive layer 051 through via holes.
  • the third pad 06 is connected to the touch wire 03, the third pad 06 includes a fifth conductive layer 061 and a sixth conductive layer 062, the fifth conductive layer 061 is set on the same layer as the touch signal line 32, and the sixth conductive layer 062 It is arranged on the same layer as the pixel electrode 6 , and the sixth conductive layer 062 is connected to the fifth conductive layer 061 through via holes.
  • an insulating layer 002 is further disposed between the third conductive layer 051 and the first conductive layer 041
  • a passivation layer 003 is further disposed between the third conductive layer 051 and the fifth conductive layer 061 .
  • the fifth conductive layer 061 is provided with a passivation layer 004 on the side away from the third conductive layer 051, and the second conductive layer 042, the fourth conductive layer 052 and the sixth conductive layer 062 are provided on the side of the passivation layer 004 away from the fifth conductive layer 061
  • the side away from the third conductive layer 051 is connected to the first conductive layer 041 , the third conductive layer 051 and the fifth conductive layer 061 respectively through via holes.
  • the second conductive layer 042 , the fourth conductive layer 052 and the sixth conductive layer 062 can be connected to the chip, so as to realize the connection between each lead wire and the chip, so as to complete the transmission of each signal.
  • the present disclosure also provides a display panel, which includes the array substrate in any of the above embodiments, and also includes a color filter substrate 8 , a plurality of spacers 4 and a liquid crystal layer 7 .
  • the color filter substrate 8 is disposed on one side of the array substrate.
  • a plurality of spacers 4 are arranged between the array substrate and the color filter substrate 8, the spacers 4 correspond to the metal blocks 31 one by one, and the tops of the spacers 4 (the end close to the array substrate) are on the bottom of the base substrate 1. At least half of the orthographic projection lies within the orthographic projection of the metal block 31 on the base substrate 1 .
  • the metal block 31 can well support the spacer 4 and prevent the spacer 4 from shifting due to unstable support.
  • a multi-dimensional electric field is generated between the pixel electrode 6 and the common electrode 5 to drive the liquid crystal in the liquid crystal layer 7 to deflect, thereby controlling the light emission of the liquid crystal display panel in the pixel area.
  • the display panel provided by the present disclosure includes a metal layer 3 and a spacer 4, wherein the metal layer 3 includes a plurality of metal blocks 31 arranged at intervals, and the spacer 4 is arranged on the side of the metal layer 3 away from the base substrate 1 , and the orthographic projection of the spacer 4 on the base substrate 1 is located within the orthographic projection of the metal block 31 on the base substrate 1, so that the metal block 31 can stably support the spacer 4 and make the spacer 4 Maintain a high level of consistency.
  • the orthographic projection of the spacer 4 on the base substrate 1 partially overlaps the gap between the orthographic projections of the source 23S and the drain 23D on the base substrate 1 . That is, there is a gap between the orthographic projections of the source 23S and the drain 23D on the base substrate 1 , and the orthographic projection of the spacer 4 on the base substrate 1 partially overlaps the gap.
  • the spacer 4 includes a main spacer 41 and an auxiliary spacer 42 , the main spacer 41 plays the role of controlling the thickness of the box, and the auxiliary spacer 42 plays the role of auxiliary support and adjustment.
  • the main spacers 41 and the secondary spacers 42 can be arranged according to certain rules.
  • the orthographic projection of the main spacer 41 on the base substrate 1 is located on the red sub-pixel region 91 and the blue sub-pixel region 93 on the base substrate 1 between the orthographic projections of .
  • the main spacer 41 may be shifted under the action of an external force, thereby affecting the display of sub-pixels in adjacent regions.
  • the present disclosure arranges the main spacer 41 between the red sub-pixel region 91 and the blue sub-pixel region 93 space, so as to reduce the impact on the display effect after the main spacer 41 is shifted.
  • the location of the sub-spacer 42 can be set according to actual design requirements, and it can be located between any two sub-pixel regions 9 .
  • the orthographic projection of the touch signal line 32 on the base substrate 1 is located between the orthographic projections of the red sub-pixel region 91 and the blue sub-pixel region 93 on the base substrate 1. That is, the touch signal line 32 is also disposed between the red sub-pixel area 91 and the blue sub-pixel area 93 .
  • the present disclosure also provides a method for manufacturing an array substrate, including:
  • Step S100 providing a base substrate 1, the base substrate 1 includes a display area 11 and a peripheral area 12 located on the periphery of the display area 11;
  • Step S200 forming a driving circuit layer 2 on one side of the base substrate 1, the driving circuit layer 2 is located in the display area 11, and includes a plurality of data lines 22 and a plurality of scanning lines 21, and the plurality of data lines 22 extend along the first direction X , arranged at intervals along the second direction Y, a plurality of scanning lines 21 extending along the second direction Y, arranged at intervals along the first direction X, the second direction Y intersects the first direction X, and the data lines 22 and the scanning lines 21 are mutually Intersect to define a plurality of sub-pixel regions 9;
  • Step S300 forming a metal layer 3 on the side of the driving circuit layer 2 away from the base substrate 1, the metal layer 3 is located in the display area 11, the metal layer 3 includes a plurality of metal blocks 31 arranged at intervals, and the metal blocks 31 are located in the data line 22 and the intersection of scan line 21.
  • forming the driving circuit layer 2 on one side of the base substrate 1 includes:
  • a gate layer 24 and a scan line 21 are formed on one side of the base substrate 1, the scan line 21 and the gate layer 24 are arranged on the same layer, the gate layer 24 includes a gate, and the scan line 21 is connected to the gate;
  • the gate insulating layer 25 covers the surface of the gate layer 24;
  • a source-drain layer 23 is formed on the side of the active layer 26 away from the base substrate 1.
  • the source-drain layer 23 covers both ends of the active layer 26.
  • the data lines 22 and the source-drain layer 23 are arranged on the same layer.
  • the pole layer 23 includes source/drain, and the data line 22 is connected to the source/drain.
  • Embodiments of the present disclosure also provide a display device, including a display panel.
  • the display panel may be the display panel in any of the above embodiments.
  • the display device of the present disclosure may be electronic equipment such as a mobile phone, a tablet computer, and a television, which will not be listed here.

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Abstract

一种阵列基板及制作方法、显示面板、显示装置。阵列基板包括衬底基板(1)；设于衬底基板(1)一侧的驱动电路层(2)，包括多条数据线(22)和多条扫描线(21)；金属层(3)，设于驱动电路层(2)远离衬底基板(1)的一侧，包括多个间隔排布的、位于数据线(22)和扫描线(21)的交叉处的金属块(31)，有助于调整交叉位置处的平整度，维持形成在该处的其他结构的高度均一性和分布位置稳定性。

Description

阵列基板及制作方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及制作方法、显示面板、显示装置。
背景技术
液晶显示面板(Liquid Crystal Di splay,LCD)通常由阵列基板和彩膜基板对盒并在两基板之间注入液晶形成。
为了保持阵列基板和彩膜基板之间的间隙(Cell Gap，盒厚)，主要采用在两个基板对盒之前在两基板之间加入一定厚度的隔垫物(Spacer)以保持盒厚。然而，现有技术中，阵列基板上走线复杂，导致隔垫物在阵列基板上高度不一。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种阵列基板及制作方法、显示面板、显示装置，该阵列基板有助于调整数据线和扫描线交叉位置处的平整度。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种显示面板，包括：
衬底基板，包括显示区和位于显示区外围的外围区；
驱动电路层，设于所述衬底基板的一侧并位于所述显示区，包括多条数据线和多条扫描线，多条所述数据线沿第一方向延伸，沿第二方向间隔排布，多条所述扫描线沿所述第二方向延伸，沿所述第一方向间隔排布，所述第二方向和所述第一方向交叉，所述数据线和所述扫描线相互交叉界定出多个子像素区；
金属层，设于所述驱动电路层远离所述衬底基板的一侧并位于所述显示区，所述金属层包括多个间隔排布的金属块，所述金属块位于所述 数据线和所述扫描线的交叉处。
在本公开的一种示例性实施例中，所述金属层还包括多条触控信号线，所述触控信号线在所述衬底基板上的正投影位于所述子像素区在所述衬底基板上的正投影之外，且所述触控信号线在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影至少部分重叠；
其中，所述金属块包括触控连接金属块和金属隔垫块，所述触控连接金属块与所述触控信号线连接，所述金属隔垫块与所述触控信号线之间有间距。
在本公开的一种示例性实施例中，所述阵列基板还包括：
公共电极，设于所述驱动电路层远离所述衬底基板的一侧，所述公共电极包括多个间隔分布的触控单元，所述触控单元包括多个相互连接的公共电极块；
多个像素电极，设于所述公共电极远离所述衬底基板的一侧；
其中，所述金属层设于所述驱动电路层和所述公共电极之间，或所述公共电极背离所述衬底基板的一侧；
所述触控连接金属块包括第一触控金属块和第二触控金属块，所述触控信号线通过所述第一触控金属块与所述触控单元中的一个所述公共电极块连接，所述第二触控金属块与所述公共电极块不连接；所述金属隔垫块与所述公共电极块通过过孔连接。
在本公开的一种示例性实施例中，所述触控单元包括阵列排布的多个公共电极块，其中，至少两个所述公共电极块沿所述第一方向排布形成列，至少两个所述公共电极块沿所述第二方向排布形成行；
所述触控单元中相邻两行所述公共电极块之间通过行连接部连接，相邻两列所述公共电极块之间通过列连接部连接；
其中，所述列连接部包括连接于所述公共电极块上部区域的上连接部和连接于所述公共电极块下部区域的下连接部。
在本公开的一种示例性实施例中，所述子像素区包括红色子像素区、绿色子像素区和蓝色子像素区，至少一个所述红色子像素区、至少一个绿色子像素区和至少一个蓝色子像素区沿所述第二方向排布组合形成一个像素单元区，一个所述像素单元区对应于一块所述公共电极块；
所述行连接部在所述衬底基板上的正投影位于所述公共电极块对应的相邻两个子像素区在所述衬底基板上的正投影之间。
在本公开的一种示例性实施例中，所述公共电极块包括主体和连接于所述主体一侧的第一凸出部和第二凸出部，所述第一凸出部连接于所述主体一侧的中部，且所述第一凸出部在所述衬底基板上的正投影位于所述公共电极块对应的相邻两个子像素区在所述衬底基板上的正投影之间，所述第二凸出部连接于所述主体的转角处；
所述金属隔垫块包括第一垫块，所述第一垫块在所述衬底基板上的正投影与所述第一凸出部至少部分重叠，且所述第一垫块通过过孔与所述第一凸出部连接；
所述第一凸出部的数量为多个，当相邻两行所述公共电极块连接时，部分所述第一凸出部复用为所述行连接部；
所述第一触控金属块在所述衬底基板上的正投影与所述触控单元中一个所述公共电极块的所述第二凸出部在所述衬底基板上的正投影至少部分重叠，且所述第一触控金属块通过过孔与所述第二凸出部连接。
在本公开的一种示例性实施例中，在所述第二方向上，部分所述数据线在所述衬底基板上的正投影位于所述触控信号线在所述衬底基板上的正投影之内。
在本公开的一种示例性实施例中，在所述第二方向上，所述触控信号线的宽度为5.2-6.2μm，所述数据线的宽度为2.5-3.5μm。
在本公开的一种示例性实施例中，所述金属隔垫块包括依次连接的第一边、第二边和第三边，所述第二边和所述第三边沿所述第一方向位于所述第一边的一侧且与所述第一边平行，所述第二边与所述第一边之间的距离大于所述第三边与所述第一边之间的距离，所述金属隔垫块与所述公共电极块的连接过孔在所述衬底基板上的正投影位于所述第一边和所述第二边在所述衬底基板上的正投影之间。
在本公开的一种示例性实施例中，所述金属隔垫块在所述第二方向上的尺寸为16-17μm，所述第一边和所述第二边之间的距离为11.6-12.6μm，所述第一边和所述第三边之间的距离为9.2-10.2μm。
在本公开的一种示例性实施例中，所述触控信号线在所述衬底基板 上的正投影位于所述红色子像素区和所述蓝色子像素区在所述衬底基板上的正投影之间。
在本公开的一种示例性实施例中，所述驱动电路层还包括：
栅极层，设于所述衬底基板的一侧，所述扫描线与所述栅极层同层设置，所述栅极层包括栅极，所述扫描线与所述栅极连接；
栅极绝缘层，设于所述栅极层远离所述衬底基板的一侧，所述栅极绝缘层覆盖所述栅极层的表面；
有源层，设于所述栅极绝缘层远离所述衬底基板的一侧；
源漏极层，包括覆盖所述有源层一端的源极和覆盖所述有源层另一端的漏极，所述数据线与所述源漏极层线同层设置，所述数据线与所述漏极连接。
在本公开的一种示例性实施例中，所述金属块在所述衬底基板上的正投影覆盖所述源极和所述漏极在所述衬底基板上的正投影之间的间隙。
在本公开的一种示例性实施例中，所述阵列基板还包括：
信号引线，设于所述衬底基板的一侧并位于所述外围区，包括数据引线和扫描引线，所述数据引线与所述数据线连接且同层设置，所述扫描引线与所述扫描线同层设置；
触控引线，设于所述衬底基板的一侧并位于所述外围区，所述触控引线与所述触控信号线连接且同层设置；
其中，所述数据引线、所述扫描引线和所述触控引线在所述衬底基板上的正投影至少部分重叠。
在本公开的一种示例性实施例中，所述外围区包括绑定区；所述阵列基板还包括：
焊盘，设于所述衬底基板的一侧并位于所述绑定区，所述焊盘包括第一焊盘、第二焊盘和第三焊盘；
其中，所述第一焊盘与所述数据引线连接，所述第一焊盘包括第一导电层和第二导电层，所述第一导电层与所述数据线同层设置，所述第二导电层与所述像素电极同层设置，所述第二导电层与所述第一导电层通过过孔连接；
所述第二焊盘与所述扫描引线连接，所述第二焊盘包括第三导电层 和第四导电层，所述第三导电层与所述扫描线同层设置，所述第四导电层与所述像素电极同层设置，所述第四导电层与所述第三导电层通过过孔连接；
所述第三焊盘与所述触控引线连接，所述第三焊盘包括第五导电层和第六导电层，所述第五导电层与所述触控信号线同层设置，所述第六导电层与所述像素电极同层设置，所述第六导电层与所述第五导电层通过过孔连接。
根据本公开的第二个方面，提供一种阵列基板的制作方法，包括：
提供衬底基板，所述衬底基板包括显示区和位于所述显示区外围的外围区；
于所述衬底基板的一侧形成驱动电路层，所述驱动电路层位于所述显示区，包括多条数据线和多条扫描线，多条所述数据线沿第一方向延伸，沿第二方向间隔排布，多条所述扫描线沿所述第二方向延伸，沿所述第一方向间隔排布，所述第二方向和所述第一方向交叉，所述数据线和所述扫描线相互交叉界定出多个子像素区；
于所述驱动电路层远离所述衬底基板的一侧形成金属层，所述金属层位于所述显示区，所述金属层包括多个间隔排布的金属块，所述金属块位于所述数据线和所述扫描线的交叉处。
根据本公开的第三个方面，提供一种显示面板，包括：
如第一方面所述的阵列基板；
彩膜基板，设于所述阵列基板的一侧；
多个隔垫物，设于所述阵列基板和所述彩膜基板之间，所述隔垫物与所述金属块一一对应，且所述隔垫物顶端在所述衬底基板上的正投影的至少一半位于所述金属块在所述衬底基板上的正投影之内；
液晶层，设于所述阵列基板和所述彩膜基板之间。
在本公开的一种示例性实施例中，所述子像素区包括红色子像素区、蓝色子像素区和绿色子像素区，所述隔垫物包括主隔垫物，所述主隔垫物在所述衬底基板上的正投影位于所述红色子像素区和所述蓝色子像素区在所述衬底基板上的正投影之间。
在本公开的一种示例性实施例中，所述隔垫物在所述衬底基板上的 正投影与所述源极和所述漏极在所述衬底基板上的正投影之间的间隙部分重叠。
根据本公开的第四个方面，提供一种显示装置，包括如第三方面所述的显示面板。
本公开提供的阵列基板，包括衬底基板、驱动电路层和金属层，其中，金属层包括多个间隔排布的金属块，且金属块位于数据线和扫描线的交叉处。该金属块有助于调整数据线和扫描线交叉位置处的平整度，以使在该金属块位置处形成的其他结构时，维持该结构在高度上的均一性和在分布位置上的稳定性。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中显示面板截面示意图；
图2是本公开另一示例性实施例中显示面板截面示意图；
图3是本公开示例性实施例中衬底基板结构示意图；
图4是本公开示例性实施例中阵列基板平面结构示意图；
图5是本公开示例性实施例中显示面板平面示意图；
图6是本公开示例性实施例中公共电极结构示意图；
图7是本公开示例性实施例中阵列基板的局部平面结构示意图；
图8是图7中A-A方向截面图；
图9是本公开示例性实施例中公共电极块结构示意图；
图10是本公开示例性实施例触控单元中公共电极块的连接结构示意图；
图11是本公开示例性实施例中金属隔垫块结构示意图；
图12是本公开示例性实施例中各引线在外围区结构示意图；
图13是图12中B-B方向截面图；
图14是本公开示例性实施例中焊盘平面结构示意图；
图15是本公开示例性实施例中焊盘截面图；
图16是本公开示例性实施例中隔垫物在阵列基板上的截面图；
图17是本公开示例性实施例中阵列基板制备方法流程示意图。
图中主要元件附图标记说明如下：
1-衬底基板；11-显示区；12-外围区；2-驱动电路层；21-扫描线；22-数据线；23-源漏极层；23S-源极；23D-漏极；24-栅极层；25-栅极绝缘层；26-有源层；27-平坦化层；3-金属层；31-金属块；311-触控连接金属块；3111-第一触控金属块；3112-第二触控金属块；312-金属隔垫块；312a-第一边；312b-第二边；312c-第三边；312d-第四边；312e-第五边；3121-第一垫块；3122-第二垫块；32-触控信号线；4-隔垫物；41-主隔垫物；42-副隔垫物；5-公共电极；51-触控单元；511-公共电极块；511a-主体；511b-第一凸出部；511c-第二凸出部；512-行连接部；513-列连接部；5131-上连接部；5132-下连接部；501-第一钝化层；502-第二钝化层；6-像素电极；7-液晶层；8-彩膜基板；9-子像素区；90-像素单元区；91-红色子像素区；92-绿色子像素区；93-蓝色子像素区；01-数据引线；02-扫描引线；03-触控引线；04-第一焊盘；041-第一导电层；042-第二导电层；05-第二焊盘；051-第三导电层；052-第四导电层；06-第三焊盘；061-第五导电层；062-第六导电层；001-绝缘层；002-绝缘层；003-钝化层；004-钝化层。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
液晶显示面板的阵列基板中通常设置有多种走线，如扫描线和数据线等。相关技术中，为了不影响显示面板的开口率，扫描线和数据线等走线的宽度通常设计的较窄，导致位于其上方的隔垫物高度不一，且稳定性不好，从而对液晶显示面板的盒厚等造成不良影响。
如图1至图4所示，本公开提供一种阵列基板，包括衬底基板1、驱动电路层2和金属层3。其中，衬底基板1包括显示区11和位于显示区11外围的外围区12；驱动电路层2设于衬底基板1的一侧并位于显示区11，包括多条数据线22和多条扫描线21，数据线22和扫描线21相互交叉界定出多个子像素区9；金属层3设于驱动电路层2远离衬底基板1的一侧并位于显示区11，金属层3包括多个间隔排布的金属块31，金属块31位于数据线22和扫描线21的交叉处。
本公开提供的阵列基板，包括衬底基板1、驱动电路层2和金属层3，其中，金属层3包括多个间隔排布的金属块31，且金属块31位于数据线22和扫描线21的交叉处。该金属块31有助于调整数据线22和扫描线21交叉位置处的平整度，以使在该金属块31位置处形成的其他结构时，维持该结构在高度上的均一性和在分布位置上的稳定性。
下面结合附图对本公开实施方式提供的阵列基板的各部件进行详细 说明：
本公开实施例中提供一种阵列基板，该阵列基板可用于形成TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶)显示面板。
如图1至图4、图7所示，衬底基板1包括显示区11和位于显示区11外围的非显示区11。衬底基板1可以为无机材料的衬底基板，也可以为有机材料的衬底基板。举例而言，在本公开的一种实施方式中，衬底基板1的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板1的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。衬底基板1也可以为柔性衬底基板，举例而言，在本公开的一种实施方式中，衬底基板1的材料可以为聚酰亚胺(polyimide，PI)。衬底基板1还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板1可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
驱动电路层2设于衬底基板1的一侧并位于显示区11，驱动电路层2包括多条数据线22和多条扫描线21，数据线22和扫描线21相互交叉以界定出多个子像素区9。数据线22设于扫描线21远离衬底基板1的一侧。数据线22和扫描线21的延伸方向和排布方向可有多种设计。
如图4所示，在一实施例中，多条数据线22沿列方向延伸，沿行方向间隔排布，多条扫描线21沿行方向延伸，沿列方向间隔排布。在此需说明的是，本公开中，行方向和列方向是相对而言的，行方向和列方向的交叉角度可以大于0°，小于等于90°。
如图7所示，在一具体实施例中，多条数据线22沿第一方向X延伸，沿第二方向Y间隔排布，第一方向X和第二方向Y交叉，角度大于0°，小于等于90°。多条扫描线21沿第二方向Y延伸，沿第一方向X 间隔排布。在一具体实施例中，第一方向X与第二方向Y垂直。
扫描线21和数据线22可以为一层导电材料，也可以为多层导电材料的层叠。举例而言，在本公开的一种实施方式中，扫描线21可以包括依次层叠的第一导电材料层、第二导电材料层和第一导电材料层，即呈现三明治结构。其中，第一导电材料层可以选用耐腐蚀的金属或者合金，例如可以选用钼；第二导电材料层可以选用高导电率的金属或者合金，例如可以选用铜、铝、银等。再举例而言，在本公开的另一种实施方式中，扫描线21可以包括一层导电材料，例如扫描线21的材料可以为钼。数据线22可以与扫描线21包含同样的导电材料。
如图1、图2、图7和图8所示，在一些实施例中，驱动电路层2还包括栅极层24，设于衬底基板1的一侧，扫描线21与栅极层24同层设置。栅极层包括栅极，扫描线21与栅极连接，用于提供扫描信号。栅极层24可以包括金属材料或者合金材料，以保证其良好的导电性能。当然，该栅极层24也可以采用透明导电材料，如ITO(氧化铟锡)、IZO(氧化铟锌)等。
栅极层24和扫描线21可通过光刻工艺形成，且扫描线21和栅极层24可通过同一道光刻工艺形成。举例而言，可以先在衬底基板1的一侧沉积形成导电材料层，然后对该导电材料层进行图案化，进而获得所需的扫描线21和栅极层24。
驱动电路层2还包括栅极绝缘层25，设于栅极层24远离衬底基板1的一侧，栅极绝缘层25覆盖栅极层24的表面。栅极绝缘层25可采用氮化硅、氧化硅、氧化铝等单膜层或由其组合形成的多膜层。栅极绝缘层25可以通过沉积的方法形成，例如可以通过气相化学沉积的方法形成一层氧化硅层作为栅极绝缘材料层，栅极绝缘材料层图案化之后可以形成栅极绝缘层25。
驱动电路层2还包括有源层26，设于栅极绝缘层25远离衬底基板1的一侧。有源层26的材料可以为多晶硅或IGZO(铟镓锌氧化物)，其可以通过掺杂等工艺改变不同位置处的导电性能。
驱动电路层2还包括源漏极层23，包括覆盖有源层26一端的源极23S和覆盖有源层26另一端的漏极23D，数据线22与源漏极层23同层 设置。数据线22与漏极23D连接。
栅极层24、栅极绝缘层25、有源层26和源漏极层23可用于形成薄膜晶体管。薄膜晶体管位于子像素区9，作为像素驱动电路的组成结构，以驱动液晶像素区。
在一实施例中，驱动电路/2还包括平坦化层27，设于源漏极层23背离衬底基板1的一侧，平坦化层27覆盖源漏极层23的表面。
如图1、图2、图4和图7所示，金属层3设于驱动电路层2远离衬底基板1的一侧并位于显示区11，金属层3包括多个间隔排布的金属块31，金属块31位于数据线22和扫描线21的交叉处。多个金属块31可呈矩阵阵列排布，数据线22和扫描线21的每个交叉点处均设置金属块31。
如图7和图8所示，在一些实施例中，金属块31在衬底基板1上的正投影覆盖源极23S和漏极23D在衬底基板1上的正投影之间的间隙。也即，源极23S和漏极23D在衬底基板1上的正投影之间具有间隙，金属块31在衬底基板1上的正投影部分位于该间隙内且将该间隙予以覆盖。
如图7所示，在本公开一些实施例中，金属层3还包括多条触控信号线32，触控信号线32在衬底基板1上的正投影位于子像素区9在衬底基板1上的正投影之外，且触控信号线32在衬底基板1上的正投影与数据线22在衬底基板1上的正投影至少部分重叠，以减少触控信号线32对像素开口率的影响。金属块31包括触控连接金属块311和金属隔垫块312，触控连接金属块311与触控信号线32连接，金属隔垫块312与触控信号线32之间有间距。具体在一实施例中，触控连接金属块311与触控信号线32直接接触连接。
在第二方向Y上，部分数据线22在衬底基板1上的正投影位于触控信号线32在衬底基板1上的正投影之内。也即，在第二方向Y上，触控信号线32的宽度大于数据线22的宽度，以降低公共电极电压扰动(vcom ripple)。在一具体实施例中，在第二方向Y上，触控信号线32的宽度为5.2-6.2μm，数据线22的宽度为2.5-3.5μm。
在该实施例中，触控连接金属块311、金属隔垫块312和触控信号线32可采用相同的材料和同一道光刻工艺形成。可以在驱动电路层2 远离衬底基板1的一侧沉积形成金属材料层，然后对该金属材料层进行图案化，进而获得所需的触控连接金属块311、金属隔垫块312和触控信号线32。
如图1、图2、图6至图8所示，在本公开一些实施例中，阵列基板还包括公共电极5和多个像素电极6。公共电极5设于驱动电路层2远离衬底基板1的一侧，多个像素电极6设于公共电极5远离衬底基板1的一侧。在一实施例中，公共电极5和像素电极6之间还形成有第一钝化层501或/和第二钝化层502，像素电极6通过过孔与源漏极层23中的源极连接。
如图6至图8所示，公共电极5包括多个间隔分布的触控单元51，触控单元51包括多个相互连接的公共电极块511。多个像素电极6设于公共电极5远离衬底基板1的一侧。一个像素电极6对应于一个子像素区9。
在该实施例中，公共电极5复用为触控电极。在相关技术中，该原理可用于制作形成触控与显示驱动器集成(Touch and Display Driver Integration，TDDI)触摸屏，将触控传感器集成到显示器中，并把触控芯片与显示芯片整合进单一芯片中，使屏幕更薄，满足了显示产品薄型化的设计需求。
如图6所示，在该实施例中，阵列基板设置有多个同层的且相互绝缘的触控单元51(自电容电极)。当人体未触碰屏幕时，各触控单元51的电容为一固定值，当人体触摸屏幕时，对应的触控单元51的电容为固定值叠加人体电容后的值。触控侦测芯片在触控时间段通过检测各触控单元51的电容值变化来判断触控位置。
如图1和图2所示，金属层3设于驱动电路层2背离衬底基板1的一侧。在一实施例中，金属层3设于公共电极5背离衬底基板1的一侧(图1)，在另一实施例中，金属层3可设于公共电极5靠近衬底基板1的一侧(图2)。
如图7所示，金属块31包括触控连接金属块311和金属隔垫块312。其中，触控连接金属块311包括第一触控金属块3111和第二触控金属块3112，触控信号线32通过第一触控金属块3111与触控单元51中的一个 公共电极块511连接，以使触控单元51的电容值可通过触控信号线32传递给触控侦测芯片，使得触控侦测芯片准确判断出所触控的电容电极，并作出相应的反应。第二触控金属块3112与公共电极块511不连接。金属隔垫块312与触控信号线32之间有间距，也即金属隔垫块312与触控信号线3未直接连接。金属隔垫块312与其对应位置处的公共电极块511连接，以使金属隔垫块312的电压与公共电极块511的电压相等，避免金属隔垫块312由于悬空(floating)对电场造成不利影响。
当金属层3设于公共电极5靠近衬底基板1的一侧，也即驱动电路层2和公共电极5之间时，可先在驱动电路层2远离衬底基板1的一侧形成金属层3，随后在金属层3背离衬底基板1的一侧形成钝化层，在形成的钝化层的特定位置处刻蚀形成过孔，以暴露该特定位置处的金属层3，之后在钝化层远离衬底基板1的一侧形成公共电极5，此时形成的公共电极5中的某些公共电极块511可通过过孔与金属层3中的某些金属块31连接。过孔的面积可设置为9-25μm2，过孔在衬底基板1上的正投影的形状大致可以为圆形、椭圆形、不规则多边形或正多边形等，具体本公开不做限定。
当金属层3设于公共电极5背离衬底基板1的一侧时，如公共电极5和像素电极6(图8)之间时，可先在驱动电路层2远离衬底基板1的一侧形成公共电极5，随后在公共电极5背离衬底基板1的一侧形成钝化层501，之后在形成的钝化层501的特定位置处刻蚀形成过孔，以暴露该特定位置处的公共电极5。之后在钝化层501远离衬底基板1的一侧形成金属层3，此时形成的金属层3中的某些金属块31可通过过孔与公共电极5中的某些公共电极块511连接。过孔的面积可设置为9-25μm2，过孔在衬底基板1上的正投影的形状大致可以为圆形、椭圆形、不规则多边形或正多边形等，具体本公开不做限定。
如图7和图11所示，在本公开一些实施例中，金属隔垫块312包括依次连接的第一边312a、第二边312b和第三边312c，第二边312b和第三边312c沿第一方向X位于第一边312a的一侧且与第一边312a大致平行，第二边312b与第一边312a之间的距离大于第三边312c与第一边312a之间的距离，金属隔垫块312与公共电极块511的连接过孔在衬底 基板1上的正投影位于第一边312a和第二边312b在衬底基板1上的正投影之间。在一具体实施例中，第一边312a、第二边312b和第三边312c大致与第二方向Y平行，且第二边312b和第三边312c的长度均小于第一边312a的长度。进一步地，金属隔垫块312还包括位于第一边312a在第二方向Y上的两端的第四边312d和第五边312e，第四边312d和第五边312e与第一边312a大致垂直。第一边312a、第四边312d、第二边312b、第三边312c和第五边312e依次连接形成一封闭图形。
如图7和图11所示，在该实施例中，通过增大第二边312b与第一边312a之间的距离，进而使得金属隔垫块312包含第二边312b的区域与其上方的公共电极块511具有层叠区域，从而便于金属隔垫块312与公共电极块511实现连接。
同理，该金属隔垫块312的形状设计也适用于第一触控金属块3111。如图7所示，当第一触控金属块3111与公共电极块511连接时，其形状可与金属隔垫块312相同。而第二触控金属块3112不需要与公共电极块连接时，其形状即可根据实际需求进行设定。举例而言，第二触控金属块3112为规则的多边形，其在衬底基板1上的正投影为呈轴对称的规则多边形，如左右对称的规则六边形或八边形等。进一步地，第二触控金属块3112在衬底基板1上的正投影也可以为呈中心对称的规则多边形。如图7所示，在一具体实施例中，第二触控金属块为左右对称的规则八边形，且第二触控金属块3112在第二方向Y上的尺寸为16-17μm，在第一方向X上的尺寸为9.2-10.2μm。
在具体一实施例中，金属隔垫块312在第二方向Y上的尺寸为16-17μm，第二边312b和第一边312a之间的距离为11.6-12.6μm，第三边312c与第一边312a之间的距离为9.2-10.2μm。
如图6、图7、图9和图10所示，在本公开一些实施例中，触控单元51包括阵列排布的多个公共电极块511，至少两个公共电极块511沿第一方向X排布形成列，至少两个公共电极块沿第二方向Y排布形成行。触控单元51中相邻两行公共电极块511之间通过行连接部512连接，相邻两列公共电极块511之间通过列连接部513连接。其中，列连接部513包括连接于公共电极块511上部区域的上连接部5111和连接于公共电极 块下部区域的下连接部5112,。也即相邻两块公共电极块511之间的列连接部513包括上连接部5131和下连接部5132，以保证公共电极块511连接时的稳定性和牢固性。行连接部512、列连接部513与公共电极块511同层设置。
公共电极块511的大小可根据实际情况进行设定。如，根据其所需对应的子像素区9或像素电极6的数量进行设定。
如图6和图7所示，在本公开一些实施例中，子像素区9包括红色子像素区91、绿色子像素区92和蓝色子像素区93，至少一个红色子像素区91、至少一个绿色子像素区92和至少一个蓝色子像素区93排布组合形成一个像素单元区90，一个像素单元区90对应于一块公共电极块511。行连接部512在衬底基板1上的正投影位于公共电极块511对应的相邻两个子像素区在衬底基板1上的正投影之间。
在一具体实施例中，一个红色子像素区91、一个绿色子像素区92和一个蓝色子像素区93沿第二方向Y依次排列形成一个像素单元区90，一个公共电极块511对应于一个像素单元区90。行连接部512在衬底基板1上的正投影位于公共电极块511对应的绿色子像素区92和蓝色子像素区93在衬底基板1上的正投影之间。
在本公开一些实施例中，第一触控金属块3111和金属隔垫块312可分别通过不同的连接位置与公共电极块511连接。
如图9和图10所示，在该实施例中，公共电极块511包括主体511a和连接于主体511a一侧的第一凸出部511b和第二凸出部511c，第一凸出部511b连接于主体511a一侧的中部，且第一凸出部511b在衬底基板1上的正投影位于公共电极块511对应的的相邻两个子像素区9在衬底基板1上的正投影之间，第二凸出部511c连接于主体511a的转角处。
其中，第一凸出部511b的数量可根据公共电极块511对应的子像素区9的数量进行设定，举例而言，当公共电极块511对应于三个子像素区9时，第一凸出部511b的数量可以为两个，分别对应位于相邻的两个子像素区9之间。
如图7、图9和图10所示，金属隔垫块312包括第一垫块3121，第一垫块3121在衬底基板1上的正投影与第一凸出部511b至少部分重叠， 且第一垫块3121通过过孔与第一凸出部511b连接。在一具体实施例中，第一凸出部511b的数量为多个，不同第一凸出部511b的形状尺寸可相同或不同。当相邻两行公共电极块511连接时，部分第一凸出部511b复用为行连接部512。举例而言，对应位于绿色子像素区92和蓝色子像素区93之间的第一凸出部511b复用为行连接部512。此时，该第一凸出部511b的尺寸可根据相邻两行公共电极块511之间的距离进行设定。
在一些实施例中，第二凸出部511b的数量为多个，其中部分第二凸出部511b对应位置处设置有触控连接金属块311，部分第二凸出部511c的对应位置处设置有金属隔垫块312。
当公共电极块511的周围设置有触控信号线32时，连接触控信号线32的触控连接金属块311可设置于该公共电极块511的第二凸出部511c对应位置处。其中，当触控信号线32需通过第一触控金属块3111与公共电极块511连接时，第一触控金属块3111在衬底基板1上的正投影与触控单元51中一个公共电极块511的第二凸出部511c在衬底基板1上的正投影至少部分重叠，且第一触控金属块3111通过过孔与第二凸出部511c连接。当公共电极块511周围不设置有触控信号线32时，该公共电极块511的第二凸出部511c的对应位置处可设置金属隔垫块312，金属隔垫块312还包括第二垫块3122，第二垫块3122在衬底基板1上的正投影与第二凸出部511c至少部分重叠，且第二垫块3122通过过孔与第二凸出部511c连接。
如图3、图12和图13所示，在本公开一些实施例中，阵列基板还包括位于外围区12的信号引线和触控引线03。信号引线设于衬底基板1的一侧并位于外围区12，包括数据引线01和扫描引线02，数据引线01与数据线22连接且同层设置，扫描引线02与扫描线21同层设置；触控引线03设于衬底基板1的一侧并位于外围区12，触控引线03与触控信号线32连接且同层设置。其中，数据引线01、扫描引线02和触控引线03在衬底基板1上的正投影至少部分重叠。
在一些实施例中，数据引线01、扫描引线02和触控引线03的各膜层之间还设置有绝缘层001。在该实施例中，数据引线01、扫描引线02和触控引线03三层重叠，有利于减小扇形区的宽度，实现阵列基板在该 区域的窄边框设计。同时，三层引线层叠设置，彼此间通过绝缘层001保持绝缘，可有效降低引线相互间的短路风险。数据引线01、扫描引线02和触控引线03的线宽可根据实际情况设定。在一具体实施例中，数据引线01、扫描引线02和触控引线03的线宽可以为2.7μm，当三层同层时，线间距可以为2.3μm。
如图14和图15所示，在本公开一些实施例中，外围区12还包括绑定区。在该区域将外围引线与芯片连接，实现触控和显示信号的传输。各引线可通过转接孔实现与芯片的连接。
阵列基板还包括焊盘，焊盘设于衬底基板1的一侧并位于绑定区，焊盘包括第一焊盘04、第二焊盘05和第三焊盘06；第一焊盘04与数据引线01连接，第一焊盘04包括第一导电层041和第二导电层042，第一导电层041与数据线22同层设置，第二导电层042与像素电极6同层设置，第二导电层042与第一导电层041通过过孔连接。
第二焊盘05与扫描引线02连接，第二焊盘05包括第三导电层051和第四导电层052，第三导电层051与扫描线21同层设置，第四导电层052与像素电极6同层设置，第四导电层052与第三导电层051通过过孔连接。
第三焊盘06与触控引线03连接，第三焊盘06包括第五导电层061和第六导电层062，第五导电层061与触控信号线32同层设置，第六导电层062与像素电极6同层设置，第六导电层062与第五导电层061通过过孔连接。
具体在一实施例中，第三导电层051和第一导电层041之间还设置有绝缘层002，第三导电层051和第五导电层061之间还设置有钝化层003。第五导电层061远离第三导电层051的一侧设置有钝化层004，第二导电层042、第四导电层052和第六导电层062设置于钝化层004远离第五导电层061远离第三导电层051的一侧，并通过过孔分别与第一导电层041、第三导电层051和第五导电层061连接。第二导电层042、第四导电层052和第六导电层062可连接于芯片，从而实现各引线与芯片的连接，以完成各信号的传输。
如图1、图2和图5所示，本公开还提供一种显示面板，包括上述 任一实施例中的阵列基板，还包括彩膜基板8、多个隔垫物4和液晶层7。彩膜基板8设于阵列基板的一侧。多个隔垫物4设于阵列基板和彩膜基板8之间，隔垫物4与金属块31一一对应，且隔垫物4的顶端(靠近阵列基板一端)在衬底基板1上的正投影的至少一半位于金属块31在衬底基板1上的正投影之内。也即，金属块31可很好的支撑隔垫物4，避免隔垫物4由于支撑不稳而发生偏移。像素电极6和公共电极5之间产生多维电场，用于驱动液晶层7中的液晶偏转，进而控制液晶显示面板在该像素区域的出光。
本公开提供的显示面板，包括金属层3和隔垫物4，其中，金属层3包括多个间隔排布的金属块31，隔垫物4设置于金属层3远离衬底基板1的一侧，且隔垫物4在衬底基板1上的正投影位于金属块31在衬底基板1上的正投影之内，从而使金属块31能够稳定支撑隔垫物4，并使隔垫物4保持高度上的一致性。
如图16所示，在一些实施例中，隔垫物4在衬底基板1上的正投影与源极23S和漏极23D在衬底基板1上的正投影之间的间隙部分重叠。也即，源极23S和漏极23D在衬底基板1上的正投影之间具有间隙，隔垫物4在衬底基板1上的正投影与该间隙有部分区域重叠。
隔垫物4包括主隔垫物41和副隔垫物42，主隔垫物41起到控制盒厚的作用，副隔垫物42起辅助支撑和调节作用。主隔垫物41和副隔垫物42可按一定的规律进行排列。
如图5和图7所示，在本公开一些实施例中，主隔垫物41在衬底基板1上的正投影位于红色子像素区91和蓝色子像素区93在衬底基板1上的正投影之间。在实际应用中，当阵列基板等受到挤压时，主隔垫物41在外力作用下可能会发生偏移，从而对相邻区域的子像素显示造成影响。通常情况下，红色子像素和蓝色子像素的透过率相比绿色子像素的较低，因此，本公开将主隔垫物41设置在红色子像素区91和蓝色子像素区93之间，以减少主隔垫物41偏移后对显示效果的影响。副隔垫物42的设置位置可根据实际设计需求进行设定，其可位于任意两个子像素区9之间。
相应地，触控信号线32在衬底基板1上的正投影位于红色子像素区 91和蓝色子像素区93在衬底基板1上的正投影之间。也即，触控信号线32也设置于红色子像素区91和蓝色子像素区93之间。
如图1至图4和图17所示，本公开还提供一种阵列基板的制作方法，包括：
步骤S100，提供衬底基板1，衬底基板1包括显示区11和位于显示区11外围的外围区12；
步骤S200，于衬底基板1的一侧形成驱动电路层2，驱动电路层2位于显示区11，包括多条数据线22和多条扫描线21，多条数据线22沿第一方向X延伸，沿第二方向Y间隔排布，多条扫描线21沿第二方向Y延伸，沿第一方向X间隔排布，第二方向Y和第一方向X交叉，数据线22和扫描线21相互交叉界定出多个子像素区9；
步骤S300，于驱动电路层2远离衬底基板1的一侧形成金属层3，金属层3位于显示区11，金属层3包括多个间隔排布的金属块31，金属块31位于数据线22和扫描线21的交叉处。
如图8所示，在本公开一些实施例中，于衬底基板1的一侧形成驱动电路层2包括：
于衬底基板1的一侧形成栅极层24和扫描线21，扫描线21与栅极层24同层设置，栅极层24包括栅极，扫描线21与栅极连接；
于栅极层24远离衬底基板1的一侧形成栅极绝缘层25，栅极绝缘层25覆盖栅极层24的表面；
于栅极绝缘层2远离衬底基板1的一侧形成有源层26；
于有源层26远离衬底基板1的一侧形成源漏极层23，源漏极层23覆盖有源层26的两端，数据线22与源漏极层23线同层设置，源漏极层23包括源/漏极，数据线22与源/漏极连接。
本公开实施方式还提供一种显示装置，包括显示面板，该显示面板可为上述任意实施方式的显示面板，其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是手机、平板电脑、电视等电子设备，在此不再一一列举。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步 骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板，包括显示区和位于显示区外围的外围区；
    驱动电路层，设于所述衬底基板的一侧并位于所述显示区，包括多条数据线和多条扫描线，多条所述数据线沿第一方向延伸，沿第二方向间隔排布，多条所述扫描线沿所述第二方向延伸，沿所述第一方向间隔排布，所述第二方向和所述第一方向交叉，所述数据线和所述扫描线相互交叉界定出多个子像素区；
    金属层，设于所述驱动电路层远离所述衬底基板的一侧并位于所述显示区，所述金属层包括多个间隔排布的金属块，所述金属块位于所述数据线和所述扫描线的交叉处。
  2. 根据权利要求1所述的阵列基板，其中，所述金属层还包括多条触控信号线，所述触控信号线在所述衬底基板上的正投影位于所述子像素区在所述衬底基板上的正投影之外，且所述触控信号线在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影至少部分重叠；
    其中，所述金属块包括触控连接金属块和金属隔垫块，所述触控连接金属块与所述触控信号线连接，所述金属隔垫块与所述触控信号线之间有间距。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    公共电极，设于所述驱动电路层远离所述衬底基板的一侧，所述公共电极包括多个间隔分布的触控单元，所述触控单元包括多个相互连接的公共电极块；
    多个像素电极，设于所述公共电极远离所述衬底基板的一侧；
    其中，所述金属层设于所述驱动电路层和所述公共电极之间，或所述公共电极背离所述衬底基板的一侧；
    所述触控连接金属块包括第一触控金属块和第二触控金属块，所述触控信号线通过所述第一触控金属块与所述触控单元中的一个所述公共电极块连接，所述第二触控金属块与所述公共电极块不连接；所述金属隔垫块与所述公共电极块通过过孔连接。
  4. 根据权利要求3所述的阵列基板，其中，所述触控单元包括阵列 排布的多个公共电极块，其中，至少两个所述公共电极块沿所述第一方向排布形成列，至少两个所述公共电极块沿所述第二方向排布形成行；
    所述触控单元中相邻两行所述公共电极块之间通过行连接部连接，相邻两列所述公共电极块之间通过列连接部连接；
    其中，所述列连接部包括连接于所述公共电极块上部区域的上连接部和连接于所述公共电极块下部区域的下连接部。
  5. 根据权利要求4所述的阵列基板，其中，所述子像素区包括红色子像素区、绿色子像素区和蓝色子像素区，至少一个所述红色子像素区、至少一个绿色子像素区和至少一个蓝色子像素区沿所述第二方向排布组合形成一个像素单元区，一个所述像素单元区对应于一块所述公共电极块；
    所述行连接部在所述衬底基板上的正投影位于所述公共电极块对应的相邻两个子像素区在所述衬底基板上的正投影之间。
  6. 根据权利要求5所述的阵列基板，其中，所述公共电极块包括主体和连接于所述主体一侧的第一凸出部和第二凸出部，所述第一凸出部连接于所述主体一侧的中部，且所述第一凸出部在所述衬底基板上的正投影位于所述公共电极块对应的相邻两个子像素区在所述衬底基板上的正投影之间，所述第二凸出部连接于所述主体的转角处；
    所述金属隔垫块包括第一垫块，所述第一垫块在所述衬底基板上的正投影与所述第一凸出部至少部分重叠，且所述第一垫块通过过孔与所述第一凸出部连接；
    所述第一凸出部的数量为多个，当相邻两行所述公共电极块连接时，部分所述第一凸出部复用为所述行连接部；
    所述第一触控金属块在所述衬底基板上的正投影与所述触控单元中一个所述公共电极块的所述第二凸出部在所述衬底基板上的正投影至少部分重叠，且所述第一触控金属块通过过孔与所述第二凸出部连接。
  7. 根据权利要求2所述的阵列基板，其中，在所述第二方向上，部分所述数据线在所述衬底基板上的正投影位于所述触控信号线在所述衬底基板上的正投影之内。
  8. 根据权利要求7所述的阵列基板，其中，在所述第二方向上，所 述触控信号线的宽度为5.2-6.2μm，所述数据线的宽度为2.5-3.5μm。
  9. 根据权利要求3所述的阵列基板，其中，所述金属隔垫块包括依次连接的第一边、第二边和第三边，所述第二边和所述第三边沿所述第一方向位于所述第一边的一侧且与所述第一边平行，所述第二边与所述第一边之间的距离大于所述第三边与所述第一边之间的距离，所述金属隔垫块与所述公共电极块的连接过孔在所述衬底基板上的正投影位于所述第一边和所述第二边在所述衬底基板上的正投影之间。
  10. 根据权利要求9所述的阵列基板，其中，所述金属隔垫块在所述第二方向上的尺寸为16-17μm，所述第一边和所述第二边之间的距离为11.6-12.6μm，所述第一边和所述第三边之间的距离为9.2-10.2μm。
  11. 根据权利要求5所述的阵列基板，其中，所述触控信号线在所述衬底基板上的正投影位于所述红色子像素区和所述蓝色子像素区在所述衬底基板上的正投影之间。
  12. 根据权利要求1所述的阵列基板，其中，所述驱动电路层还包括：
    栅极层，设于所述衬底基板的一侧，所述扫描线与所述栅极层同层设置，所述栅极层包括栅极，所述扫描线与所述栅极连接；
    栅极绝缘层，设于所述栅极层远离所述衬底基板的一侧，所述栅极绝缘层覆盖所述栅极层的表面；
    有源层，设于所述栅极绝缘层远离所述衬底基板的一侧；
    源漏极层，包括覆盖所述有源层一端的源极和覆盖所述有源层另一端的漏极，所述数据线与所述源漏极层线同层设置，所述数据线与所述漏极连接。
  13. 根据权利要求12所述的阵列基板，其中，所述金属块在所述衬底基板上的正投影覆盖所述源极和所述漏极在所述衬底基板上的正投影之间的间隙。
  14. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    信号引线，设于所述衬底基板的一侧并位于所述外围区，包括数据引线和扫描引线，所述数据引线与所述数据线连接且同层设置，所述扫描引线与所述扫描线同层设置；
    触控引线，设于所述衬底基板的一侧并位于所述外围区，所述触控引线与所述触控信号线连接且同层设置；
    其中，所述数据引线、所述扫描引线和所述触控引线在所述衬底基板上的正投影至少部分重叠。
  15. 根据权利要求14所述的阵列基板，其中，所述外围区包括绑定区；所述阵列基板还包括：
    焊盘，设于所述衬底基板的一侧并位于所述绑定区，所述焊盘包括第一焊盘、第二焊盘和第三焊盘；
    其中，所述第一焊盘与所述数据引线连接，所述第一焊盘包括第一导电层和第二导电层，所述第一导电层与所述数据线同层设置，所述第二导电层与所述像素电极同层设置，所述第二导电层与所述第一导电层通过过孔连接；
    所述第二焊盘与所述扫描引线连接，所述第二焊盘包括第三导电层和第四导电层，所述第三导电层与所述扫描线同层设置，所述第四导电层与所述像素电极同层设置，所述第四导电层与所述第三导电层通过过孔连接；
    所述第三焊盘与所述触控引线连接，所述第三焊盘包括第五导电层和第六导电层，所述第五导电层与所述触控信号线同层设置，所述第六导电层与所述像素电极同层设置，所述第六导电层与所述第五导电层通过过孔连接。
  16. 一种阵列基板的制作方法，包括：
    提供衬底基板，所述衬底基板包括显示区和位于所述显示区外围的外围区；
    于所述衬底基板的一侧形成驱动电路层，所述驱动电路层位于所述显示区，包括多条数据线和多条扫描线，多条所述数据线沿第一方向延伸，沿第二方向间隔排布，多条所述扫描线沿所述第二方向延伸，沿所述第一方向间隔排布，所述第二方向和所述第一方向交叉，所述数据线和所述扫描线相互交叉界定出多个子像素区；
    于所述驱动电路层远离所述衬底基板的一侧形成金属层，所述金属层位于所述显示区，所述金属层包括多个间隔排布的金属块，所述金属 块位于所述数据线和所述扫描线的交叉处。
  17. 一种显示面板，包括：
    如权利要求1-15任一项所述的阵列基板；
    彩膜基板，设于所述阵列基板的一侧；
    多个隔垫物，设于所述阵列基板和所述彩膜基板之间，所述隔垫物与所述金属块一一对应，且所述隔垫物顶端在所述衬底基板上的正投影的至少一半位于所述金属块在所述衬底基板上的正投影之内；
    液晶层，设于所述阵列基板和所述彩膜基板之间。
  18. 根据权利要求17所述的显示面板，其中，所述子像素区包括红色子像素区、蓝色子像素区和绿色子像素区，所述隔垫物包括主隔垫物，所述主隔垫物在所述衬底基板上的正投影位于所述红色子像素区和所述蓝色子像素区在所述衬底基板上的正投影之间。
  19. 一种显示面板，包括：
    如权利要求12或13所述的阵列基板；
    彩膜基板，设于所述阵列基板的一侧；
    多个隔垫物，设于所述阵列基板和所述彩膜基板之间，所述隔垫物与所述金属块一一对应，且所述隔垫物顶端在所述衬底基板上的正投影的至少一半位于所述金属块在所述衬底基板上的正投影之内；
    液晶层，设于所述阵列基板和所述彩膜基板之间；
    其中，所述隔垫物在所述衬底基板上的正投影与所述源极和所述漏极在所述衬底基板上的正投影之间的间隙部分重叠。
  20. 一种显示装置，包括如权利要求17-19任一项所述的显示面板。
PCT/CN2021/124215 2021-10-15 2021-10-15 阵列基板及制作方法、显示面板、显示装置 WO2023060595A1 (zh)

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