WO2023051496A1 - 半导体工艺设备和晶圆的加工方法 - Google Patents
半导体工艺设备和晶圆的加工方法 Download PDFInfo
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- WO2023051496A1 WO2023051496A1 PCT/CN2022/121573 CN2022121573W WO2023051496A1 WO 2023051496 A1 WO2023051496 A1 WO 2023051496A1 CN 2022121573 W CN2022121573 W CN 2022121573W WO 2023051496 A1 WO2023051496 A1 WO 2023051496A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
Definitions
- the application belongs to the technical field of semiconductor processing, and in particular relates to a semiconductor processing equipment and a wafer processing method.
- magnetron sputtering is a common thin film preparation process. By bombarding the target, the particles in the target are sputtered and deposited on the surface of the substrate to form a thin film.
- copper is currently mostly used as a material for forming interconnection lines.
- the current heating device for realizing copper reflow has a complex structure and low processing efficiency.
- the present application discloses a semiconductor process equipment and a wafer processing method to at least solve one of the above technical problems.
- An embodiment of the present application provides a semiconductor process equipment, including a process chamber, and a heating chamber communicated with the process chamber, the process chamber is provided with a susceptor for carrying a wafer, and the heating A carrier for carrying wafers is provided in the chamber, and a sheet transfer member is also provided in the process chamber, and the sheet transfer member is used for transferring the wafer between the base and the carrier, so A heating element is also arranged in the heating chamber, and the heating element is used for heating the wafer carried on the carrier.
- the embodiment of the present application discloses a wafer processing method, which is applied to the above-mentioned semiconductor process equipment, and the processing method includes:
- the transfer member is controlled to transport the first wafer to the heating chamber, so as to process the first wafer A wafer undergoes a heating process
- a heating chamber communicated with the process chamber is provided, and a heating element is installed in the heating chamber.
- the process chamber and the heating chamber can respectively provide a first process space and a In the second process space, the base set in the process chamber can carry wafers, the carrier set in the heating chamber can also carry wafers, and the heating element can heat the wafers carried on the carrier.
- the process chamber There is also a chip transfer part, which can transfer the wafer between the base and the carrier, so as to be able to switch between different processes.
- FIG. 1 is a schematic structural diagram of semiconductor process equipment disclosed in an embodiment of the present application.
- FIG. 2 is a schematic diagram of a part of the semiconductor process equipment disclosed in the embodiment of the present application.
- FIG. 3 is an electron micrograph of a semiconductor processed by the semiconductor process equipment disclosed in the embodiment of the present application at different temperatures;
- FIG. 4 is a flowchart of a wafer processing method disclosed in an embodiment of the present application.
- the embodiment of the present application discloses a semiconductor process equipment, which includes a process chamber 110 , and the semiconductor process equipment further includes a heating chamber 120 , and the heating chamber 120 communicates with the process chamber 110 .
- the semiconductor process equipment also includes structures such as the chip transfer member 200, the carrier, the heating element 400, the top cover 140, and the base 150.
- the semiconductor process equipment can also include magnetic
- the magnetron sputtering assembly 160 is provided with a target 170 between the magnetron sputtering assembly 160 and the base 150 .
- the process chamber 110 is a structure for accommodating the wafer 700 and other devices in the semiconductor process equipment.
- the process chamber 110 has an inner cavity, and the wafer 700 and the above-mentioned base 150 and other components can be accommodated in the inner cavity.
- the base 150 is used for carrying the wafer 700 .
- a heating chamber 120 communicating with the process chamber 110 is provided.
- the process chamber 110 is used to provide the first process space 101 for the wafer 700
- the heating chamber 120 is used to provide a second process space 102 for the wafer 700. Both of the aforementioned two process spaces can provide accommodation space for the process of the wafer 700.
- the size of the first process space 101 and the second process space 102 that is, the process
- the dimensions of the chamber 110 and the heating chamber 120 can be determined according to actual needs, and are not limited here.
- the first process space 101 and the second process space 102 communicate with each other, in this case, the wafer 700 can be switched between the first process space 101 and the second process space 102, which makes the wafer 700 in the first process After the corresponding process is completed in one of the space 101 and the second process space 102 , it can be moved to the other of the first process space 101 and the second process space 102 to continue another process. During this process, the overall process environment of the semiconductor process equipment will not be damaged, and the processing efficiency can be improved. In addition, during the working process of the above-mentioned semiconductor process equipment, the first process space 101 and the second process space 102 can respectively carry out corresponding processes, so that the processes in the first process space 101 and the second process space 102 do not interfere with each other. The processing efficiency of the wafer 700 can be further improved.
- the carrier is disposed in the heating chamber 120 , and the carrier can carry the wafer 700 , so as to provide a supporting function for the wafer 700 when performing a corresponding process in the second process space 102 .
- the carrier may be a bracket, or the carrier may further include a plurality of thimbles, which can ensure that the carrier has the ability to carry the wafer 700 .
- the carrier can be fixedly mounted on the bottom or side of the heating chamber 120 , or the carrier can also be capable of moving relative to the process chamber 110 , so that the carrier can move the wafer 700 carried on the carrier.
- the wafer transfer member 200 is installed in the process chamber 110, and the wafer transfer member 200 can move the wafer 700 for transferring the wafer 700 between the base 150 and the carrier, so that the wafer 700 can be placed in the process chamber respectively.
- the chamber 110 and the heating chamber 120 perform corresponding processes.
- the chip transfer member 200 may be a robot arm, and the position of the wafer 700 can be changed by using the chip transfer member 200 . More specifically, the wafer 700 can be switched between the first process space 101 and the second process space 102 by using the wafer transfer member 200 .
- the chip transfer member 200 can be installed on the bottom or side of the process chamber 110, and the chip transfer member 200 can specifically fix the wafer 700 by grasping or supporting, and change the wafer 700 by rotating or moving. Location.
- the heating chamber 120 is also provided with a heating element 400.
- the heating element 400 can specifically be a device with heating capability such as a resistance wire.
- the heating element 400 can be fixed on the top, side, or bottom of the heating chamber 120 for carrying The wafer 700 on the carrier provides heating to increase the temperature of the wafer 700 .
- a heating chamber 120 communicating with the process chamber 110 is provided, and a heating element 400 is installed in the heating chamber.
- the process chamber 110 and the heating chamber 120 can be wafers 700 A first process space 101 and a second process space 102 are provided, the base 150 disposed in the process chamber 110 can carry the wafer 700, the carrier disposed in the heating chamber 120 can also carry the wafer 700, and the heating element 400
- the wafer 700 carried on the carrier can be heated, and the process chamber 110 is also provided with a transfer member 200, which can transfer the wafer 700 between the base 150 and the carrier, so that it can be processed in different processes. switch between.
- corresponding processes can be performed in both the first process space 101 and the second process space 102, which can improve the processing efficiency of the semiconductor process equipment.
- the wafer 700 is processed by using the above-mentioned semiconductor process equipment, and after the barrier layer and copper layer are formed on the wafer 700 in the first process space 101, the aforementioned process will be completed under the action of the chip transfer member 200
- the wafer 700 is moved to the carrier of the second process space 102, under the heating of the heating element 400, the copper reflow process is performed, so that the copper material on the upper surface of the wafer 700 flows to the upper surface of the wafer 700 under high temperature conditions. bottoms of the grooves and through holes, thereby preventing voids and improving the yield rate of the wafer 700.
- the deposition process can be performed in the first process space 101 first, and then the wafer 700 in the first process space 101 can be moved by using the transfer member 200 to the carrier in the second process space 102, after that, the next wafer 700 can continue to be introduced into the first process space 101, and at the same time, the heating element 400 in the second process space 102 works to make the wafer 700 Carrying out the copper reflow process, obviously, the processes between the first process space 101 and the second process space 102 do not interfere with each other, which can improve the processing efficiency of semiconductor process equipment; after that, the wafer 700 in the second process space 102 is completed In the case of the copper reflow process, the wafer 700 can be transferred back to the first process space 101 for cooling and other processes by using the transfer member 200, or the wafer 700 can be transferred out of the process chamber 110, and transferred into the process chamber 110 of another semiconductor process equipment for cooling and other processes.
- the wafer 700 that was previously subjected to the deposition process in the first process space 101 can continue to be introduced into the second process space 102 and heated. for copper reflow process.
- the above-mentioned process is only one of the processes that can be performed by the semiconductor process equipment disclosed in the embodiment of the present application. Other processes, such as other reflow processes, can also be performed by using the above-mentioned semiconductor process equipment, which will not be listed here. .
- the number of the sheet transfer member 200 may be one, and the carrier is provided with a first bearing position 310 and a second bearing position 320, the first Both the carrying position 310 and the second carrying position 320 can carry the wafer 700 .
- the carrier is provided with a first bearing position 310 and a second bearing position 320, the first Both the carrying position 310 and the second carrying position 320 can carry the wafer 700 .
- at least two wafers 700 can be carried on the carrier, so that the positions of the wafers 700 in the first process space 101 and the second process workpiece can be exchanged under the action of a sheet transfer member 200 .
- the number of the chip transfer member 200 is one, on the one hand, the cost and control difficulty of the semiconductor process equipment can be reduced; Dimensions of the process chamber 110 .
- the distribution directions of the first bearing position 310 and the second bearing position 320 can be various.
- the first bearing position 310 and the second bearing position 320 are arranged flush in the bearing direction.
- the heating element 400 can be arranged on the top wall of the heating chamber 120, in this case, no matter whether the wafer 700 is carried on the first loading position 310 or the second loading position 320, it can be guaranteed that the heating element 400 can be a wafer The 700 provides reliable and efficient heating.
- the first bearing position 310 and the second bearing position 320 are distributed along the vertical direction, in this case, the first bearing position 310 and the second bearing position can be reduced 320, and can shorten the film transfer distance of the film transfer member 200 to a certain extent.
- both the first bearing position 310 and the second bearing position 320 may include brackets, and the two brackets form a preset distance in the vertical direction.
- the wafer transfer member 200 can transfer the wafer 700 on the base 150 to the first carrying position 310 or the second carrying position 320, and transfer the first carrying position 310 or the second carrying position The wafer 700 on the carrier 320 is transferred to the base 150 .
- the wafer 700 on the base 150 can be transferred to the first loading position 310 or the second loading position 320.
- the first loading position 310 and the second loading position 320 The wafer 700 carried on the base can be transferred to the base 150 by the transfer member 200, but at the same time point, only the wafer 700 on the base 150 can be transferred to the first loading position 310 and the second loading position.
- One of 320 correspondingly, the wafer 700 on one of the first loading position 310 and the second loading position 320 is transferred to the base 150 .
- the sheet transfer member 200 in order to ensure that the sheet transfer member 200 has the ability to transfer the wafer 700 to the first loading position 310 and the second loading position 320, the sheet transfer member 200 can be equipped with lifting capabilities, that is, the sheet transfer member 200 can be moved along the Vertical movement, so that when the wafer transfer member 200 transfers the wafer 700 to the first bearing position 310 and the second bearing position 320 with different heights, the transfer member 200 can lift or lower the transferred wafer 700 corresponds to the height of the corresponding supporting structure (including the first supporting position 310 and the second supporting position 320), and then, with the rotation of the sheet transfer member 200, the wafer 700 can be transferred to the corresponding supporting structure, Afterwards, the chip transfer member 200 descends, so that the wafer 700 is carried on the corresponding carrying structure.
- the semiconductor process equipment provided in the embodiment of the present application may further include a driver 510, the carrier is connected to the driver 510, and the driver 510 is used to drive the carrier to move in the vertical direction.
- the driver 510 is used to drive the carrier to move in the vertical direction.
- it is enough to make the sheet transfer member 200 only have the ability to rotate.
- the chip transfer member 200 can also transfer the wafer 700 on the base 150 to the first loading position 310 or the second loading position 320 .
- the action of the sheet conveying member 200 can be made more simple, thereby reducing the difficulty of controlling the sheet conveying member 200 and improving the reliability of the sheet conveying member 200 .
- the driver 510 can be a linear motor, etc., and the driver 510 can be installed outside the process chamber 110, and the driver 510 can be connected with the carrier by means of a connecting shaft 520 and other structures, thereby ensuring that the driver 510 can drive the carrier along the The load direction moves.
- heating elements 400 are provided above and below the carrying frame, and the heating elements 400 are fixed On the side wall of the heating chamber 120 .
- the heat generated by the heating element 400 can act on the wafer 700 .
- the upper surface of the wafer 700 carried on the carrier can be directly heated by using the heating element 400 above the carrier, so as to further improve the heating efficiency of the copper material on the upper surface of the wafer 700, thereby shortening the lifetime of the wafer 700. Heating time, improve processing efficiency.
- the wafer 700 Under the action of the heating element 400 located under the carrier, the wafer 700 can be heated on the bottom of the wafer 700 to ensure that the temperature of the entire wafer 700 is more uniform, and further improve the process effect of copper reflow. More specifically, in the vertical direction, the distance between the heating element 400 above the carrier and the first bearing position 310 and the distance between the heating element 400 below the carrier and the second bearing position 320 can be equal. 20mm to 30mm.
- a plurality of heating elements 400 spaced apart from each other in the vertical direction are arranged on the side wall of the heating chamber 120, wherein the interval between adjacent heating elements 400 can be adjusted according to the actual situation. OK, there is no limit here.
- the heating elements 400 located above and below the carrier may be distributed along the vertical direction. In this case, the heat uniformity of the wafer 700 carried on the first supporting position 310 and the second supporting position 320 can be relatively better.
- a plurality of vertical The heating elements 400 are spaced apart from each other.
- the opposite sides of the wafer 700 supported on the first supporting position 310 and the second supporting position 320 can be heated by the heating element 400 , and from the opposite sides of the wafer 700
- the heating efficiency of the wafer 700 can be further improved, and the heating uniformity of the wafer 700 can be improved to improve the process effect.
- the heating element 400 can be fixed on the side wall of the heating chamber 120, specifically, the heating element 400 can be a heating lamp tube, which can be fixed on the inner side wall of the heating chamber 120 through a lamp holder, and can be used as a lamp
- the seat is connected to an external power source, and the heating element 400 installed on the inner wall of the heating chamber 120 can provide heating for the wafer 700 carried on the first loading position 310 and the second loading position 320 .
- the semiconductor process equipment disclosed in the embodiment of the present application may further include a driver 510, the carrier is connected to the driver 510, and the driver 510 can drive the carrier Rotate around the central axis of the carrier, so that when the wafer 700 is carried on the carrier, the driver 510 can be used to drive the carrier to rotate, further improving the heating uniformity of the wafer 700 .
- the driver 510 can be a rotating motor, which can be installed outside the heating chamber, and the driver 510 can be connected to the carrier through a connecting shaft 520 to ensure that the driver 510 has the ability to drive the carrier to rotate.
- the temperature of the wafer 700 rises, and the effect of the copper reflow process is relatively better, based on Here, the heated temperature of the wafer 700 can specifically exceed 150°C. Furthermore, as the heated temperature of the wafer 700 increases, the agglomeration phenomenon at the top becomes more obvious. Therefore, the heating temperature can be controlled at Between 175°C and 225°C to ensure that the copper reflow process has the best process effect.
- the process chamber 110 and the heating chamber 120 communicate with each other, specifically, the process chamber 110 and the heating chamber 120 can be formed in an integrated manner, or the process chamber 110 and the heating chamber 120 can also be formed by It is formed by split molding, and the process chamber 110 and the heating chamber 120 are fixedly connected as a whole by means of welding.
- openings are provided on the side walls of the process chamber 110, and the heating chamber 120 is sealed and connected to the process chamber 110 at the opening, so as to ensure that the semiconductor process equipment can form a closed process environment.
- the top wall of the heating chamber 120 is provided with an inspection port.
- the inspection port can be used to install the heating chamber 120 and devices such as the carrier and the heating element 400 in the heating chamber 120. Carry out maintenance work, which can reduce the difficulty of maintenance.
- a cover plate 130 is detachably covered on the inspection port to provide a second process space 102 for the wafer 700 that meets requirements.
- the shape and size of the cover plate 130 can be correspondingly designed according to the shape and size of the inspection port of the heating chamber 120 , and the cover plate 130 and the heating chamber 120 can be detachably fixedly connected by screws 180 and other connectors.
- the heating element 400 is installed in the heating chamber 120, and the heating element 400 can be installed on the inner wall of the heating chamber 120, in this case, the heat of the heating element 400 can be transferred to the inner wall of the heating chamber 120
- the semiconductor process equipment provided by the embodiment of the present application may also include a cooling mechanism, which is arranged outside the side wall of the heating chamber 120, so as to provide cooling for the outer wall of the heating chamber 120 by means of the cooling mechanism. cooling, so as to prevent workers from contacting the outer wall of the heating chamber 120 and being scalded.
- the cooling mechanism can be a water-cooling mechanism, which can include a water inlet 610 and a water outlet 620, and by attaching the cooling pipeline of the cooling mechanism to the outer wall of the heating chamber 120, cooling water can be used to cool the heating chamber 120. Allow to cool.
- a water-cooling mechanism which can include a water inlet 610 and a water outlet 620, and by attaching the cooling pipeline of the cooling mechanism to the outer wall of the heating chamber 120, cooling water can be used to cool the heating chamber 120. Allow to cool.
- the embodiment of the present application also discloses a semiconductor heating method, which includes:
- the first wafer is controlled to transfer the first wafer to the heating chamber, so as to perform a heating process on the first wafer.
- the wafer needs to be heated so that the processing effect of the wafer is relatively better.
- a base is provided in the process chamber, and the base can provide support for the wafer, and then, when the process chamber is performing the first process, the wafer can be supported. on the base.
- the semiconductor process equipment also includes a chip transfer member, which can transfer the wafer to transfer the first wafer to the heating chamber.
- the heating chamber is provided with a carrier, which is transferred to the heating chamber. The first wafer can be carried on the carrier, and the wafer transfer member can transfer the wafer between the base and the carrier.
- the processing method disclosed in this embodiment also includes:
- the first wafer originally carried on the base of the process chamber is transported to the heating chamber by the control transfer member, and after the first wafer is removed from the base, it can continue to be placed on the base. Transfer the second wafer.
- the heating chamber and the process chamber are respectively provided with the first wafer and the second wafer, and the two need to perform the heating process and the first process respectively.
- the time period during which the second wafer undergoes the first process and the time period during which the first wafer undergoes the heating process at least partially overlap in time sequence.
- the heating process on the first wafer in the heating chamber is also carried out correspondingly, and the start time and end point of the two processes can be The same or different, and the start sequence of the two processes can also be selected according to the actual situation, which is not limited here.
- the processing efficiency of the wafer is relatively higher.
- the carrier frame is provided with a first bearing position and a second bearing position along the vertical direction. Since the technical solution of the carrier frame including the first bearing position and the second bearing position has been introduced in detail above, considering the text It is concise and will not be described in detail here. Based on the foregoing technical solutions, in the processing method disclosed in the embodiment of the present application, the above step S1 includes:
- the carrier includes the first loading position and the second loading position, when the first wafer is transferred to the first loading position, the second process position of the carrier is still in a vacant state, and further, the above In the processing method, after step S2, it also includes:
- step S3 control the transfer member to transfer the second wafer to the second loading position of the carrier in the heating chamber, so that the second The wafer undergoes a heating process. That is to say, by making the second wafer that has completed the first process also be transferred to the heating chamber, and the second wafer is carried on the second loading position, the pedestal of the process chamber can be vacant again, and then when the second wafer After a wafer completes the heating process, the base in the process chamber can be used to carry the first wafer again, and the process chamber can be used to provide an environment for the first wafer to perform the second process.
- the embodiment of the present application In the disclosed processing method, after the above step S3, it also includes:
- the time period during which the first wafer is subjected to the second process and the time period during which the second wafer is subjected to the heating process are at least partially overlapped in time sequence. That is, when the first wafer is performing the second process, the second wafer can also undergo the heating process, and the start time and end time of the two processes can be the same or different, and the start time of the two processes
- the sequence can be selected according to the actual situation, which is not limited here. In the case of adopting the above technical solution, the processing efficiency of the semiconductor process equipment can be further improved.
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Abstract
本申请公开一种半导体工艺设备和晶圆的加工方法，该半导体工艺设备包括工艺腔室，还包括与所述工艺腔室连通的加热腔室，所述工艺腔室中设置有用于承载晶圆的基座，所述加热腔室中设置有用于承载晶圆的承载架，所述工艺腔室中还设置有传片件，所述传片件用于在所述基座和所述承载架之间传输晶圆，所述加热腔室中还设置有加热件，所述加热件用于加热承载于所述承载架上的晶圆。上述技术方案可以提升半导体工艺设备的加工效率。
Description
本申请属于半导体加工技术领域，具体涉及一种半导体工艺设备和晶圆的加工方法。
在半导体的加工过程中，磁控溅射是一种常见的薄膜制备工艺，通过对靶材的轰击，使靶材中的粒子溅出，且沉积在衬底的表面形成薄膜。随着半导体的尺寸越来越小，为了保证互连线的可靠性，目前大多采用铜作为形成互联线的材料。
在铜互连的形成过程中，通常需要借助光刻的方式先在衬底上形成沟槽和通孔，之后再在通孔内借助物理气相沉积的方式形成阻挡层和铜层，最后，借助电镀的方式，将沟槽和通孔填满。但是，随着半导体的尺寸逐渐减小，通孔的深宽比在逐渐增大，从而在沉积形成铜层的过程中，因在通孔的开口处沉积的铜层的生长效率过快，容易堵塞通孔的开口，产生空洞现象，导致半导体报废。
为解决这一问题，铜回流技术获得人们的关注，在高温(通常在300℃以上)的作用下，低温下物理气相沉积的铜的表面移动性和晶粒团聚力都得到增强，在扩散作用和刻蚀出的孔道的毛细作用下，沉积铜薄膜的表面铜原子发生迁移，流入刻蚀出的深孔底部，可以避免沟道中的空洞的产生。整个回流工艺可以由多个循环组合而成，循环次数视填充结构而定直至将深孔填充完整。
但是，目前为实现铜回流而设置的加热装置结构复杂，且加工效率较低。
发明内容
本申请公开一种半导体工艺设备和晶圆的加工方法，以至少解决上述技术问题之一。
本申请实施例提供了一种半导体工艺设备，包括工艺腔室，还包括与所述工艺腔室连通的加热腔室，所述工艺腔室中设置有用于承载晶圆的基座，所述加热腔室中设置有用于承载晶圆的承载架，所述工艺腔室中还设置有传片件，所述传片件用于在所述基座和所述承载架之间传输晶圆，所述加热腔室中还设置有加热件，所述加热件用于加热承载于所述承载架上的晶圆。
第二方面，本申请实施例公开一种晶圆的加工方法，应用于上述半导体工艺设备，所述加工方法包括：
在第一晶圆于所述工艺腔室的所述基座上完成第一工艺的情况下，控制所述传片件传输所述第一晶圆至所述加热腔室，以对所述第一晶圆进行加热工艺；
在控制所述传片件将所述第一晶圆自所述工艺腔室的所述基座上移走的情况下，传输第二晶圆于所述工艺腔室的所述基座上，以对所述第二晶圆进行所述第一工艺，其中，所述第二晶圆进行所述第一工艺的时间段和所述第一晶圆进行所述加热工艺的时间段在时间顺序上至少部分重叠。
本申请实施例公开的技术方案中，设置了与工艺腔室连通的加热腔室，以及在加热腔室中安装加热件，工艺腔室和加热腔室可以分别为晶圆提供第一工艺空间和第二工艺空间，设置在工艺腔室中的基座能够承载晶圆，设置在加热腔室中的承载架亦能够承载晶圆，加热件能够加热承载于承载架上的晶圆，工艺腔室内还设置有传片件，传片件能够在基座和承载架之间传输晶圆，以能够在不同的工艺之间切换。在上述半导体工艺设备的工作过程中，第一工艺空间和第二工艺空间内均可以进行对应的工艺，这可以提升半导体工艺设备的加工效率。
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1是本申请实施例公开的半导体工艺设备的结构示意图；
图2是本申请实施例公开的半导体工艺设备中部分结构的示意图；
图3是采用本申请实施例公开的半导体工艺设备所加工的半导体在不同温度下的电镜照片；
图4是本申请实施例公开的晶圆的加工方法的流程图。
附图标记说明：
101-第一工艺空间、102-第二工艺空间、110-工艺腔室、120-加热腔室、130-盖板、140-顶盖、150-基座、160-磁控溅射组件、170-靶材、180-螺钉、
200-传片件、
310-第一承载位、320-第二承载位、
400-加热件、
510-驱动器、520-连接轴、
610-进水口、620-出水口、
700-晶圆。
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施例及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
以下结合附图，详细说明本申请各个实施例公开的技术方案。
如图1和图2所示，本申请实施例公开一种半导体工艺设备，其包括工艺腔室110，半导体工艺设备还包括加热腔室120，加热腔室120与工艺腔室110连通。当然，半导体工艺设备还包括如传片件200、承载架、加热件400、顶盖140和基座150等结构，在半导体工艺设备用以进行溅射工艺时，半导体工艺设备中还可以包括磁控溅射组件160，且磁控溅射组件160与基座150之间设置有靶材170。
其中，工艺腔室110为半导体工艺设备中用以容纳晶圆700和其他器件的结构，工艺腔室110具有内腔，晶圆700和上述基座150等部件均可以被容纳在内腔中，基座150用以承载晶圆700。并且，如上所述，本实施例公开的半导体工艺设备中，设置有与工艺腔室110连通的加热腔室120，工艺腔室110用于为晶圆700提供第一工艺空间101，加热腔室120用于为晶圆700提供第二工艺空间102，前述两个工艺空间均可以为晶圆700进行工艺提供容纳空间，第一工艺空间101和第二工艺空间102的尺寸大小，也即，工艺腔室110和加热腔室120的尺寸大小可以根据实际需求确定，此处不作限定。
第一工艺空间101和第二工艺空间102相互连通，在这种情况下，晶圆700能够在第一工艺空间101和第二工艺空间102之间相互切换，这使得晶圆700在第一工艺空间101和第二工艺空间102中的一者中完成对应的工艺之后，可以被移动至第一工艺空间101和第二工艺空间102中的另一者继续进行另一工艺。在此过程中，半导体工艺设备的整体工艺环境不会被破坏，且可以提升加工效率。另外，在上述半导体工艺设备的工作过程中，第一工艺空间101和第二工艺空间102可以分别进行对应的工艺，使得第一工艺空间101和第二工艺空间102内的工艺互不干扰，这可以进一步提升晶圆700的加工效率。
承载架设置在加热腔室120中，该承载架能够承载晶圆700，从而为晶圆700在第二工艺空间102内进行对应的工艺时提供承载作用。承载架具体可以为支架，或者，承载架还可以包括多个顶针，这均可以保证承载架具备承载晶圆700的能力。承载架可以固定安装在加热腔室120的底部或侧部，或者，承载架亦可以具备相对工艺腔室110移动的能力，使承载架能够带动承载于承载架上的晶圆700运动。
传片件200安装在工艺腔室110内，且传片件200能够移动晶圆700，以用于在基座150和承载架之间传输晶圆700，从而使晶圆700能够分别在工艺腔室110和加热腔室120进行相应的工艺。传片件200具体可以为机械手，利用传片件200能够改变晶圆700的位置。更具体地说，可以利用传片件200使晶圆700在第一工艺空间101和第二工艺空间102内切换。传片件200具体可以安装在工艺腔室110的底部或侧部，且传片件200具体可以通过抓取或承托等方式固定晶圆700，且通过转动或移动等方式改变晶圆700的位置。
加热腔室120中还设置有加热件400，加热件400具体可以为电阻丝等具备加热能力的器件，加热件400可以固定在加热腔室120的顶部、侧部或底部等位置处，以为承载于承载架的晶圆700提供加热作用，使晶圆700的温度升高。
本申请实施例公开的技术方案中，设置了与工艺腔室110连通的加热腔室120，以及在加热腔室中安装加热件400，工艺腔室110和加热腔室120可以分别为晶圆700提供第一工艺空间101和第二工艺空间102，设置在工艺腔室110中的基座150能够承载晶圆700，设置在加热腔室120中的承载架亦能够承载晶圆700，加热件400能够加热承载于承载架上的晶圆700，工艺腔室110内还设置有传片件200，传片件200能够在基座150和承载架之间传输晶圆700，以能够在不同的工艺之间切换。在上述半导体工艺设备的 工作过程中，第一工艺空间101和第二工艺空间102内均可以进行对应的工艺，这可以提升半导体工艺设备的加工效率。
可选地，利用上述半导体工艺设备对晶圆700进行加工，且可以使晶圆700在第一工艺空间101内形成阻挡层和铜层之后，在传片件200的作用下，将完成前述工艺的晶圆700移动至第二工艺空间102的承载架上，在加热件400的加热作用下，进行铜回流工艺，使晶圆700上表面的铜材料在高温条件下流动至晶圆700上沉槽和通孔的底部，从而防止出现空洞现象，提升晶圆700的良品率。
如上所述，在利用上述半导体工艺设备形成互连线的过程中，可以先在第一工艺空间101内进行沉积工艺，之后，利用传片件200将第一工艺空间101内的晶圆700移动至第二工艺空间102的承载架上，之后，可以继续向第一工艺空间101内传入下一晶圆700，与此同时，第二工艺空间102内的加热件400工作，使晶圆700进行铜回流工艺，显然，第一工艺空间101和第二工艺空间102之间的工艺互不干扰，这可以提升半导体工艺设备的加工效率；之后，在第二工艺空间102内的晶圆700完成铜回流工艺的情况下，可以利用传片件200将该晶圆700重新传回第一工艺空间101内进行冷却等工艺，或者，也可以将该晶圆700传出工艺腔室110，且传入另一半导体工艺设备的工艺腔室110进行冷却等工艺，相应地，之前在第一工艺空间101内进行沉积工艺的晶圆700则可以继续被传入至第二工艺空间102且被加热，以进行铜回流工艺。当然，上述工艺过程仅为本申请实施例公开的半导体工艺设备所能够进行的工艺中的一种，利用上述半导体工艺设备还可以进行其他工艺，例如其他的回流工艺，此处不再一一列举。
在上述过程中，为了使第一工艺空间101和第二工艺空间102内的晶圆700的位置能够互相交换，可选地，传片件200的数量为多个，多个传片件200分别为第一工艺空间101和第二工艺空间102内的晶圆700提供移位作 用，从而缩短工艺间隔，提升加工效率。
在本申请的另一实施例中，可选地，如图1所示，传片件200的数量可以为一个，并且，承载架设置有第一承载位310和第二承载位320，第一承载位310和第二承载位320均能够承载晶圆700。在这种情况下，承载架上可以承载至少两个晶圆700，从而在一个传片件200的作用下，即可完成第一工艺空间101和第二工艺工件内晶圆700的位置对换。在传片件200的数量为一个的情况下，一方面可以降低半导体工艺设备的成本和控制难度，另一方面还可以减小传片件200对半导体工艺设备内空间的占用量，进而减小工艺腔室110的尺寸。
具体地，第一承载位310和第二承载位320的分布方向可以有多种，可选地，第一承载位310和第二承载位320在承载方向上平齐设置，在这种情况下，加热件400可以设置在加热腔室120的顶壁上，在这种情况下，无论晶圆700承载于第一承载位310还是第二承载位320，均可以保证加热件400能够为晶圆700提供可靠的高效的加热作用。
在本申请的另一实施例中，可选地，第一承载位310和第二承载位320沿竖直方向分布，在这种情况下，可以减小第一承载位310和第二承载位320所占的平面空间，且可以在一定程度上缩短传片件200的传片距离。具体地，第一承载位310和第二承载位320均可以包括支架，且两个支架在竖直方向上形成预设距离。对应地，在半导体工艺设备的工作过程中，传片件200能够将基座150上的晶圆700传输至第一承载位310或第二承载位320，以及将第一承载位310或第二承载位320上的晶圆700传输至基座150上。
需要说明的是，基座150上的晶圆700既可以被传输至第一承载位310，亦可以被传输至第二承载位320上，相似地，第一承载位310和第二承载位320上所承载的晶圆700均可以被传片件200传输至基座150上，只是在同一时间点，仅能将基座150上的晶圆700传输至第一承载位310和第二承载 位320中的一者，对应地，第一承载位310和第二承载位320中的一者上的晶圆700传输至基座150上。
在上述技术方案中，为了保证传片件200具备向第一承载位310和第二承载位320传送晶圆700的能力，可以使传片件200具备升降能力，也即传片件200能够沿竖直方向运动，从而在传片件200向高度不同的第一承载位310和第二承载位320传送晶圆700时，传片件200能够通过抬升或下降的方式，使所传送的晶圆700与对应的承载结构(包括第一承载位310和第二承载位320)的高度对应，之后，随着传片件200的转动，即可使晶圆700被传送至对应的承载结构上方，之后，传片件200下降，使晶圆700承载在对应的承载结构上。
或者，本申请实施例提供的半导体工艺设备还可以包括驱动器510，承载架与驱动器510连接，进而利用驱动器510驱动承载架沿竖直方向移动。在采用这种技术方案的情况下，则使传片件200仅具备转动的能力即可。通过使承载架配合传片件200，亦可以使传片件200能够将基座150上的晶圆700传送至第一承载位310或第二承载位320上。并且，在这种情况下，可以使传片件200的动作更为单一，进而降低传片件200的控制难度，且提升传片件200的可靠性。具体地，驱动器510可以为直线电机等，驱动器510可以安装在工艺腔室110之外，且借助连接轴520等结构可以使驱动器510与承载架连接在一起，进而保证驱动器510能够驱动承载架沿承载方向移动。
在第一承载位310和第二承载位320沿竖直方向分布的情况下，可选地，在竖直方向上，承载架的上方和下方均设有加热件400，且加热件400均固定在加热腔室120的侧壁上。在采用前述技术方案的情况下，无论晶圆700承载于第一承载位310还是第二承载位320，加热件400产生的热量均可以作用在晶圆700上。并且，利用承载架上方的加热件400可以直接对承载于承载架的晶圆700的上表面进行加热，从而进一步提升位于晶圆700上表面 的铜材料的加热效率，进而可以缩短晶圆700的加热时间，提升加工效率。在位于承载架下方的加热件400的作用下，可以在晶圆700的底面对晶圆700进行加热，保证整个晶圆700的温度更为均匀，进一步提升铜回流的工艺效果。更具体地，在竖直方向上，可以使位于承载架上方的加热件400与第一承载位310之间的间距以及位于承载架下方的加热件400与第二承载位320之间的间距均为20mm～30mm。
更进一步地，如图1所示，加热腔室120的侧壁上设置有多个沿竖直方向相互间隔的加热件400，其中，相邻设置的加热件400之间的间隔可以根据实际情况确定，此处不作限定。例如，可以使位于承载架上方和下方的加热件400沿竖直方向分布。在这种情况下，可以使承载于第一承载位310和第二承载位320上的晶圆700的受热一致性相对更好。
更进一步地，如图2所示，在垂直于竖直方向的方向上，或者说，在垂直于承载架的承载方向的方向上，承载架的相背两侧均设有多个沿竖直方向相互间隔的加热件400。在这种情况下，支撑在第一承载位310和第二承载为320上的晶圆700的相背两侧均可以受到加热件400的加热作用，在自晶圆700的相背两侧一并加热晶圆700的情况下，可以进一步提升晶圆700的加热效率，且可以提升晶圆700的被加热均匀性，提升工艺效果。
更详细地，加热件400可以固定在加热腔室120的侧壁上，具体地，加热件400可以为加热灯管，其可以通过灯座固定在加热腔室120的内侧壁，且通过为灯座外接电源，即可借助安装在加热腔室120的内侧壁上的加热件400为承载于第一承载位310和第二承载位320上的晶圆700提供加热作用。
为了进一步提升承载在承载架上的晶圆700的受热均匀性，可选地，本申请实施例公开的半导体工艺设备中还可以包括驱动器510，承载架与驱动器510连接，驱动器510能够驱动承载架围绕承载架的中轴转动，从而在承载架上承载有晶圆700的情况下，可以利用驱动器510驱动承载架旋转，进 一步提升晶圆700的受热均匀性。具体地，驱动器510可以为旋转电机，其可以安装在加热腔室之外，且驱动器510可以通过连接轴520与承载架连接，保证驱动器510具备驱动承载架旋转的能力。
在利用加热的方式促进晶圆700上表面的铜材料流入通孔和沉槽的底部的过程中，如图3所示，晶圆700的温度升高，铜回流工艺的效果相对更好，基于此，晶圆700的被加热的温度具体可以超过150℃，更进一步地，由于在晶圆700的被加热温度升高的情况下，顶部团聚现象也越明显，因而，可以使加热温度控制在175℃～225℃之间，以保证铜回流工艺具有最佳的工艺效果。
如上所述，工艺腔室110和加热腔室120相互连通，具体地，工艺腔室110和加热腔室120可以采用一体成型的方式形成，或者，工艺腔室110和加热腔室120亦可以通过分体成型的方式形成，且采用焊接等方式将工艺腔室110与加热腔室120固定连接为一体，在这种技术方案中，工艺腔室110的侧壁上设置有开口，且加热腔室120在开口处于工艺腔室110密封连接，保证半导体工艺设备能够形成密闭的工艺环境。
并且，加热腔室120的顶壁开设有检修口，在半导体工艺设备的使用过程中，可以利用检修口对安装于加热腔室120和加热腔室120内的如承载架和加热件400等器件进行检修工作，这可以降低检修难度。同时，检修口上可拆卸地盖设有盖板130，为晶圆700提供满足需求的第二工艺空间102。具体地，盖板130的形状和尺寸可以根据加热腔室120的检修口的形状和尺寸对应设计，且盖板130与加热腔室120可以通过螺钉180等连接件形成可拆卸地固定连接关系。
如上所述，加热件400安装在加热腔室120，且加热件400可以安装在加热腔室120的内侧壁上，在这种情况下，加热件400的热量能够传递至加热腔室120的内壁上，基于此，可选地，本申请实施例提供的半导体工艺设 备还可以包括冷却机构，冷却机构设置在加热腔室120的侧壁的外侧，以借助冷却机构为加热腔室120的外壁进行冷却，从而防止工作人员与加热腔室120的外壁接触而被烫伤。具体地，冷却机构可以为水冷机构，其可以包括进水口610和出水口620，通过使冷却机构的冷却管路贴设设置在加热腔室120的外壁上，可以利用冷却水对加热腔室120进行冷却。
基于上述实施例公开的半导体工艺设备，本申请实施例还公开一种半导体的加热方法，其包括：
S1、在第一晶圆于工艺腔室的基座上完成第一工艺的情况下，控制传片件传输第一晶圆至加热腔室，以对第一晶圆进行加热工艺。如上所述，在晶圆完成沉积等传统工艺过程，即第一工艺之后，需要对晶圆进行加热，以使晶圆的加工效果相对更好。具体地，基于上述实施例公开的半导体工艺设备，工艺腔室中设置有基座，基座可以为晶圆提供承载支撑作用，进而，在工艺腔室进行第一工艺时，可以使晶圆承载于基座上。并且，半导体工艺设备还包括传片件，传片件可以传输晶圆，以将第一晶圆传输至加热腔室中，对应地，加热腔室中设置有承载架，传输至加热腔室的第一晶圆可以承载在承载架上，传片件能够在基座和承载架之间传输晶圆。
基于上述步骤S1，如图4所示，本实施例公开的加工方法还包括：
S2、在控制传片件将第一晶圆自工艺腔室的基座上移走的情况下，传输第二晶圆于工艺腔室的基座上，从而使第二晶圆承载在基座上，为第二晶圆能够进行第一工艺提供基础条件，相应地，当第二晶圆承载于基座上之后，则认为可以对第二晶圆进行第一工艺。
如上所述，原本承载于工艺腔室的基座上的第一晶圆被控制传片件传输至加热腔室，且在第一晶圆自基座上移走之后，可以继续向基座上传输第二晶圆，此时，加热腔室和工艺腔室中分别设置有第一晶圆和第二晶圆，且二者分别需要进行加热工艺和第一工艺，基于此，在上述步骤S2中，第二晶 圆进行第一工艺的时间段和第一晶圆进行加热工艺的时间段在时间顺序上至少部分重叠。简单地说，在工艺腔室中对第二晶圆进行第一工艺的过程中，加热腔室中对第一晶圆的加热工艺亦在相应进行，两个工艺的开始时间点和结束点可以相同，亦可以不同，且两个工艺的开始先后顺序亦可以根据实际情况选定，此处不作限定。通过采用上述技术方案，使得晶圆的加工效率相对更高。
进一步地，承载架上沿竖直方向设置有第一承载位和第二承载位，由于上文已经对承载架包括第一承载位和第二承载位的技术方案进行了详细的介绍，考虑文本简洁，此处不再详细介绍。基于前述技术方案，本申请实施例公开的加工方法中，上述步骤S1包括：
S11、在第一晶圆于工艺腔室的基座上完成第一工艺的情况下，控制传片件传输第一晶圆至加热腔室中承载架的第一承载位，以对第一晶圆进行加热工艺。也即，在承载架包括第一承载位和第二承载位的情况下，传输完成第一工艺的第一晶圆时，可以具体控制传片件将第一晶圆传输至承载架的第一承载位上，以使第一晶圆在第一承载位处进行加热工艺。
并且，基于承载架包括第一承载位和第二承载位的技术方案，当第一晶圆传输至第一承载位上的情况下，承载架的第二工艺位还处于空缺状态，进而，上述加工方法中，步骤S2之后还包括：
S3、在第二晶圆于工艺腔室的基座上完成第一工艺的情况下，控制传片件传输第二晶圆至加热腔室中的承载架的第二承载位，以对第二晶圆进行加热工艺。也即，通过使完成第一工艺的第二晶圆亦被传输至加热腔室，且使第二晶圆承载于第二承载位，可以使工艺腔室的基座上再次空缺，进而当第一晶圆完成加热工艺之后，可以利用工艺腔室中的基座再次承载第一晶圆，且利用工艺腔室为第一晶圆提供进行第二工艺的环境，具体来说，本申请实施例公开的加工方法中，上述步骤S3之后还包括：
S4、在第一晶圆于加热腔室的第一承载位上完成加热工艺的情况下，控制传片件传输第一晶圆至工艺腔室的基座上，以对第一晶圆进行第二工艺。如上所述，在第二晶圆传输至第二承载位上的情况下，可以将第一晶圆再次传输回处于空缺状态的工艺腔室的基座上，且利用工艺腔室对第一晶圆进行第二工艺。
并且，在上述步骤S4中，第一晶圆进行第二工艺的时间段和第二晶圆进行加热工艺的进行时间段在时间顺序上至少部分重叠。也即，在第一晶圆进行第二工艺的过程中，第二晶圆亦可以进行加热工艺，两个工艺的开始时间点和结束时间点可以相同，亦可以不同，且两个工艺的开始先后顺序可以根据实际情况选定，此处不作限定。在采用上述技术方案的情况下，可以进一步提升半导体工艺设备的加工效率。
本申请上文实施例中重点描述的是各个实施例之间的不同，各个实施例之间不同的优化特征只要不矛盾，均可以组合形成更优的实施例，考虑到行文简洁，在此则不再赘述。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。
Claims (10)
- 一种半导体工艺设备，包括工艺腔室，其特征在于，还包括与所述工艺腔室连通的加热腔室，所述工艺腔室中设置有用于承载晶圆的基座，所述加热腔室中设置有用于承载晶圆的承载架，所述工艺腔室中还设置有传片件，所述传片件用于在所述基座和所述承载架之间传输晶圆，所述加热腔室中还设置有加热件，所述加热件用于加热承载于所述承载架上的晶圆。
- 根据权利要求1所述的半导体工艺设备，其特征在于，所述承载架上沿竖直方向设置有第一承载位和第二承载位，所述传片件用于将所述基座上的晶圆传输至所述第一承载位或所述第二承载位，以及将所述第一承载位或所述第二承载位上的晶圆传输至所述基座上。
- 根据权利要求2所述的半导体工艺设备，其特征在于，在所述竖直方向上，所述承载架的上方和下方均设有所述加热件，所述加热件均固定于所述加热腔室的侧壁上。
- 根据权利要求2所述的半导体工艺设备，其特征在于，所述半导体工艺设备还包括驱动器，所述承载架与所述驱动器连接，所述驱动器用于驱动所述承载架沿竖直方向移动，和/或围绕所述承载架的中轴转动。
- 根据权利要求2所述的半导体工艺设备，其特征在于，所述加热腔室的侧壁上设有多个沿所述竖直方向相互间隔的所述加热件。
- 根据权利要求2-5任一项所述的半导体工艺设备，其特征在于，所述加热件为加热灯管。
- 根据权利要求1所述的半导体工艺设备，其特征在于，所述工艺腔室的侧壁上设置有开口，所述加热腔室在所述开口处与所述工艺腔室密封连接，所述加热腔室通过所述开口与所述工艺腔室连通，所述加热腔室的顶壁上开设有检修口，所述检修口上可拆卸地盖设有盖板。
- 根据权利要求1所述的半导体工艺设备，其特征在于，所述加热腔室外侧还设置有冷却机构，用于冷却所述加热腔室的外壁。
- 一种晶圆的加工方法，应用于权利要求1-8任一项所述的半导体工艺设备，其特征在于，所述加工方法包括：在第一晶圆于所述工艺腔室的所述基座上完成第一工艺的情况下，控制所述传片件传输所述第一晶圆至所述加热腔室，以对所述第一晶圆进行加热工艺；在控制所述传片件将所述第一晶圆自所述工艺腔室的所述基座上移走的情况下，传输第二晶圆于所述工艺腔室的所述基座上，以对所述第二晶圆进行所述第一工艺，其中，所述第二晶圆进行所述第一工艺的时间段和所述第一晶圆进行所述加热工艺的时间段在时间顺序上至少部分重叠。
- 根据权利要求9所述的加工方法，其特征在于，所述承载架上沿竖直方向设置有第一承载位和第二承载位，所述传片件用于将所述基座上的晶圆传输至所述第一承载位或所述第二承载位，以及将所述第一承载位或所述第二承载位上的晶圆传输至所述基座上，所述加工方法中，所述在第一晶圆于所述工艺腔室的所述基座上完成第一工艺的情况下，控制所述传片件传输所述第一晶圆至所述加热腔室，以对所述第一晶圆进行加热工艺，包括：在所述第一晶圆于所述工艺腔室的所述基座上完成所述第一工艺的情况下，控制所述传片件传输所述第一晶圆至所述加热腔室中所述承载架的所 述第一承载位，以对所述第一晶圆进行所述加热工艺；所述在控制所述传片件将所述第一晶圆自所述工艺腔室的所述基座上移走的情况下，传输第二晶圆于所述工艺腔室的所述基座上，以对所述第二晶圆进行所述第一工艺之后，还包括：在所述第二晶圆于所述工艺腔室的所述基座上完成所述第一工艺的情况下，控制所述传片件传输所述第二晶圆至所述加热腔室中所述承载架的所述第二承载位，以对所述第二晶圆进行所述加热工艺；在所述第一晶圆于所述加热腔室的所述第一承载位上完成所述加热工艺的情况下，控制所述传片件传输所述第一晶圆至所述工艺腔室的所述基座上，以对所述第一晶圆进行第二工艺，其中，所述第一晶圆进行所述第二工艺的时间段和所述第二晶圆进行所述加热工艺的时间段在时间顺序上至少部分重叠。
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102560373A (zh) * | 2010-12-16 | 2012-07-11 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 基片加热腔室、使用基片加热腔室的方法及基片处理设备 |
| CN105088151A (zh) * | 2014-04-15 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 衬底上的孔隙沉积工艺及半导体加工设备 |
| CN105441876A (zh) * | 2014-09-02 | 2016-03-30 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 一种薄膜沉积设备 |
| CN111986976A (zh) * | 2019-05-22 | 2020-11-24 | 北京北方华创微电子装备有限公司 | 工艺腔室及半导体处理设备 |
| US20210104434A1 (en) * | 2019-10-06 | 2021-04-08 | Applied Materials, Inc. | Methods and apparatuses for forming interconnection structures |
| CN113921456A (zh) * | 2021-09-30 | 2022-01-11 | 北京北方华创微电子装备有限公司 | 半导体工艺设备和晶圆的加工方法 |
-
2021
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-
2022
- 2022-09-27 TW TW111136551A patent/TW202316603A/zh unknown
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102560373A (zh) * | 2010-12-16 | 2012-07-11 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 基片加热腔室、使用基片加热腔室的方法及基片处理设备 |
| CN105088151A (zh) * | 2014-04-15 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 衬底上的孔隙沉积工艺及半导体加工设备 |
| CN105441876A (zh) * | 2014-09-02 | 2016-03-30 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 一种薄膜沉积设备 |
| CN111986976A (zh) * | 2019-05-22 | 2020-11-24 | 北京北方华创微电子装备有限公司 | 工艺腔室及半导体处理设备 |
| US20210104434A1 (en) * | 2019-10-06 | 2021-04-08 | Applied Materials, Inc. | Methods and apparatuses for forming interconnection structures |
| CN113921456A (zh) * | 2021-09-30 | 2022-01-11 | 北京北方华创微电子装备有限公司 | 半导体工艺设备和晶圆的加工方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117995736A (zh) * | 2024-04-07 | 2024-05-07 | 无锡尚积半导体科技有限公司 | 晶圆供应设备 |
| CN117995736B (zh) * | 2024-04-07 | 2024-06-04 | 无锡尚积半导体科技有限公司 | 晶圆供应设备 |
Also Published As
| Publication number | Publication date |
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| TW202316603A (zh) | 2023-04-16 |
| CN113921456A (zh) | 2022-01-11 |
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