WO2023050729A1 - 数字滤波器、滤波方法及电子设备 - Google Patents

数字滤波器、滤波方法及电子设备 Download PDF

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WO2023050729A1
WO2023050729A1 PCT/CN2022/080839 CN2022080839W WO2023050729A1 WO 2023050729 A1 WO2023050729 A1 WO 2023050729A1 CN 2022080839 W CN2022080839 W CN 2022080839W WO 2023050729 A1 WO2023050729 A1 WO 2023050729A1
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data
filter
processed
input
input data
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PCT/CN2022/080839
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English (en)
French (fr)
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邓伟翔
郭燕
王恒杰
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深圳市中兴微电子技术有限公司
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Publication of WO2023050729A1 publication Critical patent/WO2023050729A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks

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  • the present application relates to the technical field of digital circuit design, in particular to a digital filter, a filtering method and electronic equipment.
  • Digital filters are the basic building blocks in digital signal processing systems.
  • the time-division multiplexing technology can greatly reduce the number of multipliers in the digital filter, thereby reducing the area and power consumption of the digital filter.
  • current digital filters still cannot effectively reduce power consumption.
  • the application proposes a digital filter, a filtering method and electronic equipment, aiming at reducing power consumption.
  • An embodiment of the present application provides a digital filter, including a data filtering module, and the data filtering module includes: a processing unit, configured to perform correction processing on n pieces of input data to be processed, and obtain processed data, wherein the processed data Including uncorrected input data and corrected corrected data, n is an integer greater than or equal to 2; and a filtering unit for outputting target data based on the processed data, wherein the target data is not corrected Input data.
  • An embodiment of the present application provides a digital filtering method, including: performing correction processing on n input data to be processed to obtain processed data, wherein the processed data includes uncorrected input data and corrected corrected data, n is an integer greater than or equal to 2; and filtering the processed data to obtain target data, wherein the target data is uncorrected input data.
  • An embodiment of the present application provides an electronic device, including the digital filter according to the present application, for processing input data to be processed.
  • Figure 1 is a basic schematic diagram of a digital filter
  • Fig. 2 is the schematic diagram of multiplier and adder in the digital filter that adopts 1:n time division multiplexing technology
  • Fig. 3 is the timing diagram arriving at the input end of the second data filtering module in the digital filter of time division multiplexing
  • Fig. 4 is the structural representation of the digital filter provided by the present application.
  • Fig. 5 is the timing diagram of the digital filter provided by the present application.
  • FIG. 6 is a sequence diagram of a data filtering module in the related art
  • Fig. 7 increases the sequence diagram of data filtering module after the NOR gate in the digital filter that the application provides
  • FIG. 8 is a schematic structural diagram of a digital filter provided by the present application.
  • FIG. 9 is another structural schematic diagram of a digital filter provided by the present application.
  • FIG. 10 is a flow chart of the digital filtering method provided by the present application.
  • Embodiments described herein may be described with reference to plan views and/or cross-sectional views by way of idealized schematic representation of the application. Accordingly, the example illustrations may be modified according to manufacturing techniques and/or tolerances. Therefore, the embodiments are not limited to the ones shown in the drawings but include modifications of configurations formed based on manufacturing processes. Accordingly, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.
  • Fig. 1 is the basic schematic diagram of the digital filter. As shown in Figure 1, Z-1 represents the delay term of the input data, represents the multiplier, represents an adder, and h 0 , h 1 , ..., h n-1 , and h n represent filter coefficients.
  • time division multiplexing technology is often used to reduce the number of multipliers in the digital filter to reduce the area of the digital filter. For example, a digital filter with a time division multiplexing ratio of 1:n can reduce the number of multipliers to 1/n.
  • Figure 2 is a schematic diagram of multipliers and adders in digital filters using 1:n time-division multiplexing technology.
  • the digital filter comprises a plurality of time-division multiplexing modules 210 and a plurality of second adders 220, and the input terminal of the second adder 220 receives the output signal of the time-division multiplexing module 210 of the same level, and the next The output signals of the second adder 220 of each stage, that is, the second adder 220 is added stage by stage.
  • Each time division multiplexing module 210 includes a first data filtering module 201 , a second data filtering module 202 , a multiplier 203 and a first adder 204 .
  • the first data filtering module 201 is used for filtering filter coefficients, including an input end and an output end, and the input end of the first data filtering module 201 receives filter coefficients h(0), h(1), ..., h(n- 1) and the filtering condition sel, the output terminal of the first data filtering module 201 is connected to the first input terminal of the multiplier 203 .
  • the second data filtering module 202 is used to filter input data, including an input terminal and an output terminal, and the input terminal of the second data filtering module 202 receives input data x(0), x(1), . . . , x(n-1) As well as the filtering condition sel, the output terminal of the second data filtering module 202 is connected to the second input terminal of the multiplier 203 .
  • the first input of the multiplier 203 is connected with the output of the first data filtering module 201
  • the second input of the multiplier 203 is connected with the output of the second data filtering module 202
  • the output of the multiplier 203 is connected with the first addition
  • the input end of the first adder 204 is connected to the input end of the first adder 204
  • the output end of the first adder 204 is connected to the input end for inputting the feedback signal of the first adder 204 into the first adder 204 for time division multiplexing.
  • the first data filtering module 201 and the second data filtering module 202 respectively filter the filter coefficients and the input data through the filter condition sel as the input of the multiplier 203, so as to reduce the number and volume of the multipliers to 1/n.
  • the input data x(0), x(1), ..., x(n-1) input to the second data filtering module 202 is constantly changing, and the length of the input data is different, therefore, the input
  • the time when the data arrives at the input end of the second data filtering module 202 is different, a burr will be generated at the input end of the second data filtering module 202, and as many input signals as there are, there are as many burrs at the input end of the second data filtering module 202 .
  • FIG. 3 is a timing diagram for reaching the input of the second data filtering module in a time-division multiplexed digital filter. As shown in Figure 3, due to the different lengths of the input data x(0), x(1), ..., x(n), the time to reach the second data filtering module is different, resulting in the input data being in the second data filtering module A large number of glitches are generated at the input of the , resulting in increased power consumption.
  • the present application improves the digital filter (which includes the data filtering module) among the above digital filters.
  • the digital filter receives a plurality of input data and outputs a target data, and the target data is a part of the plurality of input data, such as one or more input data.
  • FIG. 4 is a schematic structural diagram of a digital filter provided by the present application.
  • the digital filter includes a data filtering module 41 for filtering input data.
  • the data filtering module 41 includes a processing unit 401 and a filtering unit 402 .
  • the processing unit 401 is configured to perform correction processing on a plurality of input data to be processed to obtain processed data, wherein the processed data includes uncorrected input data and corrected corrected data.
  • the input data is the digital code of the discrete signal to be processed. After the input data is corrected, the corrected data will not affect other input data (such as target data), will not send jumps at the input end of the filter unit 402 , and can be easily filtered out by the filter unit 402 .
  • the processed data includes an uncorrected input data, and at least one corrected corrected data.
  • the correction data may be a fixed value, which is beneficial for the filtering unit 402 to select the target data from the processed data without affecting the length of the target data. For example, the correction data is 0 or other suitable values.
  • n input data a plurality of input data is expressed as n input data, and n is an integer greater than or equal to 2.
  • the n input data are corrected to obtain processed data.
  • the processing includes identifying and correcting the input data.
  • the processed data includes the input data to be retained and the corrected data after modification of the input data. For example, after the input data is processed, if it is still the input data itself, then the input data is the target data; if it is corrected, then the input data is the data to be filtered out.
  • only one input data remains unchanged, and the other input data is corrected, which is beneficial for the filtering unit to perform filtering.
  • the filtering unit 402 is configured to filter the processed data to obtain target data, wherein the target data is uncorrected input data.
  • the target data is the input data which has not been corrected by the processing unit 401, ie the target data is one of the input data. After being filtered by the filtering unit 402, the target data is output.
  • the other input data is corrected by the processing unit 401 to a fixed value that is easy to be filtered. The fixed value enables the filtering unit 402 to select target data from the processed data, and the uncorrected input data will not be filtered out by the filtering unit 402 .
  • the processing unit 401 and the filtering unit 402 work together to retain the required input data, and modify other input data into modified data that is easy to be filtered and does not cause jumps at the input end of the filtering unit 402 .
  • the processing unit 401 after the input data is modified to 0 by the processing unit 401, no transition occurs at the input terminal of the filter unit 402, eliminating glitches and reducing power consumption.
  • the processing unit corrects a plurality of input data to be processed to obtain the processed data. Except for the target data, other input data with inconsistent data lengths are all modified into corrected data, which avoids input.
  • the impact of inconsistency in data length eliminates burrs, reduces power consumption of the digital filter, and facilitates the filtering of the filtering unit to facilitate the selection of target data.
  • the processing unit 401 may include AND gates 4011, and the number of AND gates 4011 is not less than the number of input data.
  • the quantity of AND gate 4011 can be consistent with the quantity of input data, the first input terminal of each AND gate 4011 inputs an input data, the second input terminal of each AND gate 4011 inputs a filter mark, and the output terminal of AND gate 4011 It is connected with the input end of the filter unit 402 .
  • the AND gate 4011 filters and modifies the input data by means of the filter flag, so that the required input data remains unchanged, and modifies the unnecessary input data as corrected data.
  • the filter flag is a flag corresponding to the filter condition of the input data, and the filter condition can be preset by the user.
  • the processing unit 401 includes n+1 AND gates 4011, and the first input terminals of the n+1 AND gates 4011 are respectively connected to input data x(0), x(1), . . . , x(n), n
  • the second input terminals of the +1 AND gates 4011 are respectively connected to the filter marks m(0), m(1), ... m(n), and the output terminals of the n+1 AND gates 4011 are all connected to the filter unit 402 .
  • the input data x(0), x(1), . . . , x(n) and the corresponding filter marks m(0), m(1), . . . m(n) pass through the AND gate 4011 to output processed data.
  • the bit width of the filter flag can be the same as the bit width of the input data corresponding to the target data, and each bit of the filter flag corresponding to the target data is "1"; the bit width of the filter flag can be the bit width of the input data corresponding to the correction data Each bit of the filter flag corresponding to the same width and the correction data is "0".
  • each bit of the filter flag m(0) corresponding to the input data x(0) is "1"
  • the filter flag m The bit width of (0) is the same as the bit width of the input data x(0), in other words, the filtering mark m(0) is “1” of the bit width length of the input data x(0).
  • Each bit of the filter flags m(1), m(2), ... m(n) corresponding to the input data x(1), x(2), ..., x(n) is "0", Moreover, the bit width of the filter marks m(1), m(2), ...
  • the filter marks m(1), m(2),...m(n) are the corresponding input data data x(1), x(2),..., x(n) bit width length "0".
  • the filter mark m(1) is "0" of the input data x(1) bit width length
  • the filter mark m(2) is "0" of the input data x(2) bit width length
  • the filter mark m(n-1) is "0" of the bit width length of the input data x(n-1).
  • each bit of the filter flag corresponding to the target data is set to "1"
  • each bit of the filter flag corresponding to the correction data is "0". ”, so that except for the target data, other input data are easily filtered out, that is, except for the target data, other input data are corrected so that jump correction data does not occur, so as to eliminate glitches generated by other input data.
  • FIG. 5 is a timing diagram of the digital filter provided by the present application.
  • the input data x(0) and the filter mark m(0) are obtained through the AND operation of the AND gate 4011 to obtain the output data q(0), and the input data x(1) and the filter mark m(1) are passed through
  • the output data q(1) is obtained
  • the input data x(2) and the filter mark m(2) are obtained through the AND operation of the AND gate 4011 to obtain the output data q(2), and so on
  • the output data q(n) is obtained after x(n) and the filtering mark m(n) are ANDed through the AND gate 4011 .
  • Fig. 5 the input data x(0) and the filter mark m(0) are obtained through the AND operation of the AND gate 4011 to obtain the output data q(0), and the input data x(1) and the filter mark m(1) are passed through
  • the output data q(1) is obtained
  • the input data x(2) and the filter mark m(2) are obtained through the AND operation of the
  • the input data x(0) is taken as the target data, and the filter mark m(0) is "1" with the bit width and length of the input data x(0), therefore, the output data q(0) and the target data x( 0) is the same, that is, a0, other input data x(1), x(2), ..., x(n) are the data to be filtered out, and the corresponding filter marks m(1), m(2), ... m(n) is "0", and the output data q(1), q(2), . . . , q(n) are correction data, that is, 0.
  • the filtering unit 402 is an OR gate 4021 , the input terminal of the OR gate 4021 is connected to the output terminal of the AND gate 4011 , and the output terminal of the OR gate 4021 is used as the output terminal of the data filtering module 41 .
  • the output data q(0), q(1), ..., q(n) are connected to the input terminal of the OR gate 4021, and the output terminal of the OR gate 4021 can be connected to the multiplier.
  • the processing unit is used to correct a plurality of input data to be processed to obtain uncorrected input data and corrected fixed data, so that the modified fixed value does not appear at the input end of the filter unit. A jump occurs, and then the unmodified input data is output as the target data by the filtering unit.
  • the register stores different input data and outputs it when needed, and the power consumption is much greater than the processing unit and filtering unit of this application, and the register increases the processing delay of the circuit, and the processing efficiency is low.
  • FIG. 6 is a timing diagram of the data filtering module in the related art.
  • the processing unit 401 sequentially processes input data x(0), x(1), . Therefore, the output of the processing unit 401 according to the clock cycle CLK is a0, b1, .
  • setting the output of the data filtering module 41 to 0 may easily lead to inversion of signals output by non-computing items, and the inversion produces greater power consumption.
  • the processing unit can also include a NOR gate 4012, and the input terminals of the NOR gate 4012 are respectively connected to the 0th, 1st, 2nd, ..., n-1th filter marks, or the NOR gate 4012
  • the output terminal of the NOR gate 4012 is connected to the input terminal of the nth AND gate 4011, and the output signal of the NOR gate 4012 is used as the filter mark of the nth AND gate 4011.
  • the NOR gate 4012 is provided with n input terminals, respectively connected to the filter marks m (0), m (1), ... m (n-1), the output terminal of the NOR gate 4012 and the nth AND gate 4011 input connection.
  • the filter marks may include a first filter mark and a second filter mark, and the second filter mark is obtained by ORing the 0th, 1st, 2nd, . . . , n-1th filter marks and then inverting them.
  • the first filtering mark is obtained in an existing manner, which is not limited in this application.
  • the multiplier performs calculations, based on the first filter flag, the second filter flag and the input data, the n input data to be processed are corrected by an AND operation to obtain processed data; in the case where the multiplier does not perform calculations Next, based on the second filter flag and the input data, the n pieces of input data to be processed are corrected through an AND operation to obtain processed data.
  • each bit of the filter flags m(0), m(1), ... m(n-1) is 0, and the output of the NOR gate 4012 is 1, After the output of the NOR gate 4012 is ANDed with the input data x(n), the hold value cn is obtained, the output data q(n) is ANDed with the last input data, and then output through the filtering unit 402 .
  • FIG. 7 is a timing diagram of a data filtering module after adding a NOR gate in the digital filter provided by the present application.
  • the processing unit 401 sequentially processes the input data x(0), x(1), . . . , x(n) according to the clock cycle CLK, and filters out other input data in the same clock cycle. Therefore, when the multiplier performs effective calculations, the output of the processing unit 401 according to the clock cycle CLK is a0, b1, ..., cn in sequence, and when the multiplier performs invalid calculations, the processing unit 401 passes the second filter mark m(n) Taking x(n) as a hold item makes the output of the processing unit 401 not 0.
  • the processing unit 401 outputs cn, so that the output data of the filtering unit 402 is the value of cn, which avoids inversion of signals output by non-calculation items when the multiplier performs invalid calculations, thereby reducing power consumption caused by inversion.
  • FIG. 8 is a schematic structural diagram of a digital filter provided by the present application.
  • the digital filter includes a first data filtering module 801 , a second data filtering module 802 , a multiplier 803 and a first adder 804 .
  • the input terminal of the multiplier 803 is connected to the output terminal of the first data filtering module 801
  • the output terminal of the multiplier 803 is connected to the input terminal of the first adder 804
  • the output terminal of the first adder 804 is connected to the input terminal thereof.
  • the structure and principle of the first data filtering module 801 are the same as those of the data filtering module provided in this application, and will not be repeated here.
  • the second data filtering module 802 may adopt an existing data filtering module.
  • the multiplier 803 may or may not perform calculations as required.
  • the first data filtering module 801 filters the target data from the input data in different clock cycles CLK, and filters out other input data to eliminate burrs between the input data and reduce power consumption; and
  • the first data filtering module 801 outputs the holding value cn, which avoids the inversion of the output of non-calculation items, so as to reduce the power consumption caused by the inversion.
  • FIG. 9 is another structural schematic diagram of the digital filter provided by the present application.
  • the digital filter includes multiple first data filtering modules 901 , multiple second data filtering modules 902 , multiple multipliers 903 , multiple first adders 904 and multiple second adders 905 .
  • the structure and principles of the data filtering module 901 are the same as those of the data filtering module provided in the present application example, and will not be repeated here.
  • Each first data filter module 901 corresponds to a multiplier 903, a first adder 904 and a second adder 905; each second data filter module 902 corresponds to a multiplier 903, a first adder 904 and a The second adder 905; the input end of the multiplier 903 is connected with the output end of the first data filtering module 901 and the second data filtering module 902, and the output end of the multiplier 903 is connected with the input end of the first adder 904; the first The output end of adder 904 is connected with its input end, to realize time division multiplexing, the output end of the first adder 904 is connected with the input end of the second adder 905 simultaneously; The first input end of the second adder 905 is connected with the first The output end of the adder 904 is connected, and the second input end of the second adder 905 is connected with the output ends of other second adders 905, that is, the output signal of the second adder 905 is connected to the output signal of the first adder 904 and another An
  • the digital filter also includes a delay module 906 for delaying the input data x(t).
  • the input terminal of the delay module 906 receives input data, and the output terminal of the delay module 906 is connected with the input terminal of the first data filtering module 901 and the input terminal of the next stage delay module 906 .
  • the delay module 906 is the last stage, the output terminal of the delay module 906 is only connected to the input terminal of the first data filtering module 901 .
  • Each input data corresponds to a delay module 906, and each delay module 906 can delay the corresponding input data according to the actual situation.
  • the present application does not limit the working principle and working mode of the delay module 906 , as long as it is the same as the existing delay module, and will not be introduced in detail here.
  • the digital filter provided in this embodiment can be applied to application scenarios such as video, audio, communication signal rate conversion, filter processing, etc., to complete up-sampling and down-sampling of digital signals, so as to realize various types that require a large number of multipliers Encryption Algorithm.
  • FIG. 10 is a flowchart of the digital filtering method provided in the present application. As shown in Fig. 4 and Fig. 10, the digital filtering method includes steps S1001 to S1002.
  • step S1001 correct n pieces of input data to be processed to obtain processed data, wherein the processed data includes uncorrected input data and corrected corrected data, and n is an integer greater than or equal to 2.
  • the input data is the digital code of the discrete signal to be processed. After the input data is corrected to the corrected data, no transitions will be sent at the input end of the filtering unit 402 , and it is easy to be filtered out by the filtering unit 402 .
  • the processed data includes an uncorrected input data, and at least one corrected corrected data.
  • the correction data may be a fixed value, which enables the filtering unit 402 to select the target data from the processed data without affecting the length of the target data.
  • the correction data can be 0 or other suitable values.
  • the n pieces of input data are corrected to obtain processed data, the processed data includes corrected data after correcting the input data, and also includes the input data itself. For example, if the processing data is the input data itself, the input data is the target data. In other words, within the preset clock cycle, only one input data remains unchanged, and the other input data is modified, which is beneficial for the filtering unit to perform filtering.
  • step S1002 target data is output based on the processed data, wherein the target data is uncorrected input data.
  • Target data is input data that has not been modified by the processing unit 401, ie the target data is one of the input data. After being filtered by the filtering unit 402, the target data is output. Other input data is modified by the processing unit 401 to a fixed value that is easy to be filtered, and the fixed value is easy to be filtered by the filtering unit 402, so the modified input data will be filtered by the filtering unit.
  • the required input data is retained, and other input data are modified into modified data that is easy to be filtered and does not cause jumps at the input end of the filtering unit 402 .
  • the input data is modified to 0 by the processing unit 401 , no transition will occur at the input terminal of the filter unit 402 , eliminating glitches and reducing power consumption caused by glitches.
  • a plurality of input data to be processed is corrected to obtain processed data, and then the filtering unit outputs the uncorrected input data in the processed data as target data, and other input data are corrected as corrected Data and corrected data are easily excluded by the filter unit, and the input terminal of the filter unit does not jump, eliminating burrs, thereby reducing the power consumption of the digital filter.
  • Perform correction processing on the n pieces of input data to be processed, and obtain the processed data includes: perform correction processing on the n pieces of input data to be processed based on the filter mark and the input data through an AND operation, and obtain the processed data, wherein the filter mark is the same as the input data tags corresponding to the filter criteria for the .
  • the input data is corrected by using the AND gate and the filter marks, wherein the filter marks m(0), m(1), ... m(n-1) are marks corresponding to the filter conditions of the input data, and the filter conditions Can be preset by the user.
  • each AND gate For example, set n AND gates, the first input terminal of each AND gate is respectively connected to the input data x(0), x(1), ..., x(n-1), and the second input terminal is respectively connected to the filter Mark m(0), m(1),...m(n-1), the output of each AND gate is the result of an AND operation of an input data and a filter mark, that is, the input data x(0) , x(1), ..., x(n-1) and the corresponding filter marks m(0), m(1), ... m(n-1) are ANDed to obtain n processed data.
  • the bit width of the filter flag can be the same as the bit width of the input data corresponding to the target data, and each bit of the filter flag corresponding to the target data is "1"; the bit width of the filter flag can be the bit width of the input data corresponding to the correction data Each bit of the filter flag corresponding to the same width and the correction data is "0".
  • each bit of the filter flag m(0) is "1"
  • Each bit of m(n-1) is "0".
  • the processed data obtained after the input data x(0) is ANDed with the filter mark m(0) is the input data x(0) itself, that is, a0, and since the bit width of the filter mark is the same as that of the corresponding input data , in the first clock cycle, the processed data keeps a0.
  • the processed data is 0, and since the bit width of the filter flag is the same as that of the corresponding input data, the processed data remains 0 in the first clock cycle. Therefore, the processed data includes a0 and n-1 0s. In the first clock cycle, the processed data corresponding to the input data x(0) keeps a0, and the input data x(1), x(2),..., The processing data corresponding to x(n-1) always remains 0.
  • the calculation results of the multiplier are used; but in some time periods, the calculation results of the multiplier are not used.
  • the digital filter does not perform data processing during the period of time when the calculation result of the multiplier is determined not to be used.
  • the filter marks may include a first filter mark and a second filter mark, and the second filter mark is obtained by ORing the 0th, 1st, 2nd, . . . , n-1th filter marks and then inverting them.
  • the n input data to be processed are corrected by AND operation to obtain the processed data; in the case where the multiplier does not perform calculations Next, based on the second filter flag and the input data, the n pieces of input data to be processed are corrected through an AND operation to obtain processed data.
  • the processed data is a hold value (for example, cn), which avoids the signal inversion of the output of the non-calculation items, thereby reducing the power consumption caused by the inversion.
  • the data filter and filtering method provided by this application can be used. If there is a signal inversion of the output of the non-calculation item in the digital filter, a digital filter with a NOR gate added to the processing unit can be used to avoid the inversion, thereby reducing the power consumption caused by the inversion.
  • the present application also provides an electronic device, including the digital filter provided by the present application, for correcting the input data to be processed.
  • the digital filter corrects a plurality of input data to be processed through the processing unit to obtain the processed data, and then the filtering unit outputs the uncorrected input data in the processed data as the target data, After the input data is corrected, there will be no transition when it arrives at the filter unit, and the burr is eliminated, thereby reducing the power consumption of the digital filter, that is, reducing the power consumption of the electronic device.
  • Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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Abstract

本申请公开一种数字滤波器、滤波方法及电子设备。所述数字滤波器包括数据过滤模块，数据过滤模块包括：处理单元，用于对n个待处理的输入数据进行修正处理，获得处理数据，其中，处理数据中包括未经修正的输入数据和修正后的修正数据，n为大于或等于2的整数；以及过滤单元，用于对处理数据进行过滤，获得目标数据，其中，目标数据为未经修正的输入数据。

Description

数字滤波器、滤波方法及电子设备 技术领域
本申请涉及数字电路设计技术领域，尤其涉及一种数字滤波器、滤波方法及电子设备。
背景技术
数字滤波器是数字信号处理系统中的基本组成模块。对于有时隙的数字滤波器而言，时分复用技术可以大大减少数字滤波器中乘法器的数量，从而减少数字滤波器的面积和功耗。然而，目前的数字滤波器仍不能有效降低功耗。
发明内容
本申请提出一种数字滤波器、滤波方法及电子设备，旨在降低功耗。
本申请实施例提供一种数字滤波器，包括数据过滤模块，所述数据过滤模块包括：处理单元，用于对n个待处理的输入数据进行修正处理，获得处理数据，其中，所述处理数据中包括未经修正的输入数据和修正后的修正数据，n为大于或等于2的整数；以及过滤单元，用于基于所述处理数据输出目标数据，其中，所述目标数据为未经修正的输入数据。
本申请实施例提供一种数字滤波方法，包括：对n个待处理的输入数据进行修正处理，获得处理数据，其中，所述处理数据包括未经修正的输入数据和修正后的修正数据，n为大于或等于2的整数；以及对所述处理数据进行过滤，获得目标数据，其中，所述目标数据为未经修正的输入数据。
本申请实施例提供了一种电子设备，包括根据本申请的数字滤波器，用于对待处理的输入数据进行处理。
附图说明
图1为数字滤波器的基本原理图；
图2为采用1:n时分复用技术的数字滤波器中乘法器和加法器的原理图；
图3为在有时分复用的数字滤波器中到达第二数据过滤模块的输入端的时序图；
图4为本申请提供的数字滤波器的结构示意图；
图5为本申请提供的数字滤波器的时序图；
图6为相关技术中数据过滤模块的时序图；
图7为本申请提供的数字滤波器中增加或非门后数据过滤模块的时序图；
图8为本申请提供的数字滤波器的结构示意图；
图9为本申请提供的数字滤波器的另一结构示意图；以及
图10为本申请提供的数字滤波方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本申请的技术方案，下面结合附图对本申请提供的服务器进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本申请透彻和完整，并将使本领域技术人员充分理解本申请的范围。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本申请。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
本文所述实施例可借助本申请的理想示意图而参考平面图和/ 或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。因此，实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不旨在是限制性的。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本申请的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
数字滤波器的基本原理是实现运算y(t)＝x(t)×h(n)，其中，x(t)表示输入数据，h(n)表示滤波器系数，y(t)表示输出数据，即，实现输入数据与滤波系数的卷积。图1为数字滤波器的基本原理图。如图1所示，Z-1表示输入数据的延迟项，
Figure PCTCN2022080839-appb-000001
表示乘法器，
Figure PCTCN2022080839-appb-000002
表示加法器，h 0、h 1、……、h n-1、h n表示滤波器系数。
由于乘法器占用数字滤波器较大的面积，因此，在有时隙的数字滤波器中，常采用时分复用技术来减少数字滤波器中乘法器的数量，以减少数字滤波器的面积。例如，时分复用比为1:n的数字滤波器可以将乘法器的数量减少至原来的1/n。
图2为采用1:n时分复用技术的数字滤波器中乘法器和加法器的原理图。如图2所示，数字滤波器包括多个时分复用模块210和多个第二加法器220，第二加法器220的输入端接收与其同级的时分复用模块210输出信号，以及下一级第二加法器220的输出信号，即，第二加法器220逐级相加。
每个时分复用模块210包括第一数据过滤模块201、第二数据过滤模块202、乘法器203以及第一加法器204。第一数据过滤模块201用于过滤滤波器系数，包括输入端和输出端，第一数据过滤模块201的输入端接收滤波器系数h(0)、h(1)、……、h(n-1)以及过滤条件sel，第一数据过滤模块201的输出端与乘法器203的第一输入端连接。第二数据过滤模块202用于过滤输入数据，包括输入端和输出端， 第二数据过滤模块202的输入端接收输入数据x(0)、x(1)、……、x(n-1)以及过滤条件sel，第二数据过滤模块202的输出端与乘法器203的第二输入端连接。乘法器203的第一输入端与第一数据过滤模块201的输出端连接，乘法器203的第二输入端与第二数据过滤模块202的输出端连接，乘法器203的输出端与第一加法器204的输入端连接，第一加法器204的输出端与输入端连接，用于将第一加法器204的反馈信号输入第一加法器204，用以时分复用。
第一数据过滤模块201和第二数据过滤模块202通过过滤条件sel分别过滤滤波器系数和输入数据，作为乘法器203的输入，以达到将乘法器的数量、体积减少为原来的1/n。
在实际使用过程中，输入第二数据过滤模块202的输入数据x(0)、x(1)、……、x(n-1)是不断变化的，而且输入数据的长度不同，因此，输入数据到达第二数据过滤模块202的输入端的时间不同，会在第二数据过滤模块202的输入端会产生毛刺，而且，有多少输入信号，在第二数据过滤模块202的输入端就有多少毛刺。
图3为在有时分复用的数字滤波器中到达第二数据过滤模块的输入端的时序图。如图3所示，由于输入数据x(0)、x(1)、……、x(n)的长度存在不同，达到第二数据过滤模块的时间不同，导致输入数据在第二数据过滤模块的输入端产生大量的毛刺，从而导致功耗增加。
为了消除在第二数据过滤模块的输入端的毛刺，本申请对上述数字滤波器中的数字过滤器(其包括数据过滤模块)进行了改进。数字过滤器接收多个输入数据，并输出一个目标数据，而且目标数据是多个输入数据中的部分数据，如一个或多个输入数据。
图4为本申请提供的数字滤波器的结构示意图。如图4所示，数字滤波器包括数据过滤模块41，用于过滤过滤输入数据。数据过滤模块41包括处理单元401和过滤单元402。
处理单元401用于对多个待处理的输入数据进行修正处理，获得处理数据，其中，处理数据包括未经修正的输入数据和修正后的修正数据。
输入数据是待处理的离散信号的数字代码。输入数据经过修正后，修正数据不影响其它输入数据(如目标数据)，不会在过滤单元402的输入端发送跳变，而且容易被过滤单元402过滤掉。处理数据包括一个未经修正的输入数据，和至少一个修正后的修正数据。修正数据可以为固定值，该固定值有利于使过滤单元402从处理数据选出目标数据，还不影响目标数据的长度。例如，修正数据为0或者其它适合的数值。
下面为了便于描述，将多个输入数据表述为n个输入数据，n为大于或等于2的整数。
在预设的时钟周期内，对n个输入数据进行修正处理，获得处理数据，处理包括对输入数据进行识别并修正，处理数据包括所要保留的输入数据，以及对输入数据修改后的修正数据。例如，输入数据被处理后，若仍为输入数据本身，则该输入数据为目标数据；若被修正，则该输入数据为即将被过滤掉的数据。换言之，在预设的时钟周期内，只有一个输入数据保持不变，其它的输入数据被修正处理，这样有利于过滤单元进行过滤。
过滤单元402用于对处理数据进行过滤，获得目标数据，其中，目标数据为未经修正的输入数据。
目标数据是未被处理单元401修正的输入数据，即，目标数据为输入数据之一。经过滤单元402过滤后，输出目标数据。其它的输入数据经处理单元401修正为容易被过滤的固定值，该固定值能够使过滤单元402从处理数据选出目标数据，而未被修正的输入数据不会被过滤单402元过滤掉。
本实施例中处理单元401和过滤单元402共同作用，将需要的输入数据保留，将其它输入数据修正为容易被过滤且不会在过滤单元402的输入端发生跳变的修正数据。例如，输入数据被处理单元401修改为0后，在过滤单元402的输入端不发生跳变，消除了毛刺，从而减少了功耗。
根据本申请提供的数字滤波器，通过处理单元对多个待处理的输入数据进行修正处理，获得处理数据，除目标数据外，将数据长度 不一致的其它输入数据均修改为修正数据，避免了输入数据长度不一致的影响，消除了毛刺，降低了数字滤波器的功耗，而且有利于过滤单元的过滤，方便选定目标数据。
处理单元401可以包括与门4011，与门4011的数量不少于输入数据的个数。与门4011的数量可以与输入数据的数量一致，每个与门4011的第一输入端输入一个输入数据，每个与门4011的第二输入端输入一个过滤标记，并且与门4011的输出端与过滤单元402的输入端连接。与门4011借助过滤标记过滤性地修改输入数据，使需要的输入数据维持不变，并将不需要的输入数据修改为修正数据。
过滤标记是与输入数据的过滤条件相对应的标记，过滤条件可以由用户预先设定。
例如，处理单元401包括n+1个与门4011，n+1个与门4011的第一输入端分别接入输入数据x(0)、x(1)、……、x(n)，n+1个与门4011的第二输入端分别接入过滤标记m(0)、m(1)、……m(n)，n+1个与门4011的输出端均与过滤单元402连接。输入数据x(0)、x(1)、……、x(n)和对应的过滤标记m(0)、m(1)、……m(n)经与门4011后，输出处理数据。
过滤标记的位宽可以与目标数据对应的输入数据的位宽相同，且目标数据对应的过滤标记的每个比特位为“1”；过滤标记的位宽可以与修正数据对应的输入数据的位宽相同且修正数据对应的过滤标记的每个比特位为“0”。
例如，当数字过滤器依据过滤条件sel将输入数据x(0)作为目标数据时，与输入数据x(0)对应的过滤标记m(0)的每个比特位为“1”，过滤标记m(0)的位宽与输入数据x(0)的位宽相同，换言之，过滤标记m(0)为输入数据x(0)位宽长度的“1”。输入数据x(1)、x(2)、……、x(n)对应的过滤标记m(1)、m(2)、……m(n)的每个比特位均为“0”，而且，过滤标记m(1)、m(2)、……m(n)的位宽与对应的输入数据据x(1)、x(2)、……、x(n)的位宽相同，换言之，过滤标记m(1)、m(2)、……m(n)分别为与之对应的输入数据据x(1)、x(2)、……、x(n)位宽长度的“0”。例如，过滤标记m(1)为输入数据x(1)位宽长 度的“0”，过滤标记m(2)为输入数据x(2)位宽长度的“0”，以此类推，过滤标记m(n-1)为输入数据x(n-1)位宽长度的“0”。
通过将过滤标记中每个比特位设置为“0”和“1”，目标数据对应的过滤标记的每个比特位设置为“1”，修正数据对应的过滤标记的每个比特位为“0”，这样除目标数据外，其它输入数据容易被过滤掉，即，除目标数据外，其它输入数据被修正为不会发生跳变修正数据，以消除其它输入数据产生的毛刺。
图5为本申请提供的数字滤波器的时序图。参阅图4和图5，输入数据x(0)和过滤标记m(0)经过与门4011进行与操作后获得输出数据q(0)，输入数据x(1)和过滤标记m(1)经过与门4011进行与操作后获得输出数据q(1)，输入数据x(2)和过滤标记m(2)经过与门4011进行与操作后获得输出数据q(2)，以此类推，输入数据x(n)和过滤标记m(n)经过与门4011进行与操作后获得输出数据q(n)。在图5中，将输入数据x(0)作为目标数据，过滤标记m(0)为输入数据x(0)位宽长度的“1”，因此，输出数据q(0)与目标数据x(0)相同，即a0，其它输入数据x(1)、x(2)、……、x(n)为被过滤掉的数据，对应的过滤标记m(1)、m(2)、……m(n)为“0”，输出数据q(1)、q(2)、……、q(n)为修正数据，即，0。将输出数据q(0)、q(1)、……、q(n)输入过滤单元402，由于修正数据为0，因此不会在过滤单元402的输入端造成毛刺，而且局部IR压降(电流和电阻引起的压降，翻转越多，IR压降越大)有极大的改善。
如图4所示，过滤单元402为或门4021，或门4021的输入端与与门4011的输出端连接，或门4021的输出端作为数据过滤模块41的输出端。例如，输出数据q(0)、q(1)、……、q(n)与或门4021的输入端连接，或门4021的输出端可以与乘法器连接。
根据本申请提供的数字滤波器，利用处理单元对多个待处理的输入数据进行修正处理，获得未经修正的输入数据和修正的固定数据，使修改后的固定值在过滤单元的输入端不发生跳变，再由过滤单元将未经修正的输入数据作为目标数据输出。另外，寄存器是将不同的输入数据寄存，待需要时输出，功耗远大于本申请的处理单元和过滤单 元，而且寄存器增加电路的处理延时，处理效率低。
在实际应用中，数据过滤模块将输出结果输出至乘法器，但乘法器有时不进行计算，即，属于非计算项输出，图6为相关技术中数据过滤模块的时序图。如图6所示，处理单元401按照时钟周期CLK依次处理输入数据x(0)、x(1)、……、x(n)，并将同一时钟周期内的其他输入数据修改为修正数据。因此，处理单元401按照时钟周期CLK的输出依次是a0、b1、……、cn，之后的某段时钟周期内数据过滤模块41的输出被置0来降低静态功耗。但是，将数据过滤模块41的输出置0容易导致非计算项输出的信号翻转，而翻转产生的功耗更大。
如图4所示，处理单元还可以包括或非门4012，或非门4012的输入端分别接入第0、第1、第2、……、第n-1个过滤标记，或非门4012的输出端与第n个与门4011的输入端连接，或非门4012的输出信号作为第n个与门4011的过滤标记。
例如，或非门4012设置有n个输入端，分别接入过滤标记m(0)、m(1)、……m(n-1)，或非门4012的输出端与第n个与门4011的输入端连接。
过滤标记可以包括第一过滤标记和第二过滤标记，而且第二过滤标记是将第0、第1、第2、……、第n-1个过滤标记进行或操作后取反获得。第一过滤标记采用现有的方式获得，本申请对此不作限定。
在乘法器进行计算的情况下，基于第一过滤标记、第二过滤标记和输入数据，通过与操作对n个待处理的输入数据进行修正处理，获得处理数据；在乘法器不进行计算的情况下，基于第二过滤标记和输入数据，通过与操作对n个待处理的输入数据进行修正处理，获得处理数据。
例如，在乘法器不进行计算的情况下，过滤标记m(0)、m(1)、……m(n-1)的每个比特位均为0，或非门4012的输出为1，将或非门4012的输出与输入数据x(n)进行与操作后，获得保持值cn，输出数据q(n)与最后一个输入数据进行与操作，然后经过过滤单元402输出。
图7为本申请提供的数字滤波器中增加或非门后数据过滤模块的时序图。如图7所示，处理单元401按照时钟周期CLK依次处理输入数据x(0)、x(1)、……、x(n)，并将同一时钟周期内将其他输入数据过滤掉。因此，在乘法器进行有效计算时，处理单元401按照时钟周期CLK的输出依次是a0、b1、……、cn，在乘法器进行无效计算时，处理单元401通过第二过滤标记m(n)将x(n)作为保持项，使得处理单元401的输出不是0。处理单元401输出cn，使得过滤单元402的输出data为cn值，避免了乘法器进行无效计算时，非计算项输出的信号翻转，从而降低了翻转导致的功耗。
图8为本申请提供的数字滤波器的结构示意图。如图8所示，数字滤波器包括第一数据过滤模块801、第二数据过滤模块802、乘法器803和第一加法器804。乘法器803的输入端与第一数据过滤模块801的输出端连接，乘法器803的输出端与第一加法器804的输入端连接，第一加法器804的输出端与其输入端连接。第一数据过滤模块801的结构和原理与本申请提供的数据过滤模块相同，在此不再赘述。第二数据过滤模块802可以采用现有的数据过滤模块。
如上文所述，乘法器803可以根据需要进行计算，也可以不进行计算。在乘法器803进行计算时，第一数据过滤模块801在不同的时钟周期CLK内从输入数据过滤目标数据，并将其它输入数据过滤掉，以消除输入数据之间的毛刺，降低功耗；而在乘法器803不进行计算时，第一数据过滤模块801输出保持值cn，避免了非计算项输出的翻转，以减少翻转导致的功耗。
图9为本申请提供的数字滤波器的另一结构示意图。如图9所示，数字滤波器包括多个第一数据过滤模块901、多个第二数据过滤模块902、多个乘法器903、多个第一加法器904和多个第二加法器905。数据过滤模块901的结构与和原理与本申请例提供的数据过滤模块相同，在此不再赘述。
每个第一数据过滤模块901对应一个乘法器903、一个第一加法器904和一个第二加法器905；每个第二数据过滤模块902对应一个乘法器903、一个第一加法器904和一个第二加法器905；乘法器903 的输入端与第一数据过滤模块901和第二数据过滤模块902的输出端连接，乘法器903的输出端与第一加法器904的输入端连接；第一加法器904的输出端与其输入端连接，以实现时分复用，第一加法器904的输出端同时与第二加法器905的输入端连接；第二加法器905的第一输入端与第一加法器904的输出端连接，第二加法器905的第二输入端与其它第二加法器905的输出端连接，即，第二加法器905同时接入第一加法器904的输出信号和另一第二加法器905的输出信号。第二数据过滤模块902用于过滤滤波器系数，可以采用现有的数据过滤模块，也可以采用本申请提供的数据过滤模块。
数字滤波器还包括延迟模块906，用于对输入数据x(t)进行延迟。延迟模块906的输入端接收输入数据，延迟模块906的输出端与第一数据过滤模块901的输入端以及下一级延迟模块906的输入端连接。当延迟模块906为最后一级时，延迟模块906的输出端仅与第一数据过滤模块901的输入端连接。
每个输入数据对应一个延迟模块906，每个延迟模块906可以根据实际情况对与之对应的输入数据进行延迟。本申请对延迟模块906的工作原理和工作方式不进行限定，与现有的延迟模块相同即可，在此不详细介绍。
需要说明的是，本实施例提供的数字滤波器可以应用于视频、音频、通讯信号速率变换、滤波处理等应用场景，完成数字信号的上采样和下采样，以实现各类需要大量乘法器的加密算法。
本申请还提供一种数字滤波方法，图10为本申请提供的数字滤波方法的流程图。如图4和图10所示，数字滤波方法包括步骤S1001至S1002。
在步骤S1001，对n个待处理的输入数据进行修正处理，获得处理数据，其中，处理数据中包括未经修正的输入数据和修正后的修正数据，n为大于或等于2的整数。
输入数据是待处理的离散信号的数字代码。输入数据修正为修正数据后，不会在过滤单元402的输入端发送跳变，而且容易被过滤单元402过滤掉。处理数据包括一个未经修正的输入数据，和至少一 个修正后的修正数据。修正数据可以为固定值，该固定值能够使过滤单元402从处理数据选出目标数据，还不影响目标数据的长度。例如，修正数据可以为0或者其它适合的数值。
在预设的时钟周期内，对n个输入数据进行修正处理，获得处理数据，处理数据包括对输入数据进行修正处理后的修正数据，还包括输入数据本身。例如，若处理数据为输入数据本身，则该输入数据即为目标数据。换言之，在预设的时钟周期内，只有一个输入数据保持不变，其它的输入数据被修正，这样有利于过滤单元进行过滤。
在步骤S1002，基于处理数据输出目标数据，其中，目标数据为未经修正的输入数据。
目标数据是未被处理单元401修改的输入数据，即，目标数据为输入数据之一。经过滤单元402过滤后，输出目标数据。其它的输入数据经处理单元401修改为容易被过滤的固定值，该固定值容易被过滤单元402过滤，因此修正后的输入数据会被过滤单元过滤掉。
本申请实施例将需要的输入数据保留，并且将其它输入数据修正为容易被过滤且不会在过滤单元402的输入端发生跳变的修正数据。例如，输入数据被处理单元401修改为0后，不会在过滤单元402的输入端发生跳变，消除了毛刺，从而减少毛刺导致的功耗。
根据本申请提供的数字滤波方法，对多个待处理的输入数据进行修正处理，获得处理数据，再由过滤单元将处理数据中未经修正的输入数据作为目标数据输出，其它输入数据修正为修正数据，修正数据容易被过滤单元排除掉，而且不会在过滤单元的输入端发生跳变，消除了毛刺，从而降低了数字滤波器的功耗。
对n个待处理的输入数据进行修正处理，获得处理数据包括：基于过滤标记和输入数据通过与操作对n个待处理的输入数据进行修正处理，获得处理数据，其中，过滤标记是与输入数据的过滤条件相对应的标记。
利用与门并通过过滤标记对输入数据进行修正处理，其中，过滤标记m(0)、m(1)、……m(n-1)是与输入数据的过滤条件相对应的标记，过滤条件可以由用户预先设定。
例如，设置n个与门，每个与门的第一输入端分别接入输入数据x(0)、x(1)、……、x(n-1)，第二输入端分别接入过滤标记m(0)、m(1)、……m(n-1)，每个与门的输出端为一个输入数据和一个过滤标记的与操作后的结果，即，输入数据x(0)、x(1)、……、x(n-1)和对应的过滤标记m(0)、m(1)、……m(n-1)经与操作后，得到n个处理数据。
过滤标记的位宽可以与目标数据对应的输入数据的位宽相同，且目标数据对应的过滤标记的每个比特位为“1”；过滤标记的位宽可以与修正数据对应的输入数据的位宽相同且修正数据对应的过滤标记的每个比特位为“0”。
例如，若根据过滤条件sel确定在第一时钟周期内过滤输入数据x(0)，那么过滤标记m(0)的每个比特位为“1”，过滤标记m(1)、m(2)、……m(n-1)的每个比特位为“0”。输入数据x(0)与过滤标记m(0)进行与操作后获得的处理数据是输入数据x(0)本身，即，a0，而且由于过滤标记的位宽与对应的输入数据的位宽相同，在第一时钟周期内，处理数据一直保持a0。输入数据x(1)、x(2)、……、x(n-1)与对应的过滤标记m(1)、m(2)、……m(n-1)进行与操作后获得的处理数据为0，而且由于过滤标记的位宽与对应的输入数据的位宽相同，在第一时钟周期内，处理数据一直保持0。因此，处理数据包括一个a0和n-1个0，在第一时钟周期内，输入数据x(0)对应的处理数据一直保持a0，输入数据x(1)、x(2)、……、x(n-1)对应的处理数据一直保持0。
在某些时间段，乘法器的计算结果被采用；但有些时间段，乘法器的计算结果不被采用。为了降低功耗，在确定不采用乘法器的计算结果的时间段，数字滤波器不进行数据处理。
过滤标记可以包括第一过滤标记和第二过滤标记，第二过滤标记是将第0、第1、第2、……、第n-1个过滤标记进行或操作后取反获得。
在乘法器进行计算的情况下，基于第一过滤标记、第二过滤标记和输入数据，通过与操作对n个待处理的输入数据进行修正处理， 获得处理数据；在乘法器不进行计算的情况下，基于第二过滤标记和输入数据，通过与操作对n个待处理的输入数据进行修正处理，获得处理数据。
在乘法器不进行计算的情况下，处理数据为保持值(例如，cn)，避免了非计算项输出的信号翻转，从而降低了翻转导致的功耗。
在使用数字滤波器及数字滤波方法进行滤波之前，需要判断数字滤波器中的乘法器是否能够进行时分复用，如果能够进行时分复用，则可以采用本申请提供的数据滤波器及滤波方法。如果数字滤波器存在非计算项输出的信号翻转，则可采用处理单元中增设或非门的数字滤波器，以避免翻转，从而降低翻转导致的功耗。
本申请还提供一种电子设备，包括本申请提供的数字滤波器，以对待处理的输入数据进行修正处理。
本申请实施例提供的电子设备，数字滤波器通过处理单元对多个待处理的输入数据进行修正处理，获得处理数据，再由过滤单元将处理数据中未经修正的输入数据作为目标数据输出，输入数据修正后到达过滤单元不会发生跳变，消除了毛刺，从而降低了数字滤波器的功耗，即降低了电子设备的功耗。
本领域普通技术人员可以理解，上文中所申请方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其它数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质 包括但不限于RAM、ROM、EEPROM、闪存或其它存储器技术、CD-ROM、数字多功能盘(DVD)或其它光盘存储、磁盒、磁带、磁盘存储或其它磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其它的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其它传输机制之类的调制数据信号中的其它数据，并且可包括任何信息递送介质。
本文已经申请了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其它实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本申请的范围的情况下，可进行各种形式和细节上的改变。

Claims (14)

  1. 一种数字滤波器，包括数据过滤模块，所述数据过滤模块包括：
    处理单元，用于对n个待处理的输入数据进行修正处理，获得处理数据，其中，所述处理数据包括未经修正的输入数据和修正后的修正数据，n为大于或等于2的整数；以及
    过滤单元，用于对所述处理数据进行过滤，获得目标数据，其中，所述目标数据为所述未经修正的输入数据。
  2. 根据权利要求1所述的数字滤波器，其中，所述处理单元包括：
    n个与门，所述n个与门中的每个与门的第一输入端输入所述n个待处理的输入数据中的一个输入数据，所述与门的第二输入端输入一个过滤标记，其中，所述过滤标记是与所述n个待处理的输入数据的过滤条件相对应的标记，并且所述与门的输出端与所述过滤单元的输入端连接。
  3. 根据权利要求2所述的数字滤波器，其中，所述过滤标记的位宽与所述目标数据对应的输入数据的位宽相同，且所述目标数据对应的过滤标记的每个比特位为1，并且
    所述过滤标记的位宽与所述修正数据对应的输入数据的位宽相同，且所述修正数据对应的过滤标记的每个比特位为0。
  4. 根据权利要求2所述的数字滤波器，其中，所述处理单元还包括：
    或非门，所述或非门的输入端接入第1、第2、……、第n-1个过滤标记，所述或非门的输出端与所述n个与门中的第n个与门的输入端连接，所述或非门的输出信号作为输入至所述第n个与门的过滤标记。
  5. 根据权利要求2所述的数字滤波器，其中，所述过滤单元包括或门，所述或门的输入端与所述n个与门的输出端连接，所述或门的输出端作为所述数据过滤模块的输出端。
  6. 根据权利要求1至5中任一所述的数字滤波器，还包括乘法器和第一加法器，
    其中，所述乘法器的输入端与所述数据过滤模块的输出端连接，所述乘法器的输出端与所述第一加法器的输入端连接，并且所述第一加法器的输出端与其输入端连接。
  7. 根据权利要求6所述的数字滤波器，还包括第二加法器，
    其中，所述第二加法器的输入端与所述第一加法器的输出端连接，所述第二加法器的输出端作为所述数字滤波器的输出端。
  8. 根据权利要求1至7中任一所述的数字滤波器，还包括：
    延迟模块，用于对所述n个待处理的输入数据进行延迟处理，所述延迟模块的输入端接收所述n个待处理的输入数据，所述延迟模块的输出端与所述数据过滤模块的输入端以及下一级延迟模块的输入端连接。
  9. 一种数字滤波方法，包括：
    对n个待处理的输入数据进行修正处理，获得处理数据，其中，所述处理数据包括未经修正的输入数据和修正后的修正数据，n为大于或等于2的整数；以及
    对所述处理数据进行过滤，获得目标数据，其中，所述目标数据为所述未经修正的输入数据。
  10. 根据权利要求9所述的数字滤波方法，其中，对所述n个待处理的输入数据进行修正处理，获得处理数据包括：
    基于n个过滤标记和所述n个待处理的输入数据，通过与操作对所述n个待处理的输入数据进行修正处理，获得处理数据，其中，所述n个过滤标记是与所述n个待处理的输入数据的过滤条件相对应的标记。
  11. 根据权利要求10所述的数字滤波方法，其中，所述过滤标记的位宽与所述目标数据对应的输入数据的位宽相同，且所述目标数据对应的过滤标记的每个比特位为1，并且
    所述过滤标记的位宽与所述修正数据对应的输入数据的位宽相同，且所述修正数据对应的过滤标记的每个比特位为0。
  12. 根据权利要求10所述的数字滤波方法，其中，所述过滤标记包括第一过滤标记和第二过滤标记，并且将第1、第2、……、第n-1个过滤标记进行或操作后取反获得所述第二过滤标记。
  13. 根据权利要求12所述的数字滤波方法，其中，基于所述n个过滤标记和所述n个待处理的输入数据，通过与操作对所述n个待处理的输入数据进行修正处理，获得处理数据包括：
    在乘法器进行计算的情况下，基于所述第一过滤标记、所述第二过滤标记和所述n个待处理的输入数据，通过与操作对所述n个待处理的输入数据进行修正处理，获得处理数据；
    在乘法器不进行计算的情况下，基于所述第二过滤标记和所述n个待处理的输入数据，通过与操作对所述n个待处理的输入数据进行修正处理，获得处理数据。
  14. 一种电子设备，包括权利要求1至8中任意一项所述的数字滤波器，用于对待处理的输入数据进行处理。
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CN1397935A (zh) * 2001-07-18 2003-02-19 松下电器产业株式会社 光盘重放装置
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Publication number Priority date Publication date Assignee Title
JPH0879012A (ja) * 1994-08-31 1996-03-22 Oki Electric Ind Co Ltd ディジタルフィルタ
CN1309467A (zh) * 1999-12-28 2001-08-22 日本电气株式会社 可变增益数字滤波器
CN1397935A (zh) * 2001-07-18 2003-02-19 松下电器产业株式会社 光盘重放装置
CN101326715A (zh) * 2005-12-16 2008-12-17 松下电器产业株式会社 数字滤波器

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