WO2023050250A1 - 薄膜晶体管及其制造方法、显示基板以及显示装置 - Google Patents

薄膜晶体管及其制造方法、显示基板以及显示装置 Download PDF

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WO2023050250A1
WO2023050250A1 PCT/CN2021/122026 CN2021122026W WO2023050250A1 WO 2023050250 A1 WO2023050250 A1 WO 2023050250A1 CN 2021122026 W CN2021122026 W CN 2021122026W WO 2023050250 A1 WO2023050250 A1 WO 2023050250A1
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layer
gate
base substrate
barrier layer
thin film
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PCT/CN2021/122026
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English (en)
French (fr)
Inventor
屈财玉
郝艳军
张慧娟
樊宜冰
陈登云
宋尊庆
李栋
刘政
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京东方科技集团股份有限公司
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Priority to US17/789,284 priority Critical patent/US20230189565A1/en
Priority to PCT/CN2021/122026 priority patent/WO2023050250A1/zh
Priority to CN202180002777.XA priority patent/CN116210087A/zh
Publication of WO2023050250A1 publication Critical patent/WO2023050250A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a thin film transistor, a manufacturing method thereof, a display substrate, and a display device.
  • the screen display of medium and large-sized display products is uneven.
  • the gate line With the growth of the gate line, the gate line itself has resistance, and the delay of the scanning signal will lead to insufficient gate turn-on time, resulting in poor display effect.
  • the brightness is not uniform.
  • the middle of the screen is relative to the edges on both sides of the screen.
  • the middle of the screen is cyan, and the edges on both sides of the screen are purple, which seriously affects the display effect.
  • a thin film transistor disposed on a substrate, wherein the thin film transistor includes: a first active layer disposed on one side of the substrate; a first gate disposed on the substrate The side of the first active layer away from the base substrate; the first insulating layer is arranged on the side of the first grid far away from the base substrate; the source and the drain are arranged on the The first insulating layer is away from the side of the substrate, and the source and drain are electrically connected to the first active layer; wherein, the first gate includes a stacked structure, and the stacked The structure includes: a first conductive layer; and a first barrier layer disposed on a side of the first conductive layer away from the base substrate, and the first barrier layer is connected to the side of the base substrate away from the base substrate.
  • the first insulating layer is in direct contact with a side close to the substrate; wherein the first barrier layer includes TiN x1 , where 0 ⁇ x1 ⁇ 0.2, and x1 is the molar ratio of N/Ti
  • the stacked structure of the first gate further includes: a second barrier layer disposed between the first conductive layer and the first barrier layer, the second barrier layer Including TiN x2 , wherein, 0.1 ⁇ x2 ⁇ 0.8, x2 is the molar ratio of N/Ti.
  • the adhesive force between the material of the first barrier layer and the material of the first insulating layer is greater than that between the material of the second barrier layer and the material of the first insulating layer of adhesive force.
  • the first barrier layer has a first grain size
  • the second barrier layer has a second grain size
  • the first grain size is smaller than the second grain size
  • the first barrier layer has a thickness ranging from 30 to 150 nanometers; and/or, the second barrier layer has a thickness ranging from 30 to 150 nanometers.
  • the sum of the thickness of the first barrier layer and the thickness of the second barrier layer is in the range of 30 nm to 150 nm.
  • the stacked structure of the first gate further includes: a third barrier layer disposed between the first conductive layer and the base substrate, the third barrier layer includes TiN x3 , wherein, 0 ⁇ x3 ⁇ 0.2, and x3 is the molar ratio of N/Ti.
  • the thin film transistor further includes a second gate, wherein the second gate is disposed between the first active layer and the base substrate; the second gate
  • the electrode includes a stacked structure, and the stacked structure of the second gate is the same as that of the first gate.
  • the first conductive layer includes aluminum alloy material.
  • a method for manufacturing a thin film transistor including: forming a first active layer on a base substrate; forming a first active layer on a side of the first active layer away from the base substrate.
  • a gate forming a first insulating layer on a side of the first gate away from the base substrate; forming a source and a drain on a side of the first insulating layer away from the base substrate, The source and the drain are electrically connected to the first active layer;
  • forming the first gate includes: forming a first gate on a side of the first active layer away from the base substrate a conductive layer; and a first barrier layer is formed on a side of the first conductive layer away from the base substrate, and a side of the first barrier layer away from the base substrate is close to the first insulating layer
  • the first barrier layer includes TiN x1 , where 0 ⁇ x1 ⁇ 0.2, and x1 is the molar ratio of N/Ti
  • the manufacturing method of the thin film transistor further includes: before forming the first active layer, forming a second gate on the base substrate.
  • a display substrate including: a base substrate; and a first transistor disposed on the base substrate, wherein the first transistor is the thin film transistor as described above.
  • the display substrate further includes a capacitor disposed on the base substrate; wherein the capacitor includes a first capacitor electrode and a second capacitor electrode, and the first capacitor electrode and the The first gate is located on the same layer, the first capacitor electrode has a stacked structure, and the stacked structure of the first capacitor electrode is the same as that of the first gate.
  • the second capacitive electrode is electrically connected to the first active layer, the second capacitive electrode has a laminated structure, and the laminated structure of the second capacitive electrode is connected to the first active layer.
  • the stacked structure of a gate is the same.
  • the display substrate further includes a second transistor disposed on the base substrate, and the second transistor includes: a third gate, disposed on one side of the base substrate; Two insulating layers, arranged on the side of the third gate away from the base substrate; the second active layer, arranged on the side of the second insulating layer away from the base substrate; the third The gate is located at the same layer as the first gate, and the third gate has the same stacked structure as the first gate.
  • the second transistor further includes: a fourth gate, disposed on a side of the second active layer away from the base substrate, the fourth gate has a The same stacked structure as the first gate.
  • the first active layer includes a polysilicon material
  • the second active layer includes a semiconductor oxide material
  • the display substrate further includes a shielding layer, wherein the shielding layer is disposed between the first active layer of the first transistor and the base substrate.
  • a display device including the above-mentioned display substrate.
  • Fig. 1a schematically shows a schematic cross-sectional structure diagram of a thin film transistor according to an exemplary embodiment of the present disclosure
  • Fig. 1b schematically shows a cross-sectional schematic diagram of a thin film transistor according to another exemplary embodiment of the present disclosure
  • Fig. 2a schematically shows a cross-sectional schematic diagram of a first gate according to an exemplary embodiment of the present disclosure
  • Fig. 2b schematically shows a cross-sectional schematic diagram of a first gate according to another exemplary embodiment of the present disclosure
  • Fig. 2c schematically shows a cross-sectional schematic diagram of a first gate according to yet another exemplary embodiment of the present disclosure
  • Fig. 3a schematically shows a schematic diagram of adhering a first insulating layer on a first barrier layer according to an embodiment of the present disclosure
  • Fig. 3b schematically shows a schematic diagram of splitting of the first barrier layer and the first insulating layer when the N content of the first barrier layer material is high according to an embodiment of the present disclosure
  • Fig. 3c schematically shows a schematic diagram of the bonding of the first barrier layer and the first insulating layer when the N content of the first barrier layer material is low according to an embodiment of the present disclosure
  • Fig. 4a schematically shows a schematic diagram of the grain size in the first barrier layer according to an embodiment of the present disclosure
  • Fig. 4b schematically shows a schematic diagram of the grain size in the second barrier layer according to an embodiment of the present disclosure
  • FIG. 4c schematically shows a schematic diagram of the performance of the barrier layer material in resisting the etching of the ILD dielectric layer etching solution according to an embodiment of the present disclosure
  • Fig. 4d schematically shows a schematic diagram of the performance of the barrier layer material in resisting BOE etchant etching according to an embodiment of the present disclosure
  • Fig. 4e schematically shows a cross-sectional view of a first gate with a third barrier layer according to an exemplary embodiment of the present disclosure
  • FIG. 5 schematically shows a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 6 schematically shows the specific process of the thin film transistor in step S2 according to an exemplary embodiment of the present disclosure
  • FIG. 7a schematically shows a schematic diagram of the interface structure of a thin film transistor in step S1 according to an exemplary embodiment of the present disclosure
  • Fig. 7b schematically shows a schematic diagram of the interface structure of the thin film transistor in step S2 according to an exemplary embodiment of the present disclosure
  • FIG. 7c schematically shows a schematic diagram of the interface structure of the thin film transistor in step S3 according to an exemplary embodiment of the present disclosure
  • Fig. 7d schematically shows a schematic diagram of the interface structure of the thin film transistor in step S4 according to an exemplary embodiment of the present disclosure
  • FIG. 8 schematically shows a schematic structural view of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 9 schematically shows a schematic structural view of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 10 schematically shows a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.
  • connection may refer to a physical connection, an electrical connection, a communicative connection, and/or a fluid connection.
  • the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a wider sense.
  • the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as meaning only X, only Y, only Z, or Any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • first means for describing various components, components, elements, regions, layers and/or sections
  • these components, components, elements, regions, layers and/or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, component, element, region, layer and/or section from another.
  • a first component, first member, first element, first region, first layer, and/or first portion discussed below could be termed a second component, second member, second element, second region , the second layer and/or the second portion, without departing from the teachings of the present disclosure.
  • spatially relative terms such as “upper,” “lower,” “left,” “right,” etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. relation. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features.
  • the expression "adhesive force” can indicate the magnitude of the bonding force between two contacting material layers.
  • the contact between materials can be different material layers formed by different processes, or it can be For layers of different materials formed by the same process, the adhesive force represents the bonding strength between the two materials. The greater the bonding strength, the greater the bonding force. Conversely, the smaller the bonding strength, the smaller the bonding force.
  • Fig. 1a schematically shows a schematic cross-sectional structure diagram of a thin film transistor according to an exemplary embodiment of the present disclosure.
  • Fig. 1b schematically shows a schematic cross-sectional structure diagram of a thin film transistor according to another exemplary embodiment of the present disclosure.
  • the thin film transistor is disposed on the upper side of the substrate 10 , wherein the thin film transistor includes a first active layer 11 , a first gate 12 , a first insulating layer 13 , a source and a drain 14 .
  • the first active layer 11 is disposed on one side of the base substrate 10 .
  • the film layer structure 15 on the base substrate 10 may be a polyimide film layer or a buffer film layer.
  • the first active layer 11 can be disposed on the polyimide film layer, or on the buffer film layer.
  • the film structure 15 may be a single-layer film structure, or a multi-layer film structure.
  • a first gate insulating layer 16 is disposed on the first active layer 11 .
  • the material of the first gate insulating layer 16 can be, for example, silicon oxide or silicon nitride, or a double-layer structure composed of silicon oxide film and silicon nitride film, etc. can be used.
  • the first gate 12 is disposed on a side of the first active layer 11 away from the base substrate 10 .
  • it is provided on the first gate insulating layer 16 .
  • the first insulating layer 13 is disposed on a side of the first gate 12 away from the base substrate 10 .
  • the first insulating layer 13 is disposed on a side of the first gate insulating layer 16 away from the base substrate 10 , and the first insulating layer 13 is disposed covering the first gate 12 .
  • the source and drain 14 are disposed on the side of the first insulating layer 13 away from the base substrate 10 , and the source and drain 14 are electrically connected to the first active layer 11 .
  • an interlayer insulating layer 17 is disposed on the side of the first insulating layer 13 away from the base substrate 10, the source and drain 14 are disposed on the interlayer insulating layer 17, and part of the source and drain 14 pass through through the interlayer insulating layer 17 , the first insulating layer 13 and the first gate insulating layer 16 , and is electrically connected to the active layer 11 .
  • the thin film transistor may further include a second gate 18 disposed between the first active layer 11 and the base substrate 10 .
  • a second gate 18 disposed between the first active layer 11 and the base substrate 10 .
  • it is arranged between the film layer structure 15 and the base substrate 10 .
  • a multi-layer film structure is provided on the source electrode and the drain electrode 14 for encapsulating the thin film transistor.
  • it may include a flat layer 19 , a pixel defining layer 20 , a light emitting layer 21 , a cathode 22 , an encapsulation layer 23 and an anode 24 .
  • the encapsulation layer 23 may include a plurality of inorganic thin film layers.
  • FIG. 2a to 2c schematically illustrate the schematic cross-sectional structure of the first gate according to an exemplary embodiment of the present disclosure.
  • the first gate 12 has a stacked structure including a first conductive layer 121 and a first barrier layer 122 .
  • the first conductive layer 121 is disposed on a side of the first active layer 11 away from the base substrate 10 , specifically, the first conductive layer 121 is disposed on a side of the first gate insulating layer 16 far away from the base substrate 10 . side.
  • the first barrier layer 122 is disposed on a side of the first conductive layer 121 away from the base substrate 10 , that is, disposed on the upper side of the first conductive layer 121 .
  • the material of the first conductive layer 121 can be aluminum or aluminum alloy, which has good electrical conductivity on the one hand, and lower Young's modulus on the other hand.
  • the aluminum alloy may include at least one of the following elements: Ce, Zr, Sc, Mn, Ni, La.
  • Mo is used to make the gate metal layer, and the resistivity of Mo is as high as 17.6 micro-ohm cm.
  • the resistivity of the first conductive layer is 4.2 micro-ohm. cm, much smaller than the resistivity of Mo, with good electrical conductivity.
  • the use of aluminum and aluminum alloy can make the grid line of the first grid have lower resistance, and the delay time of the scanning signal is shorter, which can ensure the display effect of the display substrate.
  • the low-resistance first gate material is made of aluminum or an aluminum alloy material, and its Young's modulus is 90 GPa, which is lower than that of the gate Mo (Young's modulus is 137 GPa) in the related art.
  • the bending resistance is better. In the bending test with a radius of 3 mm, the strain is 5.97E-03.
  • the Mo metal wire is completely broken after being bent 2300 times.
  • aluminum or aluminum alloy materials are not broken after being bent 100,000 times, and the resistance value is almost unchanged, so the effect as a folding product is better.
  • the first barrier layer 122 includes TiN x1 , where 0 ⁇ x1 ⁇ 0.2, x1 is the molar ratio of N/Ti, preferably 0.1 ⁇ x1 ⁇ 0.15.
  • the first barrier layer 122 is used for bonding with the first insulating layer 13 to prevent peeling between the first barrier layer 122 and the first insulating layer 13 .
  • the content of the N element and the Ti element are different, resulting in a different adhesion between the material of the first barrier layer and the inorganic layer SiN, and the molar ratio M of the content of N and Ti in the first barrier layer 122 is in the range of 0 ⁇ M ⁇ 0.2 Better adhesion between the first barrier layer 122 and the first insulating layer 13 can be achieved.
  • the content of N in the first barrier layer 122 of the present disclosure is set to a relatively low range, on the one hand, it has better adhesion performance with the first insulating layer 13, on the other hand, it inhibits the first
  • the occurrence of surface defects in the conductive layer 121 during the manufacturing process for example, suppresses the occurrence of protrusions on the surface of the first conductive layer 121, and at the same time suppresses the damage of the etchant to the surface of the metal lines.
  • the first barrier layer 122 can effectively prevent the etchant from damaging the surface of the metal line during the manufacturing process of the thin film transistor. For example, it can suppress the damage of BOE etchant and ILD dielectric layer etchant to the surface of metal lines.
  • the stacked structure of the first gate 12 may further include a second barrier layer 123, wherein the second barrier layer 123 is disposed between the first conductive layer 121 and the first barrier layer 122, and the second barrier layer 123 Including TiN x2 , where 0.1 ⁇ x2 ⁇ 0.8, x2 is the molar ratio of N/Ti, x2 is preferably 0.5 ⁇ x2 ⁇ 0.8.
  • both the first barrier layer 122 and the second barrier layer 123 are made of titanium nitride, and the content of N element in titanium nitride has a great influence on its performance, specifically including titanium nitride The ability to inhibit the etching resistance of the etchant, and the size of the adhesion between titanium nitride and other materials.
  • the effect of the content of N element in titanium nitride on its performance is not a linear relationship.
  • the content of N element when the content of N element is low, its ability to resist BOE etching solution or ILD dielectric layer etching solution is high, and when the content of N element is 0, it can resist BOE etching solution or ILD dielectric layer etching
  • the etching ability of the etching solution is weak. That is, the content of N element needs to be kept in a low range, so as to achieve a relatively excellent ability to resist etching by etching solution.
  • the adhesive force between the material of the first barrier layer 122 and the material of the first insulating layer 13 is greater than the adhesive force between the material of the second barrier layer 123 and the material of the first insulating layer 13 .
  • Fig. 3a schematically shows a schematic diagram of adhering a first insulating layer on a first barrier layer according to an embodiment of the present disclosure.
  • Titanium nitride with a lower N content in the material of the first barrier layer has higher adhesion between titanium nitride with a lower N content and the material of the first insulating layer 13 than titanium nitride with a higher N content force.
  • TiN x1 has higher adhesion than TiN x2 , that is, TiN x1 can better adhere to the first insulating layer 13 .
  • FIG. 3 a when the value of x1 is 0.15, the adhesion between the first barrier layer 122 comprising TiN 0.15 and the first insulating layer 13 is better. After laying the first insulating layer 13 on the gate material 12, no peeling occurs.
  • FIG. 3 a when the value of x1 is 0.15, the adhesion between the first barrier layer 122 comprising TiN 0.15 and the first insulating layer 13 is better. After laying the first insulating layer 13 on the gate material 12, no peeling occurs.
  • FIG. 3 a when the value of x1 is 0.
  • the adhesion between the first barrier layer 122 and the first insulating layer can be improved by using titanium nitride with a low N content as the material.
  • the N content in the material of the second barrier layer is higher than that of the material of the first barrier layer, therefore, the adhesive force between the material of the second barrier layer 123 and the material of the first insulating layer 13 is smaller than that of the first barrier layer.
  • the adhesive force between the material of 122 and the material of the first insulating layer 13 is smaller than that of the first barrier layer.
  • titanium nitride with a higher N content can better suppress defects in the first conductive layer 121 during the manufacturing process on the first conductive layer 121 . That is, the material of the second barrier layer 123 has better performance in suppressing defects of the first conductive layer 121 than the material of the first barrier layer 122 .
  • the material of the first barrier layer 122 has better adhesive performance in terms of bonding with the first insulating layer 13 .
  • Fig. 3b schematically shows a schematic diagram of splitting of the first barrier layer and the first insulating layer when the N content of the material of the first barrier layer is high according to an embodiment of the present disclosure.
  • Fig. 3c schematically shows a schematic diagram of the bonding of the first barrier layer and the first insulating layer when the N content of the first barrier layer material is low according to an embodiment of the present disclosure.
  • a second barrier layer is introduced here , and set the N content of the second barrier layer higher than that of the first barrier layer.
  • a second barrier layer is provided between the first barrier layer and the first insulating layer, on the one hand to prevent the formation of cracks between the first barrier layer and the first insulating layer, and on the other hand to prevent the formation of the first conductive layer Manufacturing defects appear on the surface. As shown in FIG. 3c, no cracks occur between the first barrier layer and the first insulating layer, and no defects appear on the surface of the first conductive layer.
  • disposing the first barrier layer 122 on the first conductive layer 121 improves the bonding state between the first gate 12 and the first insulating layer 13 and prevents the first gate 12 from contacting the first insulating layer 13 There is separation between them.
  • disposing the second barrier layer 123 between the first conductive layer 121 and the first barrier layer 122 can make up for the deficiency of the first barrier layer 122 in suppressing surface defects of the first conductive layer 121 .
  • Fig. 4a schematically shows a schematic diagram of the grain size in the first barrier layer according to an embodiment of the present disclosure.
  • Fig. 4b schematically shows a schematic diagram of the grain size in the second barrier layer according to an embodiment of the present disclosure.
  • the material of the first barrier layer 122 is titanium nitride with low nitrogen content, such as TiN 0.15 , which has better adhesion to the first insulating layer than titanium nitride with high nitrogen content.
  • the material of the first barrier layer 122 has finer grains, such as the enlarged area in box A, its grain size is smaller, and the grain size distribution is in the range of 100 nm to 200 nm, and the fine grains It has more excellent etch resistance in terms of etch resistance.
  • the material of the second barrier layer 123 is titanium nitride with a higher nitrogen content, such as TiN 0.5 , which has a better effect on defects in the first conductive layer than titanium nitride with a low nitrogen content. inhibition.
  • the material of the second barrier layer 123 has finer and larger grains, such as the enlarged area in box B, the grain size is relatively large, and the grain size distribution is in the range of 300 nm to 500 nm, and the coarse grain size Compared with fine grains, grains have relatively poor etch resistance in terms of etch resistance.
  • Fig. 4c schematically shows the performance of the barrier layer material in resisting etching by an etchant for the ILD dielectric layer according to an embodiment of the present disclosure.
  • titanium nitrides with different nitrogen contents have different etching resistance properties.
  • the materials represented by (a)-(f) are respectively without barrier layer (a), with barrier layer Ti (b), with barrier layer TiN 0.15 (c), with barrier layer TiN 0.3 (d), comprising the barrier layer TiN 0.5 (e), comprising the barrier layer TiN 0.9 (f).
  • Fig. 4d schematically shows the performance of the barrier layer material in resisting etching by BOE etching solution according to an embodiment of the present disclosure.
  • the performance of resisting the etching of BOE etching solution is also related to the nitrogen content of titanium nitride.
  • the materials represented by (a)-(d) do not contain the barrier layer (a) , containing the barrier layer Ti(b), containing the barrier layer TiN 0.5 (c), containing the barrier layer TiN 0.9 (d), the nitrogen content of titanium nitride increases sequentially. It can be seen from Figure 4d that the lower nitrogen content has more excellent corrosion resistance. Specifically, when the barrier layer TiN 0.5 (c) is included, the remaining unetched thickness is 47 nanometers, and its surface is flat.
  • the remaining unetched thickness is 20 nanometers, and the surface has an uneven structure caused by etching. Therefore, when the N content is 0.5, it can effectively block the corrosion of the BOE corrosion solution. Moreover, the etched surface has a relatively smooth plane, and when other film structures are formed on the surface, it has lower resistance. Therefore, in order to make the surface to be etched have a relatively smooth plane and improve the etching resistance, a barrier layer material with a lower N content can be selected.
  • the thickness of the first barrier layer 122 ranges from 30 to 150 nm, preferably 100 to 120 nm.
  • the thickness of the second barrier layer 123 ranges from 30 nm to 150 nm, preferably from 30 nm to 50 nm.
  • the sum of the thickness of the first barrier layer 122 and the thickness of the second barrier layer 123 is in the range of 30 nm to 150 nm. That is, the sum of the thicknesses between the first barrier layer 122 and the second barrier layer 123 satisfies a set range, for example, the sum of the thicknesses is 50 nanometers, or 100 nanometers, and so on. It can be adjusted according to actual needs.
  • the stacked structure of the first gate 12 further includes a third barrier layer 124, which is disposed between the first conductive layer 121 and the base substrate 10 .
  • the third barrier layer 124 is disposed on the first gate insulating layer 16 , and the upper side of the third barrier layer 124 is the first conductive layer 121 .
  • the material of the third barrier layer 124 includes TiN x3 , wherein 0 ⁇ x3 ⁇ 0.2, preferably 0.1 ⁇ x3 ⁇ 0.15.
  • the conductive layer of the first gate 12 may also be in contact with the first active layer.
  • the third barrier layer 124 can prevent the contact between the first conductive layer 121 of the first gate 12 and the active layer from co-dissolution.
  • Fig. 4e schematically shows a cross-sectional view of a first gate with a third barrier layer according to an exemplary embodiment of the present disclosure.
  • the first barrier layer in this embodiment includes TiN 0.15
  • the first conductive layer is aluminum alloy
  • the second barrier layer is TiN 0.5
  • the third barrier layer is TiN 0.15 .
  • the first gate with the stacked structure has a higher yield rate during production.
  • the third barrier layer 124 by setting the third barrier layer 124, on the one hand, prevent the high-temperature aluminum alloy (that is, the first conductive layer) from producing bumps (hillock) to damage the underlying film layer;
  • the high N content causes peeling with the inorganic layer, reducing the probability of defects in the manufacturing process.
  • the thickness of the third barrier layer 124 is between 30 nm and 150 nm, preferably between 30 nm and 50 nm.
  • the first gate structure adopts the above-mentioned stacked structure, which has lower resistance.
  • the first gate structure with low resistance includes two layers, an Al alloy close to the substrate Material layer and TiN 0.15 layer.
  • the low-resistance first gate structure includes four layers, which are a TiN 0.15 layer, an Al alloy material layer, a TiN 0.5 layer, and a TiN 0 layer in sequence.
  • the second gate 18 also has a stacked structure, and the stacked structure of the second gate 18 is the same as that of the first gate 12 .
  • the stacked structure of the second gate 18 may include a first conductive layer, a first barrier layer, and one or more of the second barrier layer and the third barrier layer.
  • FIG. 5 schematically shows a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 6 schematically shows the specific process of the thin film transistor in step S2 according to an exemplary embodiment of the present disclosure.
  • the manufacturing method of the thin film transistor according to the embodiment of the present disclosure includes steps S01 to S05 .
  • Fig. 7a schematically shows the interface structure of the thin film transistor in step S1 according to an exemplary embodiment of the present disclosure.
  • step S1 as shown in FIG. 5 and FIG. 7 a , a first active layer 11 is formed on the base substrate 10 .
  • the base substrate 10 for example, a glass substrate
  • the film layer structure 15 is formed on the base substrate 10, for example, a double-layer PI glue is coated on the base substrate 10, and heated at 300-400° C.
  • a PI thin film of about 10 um is formed to form a PI film layer 151 .
  • a buffer layer 152 is deposited by plasma enhanced chemical vapor deposition (PECVD) (the buffer layer is a double-layer structure SiN x /SiO 2 thin film), first depositing a silicon nitride layer of 50-300nm, and then depositing a silicon dioxide layer of 100-300nm. Afterwards, a 40-50 nm amorphous silicon layer is deposited as required. After the deposition of the amorphous silicon layer is completed, the amorphous silicon layer is subjected to heat treatment at a temperature of 400° C. for 0.5 ⁇ 3 hours. Then, the excimer laser annealing (ELA) process is performed on the amorphous silicon region at the same time, the polysilicon is patterned to form a channel, Vth Doping is performed, and finally the first active layer 11 is formed.
  • PECVD plasma enhanced chemical vapor deposition
  • the specific manufacturing process of the first gate insulating layer 16 is: adopt plasma enhanced chemical vapor deposition (PECVD) method to deposit dielectric layer (dielectric layer It is a double-layer structure SiN x /SiO 2 thin film), first depositing a 400-1000nm silicon oxide layer, and then depositing a 100-500nm silicon nitride layer.
  • PECVD plasma enhanced chemical vapor deposition
  • Fig. 7b schematically shows a schematic view of the interface structure of the thin film transistor in step S2 according to an exemplary embodiment of the present disclosure.
  • step S2 as shown in FIG. 5 and FIG. 7 b , a first gate 12 is formed on the side of the first active layer 11 away from the base substrate 10 .
  • the first gate 12 is deposited by plasma sputtering (Sputter). And the first gate 12 layer is patterned.
  • Fig. 7c schematically shows a schematic view of the interface structure of the thin film transistor in step S3 according to an exemplary embodiment of the present disclosure.
  • step S3 as shown in FIG. 5 and FIG. 7 c , a first insulating layer 13 is formed on a side of the first gate 12 away from the base substrate 10 .
  • the first insulating layer 13 (GI2 thin film layer) is deposited on the side of the first grid 12 away from the base substrate 10.
  • the specific manufacturing process of the first insulating layer 13 is: a dielectric is deposited by plasma enhanced chemical vapor deposition (PECVD) layer (the dielectric layer is SiNx with a single-layer structure of 100-150nm).
  • PECVD plasma enhanced chemical vapor deposition
  • an interlayer insulating layer 17 (ILD thin film layer) is formed, and the specific manufacturing process of forming the interlayer insulating layer is: adopting plasma enhanced chemical vapor deposition (PECVD) to deposit a dielectric layer (the dielectric layer is a double-layer structure SiN x /SiO 2 thin film), first deposit a 150-200nm silicon oxide layer, then deposit a 200-300nm silicon nitride layer, pattern the interlayer insulating layer, and etch by one-step etching or step-by-step etching .
  • PECVD plasma enhanced chemical vapor deposition
  • Fig. 7d schematically shows a schematic view of the interface structure of the thin film transistor in step S4 according to an exemplary embodiment of the present disclosure.
  • step S4 as shown in Figure 5 and Figure 7d, the source and drain 14 are formed on the side of the first insulating layer 13 away from the base substrate 10, and the source and drain 14 are electrically connected to the first active layer 11 .
  • interlayer insulating layer 17 After the above-mentioned interlayer insulating layer 17 is formed, continue to form source and drain 14, and source and drain 14 are electrically connected with the first active layer 11, continue to be in source and drain 14 away from the substrate afterwards
  • One side of the substrate 10 is sequentially formed with film layers such as a flat layer 19 , a pixel defining layer 20 , a light emitting layer 21 , an anode 24 , a cathode 22 , and an encapsulation layer 23 .
  • the manufacturing method of the thin film transistor further includes step S0 , in step S0 , forming the second gate 18 on the base substrate 10 before forming the first active layer 11 .
  • step S2 forming the first gate 12 may specifically include steps S21 to S24 . According to the different structures of the first gate 12 , the specific steps of forming the first gate are also different.
  • the step of forming the first gate 12 includes S22 and S24 . That is, in step S22 , the first conductive layer 121 is formed on the side of the first active layer 11 away from the base substrate 10 . After the first conductive layer 121 is formed, step S24 is performed, that is, the first barrier layer 122 is formed on the side of the first conductive layer 121 away from the base substrate 10 .
  • the step of forming the first gate includes step S22 , step S23 and step S24 .
  • step S22 the first conductive layer 121 is formed on the side of the first active layer 11 away from the base substrate 10 .
  • step S23 is performed to form the second barrier layer 123 on the side of the first conductive layer 121 away from the base substrate.
  • step S24 is performed to form the first barrier layer 122 on the side of the first conductive layer 121 away from the base substrate 10 (that is, on the second barrier layer 123 ).
  • the step of forming the first gate includes step S21 , step S22 , step S23 and step S24 .
  • step S21 a third barrier layer 124 is formed on the side of the first active layer away from the base substrate.
  • step S22 is performed, that is, the first conductive layer 121 is formed on the side of the first active layer away from the base substrate, specifically, the first conductive layer 121 is formed on the third barrier layer 124 The side away from the base substrate.
  • step S23 is performed to form the second barrier layer 123 on the side of the first conductive layer 121 away from the base substrate.
  • step S24 is performed to form the first barrier layer 122 on the side of the first conductive layer 121 away from the base substrate 10 (that is, on the second barrier layer 123 ).
  • FIG. 8 schematically shows a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • the display substrate shown in FIG. 8 the display substrate includes a base substrate 10, and a first transistor disposed on the base substrate 10, the first transistor is the above-mentioned thin film transistor, that is, includes a first active layer 11 , the first gate 12 and the source and drain 14.
  • a film layer structure 15 is provided on the upper layer of the base substrate 10 , and the film layer structure 15 may include, for example, a PI film layer 151 and a buffer layer 152 .
  • a first transistor is formed on a side of the buffer layer 152 away from the base substrate 10 .
  • the display substrate also includes a capacitor 25 disposed on the base substrate, the capacitor includes a first capacitor electrode 251 and a second capacitor electrode 252, the first capacitor electrode 251 is located on the same layer as the first grid 12, and the first capacitor electrode 251 It has a stacked structure, and the stacked structure of the first capacitor electrode 251 is the same as that of the first gate 12 .
  • FIG. 9 schematically shows a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 9 shows another structure of a display substrate.
  • the display substrate also includes the above-mentioned thin film transistor, wherein the display substrate further includes a capacitor 25' disposed on the base substrate, and the capacitor 25' includes a first The capacitor electrode 251' and the second capacitor electrode 252', the second capacitor electrode 252' is electrically connected to the first active layer 11, the second capacitor electrode 252' has a laminated structure, and the laminated structure of the second capacitor electrode 252' and The stacked structure of the first gate 12 is the same.
  • FIG. 10 schematically shows a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 10 shows another structure of a display substrate.
  • the display substrate includes a second transistor arranged on the base substrate 10, located in the area where C is located in the figure.
  • the second transistor includes: a third gate 26, arranged on the substrate One side of the base substrate 10; the second insulating layer 153 is arranged on the side of the third gate 26 away from the base substrate 10; the second active layer 27 is arranged on the side of the second insulating layer 153 away from the base substrate 10 ;
  • the third gate 26 is located at the same layer as the first gate 12 , and the third gate 26 has the same stacked structure as the first gate 12 .
  • the second transistor further includes: a fourth gate 28 disposed on a side of the second active layer 27 away from the base substrate 10 , and the fourth gate 28 has the same stacked structure as the first gate 12 .
  • the first active layer 11 includes a polysilicon material
  • the second active layer 27 includes a semiconductor oxide material
  • the first active layer 12 may include non-silicon-based semiconductor materials such as polysilicon semiconductor materials (such as low-temperature polysilicon), amorphous silicon semiconductor materials, and carbon nanotubes.
  • the second active layer 27 may be formed of an oxide semiconductor, for example, may include a ZnO-based oxide layer.
  • the second active layer 27 may further contain a Group III element such as In or Ga, a Group IV element such as Sn, a combination thereof, or other elements.
  • the active layer 27 may include a Cu oxide layer (CuBO 2 layer, CuAlO 2 layer, CuGaO 2 layer, CuInO 2 layer, etc.), a Ni oxide layer, a Ni oxide layer doped with Ti, a Ni oxide layer doped with A ZnO-based oxide layer of at least one of Group I, Group II, and Group V elements, a ZnO-based oxide layer doped with Ag, a PbS layer, a LaCuOS layer, or a LaCuOSe layer.
  • a Cu oxide layer CuBO 2 layer, CuAlO 2 layer, CuGaO 2 layer, CuInO 2 layer, etc.
  • a Ni oxide layer a Ni oxide layer doped with Ti
  • a Ni oxide layer doped with A ZnO-based oxide layer of at least one of Group I, Group II, and Group V elements a ZnO-based oxide layer doped with Ag, a PbS layer, a LaCuOS layer, or a LaCuOSe layer.
  • the second active layer 27 may include indium gallium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO), indium tin zinc oxide (Indium Tin Zinc Oxide, abbreviated as ITZO) or indium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO).
  • Zinc Oxide abbreviated as IZO).
  • the display substrate further includes a shielding layer 29 , wherein the shielding layer 29 is disposed between the first active layer 11 of the first transistor and the base substrate 10 .
  • the present disclosure also provides a display device, which includes the above-mentioned display substrate.

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Abstract

一种薄膜晶体管及其制造方法、显示基板以及显示装置，薄膜晶体管设置于衬底基板（10）上，该薄膜晶体管包括：第一有源层（11），设置于衬底基板（10）一侧；第一栅极（12），设置于第一有源层（11）的远离衬底基板（10）的一侧；第一绝缘层（13），设置于第一栅极（12）的远离衬底基板（10）的一侧；源极和漏极（14），设置于第一绝缘层（13）远离衬底基板（10）的一侧，源极和漏极（14）与第一有源层（11）电连接；其中，第一栅极（12）包括叠层结构，叠层结构包括：第一导电层（121）；和第一阻挡层（122），设置于第一导电层（121）的远离衬底基板（10）的一侧，第一阻挡层（122）远离衬底基板（10）的一侧与第一绝缘层（13）靠近衬底基板（10）的一侧直接接触；其中，第一阻挡层（122）包括TiN x1，其中，0≤x1＜0.2，x1为N/Ti的摩尔比。

Description

薄膜晶体管及其制造方法、显示基板以及显示装置 技术领域
本公开涉及显示技术领域，并且具体地涉及一种薄膜晶体管及其制造方法、显示基板以及显示装置。
背景技术
相关技术中，中大尺寸的显示产品的屏幕内显示不均匀，随着栅极走线的增长，栅极线自身存在电阻，扫描信号延迟会导致没有足够的栅极开启时间，引起显示效果差，亮度不均一。视觉显示上屏幕中间相对于屏幕两侧边缘，屏幕中间呈现青色，屏幕两侧边缘呈现紫色，严重影响显示效果。
发明内容
在一个方面，提供一种薄膜晶体管，设置于衬底基板上，其中，所述薄膜晶体管包括：第一有源层，设置于在所述衬底基板一侧；第一栅极，设置于所述第一有源层的远离所述衬底基板的一侧；第一绝缘层，设置于所述第一栅极的远离所述衬底基板的一侧；源极和漏极，设置于所述第一绝缘层远离所述衬底基板的一侧，所述源极和漏极与所述第一有源层电连接；其中，所述第一栅极包括叠层结构，所述叠层结构包括：第一导电层；和第一阻挡层，设置于所述第一导电层的远离所述衬底基板的一侧，所述第一阻挡层远离所述衬底基板的一侧与所述第一绝缘层靠近所述衬底基板的一侧直接接触；其中，所述第一阻挡层包括TiN x1，其中，0≤x1＜0.2，x1为N/Ti的摩尔比。
根据一些示例性的实施例，所述第一栅极的叠层结构还包括：第二阻挡层，设置于所述第一导电层和所述第一阻挡层之间，所述第二阻挡层包括TiN x2，其中，0.1≤x2＜0.8，x2为N/Ti的摩尔比。
根据一些示例性的实施例，所述第一阻挡层的材料与所述第一绝缘层的材料之间的黏合力大于所述第二阻挡层的材料与所述第一绝缘层的材料之间的黏合力。
根据一些示例性的实施例，所述第一阻挡层具有第一晶粒尺寸，所述第二阻挡层具有第二晶粒尺寸，所述第一晶粒尺寸小于所述第二晶粒尺寸。
根据一些示例性的实施例，所述第一阻挡层的厚度范围为30至150纳米；和/或，所述第二阻挡层的厚度范围为30至150纳米。
根据一些示例性的实施例，所述第一阻挡层的厚度与所述第二阻挡层的厚度之和在30纳米至150纳米的范围内。
根据一些示例性的实施例，所述第一栅极的叠层结构还包括：第三阻挡层，设置于所述第一导电层与所述衬底基板之间，所述第三阻挡层包括TiN x3，其中，0≤x3＜0.2，x3为N/Ti的摩尔比。
根据一些示例性的实施例，所述薄膜晶体管还包括第二栅极，其中，所述第二栅极设置在所述第一有源层和所述衬底基板之间；所述第二栅极包括叠层结构，所述第二栅极的叠层结构与所述第一栅极的叠层结构相同。
根据一些示例性的实施例，所述第一导电层包括铝合金材料。
在另一方面，还提供了一种薄膜晶体管的制造方法，包括：在衬底基板上形成第一有源层；在所述第一有源层的远离所述衬底基板的一侧形成第一栅极；在所述第一栅极的远离所述衬底基板的一侧形成第一绝缘层；在所述第一绝缘层远离所述衬底基板的一侧形成源极和漏极，所述源极和漏极与所述第一有源层电连接；其中，形成所述第一栅极包括：在所述第一有源层的远离所述衬底基板的一侧形成第一导电层；和在所述第一导电层的远离所述衬底基板的一侧形成第一阻挡层，所述第一阻挡层远离所述衬底基板的一侧与所述第一绝缘层靠近所述衬底基板的一侧直接接触；其中，所述第一阻挡层包括TiN x1，其中0≤x1＜0.2，x1为N/Ti的摩尔比。
根据一些示例性的实施例，所述薄膜晶体管的制造方法还包括：在形成所述第一有源层之前，在所述衬底基板上形成第二栅极。
在另一方面，还提供了一种显示基板，包括：衬底基板；以及设置于所述衬底基板上的第一晶体管，其中，所述第一晶体管为如上文所述的薄膜晶体管。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的电容；其中，所述电容包括第一电容电极和第二电容电极，所述第一电容电极与所述第一栅极位于同一层，所述第一电容电极具有叠层结构，所述第一电容电极的叠层结构与所述第一栅极的叠层结构相同。
根据一些示例性的实施例，所述第二电容电极与所述第一有源层电连接，所述第二电容电极具有叠层结构，所述第二电容电极的叠层结构与所述第一栅极的叠层结构相同。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的第二晶体管，所述第二晶体管包括：第三栅极，设置于所述衬底基板一侧；第二绝缘层，设置于所述第三栅极远离所述衬底基板的一侧；第二有源层，设置于所述第二绝缘层远离所述衬底基板的一侧；所述第三栅极与所述第一栅极位于同于层，并且所述第三栅极具有与所述第一栅极相同的层叠结构。
根据一些示例性的实施例，所述第二晶体管还包括：第四栅极，设置于所述第二有源层远离所述衬底基板的一侧，所述第四栅极具有与所述第一栅极相同的层叠结构。
根据一些示例性的实施例，所述第一有源层包含多晶硅材料，所述第二有源层包含半导体氧化物材料。
根据一些示例性的实施例，所述显示基板还包括遮挡层，其中，所述遮挡层设置在所述第一晶体管的第一有源层和所述衬底基板之间。
在另一方面，还提供了一种显示装置，包括如上文所述的显示基板。
附图说明
通过参照附图详细描述本公开的示例性实施例，本公开的特征及优点将变得更加明显。
图1a示意性示出了根据本公开的一个示例性实施例的薄膜晶体管的截面结构示意图；
图1b示意性示出了根据本公开的另一个示例性实施例的薄膜晶体管的截面结构示意图；
图2a示意性示出了根据本公开的一个示例性实施例的第一栅极的截面结构示意图；
图2b示意性示出了根据本公开的另一个示例性实施例的第一栅极的截面结构示意图；
图2c示意性示出了根据本公开的又一个示例性实施例的第一栅极的截面结构示意图；
图3a示意性示出了根据本公开的实施例的在第一阻挡层上黏合第一绝缘层的示意图；
图3b示意性示出了根据本公开的实施例的第一阻挡层材料的N含量高时第一阻挡层与第一绝缘层劈裂的示意图；
图3c示意性示出了根据本公开的实施例的第一阻挡层材料的N含量低时第一阻挡层与第一绝缘层黏合的示意图；
图4a示意性的示出了根据本公开的实施例的在第一阻挡层的晶粒尺寸的示意图；
图4b示意性的示出了根据本公开的实施例的在第二阻挡层的晶粒尺寸的示意图；
图4c示意性的示出了根据本公开的实施例的阻挡层材料在抵抗ILD介质层刻蚀液刻蚀的性能示意图；
图4d示意性的示出了根据本公开的实施例的阻挡层材料在抵抗BOE刻蚀液刻蚀的性能示意图；
图4e示意性示出了根据本公开的一个示例性实施例的具有第三阻挡层的第一栅极的截面图；
图5示意性的示出了根据本公开的实施例的薄膜晶体管的制造方法的流程图；
图6示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S2的具体流程；
图7a示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S1的界面结构示意图；
图7b示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S2的界面结构示意图；
图7c示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S3的界面结构示意图；
图7d示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S4的界面结构示意图；
图8示意性的示出了根据本公开的示例性实施例的一种显示基板的结构示意图；
图9示意性的示出了根据本公开的示例性实施例的另一种显示基板的结构示意图；
图10示意性的示出了根据本公开的示例性实施例的又一种显示基板的结构示意图。
具体实施例
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XYY、YZ和ZZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、 第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
需要说明的是，在本文中，表述“黏合力”可以表示两种接触的材料层之间的结合力的大小，例如材料之间接触可以是不同的工艺形成的不同的材料层，也可以是相同的工艺形成的不同材料层，黏合力表示两种材料之间的结合强度，结合强度越大，黏合力越大，反之，结合强度越小，黏合力越小。
图1a示意性示出了根据本公开的一个示例性实施例的薄膜晶体管的截面结构示意图。
图1b示意性示出了根据本公开的另一个示例性实施例的薄膜晶体管的截面结构示意图。
下面结合图1a来具体描述根据本公开的一个示例性的薄膜晶体管的结构。
如图1a所示，薄膜晶体管设置于衬底基板10上侧，其中，薄膜晶体管包括第一有源层11、第一栅极12、第一绝缘层13、源极和漏极14。
其中，第一有源层11设置于在衬底基板10的一侧。例如，设置在衬底基板10的上侧的膜层结构15上，衬底基板10上的膜层结构15可以是聚酰亚胺膜层或者缓冲膜层。第一有源层11可以设置在聚酰亚胺膜层上，或者设置在缓冲膜层上。膜层结构15可以是单层膜层结构，也可以是多层膜层结构。
在第一有源层11上设置有第一栅极绝缘层16。该第一栅极绝缘层16的材料例如可以采用氧化硅或氮化硅，还可以采用由氧化硅薄膜和氮化硅薄膜组成的双层结构等。
第一栅极12设置于第一有源层11的远离衬底基板10的一侧。例如设置在第一栅极绝缘层16上。
第一绝缘层13设置于第一栅极12的远离衬底基板10的一侧。例如，第一绝缘层13设置在第一栅极绝缘层16的远离衬底基板10的一侧，并且第一绝缘层13覆盖第一栅极12设置。
源极和漏极14设置于第一绝缘层13的远离衬底基板10的一侧，源极和漏极14与第一有源层11电连接。例如，在第一绝缘层13的远离衬底基板10的一侧设置有层间绝缘层17，源极和漏极14设置在层间绝缘层17上，并且源极和漏极14的一部分穿过层间绝缘层17、第一绝缘层13以及第一栅极绝缘层16，并与有源层11电连接。
在本公开的示例性实施方式中，如图1b所示，薄膜晶体管还可以包括第二栅极18，第二栅极18设置在第一有源层11和衬底基板10之间。例如，设置在膜层结构15和衬底基板10之间。
在本公开的示例性实施方式中，在源极和漏极14上设置有多层膜层结构，用于封装薄膜晶体管。例如可以包括平坦层19、像素界定层20、发光层21、阴极22、封装层23以及阳极24。封装层23可以包括多个无机薄膜层。
图2a至2c示意性示出了根据本公开的示例性实施例的第一栅极的截面结构示意图。
在本公开的一个示例性实施方式中，如图2a所示，第一栅极12具有叠层结构，叠层结构包括第一导电层121和第一阻挡层122。其中，第一导电层121设置在第一有源层11的远离衬底基板10的一侧，具体地，第一导电层121设置于第一栅极绝缘层16的远离衬底基板10的一侧。第一阻挡层122设置于第一导电层121的远离衬底基板10的一侧，即设置在第一导电层121的上侧。
第一导电层121的材料可以采用铝或铝合金，铝或铝合金一方面具有良好的导电性能，另一方面具有较低的杨氏模量。该铝合金可以包括以下至少一种元素：Ce、Zr、Sc、Mn、Ni、La。相关技术中，采用Mo制作栅金属层，Mo的电阻率高达17.6微欧·厘米，相比而言，在第一导电层为铝或铝合金时，第一导电层的电阻率为4.2微欧·厘米，远小于Mo的电阻率，具有良好的导电性能。采用铝和铝合金可以使第一栅极的栅线具有较低的电阻，扫描信号延迟时间较小，可以保证显示基板的显示效果。
根据本公开的实施例，采用铝和铝合金作为第一导电层材料可以保证中大尺寸产品的屏幕内显示均匀，降低栅线自身电阻，进而缩短扫描信号延迟时间，提升显示效果。此外，低电阻的第一栅极材料选用铝或铝合金材料，其杨氏模量在90GPa，相对相关技术中的栅极Mo(杨氏模量为137GPa)更低，铝或者铝合金材料的耐弯折性能更优，在半径为3毫米的弯折实验中，应变为5.97E-03。相关技术中，Mo金属线弯折 2300次后全部断裂。而铝或者铝合金材料弯折10万次后，没有断裂，且电阻值几乎不变，因此作为折叠产品效果更优。
在本公开的实施例中，第一阻挡层122包括TiN x1，其中，0≤x1＜0.2，x1为N/Ti的摩尔比，优选为0.1≤x1≤0.15。第一阻挡层122用于与第一绝缘层13黏合，防止第一阻挡层122与第一绝缘层13之间出现剥离的情况出现。N元素与Ti元素的含量不同，导致第一阻挡层的材料的与无机层SiN的黏合性能不一样，第一阻挡层122中的N与Ti含量的摩尔比值M的范围为0≤M＜0.2可以使第一阻挡层122与第一绝缘层13之间具有较好的粘合性。也就是说，本公开的第一阻挡层122中的N含量设定为相对较低的范围，其一方面与第一绝缘层13之间具有较好的黏合性能，另一方面，抑制第一导电层121在制造过程中表面缺陷的产生，例如，抑制第一导电层121表面产生凸起，同时抑制刻蚀液对金属线表面的损伤。此外，第一阻挡层122在薄膜晶体管的制造过程中，能够有效抑制刻蚀液对金属线表面的损伤。例如，抑制BOE刻蚀液以及ILD介质层刻蚀液对金属线表面的损伤。
如图2b所示，第一栅极12的层叠结构还可以包括第二阻挡层123，其中第二阻挡层123设置于第一导电层121和第一阻挡层122之间，第二阻挡层123包括TiN x2，其中，0.1≤x2＜0.8，x2为N/Ti的摩尔比，x2优选为0.5≤x2＜0.8。在本公开的实施例中，第一阻挡层122和第二阻挡层123都采用氮化钛材料，而氮化钛中的N元素的含量对其性能具有较大的影响，具体包括氮化钛的抑制刻蚀液抗刻蚀能力，以及氮化钛与其他材料的黏合力的大小。
在进行相关的实验中，发现氮化钛中的N元素的含量对其性能的影响并非是线性关系。例如当N元素的含量较低时，其抵抗BOE刻蚀液或者ILD介质层刻蚀液的刻蚀能力较高，而N元素的含量为0时，其抵抗BOE刻蚀液或者ILD介质层刻蚀液的刻蚀能力较弱。即，N元素的含量需要保持在较低的范围内，才可以实现较为优异的抵抗刻蚀液刻蚀的能力。
试验中发现氮化钛中的N元素的含量对第一阻挡层材料与第一绝缘层材料之间的黏合力也有较大的影响。
在本公开的实施例中，第一阻挡层122的材料与第一绝缘层13的材料之间的黏合力大于第二阻挡层123的材料与第一绝缘层13的材料之间的黏合力。
图3a示意性示出了根据本公开的实施例的在第一阻挡层上黏合第一绝缘层的示意图。
第一阻挡层材料中的N含量较低的氮化钛相比于N含量较高的氮化钛，N含量较低的氮化钛与第一绝缘层13的材料之间具有更高的黏合力。例如，TiN x1相比于TiN x2具有更高的黏合力，即TiN x1能更好的与第一绝缘层13黏合。如图3a所示，当x1取值为0.15时，包含TiN 0.15的第一阻挡层122与第一绝缘层13的黏合性较好。在栅极材料12上铺设第一绝缘层13后，没有剥离的情况产生。在图3a中，虽然在方框内存在白色亮点区域H，但是该亮点区域H是层间绝缘层17的打孔位置，而不是制造工艺中存在的剥离情况。从图3a中可以看出第一阻挡层122的材料通过采用N含量较低的氮化钛能够提高其与第一绝缘层之间的黏合力。
第二阻挡层材料中的N含量相比于第一阻挡层材料的N含量较高，因此，第二阻挡层123的材料与第一绝缘层13的材料之间的黏合力小于第一阻挡层122的材料与第一绝缘层13的材料之间的黏合力。相比而言，N含量较高的氮化钛，在第一导电层121上，能够更好的抑制第一导电层121在制造过程中出现的缺陷。即第二阻挡层123的材料相比于第一阻挡层122的材料，在抑制第一导电层121的缺陷方面具有更优异的性能。而第一阻挡层122的材料相比于第二阻挡层123的材料，在与第一绝缘层13黏合的方面，具有更加优异的黏合性能。
图3b示意性示出了根据本公开的实施例的第一阻挡层材料的N含量高时第一阻挡层与第一绝缘层劈裂的示意图。图3c示意性示出了根据本公开的实施例的第一阻挡层材料的N含量低时第一阻挡层与第一绝缘层黏合的示意图。
如图3b所示，当第一阻挡层中TiN x1的N含量较高时，容易造成劈裂(peeling)，即在第一阻挡层(图3b中的TiN 0.9)和第一绝缘层(图3b中的GI2+ILD)之间形成裂纹，造成良品率低。因此，需要降低TiN x1中N的含量，提高第一阻挡层和第一绝缘层之间的黏合力。另一方面，当TiN中N含量低，无法有效抑制第一导电层在制造过程中的缺陷，为了能够更好的抑制第一导电层在制造过程中出现的缺陷，在此引入第二阻挡层，并将第二阻挡层的N含量设置较第一阻挡层高，例如第二阻挡层包括TiN x2，其中，0.1≤x2＜0.8，优选为0.5≤x2＜0.8的范围，本实施例中为x2＝0.5，实现第二阻挡层对第一导电层的缺陷的抑制效果。如图3c所示，在第一阻挡层和第一绝缘层之间设置第二阻挡层，一方面防止第一阻挡层和第一绝缘层之间形成裂纹，另一 方面可以方式第一导电层表面出现制造缺陷，如图3c所示，在第一阻挡层和第一绝缘层之间没有裂纹产生，在第一导电层表面也没有出现缺陷。
根据本公开的实施方式，在第一导电层121上设置第一阻挡层122改善第一栅极12与第一绝缘层13之间的黏合状态，防止第一栅极12与第一绝缘层13之间出现剥离的情况。此外，在第一导电层121和第一阻挡层122之间设置第二阻挡层123能够弥补第一阻挡层122对第一导电层121表面缺陷抑制能力的不足。
图4a示意性的示出了根据本公开的实施例的在第一阻挡层的晶粒尺寸的示意图。
图4b示意性的示出了根据本公开的实施例的在第二阻挡层的晶粒尺寸的示意图。
如图4a所示，第一阻挡层122的材料选用含氮量较低的氮化钛，例如TiN 0.15，其相比含氮量高的氮化钛与第一绝缘层具有更好的黏合性能。此外，第一阻挡层122的材料具有更细小的晶粒，如方框A中的放大区域，其晶粒尺寸较小，晶粒尺寸分布在100纳米至200纳米的范围内，细小的晶粒在抵抗刻蚀性方面具有更优异的抗刻蚀性能。
如图4b所示，第二阻挡层123的材料选用含氮量较高的氮化钛，例如TiN 0.5，其相比含氮量低的氮化钛对第一导电层的缺陷具有更好的抑制作用。此外，第二阻挡层123的材料具有更细大的晶粒，如方框B中的放大区域，其晶粒尺寸较大，晶粒尺寸分布在300纳米至500纳米的范围内，粗大的晶粒在抵抗刻蚀性方面相比细小晶粒，其抗刻蚀性能相对较差。
图4c示意性的示出了根据本公开的实施例的阻挡层材料在抵抗ILD介质层刻蚀液刻蚀的性能示意图。
在进行ILD介质层刻蚀液刻蚀时，含氮量不同的氮化钛具有不同的抵抗刻蚀的性能。如图4c所示，从(a)-(f)所代表的材料分别为不包含阻挡层(a)、包含阻挡层Ti(b)、包含阻挡层TiN 0.15(c)、包含阻挡层TiN 0.3(d)、包含阻挡层TiN 0.5(e)、包含阻挡层TiN 0.9(f)。由图可知，(b)被刻蚀深度为51.6纳米，(c)被刻蚀深度为47.4纳米，(d)被刻蚀深度为55.6纳米，(e)被刻蚀深度为75.1纳米，(f)被刻蚀深度为83纳米，随着N含量的升高，放刻蚀性能下降。即含氮量越多，被ILD介质层刻蚀液刻蚀的深度越深，因此采用较低含量的氮化钛(例如TiN 0.15)提高第一阻挡层的抗刻蚀性能。
图4d示意性的示出了根据本公开的实施例的阻挡层材料在抵抗BOE刻蚀液刻蚀的性能示意图。
此外，抵抗BOE刻蚀液的刻蚀的性能也与氮化钛的含氮量有关，如图4d所示，从(a)-(d)所代表的材料分别为不包含阻挡层(a)、包含阻挡层Ti(b)、包含阻挡层TiN 0.5(c)、包含阻挡层TiN 0.9(d)，氮化钛的氮含量依次升高。从图4d中可以看出，氮含量较低时，具有更优异的耐腐蚀性能。具体地，在包含阻挡层TiN 0.5(c)时，剩余未被刻蚀厚度为47纳米，其表面平整。在包含阻挡层TiN 0.9(d)，剩余未被刻蚀厚度为20纳米，并且其表面产生因刻蚀导致的凹凸不平的结构。因此，在N含量为0.5时，可以有效阻挡BOE的腐蚀液的腐蚀。而且，被刻蚀的表面具有较为平整的平面，在其表面形成其他膜层结构时，具有更小的电阻。由此，为了是被刻蚀表面具有较为平整的平面，同时提高耐刻蚀性能，可以选用N含量较低的阻挡层材料。
在本公开的示例性实施例中，第一阻挡层122的厚度范围为30至150纳米，优选为100纳米至120纳米。第二阻挡层123的厚度范围为30纳米至150纳米，优选为30纳米至50纳米。
第一阻挡层122的厚度与第二阻挡层123的厚度之和在30纳米至150纳米的范围内。即第一阻挡层122和第二阻挡层123之间的厚度之和满足设定的范围，例如厚度之和为50纳米，或者100纳米等等。可以根据实际的需求进行调整。
在本公开的示例性实施例中，如图2c所示，第一栅极12的叠层结构还包括第三阻挡层124，其设置于第一导电层121与所述衬底基板10之间。具体地，第三阻挡层124设置在第一栅极绝缘层16上，第三阻挡层124的上侧为第一导电层121。第三阻挡层124的材料包括TiN x3，其中，0≤x3＜0.2，优选为0.1≤x3≤0.15。
在一些实施例中，第一栅极12的导电层还可能与第一有源层接触，为了避免第一栅极的导电层金属与第一有源层的硅接触时发生共溶，需要设置如图2c所示的第三阻挡层124。第三阻挡层124能够防止第一栅极12的第一导电层121与有源层接触发生共溶。
图4e示意性示出了根据本公开的一个示例性实施例的具有第三阻挡层的第一栅极的截面图。
例如，如图4e所示，本实施例中的第一阻挡层包括TiN 0.15，第一导电层为铝合金，第二阻挡层为TiN 0.5，第三阻挡层为TiN 0.15。具有该叠层结构的第一栅极在生成制造时，具有更高的成品率。
根据本公开的实施例，通过设置第三阻挡层124，一方面防止高温铝合金(即第一导电层)产生凸起(hillock)对下层膜层产生损伤，另一方面，避免因TiN中的N含量高而与无机层发生劈裂(peeling)，降低制造过程中产生缺陷的概率。
第三阻挡层124的厚度范围在30纳米至150纳米之间，优选为30至50纳米之间。
在本公开的实施例中，第一栅极结构采用上文所述的叠层结构，具有较低的电阻，例如，低电阻的第一栅极结构包括两层，靠近衬底基板的Al合金材料层及TiN 0.15层。又例如，低电阻的第一栅极结构包括四层，依次为TiN 0.15层、Al合金材料层、TiN 0.5层、TiN 0层。
在本公开的示例性实施方式中，第二栅极18也具有叠层结构，并且第二栅极18的叠层结构与第一栅极12的叠层结构相同。例如第二栅极18的层叠结构可以包括第一导电层、第一阻挡层，以及第二阻挡层和第三阻挡层中的一个或多个。
图5示意性的示出了根据本公开的实施例的薄膜晶体管的制造方法的流程图。
图6示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S2的具体流程。
如图5所示，本公开实施例的薄膜晶体管的制造方法包括步骤S01至S05。
图7a示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S1的界面结构示意图。
在步骤S1，如图5以及图7a所示，在衬底基板10上形成第一有源层11。
首先，对衬底基板10(例如，玻璃基板)进行初始清洗，在衬底基板10上形成膜层结构15，例如，在衬底基板10上涂覆双层PI胶，并在300～400℃固化形成10um左右的PI薄膜形成PI膜层151。
随后在衬底基板/PI衬底之上制作薄膜层，薄膜层的具体制作过程为：采用等离子体增强化学气相沉积(PECVD)方法沉积缓冲层152(缓冲层为双层结构SiN x/SiO 2薄膜)，先沉积50～300nm的氮化硅层，再沉积100～300nm的二氧化硅层。之后按照要求进行40～50nm非晶硅层的沉积。再完成非晶硅层的沉积后，于400℃的温度下， 对非晶硅层进行0.5～3小时的加热处理。然后再同时对非晶硅区进行准分子激光退火(ELA)工艺，将多晶硅图案化形成沟道，进行Vth Doping，最终形成第一有源层11。
然后，此基础上，沉积第一栅极绝缘层16(GI1薄膜层)，第一栅极绝缘层16的具体制作过程为：采用等离子体增强化学气相沉积(PECVD)方法沉积介质层(介质层为双层结构SiN x/SiO 2薄膜)，先沉积400-1000nm的氧化硅层，再沉积100～500nm的氮化硅层。
图7b示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S2的界面结构示意图。
在步骤S2，如图5和图7b所示，在第一有源层11的远离衬底基板10的一侧形成第一栅极12。
例如，在形成第一栅极绝缘层16之后，采用等离子溅射(Sputter)方式沉积第一栅极12。并将第一栅极12层图案化。
图7c示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S3的界面结构示意图。
在步骤S3，如图5和图7c所示，在第一栅极12的远离衬底基板10的一侧形成第一绝缘层13。
在第一栅极12的远离衬底基板10的一侧沉积第一绝缘层13(GI2薄膜层)，第一绝缘层13的具体制作过程为：采用等离子增强化学气相沉积(PECVD)方法沉积介质层(介质层为单层结构100-150nm的SiNx)。
在上述基础上，形成层间绝缘层17(ILD薄膜层)，形成层间绝缘层的具体制作过程为：采用等离子体增强化学气相沉积(PECVD)方法沉积介质层(介质层为双层结构SiN x/SiO 2薄膜)，先沉积150-200nm的氧化硅层，再沉积200-300nm的氮化硅层，将层间绝缘层图案化，采取一步刻蚀或分步刻蚀的方式进行刻蚀。
图7d示意性的示出了根据本公开的示例性实施例的薄膜晶体管在步骤S4的界面结构示意图。
在步骤S4，如图5和图7d所示，在第一绝缘层13远离衬底基板10的一侧形成源极和漏极14，源极和漏极14与第一有源层11电连接。
在上述的层间绝缘层17形成后，继续形成源极和漏极14，源极和漏极14与第一有源层11电连接，之后在继续在源极和漏极14的远离衬底基板10的一侧依次形成平坦层19、像素界定层20、发光层21、阳极24、阴极22、封装层23等膜层。
在本公开的示例性实施方式中，薄膜晶体管的制造方法还包括步骤S0，在步骤S0，在形成第一有源层11之前，在衬底基板上10形成第二栅极18。
在本公开的示例性实施方式中，如图6所示，在步骤S2中，形成第一栅极12具体可以包括步骤S21至S24。根据第一栅极12的结构不同，形成第一栅极的具体步骤也不同。
例如，当第一栅极12的结构如图2a所示，则形成第一栅极12的步骤包括S22和步骤S24。即在步骤S22，在第一有源层11的远离衬底基板10的一侧形成第一导电层121。形成第一导电层121之后，进行步骤S24，即在第一导电层121的远离衬底基板10的一侧形成第一阻挡层122。
再例如，当第一栅极12的结构如图2b所示，形成第一栅极的步骤包括步骤S22、步骤S23、步骤S24。具体地，在步骤S22，在第一有源层11的远离衬底基板10的一侧形成第一导电层121。形成第一导电层121之后，进行步骤S23，在第一导电层121的远离衬底基板的一侧形成第二阻挡层123。然后进行步骤S24，在第一导电层121的远离衬底基板10的一侧(即在第二阻挡层123上)形成第一阻挡层122。
又例如，当第一栅极12的结构如图2c所示，形成第一栅极的步骤包括步骤S21、步骤S22、步骤S23、步骤S24。具体地，在步骤S21，在第一有源层的远离衬底基板的一侧形成第三阻挡层124。在形成第三阻挡层124之后，进行步骤S22，即在第一有源层的远离衬底基板的一侧形成第一导电层121，具体地，第一导电层121形成在第三阻挡层124的远离衬底基板的一侧。形成第一导电层121之后，进行步骤S23，在第一导电层121的远离衬底基板的一侧形成第二阻挡层123。然后进行步骤S24，在第一导电层121的远离衬底基板10的一侧(即在第二阻挡层123上)形成第一阻挡层122。
图8示意性的示出了根据本公开的示例性实施例的一种显示基板的结构示意图。
如图8所示的显示基板，显示基板包括衬底基板10，以及设置在衬底基板10上的第一晶体管，第一晶体管为上文所述的薄膜晶体管，即包括第一有源层11、第一栅极12以及源极和漏极14。
具体地，在衬底基板10的上层设有膜层结构15，膜层结构15例如可以包括PI膜层151以及缓冲层152。在缓冲层152的远离衬底基板10的一侧形成第一晶体管。
该显示基板还包括设置在衬底基板上的电容25，该电容包括第一电容电极251和第二电容电极252，第一电容电极251与第一栅极12位于同一层，第一电容电极251具有叠层结构，第一电容电极251的叠层结构与第一栅极12的叠层结构相同。
图9示意性的示出了根据本公开的示例性实施例的另一种显示基板的结构示意图。
图9示出了另一种显示基板的结构，显示基板同样包括上文所述的薄膜晶体管，其中，该显示基板还包括设置在衬底基板上的电容25’，该电容25’包括第一电容电极251’和第二电容电极252’，第二电容电极252’与第一有源层11电连接，第二电容电极252’具有叠层结构，第二电容电极252’的叠层结构与第一栅极12的叠层结构相同。
图10示意性的示出了根据本公开的示例性实施例的又一种显示基板的结构示意图。
图10示出了又一种显示基板的结构，显示基板包括设置于衬底基板10上的第二晶体管，位于图中C所在的区域，第二晶体管包括：第三栅极26，设置于衬底基板10一侧；第二绝缘层153，设置于第三栅极26远离衬底基板10的一侧；第二有源层27，设置于第二绝缘层153远离衬底基板10的一侧；第三栅极26与第一栅极12位于同一层，并且第三栅极26具有与第一栅极12相同的层叠结构。
第二晶体管还包括：第四栅极28，设置于第二有源层27远离衬底基板10的一侧，第四栅极28具有与第一栅极12相同的层叠结构。
在本公开的实施例中，第一有源层11包含多晶硅材料，第二有源层27包含半导体氧化物材料。
例如，第一有源层12例如可以包括多晶硅半导体材料(例如低温多晶硅)、非晶硅半导体材料、碳纳米管等非硅基半导体材料。在本公开的实施例中，第二有源层27可以由氧化物半导体形成，例如可以包括ZnO基氧化物层。第二有源层27还可以包含诸如In或Ga的第III族元素、诸如Sn的第IV族元素、它们的组合或者其它元素。再例如，有源层27可以包括Cu氧化物层(CuBO 2层、CuAlO 2层、CuGaO 2层、CuInO 2层等)、Ni氧化物层、掺杂有Ti的Ni氧化物层、掺杂有第I族、第II族和第V族元素中的至少一种的ZnO基氧化物层、掺杂有Ag的ZnO基氧化物层、PbS层、LaCuOS 层或者LaCuOSe层。作为一个示例，第二有源层27可以包括铟镓锌氧化物(Indium Gallium Zinc Oxide，缩写为IGZO)、铟锡锌氧化物(Indium Tin Zinc Oxide，缩写为ITZO)或铟锌氧化物(Indium Zinc Oxide，缩写为IZO)。
在本公开的实施方式中，显示基板还包括遮挡层29，其中，遮挡层29设置在第一晶体管的第一有源层11和衬底基板10之间。
本公开还提供了一种显示装置，其包括如上文所述的显示基板。
虽然本公开的总体技术构思的一些实施例已被显示和说明，本领域普通技术人员将理解，在不背离所述总体技术构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (19)

  1. 一种薄膜晶体管，设置于衬底基板上，其中，所述薄膜晶体管包括：
    第一有源层，设置于在所述衬底基板一侧；
    第一栅极，设置于所述第一有源层的远离所述衬底基板的一侧；
    第一绝缘层，设置于所述第一栅极的远离所述衬底基板的一侧；
    源极和漏极，设置于所述第一绝缘层远离所述衬底基板的一侧，所述源极和漏极与所述第一有源层电连接；
    其中，所述第一栅极包括叠层结构，所述叠层结构包括：
    第一导电层；和
    第一阻挡层，设置于所述第一导电层的远离所述衬底基板的一侧，
    所述第一阻挡层远离所述衬底基板的一侧与所述第一绝缘层靠近所述衬底基板的一侧直接接触；
    其中，所述第一阻挡层包括TiN x1，其中，0≤x1＜0.2，x1为N/Ti的摩尔比。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一栅极的叠层结构还包括：
    第二阻挡层，设置于所述第一导电层和所述第一阻挡层之间，所述第二阻挡层包括TiN x2，其中，0.1≤x2＜0.8，x2为N/Ti的摩尔比。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述第一阻挡层的材料与所述第一绝缘层的材料之间的黏合力大于所述第二阻挡层的材料与所述第一绝缘层的材料之间的黏合力。
  4. 根据权利要求2或3所述的薄膜晶体管，其中，所述第一阻挡层具有第一晶粒尺寸，所述第二阻挡层具有第二晶粒尺寸，所述第一晶粒尺寸小于所述第二晶粒尺寸。
  5. 根据权利要求2所述的薄膜晶体管，其中，所述第一阻挡层的厚度范围为30至150纳米；和/或，
    所述第二阻挡层的厚度范围为30至150纳米。
  6. 根据权利要求5所述的薄膜晶体管，其中，所述第一阻挡层的厚度与所述第二阻挡层的厚度之和在30纳米至150纳米的范围内。
  7. 根据权利要求1至6中任一项所述的薄膜晶体管，其中，所述第一栅极的叠层结构还包括：
    第三阻挡层，设置于所述第一导电层与所述衬底基板之间，所述第三阻挡层包括TiN x3，其中，0≤x3＜0.2，x3为N/Ti的摩尔比。
  8. 根据权利要求1至6中任一项所述的薄膜晶体管，还包括第二栅极，其中，所述第二栅极设置在所述第一有源层和所述衬底基板之间；
    所述第二栅极包括叠层结构，所述第二栅极的叠层结构与所述第一栅极的叠层结构相同。
  9. 根据权利要求1至6中任一项所述的薄膜晶体管，所述第一导电层包括铝合金材料。
  10. 一种薄膜晶体管的制造方法，包括：
    在衬底基板上形成第一有源层；
    在所述第一有源层的远离所述衬底基板的一侧形成第一栅极；
    在所述第一栅极的远离所述衬底基板的一侧形成第一绝缘层；
    在所述第一绝缘层远离所述衬底基板的一侧形成源极和漏极，所述源极和漏极与所述第一有源层电连接；
    其中，形成所述第一栅极包括：
    在所述第一有源层的远离所述衬底基板的一侧形成第一导电层；和
    在所述第一导电层的远离所述衬底基板的一侧形成第一阻挡层，所述第一阻挡层远离所述衬底基板的一侧与所述第一绝缘层靠近所述衬底基板的一侧直接接触；
    其中，所述第一阻挡层包括TiN x1，其中0≤x1＜0.2，x1为N/Ti的摩尔比。
  11. 根据权利要求10所述的薄膜晶体管的制造方法，还包括：
    在形成所述第一有源层之前，在所述衬底基板上形成第二栅极。
  12. 一种显示基板，包括：
    衬底基板；以及
    设置于所述衬底基板上的第一晶体管，
    其中，所述第一晶体管为如权利要求1至9中任一项所述的薄膜晶体管。
  13. 根据权利要求12所述的显示基板，还包括设置于所述衬底基板上的电容；
    其中，所述电容包括第一电容电极和第二电容电极，所述第一电容电极与所述第一栅极位于同一层，所述第一电容电极具有叠层结构，所述第一电容电极的叠层结构与所述第一栅极的叠层结构相同。
  14. 根据权利要求13所述的显示基板，其中，所述第二电容电极与所述第一有源层电连接，所述第二电容电极具有叠层结构，所述第二电容电极的叠层结构与所述第一栅极的叠层结构相同。
  15. 根据权利要求12所述的显示基板，其中，所述显示基板还包括设置于所述衬底基板上的第二晶体管，所述第二晶体管包括：
    第三栅极，设置于所述衬底基板一侧；
    第二绝缘层，设置于所述第三栅极远离所述衬底基板的一侧；
    第二有源层，设置于所述第二绝缘层远离所述衬底基板的一侧；
    所述第三栅极与所述第一栅极位于同于层，并且所述第三栅极具有与所述第一栅极相同的层叠结构。
  16. 根据权利要求15所述的显示基板，其中，所述第二晶体管还包括：
    第四栅极，设置于所述第二有源层远离所述衬底基板的一侧，
    所述第四栅极具有与所述第一栅极相同的层叠结构。
  17. 根据权利要求15或16所述的显示基板，其中，所述第一有源层包含多晶硅材料，所述第二有源层包含半导体氧化物材料。
  18. 根据权利要求12所述的显示基板，还包括遮挡层，其中，所述遮挡层设置在所述第一晶体管的第一有源层和所述衬底基板之间。
  19. 一种显示装置，包括如权利要求12至18中任一项所述的显示基板。
PCT/CN2021/122026 2021-09-30 2021-09-30 薄膜晶体管及其制造方法、显示基板以及显示装置 WO2023050250A1 (zh)

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