WO2023047227A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023047227A1
WO2023047227A1 PCT/IB2022/058438 IB2022058438W WO2023047227A1 WO 2023047227 A1 WO2023047227 A1 WO 2023047227A1 IB 2022058438 W IB2022058438 W IB 2022058438W WO 2023047227 A1 WO2023047227 A1 WO 2023047227A1
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Prior art keywords
insulator
oxide
conductor
region
oxygen
Prior art date
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Ceased
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PCT/IB2022/058438
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English (en)
French (fr)
Japanese (ja)
Inventor
國武寛司
方堂涼太
神保安弘
倉田求
笹川慎也
福島邦宏
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to KR1020247011431A priority Critical patent/KR20240067242A/ko
Priority to CN202280061603.5A priority patent/CN117916893A/zh
Priority to JP2023549159A priority patent/JPWO2023047227A1/ja
Priority to US18/691,097 priority patent/US20240379866A1/en
Publication of WO2023047227A1 publication Critical patent/WO2023047227A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Definitions

  • One aspect of the present invention relates to a method for producing a metal oxide.
  • one embodiment of the present invention relates to transistors, semiconductor devices, and electronic devices.
  • one embodiment of the present invention relates to a method for manufacturing a semiconductor device.
  • one aspect of the present invention relates to semiconductor wafers and modules.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are examples of semiconductor devices.
  • a display device (such as a liquid crystal display device or a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like can be said to include a semiconductor device in some cases.
  • One aspect of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method.
  • One aspect of the invention also relates to a process, machine, manufacture, or composition of matter.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components of various electronic devices.
  • Patent Document 1 discloses a low-power-consumption CPU and the like that utilize a characteristic that a transistor including an oxide semiconductor has a small leakage current.
  • Patent Document 2 discloses a memory device or the like that can retain stored data for a long period of time by utilizing the characteristic that a transistor including an oxide semiconductor has low leakage current.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with high on-state current. Another object is to provide a semiconductor device with low power consumption.
  • One embodiment of the present invention is a semiconductor device including a transistor.
  • the transistor includes an oxide, a first conductor and a second conductor over the oxide, and a first insulator having an opening over the first conductor and the second conductor. , a second insulator in the opening of the first insulator, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third insulator on the third insulator. and a third conductor on insulator.
  • the opening in the first insulator has a region that overlaps with the oxide.
  • the third conductor has a region overlapping with the oxide with the second insulator, the third insulator, and the fourth insulator interposed therebetween.
  • the second insulator has regions in contact with the top surface of the oxide and the sidewalls of the opening of the first insulator.
  • the second insulator has a region with a thickness smaller than that of the third insulator.
  • the fourth insulator is less permeable to oxygen than the third insulator.
  • the third conductor has a region with a width of 3 nm or more and 15 nm or less.
  • the transistor includes an oxide, a first conductor and a second conductor over the oxide, and a first insulator having an opening over the first conductor and the second conductor. , a second insulator in the opening of the first insulator, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third insulator on the third insulator. and a third conductor on insulator.
  • the opening in the first insulator has a region that overlaps with the oxide.
  • the third conductor has a region overlapping with the oxide with the second insulator, the third insulator, and the fourth insulator interposed therebetween.
  • the second insulator has regions in contact with the top surface of the oxide and the sidewalls of the opening of the first insulator.
  • the second insulator has a region with a thickness smaller than that of the third insulator.
  • the fourth insulator is less permeable to oxygen than the third insulator.
  • the third conductor In a cross-sectional view of the transistor in the channel length direction, the third conductor has a region with a width of 3 nm or more and 15 nm or less.
  • the distance between the lower end of the first conductor and the lower end of the second conductor is 10 nm or more and less than 40 nm.
  • the transistor includes an oxide, a first conductor and a second conductor over the oxide, and a first insulator having an opening over the first conductor and the second conductor. , a second insulator in the opening of the first insulator, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third insulator on the third insulator. 4 insulators, a third conductor and a fifth insulator.
  • the opening in the first insulator has a region that overlaps with the oxide.
  • the third conductor has a region overlapping with the oxide with the second insulator, the third insulator, and the fourth insulator interposed therebetween.
  • the second insulator has regions in contact with the top surface of the oxide and the sidewalls of the opening of the first insulator.
  • the second insulator has a region with a thickness smaller than that of the third insulator.
  • the fourth insulator is less permeable to oxygen than the third insulator.
  • the third conductor has a region with a width of 3 nm or more and 15 nm or less.
  • a fifth insulator is provided between the first conductor and the second conductor and the first insulator, and has an opening that overlaps with the opening of the first insulator; Furthermore, it is less permeable to oxygen than the third insulator, and has regions in contact with the side surface of the oxide, the side surface of the first conductor, and the side surface of the second conductor.
  • the second insulator has a region in contact with the sidewall of the opening of the fifth insulator.
  • the oxide comprises indium, zinc, and one or more selected from gallium, aluminum, and tin. Oxides have crystals, and the c-axis of the crystals is approximately perpendicular to the surface or surface of the oxide to be formed.
  • the third conductor is a laminate of a fourth conductor and a fifth conductor on the fourth conductor, and the first conductor, the second conductor, and the fifth conductor preferably comprise metal and nitrogen.
  • the transistor includes a first layer and a second layer, and the first layer is located between the first conductor and the second insulator.
  • the second layer is located between the second conductor and the second insulator, the length in the channel length direction of the first layer being smaller than the width, and the channel of the second layer
  • the longitudinal length is less than the width, and each of the first layer and the second layer comprises metal and oxygen.
  • the bottom surface of the third conductor has a flat region and the width is the width of the flat region.
  • the third conductor has an arcuate bottom surface with a center of curvature located within the third conductor, and the width includes the center of curvature and is parallel to the bottom surface of the oxide. It is preferably the width of the region where the straight line and the third conductor overlap.
  • the oxide preferably has a region in which the thickness of the oxide region overlapping with the third conductor is smaller than the thickness of the oxide region overlapping with the first conductor.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with little variation in electrical characteristics of transistors can be provided.
  • a semiconductor device with favorable electrical characteristics can be provided.
  • a semiconductor device with large on-current can be provided.
  • a semiconductor device with low power consumption can be provided.
  • FIG. 1A is a top view of a semiconductor device which is one embodiment of the present invention.
  • 1B to 1D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
  • 2A and 2B are cross-sectional views of a semiconductor device that is one embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a semiconductor device which is one embodiment of the present invention.
  • 4A to 4F are cross-sectional views of semiconductor devices that are one embodiment of the present invention.
  • 5A and 5B are cross-sectional views of a semiconductor device that is one embodiment of the present invention.
  • FIG. 6A is a top view of a semiconductor device which is one embodiment of the present invention.
  • 6B to 6D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
  • FIG. 7A is a top view of a semiconductor device which is one embodiment of the present invention.
  • 7B to 7D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
  • FIG. 8A is a top view of a semiconductor device which is one embodiment of the present invention.
  • 8B to 8D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
  • FIG. 9A is a top view of a semiconductor device which is one embodiment of the present invention.
  • 9B to 9D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
  • FIG. 10A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 11A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 12A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 13A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 14A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 15A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 16A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 17A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 18A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 19A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 19B to 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 20A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 21 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention.
  • FIG. 22 is a schematic cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention.
  • FIG. 23 is a cross-sectional schematic diagram illustrating a microwave processing apparatus according to one embodiment of the present invention.
  • FIG. 20A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 21 is
  • FIG. 24 is a schematic diagram illustrating a microwave processing apparatus according to one aspect of the present invention.
  • FIG. 25A is a top view of a semiconductor device according to one embodiment of the present invention.
  • 25B and 25C are cross-sectional views of a semiconductor device that is one embodiment of the present invention.
  • FIG. 26 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 27 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 28 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 29A and 29B are cross-sectional views of semiconductor devices according to one embodiment of the present invention.
  • FIG. 30 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 31A is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 31B is a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • 32A to 32H are circuit diagrams illustrating configuration examples of memory devices according to one embodiment of the present invention.
  • 33A and 33B are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
  • 34A and 34B are diagrams illustrating an example of an electronic component.
  • 35A to 35E are schematic diagrams of a memory device according to one embodiment of the present invention.
  • 36A to 36H are diagrams illustrating electronic devices according to one embodiment of the present invention.
  • 44B is a diagram explaining the TEG for cutoff frequency measurement.
  • 45A and 45B are diagrams showing measurement results of cutoff frequencies of transistors.
  • FIG. 46 is a diagram showing a roadmap of OS transistors.
  • FIG. 47 shows the Id-Vd characteristics of the transistor.
  • FIG. 48A is a diagram showing measurement results of cutoff frequencies of transistors.
  • FIG. 48B is a diagram showing measurement results of the maximum oscillation frequency of the transistor.
  • 49A to 49D are Id-Vg characteristics of transistors.
  • 50A to 50D are Id-Vg characteristics of transistors.
  • FIG. 51 is a schematic diagram showing the structure of a prototype sample.
  • 52A and 52B are the Id-Vg characteristics of the transistor.
  • top views also referred to as “plan views”
  • perspective views also referred to as “plan views”
  • description of some hidden lines may be omitted.
  • connection relationships other than the connection relationships shown in the drawings or the text are not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or the text.
  • X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a region in which a channel is formed (hereinafter also referred to as a channel formation region) is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode).
  • a current can flow between the source and the drain through the formation region.
  • a channel formation region means a region where current mainly flows.
  • the function of the source or drain may be switched when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably in some cases.
  • the channel length is, for example, a region in which a semiconductor (or a portion of the semiconductor in which current flows when the transistor is on) overlaps with a gate electrode in a top view of a transistor, or the source length in a channel formation region.
  • the channel length does not always have the same value in all regions of one transistor. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one value, maximum value, minimum value, or average value in the channel forming region.
  • the channel width is the region in which the semiconductor (or the portion of the semiconductor where current flows when the transistor is on) and the gate electrode overlap each other, or the channel length direction in the channel formation region.
  • a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) and a channel width shown in a top view of a transistor ( hereinafter also referred to as “apparent channel width”) may be different.
  • the effective channel width becomes larger than the apparent channel width, and its influence cannot be ignored.
  • the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width may refer to the apparent channel width.
  • channel width may refer to the effective channel width.
  • the channel length, channel width, effective channel width, or apparent channel width can be determined by analyzing cross-sectional TEM images, for example.
  • silicon oxynitride contains more oxygen than nitrogen as its composition.
  • Silicon nitride oxide contains more nitrogen than oxygen in its composition.
  • aluminum oxynitride has a higher content of oxygen than nitrogen as its composition.
  • aluminum oxynitride has a composition in which the content of nitrogen is higher than that of oxygen.
  • hafnium oxynitride has a higher content of oxygen than nitrogen as its composition.
  • hafnium oxynitride has a composition in which the content of nitrogen is higher than that of oxygen.
  • insulator can be replaced with an insulating film or an insulating layer.
  • conductor can be replaced with a conductive film or a conductive layer.
  • semiconductor can be interchanged with a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of ⁇ 5 degrees or more and 5 degrees or less is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • substantially perpendicular means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • a metal oxide is a metal oxide in a broad sense.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like.
  • oxide semiconductors also referred to as oxide semiconductors or simply OSs
  • an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.
  • the term “normally-off” means that the drain current per 1 ⁇ m of the channel width flowing through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate is 1 ⁇ 10 ⁇ 1 at room temperature. 20 A or less, 1 ⁇ 10 ⁇ 18 A or less at 85° C., or 1 ⁇ 10 ⁇ 16 A or less at 125° C.
  • the heights are the same or approximately the same” refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view.
  • planarization processing typically CMP processing
  • CMP processing may expose the surface of a single layer or multiple layers.
  • the surfaces to be CMP-processed have the same height from the reference surface.
  • the heights of the layers may differ depending on the processing equipment, processing method, or material of the surface to be processed during the CMP processing. In this specification and the like, this case is also treated as "the height matches or roughly matches".
  • the height of the top surface of the first layer and the height of the second layer A case where the height difference from the upper surface is 20 nm or less is also referred to as "matching or substantially matching heights".
  • the ends match or roughly match means that at least part of the outline overlaps between the laminated layers when viewed from the top.
  • the upper layer and the lower layer may be processed with the same mask pattern or partially with the same mask pattern.
  • the contours do not overlap, and the upper contour may be positioned inside the lower contour, or the upper contour may be positioned outside the lower contour. “match or approximate match”.
  • an off-state current sometimes refers to a current that flows between a source and a drain when a transistor is in an off state, for example.
  • a semiconductor device which is one embodiment of the present invention includes a transistor.
  • FIG. 1A-1D are top and cross-sectional views of a semiconductor device having a transistor 200.
  • FIG. 1A is a top view of the semiconductor device.
  • 1B to 1D are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 1C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG.
  • FIG. 1A is also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIG. 1D is sectional drawing of the site
  • a semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, and an insulator 280 over the transistor 200. , insulator 282 on insulator 280 , insulator 283 on insulator 282 , insulator 274 on insulator 283 , insulator 285 on insulator 283 and insulator 274 .
  • the insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, the insulator 285, the insulator 274, and the insulator 285 function as interlayer films.
  • an insulator 241a is provided in contact with a side surface of the conductor 240a
  • an insulator 241b is provided in contact with a side surface of the conductor 240b.
  • a conductor 246a that is electrically connected to the conductor 240a and functions as a wiring is provided over the insulator 285 and the conductor 240a
  • the conductor 240b is provided over the insulator 285 and the conductor 240b.
  • a conductor 246b is provided which is electrically connected to and functions as a wiring.
  • the insulator 283 is in contact with part of the top surface of the insulator 214 , the side surfaces of the insulator 280 , and the side surfaces and top surface of the insulator 282 .
  • An insulator 241a is provided in contact with the inner wall of the opening of the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and the conductor 240a is provided in contact with the side surface of the insulator 241a.
  • An insulator 241b is provided in contact with the inner wall of the opening of the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and the conductor 240b is provided in contact with the side surface of the insulator 241b.
  • Each of the insulators 241a and 241b has a structure in which a first insulator is provided in contact with the inner wall of the opening, and a second insulator is provided inside.
  • the conductor 240a has a structure in which a first conductor is provided in contact with the side surface of the insulator 241a and a second conductor is provided inside.
  • the conductor 240b has a structure in which a first conductor is provided in contact with the side surface of the insulator 241b and a second conductor is provided inside.
  • the height of the top surface of the conductor 240a and the height of the top surface of the insulator 285 in the region overlapping with the conductor 246a can be made approximately the same.
  • the top surface of the conductor 240b and the top surface of the insulator 285 in the region overlapping with the conductor 246b can be approximately the same height.
  • the insulator 241a and the insulator 241b each have a structure in which a first insulator and a second insulator are stacked, but the present invention is not limited to this.
  • each of the insulator 241a and the insulator 241b may be provided as a single layer or a stacked structure of three or more layers.
  • the conductor 240a and the conductor 240b each have a structure in which a first conductor and a second conductor are stacked, but the present invention is not limited to this.
  • each of the conductor 240a and the conductor 240b may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.
  • the transistor 200 includes an insulator 216 over an insulator 214, conductors 205 (a conductor 205a and a conductor 205b) embedded in the insulator 216, Insulator 222 over insulator 216 and over conductor 205, insulator 224 over insulator 222, oxide 230a over insulator 224, oxide 230b over oxide 230a, and oxide 230b conductor 242a, insulator 271a over conductor 242a, conductor 242b over oxide 230b, insulator 271b over conductor 242b, insulator 252 over oxide 230b, and insulator 252 over oxide 230b.
  • insulator 252 includes a top surface of insulator 222, sides of insulator 224, sides of oxide 230a, sides and top of oxide 230b, conductor 242a and conductor 242 b , the insulators 271 a and 271 b , the insulator 275 , the insulator 280 , and the bottom surface of the insulator 250 .
  • the top surface of the conductor 260 is arranged so that the top surface of the insulator 254 , the top surface of the insulator 250 , the top surface of the insulator 252 , and the top surface of the insulator 280 are substantially flush with each other.
  • the insulator 282 is in contact with at least part of the upper surface of each of the conductor 260 , the insulator 252 , the insulator 250 , the insulator 254 , and the insulator 280 .
  • oxide 230a and the oxide 230b may be collectively referred to as the oxide 230 below.
  • the conductor 242a and the conductor 242b are collectively referred to as the conductor 242 in some cases.
  • the insulator 271a and the insulator 271b are collectively referred to as the insulator 271 .
  • the insulator 280 and the insulator 275 are provided with openings reaching the oxide 230b. That is, it can be said that the opening has a region overlapping with the oxide 230b. In addition, it can be said that the insulator 275 has an opening that overlaps with the opening of the insulator 280 .
  • An insulator 252, an insulator 250, an insulator 254, and a conductor 260 are arranged in the opening. That is, the conductor 260 has a region overlapping with the oxide 230b with the insulators 252, 250, and 254 interposed therebetween.
  • a conductor 260, an insulator 252, an insulator 250, and an insulator 254 are provided between the insulator 271a and the conductor 242a and the insulator 271b and the conductor 242b. is provided.
  • the insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260 .
  • the oxide 230 preferably has an oxide 230a overlying the insulator 224 and an oxide 230b overlying the oxide 230a.
  • the oxide 230 has a structure in which two layers of the oxide 230a and the oxide 230b are stacked; however, the present invention is not limited to this.
  • a single layer of the oxide 230b or a layered structure of three or more layers may be provided, or each of the oxides 230a and 230b may have a layered structure.
  • the conductor 260 functions as a first gate (also called top gate) electrode, and the conductor 205 functions as a second gate (also called back gate) electrode.
  • insulators 252, 250, and 254 function as a first gate insulator
  • insulators 222 and 224 function as a second gate insulator.
  • the gate insulator is sometimes called a gate insulating layer or a gate insulating film.
  • the conductor 242a functions as one of the source electrode and the drain electrode
  • the conductor 242b functions as the other of the source electrode and the drain electrode. At least part of the region of the oxide 230 overlapping with the conductor 260 functions as a channel formation region.
  • FIG. 2A shows an enlarged view of the vicinity of the channel forming region in FIG. 1B.
  • the oxide 230b includes a region 230bc functioning as a channel formation region of the transistor 200, and regions 230ba and 230bb functioning as a source region or a drain region and provided to sandwich the region 230bc.
  • the region 230bc overlaps the conductor 260 .
  • the region 230bc is provided in a region between the conductors 242a and 242b.
  • the region 230ba is provided so as to overlap with the conductor 242a
  • the region 230bb is provided so as to overlap with the conductor 242b.
  • region 230bc functioning as a channel forming region is a high-resistance region with a lower carrier concentration because it has less oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb.
  • region 230bc can be said to be i-type (intrinsic) or substantially i-type.
  • the region 230ba and the region 230bb functioning as a source region or a drain region have many oxygen vacancies or have a high impurity concentration such as hydrogen, nitrogen, or a metal element, so that the carrier concentration is increased and the resistance is lowered.
  • the regions 230ba and 230bb are n-type regions having a higher carrier concentration and a lower resistance than the region 230bc.
  • the carrier concentration of the region 230bc functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , and 1 ⁇ 10 16 cm It is more preferably less than ⁇ 3 , more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the region 230bc functioning as a channel forming region is not particularly limited, but can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the carrier concentration is equal to or lower than the carrier concentration of the region 230ba and the region 230bb, and equal to or higher than the carrier concentration of the region 230bc.
  • a region may be formed. That is, the region functions as a junction region between the region 230bc and the region 230ba or the region 230bb.
  • the bonding region may have a hydrogen concentration equal to or lower than that of the regions 230ba and 230bb and equal to or higher than that of the region 230bc.
  • the bonding region may have oxygen vacancies equal to or less than those of the regions 230ba and 230bb and equal to or greater than those of the region 230bc.
  • FIG. 2A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b
  • the present invention is not limited to this.
  • each of the above regions may be formed up to oxide 230a as well as oxide 230b.
  • the concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes for each region, and may change continuously within each region. In other words, the closer the region is to the channel formation region, the lower the concentrations of the metal elements and the impurity elements such as hydrogen and nitrogen.
  • metal oxides functioning as semiconductors are preferably used for the oxides 230 (the oxides 230a and 230b) including a channel formation region.
  • an In-M-Zn oxide containing indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium).
  • element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.
  • an In--Ga oxide, an In--Zn oxide, or an indium oxide may be used.
  • the oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions.
  • the atomic ratio of the element M to the main component metal element is the same as the atomic ratio of the element M to the main component metal element in the metal oxide used for the oxide 230b. Larger is preferable.
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. With this structure, diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b can be suppressed.
  • the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the transistor 200 can have high on-state current and high frequency characteristics.
  • the oxides 230a and 230b have a common element other than oxygen as a main component, the defect level density at the interface between the oxides 230a and 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
  • the neighboring composition includes a range of ⁇ 30% of the desired atomic number ratio.
  • the element M it is preferable to use gallium.
  • a metal oxide that can be used for the oxide 230a may be used as the oxide 230b.
  • the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, and the atomic ratio of the sputtering target used for the deposition of the metal oxide. may be
  • the oxide 230b preferably has crystallinity.
  • CAAC-OS c-axis aligned crystal oxide semiconductor
  • CAAC-OS is a metal oxide that has a dense structure with high crystallinity and few impurities and defects (such as oxygen vacancies).
  • heat treatment is performed at a temperature at which the metal oxide does not become polycrystalline (for example, 400° C. or higher and 600° C. or lower), so that the CAAC-OS has a dense structure with higher crystallinity.
  • a temperature at which the metal oxide does not become polycrystalline for example, 400° C. or higher and 600° C. or lower
  • the oxide 230b by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Accordingly, extraction of oxygen from the oxide 230b can be reduced even if heat treatment is performed, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • a transistor including an oxide semiconductor if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to vary, and reliability may be degraded.
  • hydrogen in the vicinity of oxygen vacancies may form defects in which hydrogen enters oxygen vacancies (hereinafter sometimes referred to as V OH ) to generate electrons serving as carriers. Therefore, if oxygen vacancies are included in the region where the channel is formed in the oxide semiconductor, the transistor has normally-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and current flows through the transistor). flow characteristics). Therefore, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in a region where a channel is formed in the oxide semiconductor. In other words, the region in which the channel is formed in the oxide semiconductor preferably has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.
  • an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor, and heat treatment is performed so that the oxide semiconductor is converted from the insulator.
  • Oxygen can be supplied and oxygen vacancies and VOH can be reduced.
  • the on-state current or the field-effect mobility of the transistor 200 might decrease.
  • variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface cause variations in the characteristics of the semiconductor device having transistors.
  • oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor is oxidized and the conductivity is impaired. It may adversely affect the electrical characteristics and reliability of the transistor.
  • the region 230bc functioning as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type.
  • Region 230bb has a high carrier concentration and is preferably n-type.
  • the semiconductor device is configured to efficiently supply oxygen to the region 230bc and suppress oxidation of the conductors 242a, 242b, and 260.
  • the insulator 250 In order to supply oxygen to the region 230bc, it is preferable to use an insulator that easily transmits oxygen as the insulator 250 .
  • An insulator containing excess oxygen is preferably used as the insulator 280 . With this structure, oxygen contained in the insulator 280 can be supplied to the region 230bc through the insulator 250 .
  • an insulator having a function of suppressing diffusion of oxygen is provided near each of the conductors 242a, 242b, and 260. It is preferable to provide In the semiconductor device described in this embodiment, the insulators are the insulators 252, 254, and 275, for example.
  • the insulator 252 preferably has a barrier property against oxygen.
  • the insulator 252 is provided between the insulator 250 and the conductor 242a and between the insulator 250 and the conductor 242b. Therefore, oxygen contained in the insulator 250 can be prevented from diffusing into the conductors 242a and 242b, and oxidation of the conductors 242a and 242b can be suppressed.
  • layers formed on side surfaces of the conductors 242a and 242b (corresponding to layers 244a and 244b described later) in which the amount of oxygen contained in the insulator 250 that diffuses into the conductors 242a and 242b is reduced. can be thinned.
  • the insulator 252 is provided between the insulator 250 and the oxide 230b. Therefore, when heat treatment or the like is performed, desorption of oxygen from the region 230bc of the oxide 230b can be suppressed.
  • the film thickness of the insulator 252 is preferably thin.
  • the insulator 252 preferably has a region with a thickness smaller than that of the insulator 250 .
  • Insulator 250 has a region that contacts the top surface of oxide 230b.
  • oxygen contained in the insulator 250 can be supplied to the region 230bc of the oxide 230b, and excessive supply of oxygen contained in the insulator 250 can be suppressed.
  • the insulator 252 is provided between the insulators 280 and 250 and has a region in contact with the sidewall of the opening of the insulator 280 .
  • oxygen contained in the insulator 280 can be supplied to the insulator 250 and excessive supply of oxygen contained in the insulator 280 can be suppressed.
  • the insulator 254 preferably has a barrier property against oxygen. Insulator 254 is provided between insulator 250 and conductor 260 . Therefore, oxygen contained in the insulator 250 can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Note that the insulator 254 should be at least less permeable to oxygen than the insulator 250 .
  • the insulator 275 it is preferable to use an insulator having a function of suppressing permeation of oxygen.
  • the insulator 275 is provided between the insulator 280 and the conductors 242a and 242b. With this structure, diffusion of oxygen contained in the insulator 280 to the conductors 242a and 242b can be suppressed. Therefore, the oxygen contained in the insulator 280 can prevent the conductors 242a and 242b from being oxidized to increase the resistivity and reduce the on-current.
  • the insulator 275 should be at least less permeable to oxygen than the insulator 250 .
  • the region 230bc functioning as a channel forming region can be i-type or substantially i-type, and the regions 230ba and 230bb functioning as a source region or a drain region can be n-type.
  • a semiconductor device having electrical characteristics can be provided. Further, with the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. For example, even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, or 7 nm or less, or 2 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. Note that the gate length will be described later.
  • miniaturization of the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.
  • the cutoff frequency of the transistor can be, for example, 50 GHz or higher, or 100 GHz or higher in a room temperature environment.
  • a conductive material that is difficult to oxidize a conductive material that has a function of suppressing diffusion of oxygen, or the like is preferably used.
  • the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Accordingly, a decrease in the conductivity of the conductors 242a, 242b, and 260 can be suppressed.
  • the conductors 242a, 242b, and 260 contain at least metal and nitrogen.
  • any one or more of the conductors 242a, 242b, and 260 may have a laminated structure.
  • a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing diffusion of oxygen, or the like is used as a layer in contact with the oxide 230b. good.
  • the conductor 260a is made of a conductive material that is difficult to oxidize or has a function of suppressing the diffusion of oxygen. It is preferable to use a conductive material having
  • a crystalline oxide such as CAAC-OS is preferably used as the oxide 230b.
  • a metal oxide that can be applied to the oxide 230 described above is preferably used.
  • CAAC-OS is an oxide having crystals, and the c-axis of the crystals is substantially perpendicular to the surface of the oxide or the formation surface. Accordingly, extraction of oxygen from the oxide 230b by the conductor 242a or the conductor 242b can be suppressed. In addition, it is possible to suppress the decrease in conductivity of the conductors 242a and 242b.
  • the insulator 282 provided over the insulator 280 is preferably formed by a method by which oxygen can be added to the insulator 280 .
  • the insulator 280 can contain excess oxygen.
  • the semiconductor device in this embodiment mode has a structure in which entry of hydrogen into the transistor 200 is suppressed.
  • an insulator having a function of suppressing diffusion of hydrogen is provided so as to cover the transistor 200 .
  • the insulators are the insulators 212 and 283, for example.
  • An insulator having a function of suppressing diffusion of hydrogen is preferably used as the insulator 212 . Accordingly, diffusion of hydrogen into the transistor 200 from below the insulator 212 can be suppressed.
  • an insulator having a function of suppressing diffusion of hydrogen as the insulator 283 . Accordingly, diffusion of hydrogen into the transistor 200 from above the insulator 283 can be suppressed. In addition, diffusion of hydrogen contained in the insulator 274 to the transistor 200 can be suppressed.
  • FIG. 3 An enlarged view of the vicinity of the channel forming region in FIG. 1B is shown in FIG.
  • the solid arrows shown in FIG. 3 visualize how oxygen diffuses.
  • the dotted arrows shown in FIG. 3 visualize how hydrogen diffuses.
  • FIG. 4A is a cross-sectional view of the transistor 200 in the channel length direction.
  • insulator 252, insulator 250, and insulator 254 function as the first gate insulator.
  • the insulator 252, the insulator 250, and the insulator 254 may be collectively referred to as an insulator 256.
  • insulator 256 has insulator 252 , insulator 250 over insulator 252 , and insulator 254 over insulator 250 .
  • Insulator 256 also functions as a first gate insulator.
  • FIG. 4B shows a cross-sectional view in which the insulator 252, the insulator 250, and the insulator 254 included in FIG. 4A are replaced with the insulator 256.
  • FIG. 4B the conductor 260 is shown as a single layer for simplification of the drawing. As described above, the conductor 260 may have a laminated structure of the conductors 260a and 260b, or may have a laminated structure of three or more layers.
  • the width Lg shown in FIGS. 4A and 4B is the width of the bottom surface of the conductor 260 in the region overlapping with the oxide 230b in a cross-sectional view in the channel length direction.
  • the bottom surface of the conductor 260 in the region overlapping with the oxide 230b in a cross-sectional view in the channel length direction may simply be referred to as the bottom surface of the conductor 260 in the region overlapping with the oxide 230b. That is, the bottom surface of the conductor 260 in the region overlapping with the oxide 230b, which will be described later, can be read as the bottom surface of the conductor 260 in the region overlapping with the oxide 230b in a cross-sectional view in the channel length direction. .
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in the top view of the transistor.
  • the gate length is the width of the bottom surface of the conductor 260 in the region overlapping with the oxide 230b in a cross-sectional view in the channel length direction. That is, the gate length becomes the width Lg shown in FIGS. 4A and 4B.
  • the conductor 260 is provided inside the openings of the insulators 275 and 280 .
  • the sidewall of the opening is perpendicular to the substrate surface or inclined with respect to the substrate surface.
  • the minimum width of the conductor 260 in the region overlapping with the oxide 230b is the width Lg. Therefore, it can be said that the conductor 260 has a region with a width Lg in a cross-sectional view in the channel length direction.
  • the bottom surface of the conductor 260 in the region overlapping with the oxide 230b preferably has a flat region. As shown in FIGS. 4A and 4B, if the bottom surface of conductor 260 in the region overlapping oxide 230b has a flat area, width Lg is the width of the flat area. Since the bottom surface of the conductor 260 in the region overlapping with the oxide 230 b has a flat region, an electric field can be uniformly generated in the channel formation region of the oxide 230 .
  • FIGS. 4A and 4B show a structure in which the bottom surface of the conductor 260 in the region overlapping with the oxide 230b has a flat region, the present invention is not limited to this.
  • the bottom surface of the conductor 260 in the region overlapping with the oxide 230b may have a curved line when viewed in cross section in the channel length direction.
  • FIG. 4C is a cross-sectional view of the transistor 200 in the channel length direction.
  • the bottom surface of conductor 260 in the region overlapping oxide 230b may have flat regions and curved regions. Note that the curved regions are located at both ends of the bottom surface.
  • the point where the curve of the bottom surface on the side of the conductor 242a contacts the side surface of the conductor 260 on the side of the conductor 242a is defined as a point Qa.
  • a point Qb is a point where the curve of the bottom surface on the side of the conductor 242b contacts the side surface of the conductor 260 on the side of the conductor 242b.
  • the width Lg is the length of the line segment connecting the points Qa and Qb.
  • FIG. 4D shows a modification of the transistor 200 shown in FIG. 4B.
  • FIG. 4D is a cross-sectional view of the transistor 200 in the channel length direction.
  • conductor 260 may have an arcuate bottom surface, as shown in FIG. 4D.
  • the arc has a center of curvature P located within the conductor 260 and a radius r.
  • the width Lg is the width of a region where a straight line including the center of curvature P and parallel to the bottom surface of the oxide 230b overlaps with the conductor 260 in a cross-sectional view in the channel length direction. In other words, the width Lg is twice the radius r.
  • 4D is a straight line including the center of curvature P and parallel to the bottom surface of the oxide 230b.
  • the width Lg shown in FIG. 4C may be applied as the gate length of the shape. That is, the width Lg may be calculated by determining the points Qa and Qb for the shape of the bottom surface of the conductor 260 shown in FIG. 4D.
  • the width Lg shown in FIG. 4D may be applied as the gate length of the shape. That is, the width Lg may be calculated by determining the center of curvature P for the shape of the bottom surface of the conductor 260 shown in FIG. 4C.
  • distance L be the distance between the lower end of the conductor 242a and the lower end of the conductor 242b.
  • Distance L corresponds to the channel length of transistor 200 .
  • the channel length is set according to the material used for the conductor 260, the gate length, and the material and film thickness used for the first gate insulator.
  • the channel length may be, for example, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less, and 10 nm or more, 15 nm or more, or 20 nm or more.
  • the upper portion of the oxide 230b overlapping with the opening may be removed.
  • the film thickness of the region of the oxide 230b overlapping the conductor 260 is smaller than the film thickness of the region of the oxide 230b overlapping the conductor 242a.
  • the transistor 200 shown in FIG. 4E is a modification of the transistor 200 shown in FIG. 4B.
  • FIG. 4E is a cross-sectional view of the transistor 200 in the channel length direction.
  • the difference between the thickness of the oxide 230b in the region overlapping with the conductor 260 and the thickness of the oxide 230b in the region overlapping with the conductor 242a is defined as the difference Lt (see FIG. 4E). If the difference Lt is small, the distance L may be regarded as the channel length.
  • a layer 244a may be formed between the conductor 242a and the insulator 256 as shown in FIG. 4F.
  • layer 244b may be formed between conductor 242b and insulator 256 .
  • the transistor 200 may have a layer 244a located between the conductor 242a and the insulator 256 and a layer 244b located between the conductor 242b and the insulator 256.
  • FIG. 4F is a modification of the transistor 200 shown in FIG. 4E.
  • FIG. 4F is a cross-sectional view of the transistor 200 in the channel length direction.
  • the layers 244a and 244b are formed by oxidizing the side surfaces of the conductors 242a and 242b, respectively. Therefore, the layer 244a contains an element included in the conductor 242a and oxygen. In addition, the layer 244b contains an element included in the conductor 242b and oxygen. For example, if conductors 242a and 242b each comprise a metal and nitrogen, then layers 244a and 244b each comprise that metal and oxygen.
  • the length of the layer 244a in the channel length direction in a cross-sectional view in the channel length direction is defined as length Lo (see FIG. 4F).
  • the length of the layer 244b in the channel length direction is the same as or substantially the same as the length Lo.
  • the length Lo is small.
  • length Lo is preferably smaller than width Lg.
  • the length Lo is preferably 1 nm or more and less than 8 nm, and more preferably 2 nm or more and less than 5 nm.
  • a semiconductor device having good electrical characteristics can be provided. Further, a semiconductor device that can be miniaturized or highly integrated can be provided. In addition, a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated can be provided.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequencies such as RF, and the oxygen plasma can act. At this time, the region 230bc can also be irradiated with microwaves or high frequencies such as RF.
  • V OH in the region 230bc can be divided into oxygen vacancies and hydrogen, the hydrogen can be removed from the region 230bc, and the oxygen vacancies can be compensated with oxygen. Therefore, the hydrogen concentration, oxygen vacancies, and VOH in the region 230bc can be reduced, and the carrier concentration can be lowered.
  • the effects of microwaves, high frequencies such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb.
  • the effects of oxygen plasma can be reduced by insulators 271 and 280 provided over oxide 230b and conductor 242 .
  • V OH is reduced and an excessive amount of oxygen is not supplied in the regions 230ba and 230bb during the microwave treatment, so that a decrease in carrier concentration can be prevented.
  • the oxygen injected into the region 230bc has various forms such as oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, atoms or molecules with unpaired electrons, or ions).
  • the oxygen injected into the region 230bc may be one or more of the above forms, and oxygen radicals are particularly preferable.
  • the film quality of the insulator 252 and the insulator 250 can be improved, the reliability of the transistor 200 is improved.
  • oxygen vacancies and V OH can be selectively removed from the oxide semiconductor region 230bc to make the region 230bc i-type or substantially i-type. Furthermore, excessive supply of oxygen to the regions 230ba and 230bb functioning as the source region or the drain region can be suppressed, and the state of the n-type region before the microwave treatment can be maintained. As a result, variations in the electrical characteristics of the transistor 200 can be suppressed, and variation in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.
  • a semiconductor device with little variation in transistor characteristics can be provided by adopting the configuration described above. Moreover, a highly reliable semiconductor device can be provided. Moreover, a semiconductor device having favorable electrical characteristics can be provided. Further, a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a curved surface may be provided between the side surface of the oxide 230b and the top surface of the oxide 230b in a cross-sectional view of the transistor 200 in the channel width direction. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter also referred to as round shape).
  • the radius of curvature of the curved surface is preferably larger than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region without the curved surface.
  • the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and more preferably greater than or equal to 2 nm and less than or equal to 10 nm.
  • the interface between the oxide 230 and the insulator 252 and its vicinity can be Indium contained in the oxide 230 may be unevenly distributed.
  • the vicinity of the surface of the oxide 230 has an atomic ratio close to that of indium oxide or an atomic ratio close to that of In—Zn oxide.
  • At least one of the insulator 212 , the insulator 214 , the insulator 271 , the insulator 275 , the insulator 282 , the insulator 283 , and the insulator 285 is exposed to impurities such as water and hydrogen from the substrate side or the transistor 200 . It preferably functions as a barrier insulating film that suppresses diffusion from above into the transistor 200 .
  • At least one of the insulators 212, 214, 271, 275, 282, 283, and 285 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.) and copper atoms (thus, the above impurities hardly permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (through which oxygen hardly permeates).
  • the insulators 212, 214, 271, 275, 282, 283, and 285 are insulators having a function of suppressing diffusion of water, impurities such as hydrogen, and oxygen. is preferably used, and for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used.
  • the insulator 212, the insulator 275, and the insulator 283 are preferably made of silicon nitride or the like, which has a higher hydrogen barrier property.
  • the insulator 214, the insulator 271, the insulator 282, and the insulator 285 are preferably made of aluminum oxide, magnesium oxide, or the like, which has high functions of capturing and fixing hydrogen. Accordingly, diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214 can be suppressed. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 200 from an interlayer insulating film or the like arranged outside the insulator 285 . Alternatively, diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulators 212 and 214 can be suppressed.
  • the transistor 200 and the semiconductor device with favorable characteristics and high reliability can be manufactured.
  • the insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but part of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 has a polycrystalline structure. may be formed.
  • the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 are multilayers in which a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. It may be a structure. For example, a laminated structure in which a layer of polycrystalline structure is formed on a layer of amorphous structure may be used.
  • insulators 212, 275, and 283 It may also be desirable to reduce the resistivity of insulators 212, 275, and 283.
  • the resistivity of the insulator 212, the insulator 275, and the insulator 283 can be approximately 1 ⁇ 10 13 ⁇ cm, the insulator 212, the insulator 275, and the insulator 283 can be processed using plasma or the like in a manufacturing process of a semiconductor device. Insulator 283 can mitigate charge-up in conductor 205, conductor 242, conductor 260, or conductor 246 in some cases.
  • Each of the insulator 212, the insulator 275, and the insulator 283 preferably has a resistivity of 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the insulator 216, the insulator 274, the insulator 280, and the insulator 285 preferably have a lower dielectric constant than the insulator 214.
  • the parasitic capacitance generated between wirings can be reduced.
  • the insulator 216, the insulator 274, the insulator 280, and the insulator 285 include silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Silicon oxide having vacancies or the like may be used as appropriate.
  • the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260 .
  • the conductor 205 is preferably embedded in an opening formed in the insulator 216 . Also, part of the conductor 205 is embedded in the insulator 214 in some cases.
  • the conductor 205 has a conductor 205a and a conductor 205b.
  • a conductor 205a is provided in contact with the bottom and side walls of the opening.
  • the conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a.
  • the height of the top surface of the conductor 205b approximately matches the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216 .
  • the conductor 205a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N 2 O, NO, NO 2 ), and copper atoms. It is preferable to use a conductive material having a Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 205b.
  • tungsten may be used for the conductor 205b.
  • the conductor 205 may function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 .
  • Vth of the transistor 200 can be increased and off-state current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.
  • the electric resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electric resistivity. Also, the thickness of the insulator 216 is almost the same as that of the conductor 205 . Here, it is preferable to reduce the film thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205 . By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced;
  • the conductor 205 is preferably provided larger than a region of the oxide 230 that does not overlap with the conductors 242a and 242b, as shown in FIG. 1A.
  • the conductor 205 preferably extends also in regions outside the ends of the oxides 230a and 230b in the channel width direction.
  • the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the oxide 230 in the channel width direction.
  • the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode electrically surround the channel formation region of the oxide 230 .
  • a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.
  • a transistor with an S-channel structure represents a transistor structure in which a channel formation region is electrically surrounded by electric fields of one and the other of a pair of gate electrodes.
  • the S-channel structure disclosed in this specification and the like is different from the Fin type structure and the planar type structure.
  • the transistor can have increased resistance to the short channel effect, in other words, a transistor in which the short channel effect is less likely to occur.
  • the conductor 205 is extended to function as wiring.
  • a structure in which a conductor functioning as a wiring is provided under the conductor 205 may be employed.
  • one conductor 205 does not necessarily have to be provided for each transistor.
  • the conductor 205 may be shared by a plurality of transistors.
  • the conductor 205 has a structure in which the conductor 205a and the conductor 205b are stacked; however, the present invention is not limited to this.
  • the conductor 205 may be provided as a single layer or a laminated structure of three or more layers.
  • the insulator 222 and the insulator 224 function as gate insulators.
  • the insulator 222 preferably has a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules). Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224 does.
  • hydrogen for example, at least one of hydrogen atoms and hydrogen molecules
  • oxygen eg, at least one of oxygen atoms and oxygen molecules
  • the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224 does.
  • the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
  • the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 and the oxide 230 .
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • these insulators may be stacked with silicon oxide, silicon oxynitride, or silicon nitride.
  • the insulator 222 may be a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • thinning of gate insulators may cause problems such as leakage current.
  • the gate potential during transistor operation can be reduced while maintaining the physical film thickness.
  • silicon oxide, silicon oxynitride, or the like may be used as appropriate.
  • Examples of the conductor 242 include nitride containing tantalum, nitride containing titanium, nitride containing molybdenum, nitride containing tungsten, nitride containing tantalum and aluminum, It is preferable to use a nitride or the like containing titanium and aluminum. In one aspect of the present invention, nitrides containing tantalum are particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even after absorbing oxygen.
  • the conductor 242a1 and the conductor 242b1 may be collectively referred to as the lower layer of the conductor 242. Further, the conductor 242a2 and the conductor 242b2 may be collectively referred to as an upper layer of the conductor 242 in some cases.
  • the lower layers of the conductor 242 are preferably made of a conductive material that is resistant to oxidation. Accordingly, it is possible to prevent the lower layer of the conductor 242 from being oxidized and the conductivity of the conductor 242 from decreasing. Note that the lower layer of the conductor 242 may have a property of easily absorbing (releasing) hydrogen. As a result, hydrogen in the oxide 230 diffuses into the lower layer of the conductor 242, so that the hydrogen concentration in the oxide 230 can be reduced. Therefore, the transistor 200 can have stable electrical characteristics.
  • the upper layer of the conductor 242 may have the property of easily absorbing hydrogen. As a result, hydrogen absorbed in the lower layer of the conductor 242 diffuses into the upper layer of the conductor 242, so that the concentration of hydrogen in the oxide 230 can be further reduced. Therefore, the transistor 200 can have stable electrical characteristics.
  • the lower layer of the conductor 242 and the upper layer of the conductor 242 are preferably made of conductive materials having the same constituent elements and different chemical compositions.
  • the lower layer of the conductor 242 and the upper layer of the conductor 242 can be continuously formed without being exposed to the atmospheric environment.
  • impurities or moisture from the atmospheric environment can be prevented from adhering to the surface of the lower layer of the conductor 242, and the vicinity of the interface between the lower layer and the upper layer of the conductor 242 can be prevented. can be kept clean.
  • a nitride containing tantalum with a high nitrogen to tantalum atomic ratio is used for the lower layer of the conductor 242
  • a tantalum containing nitride with a low nitrogen to tantalum atomic ratio is used for the upper layer of the conductor 242 .
  • the lower layer of the conductor 242 tantalum with an atomic ratio of nitrogen to tantalum of 1.0 to 2.0, preferably 1.1 to 1.8, more preferably 1.2 to 1.5
  • the upper layer of the conductor 242 has an atomic ratio of nitrogen to tantalum of 0.3 to 1.5, preferably 0.5 to 1.3, more preferably 0.6 to 1.0. of tantalum-containing nitride is used.
  • oxidation of the nitride containing tantalum can be suppressed.
  • the oxidation resistance of the nitride containing tantalum can be enhanced.
  • diffusion of oxygen into the nitride containing tantalum can be suppressed. Therefore, it is preferable to use a nitride containing tantalum, which has a high atomic ratio of nitrogen to tantalum, for the lower layer of the conductor 242 . This can prevent the formation of an oxide layer between the lower layer of the conductor 242 and the oxide 230 or reduce the thickness of the oxide layer.
  • a nitride containing tantalum by lowering the atomic ratio of nitrogen to tantalum, the resistivity of the nitride can be lowered. Therefore, it is preferable to use a nitride containing tantalum, which has a low atomic ratio of nitrogen to tantalum, for the top layer of the conductor 242 . Thereby, a semiconductor device in which wiring delay is suppressed can be manufactured.
  • the structures of the lower layer of the conductor 242 and the upper layer of the conductor 242 are not limited to the above.
  • the lower layer of the conductor 242 and the upper layer of the conductor 242 may have different one or more selected from constituent elements, chemical compositions, and film formation conditions.
  • a nitride containing tantalum may be used as the lower layer of the conductor 242 and a nitride containing titanium may be used as the upper layer of the conductor 242 .
  • the insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b.
  • the insulator 271 preferably functions as a barrier insulating film against at least oxygen. Therefore, the insulator 271 preferably has a function of suppressing diffusion of oxygen. For example, the insulator 271 preferably has a function of suppressing diffusion of oxygen more than the insulator 280 does.
  • an insulator such as silicon nitride, aluminum oxide, or magnesium oxide may be used.
  • the insulator 275 is provided so as to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 271. Specifically, the insulator 275 has regions in contact with the side surfaces of the oxide 230b, the conductor 242a, and the conductor 242b.
  • the insulator 275 preferably has a function of trapping hydrogen and fixing hydrogen.
  • the insulator 275 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide.
  • the insulator 275 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.
  • the insulator 252 functions as part of the gate insulator.
  • a barrier insulating film against oxygen is preferably used.
  • any of the insulators that can be used for the insulator 282 may be used.
  • an insulator containing oxides of one or both of aluminum and hafnium is preferably used.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used.
  • aluminum oxide is used as the insulator 252 .
  • the insulator 252 contains at least oxygen and aluminum.
  • the insulator 252 is provided in contact with the side surfaces of the conductor 242, the insulator 271, the insulator 275, and the insulator 280, respectively. Therefore, the side surfaces of the conductor 242 are oxidized and formation of an oxide film on the side surfaces can be reduced. Accordingly, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.
  • the thickness of the insulator 252 is preferably thin.
  • the insulator 252 has a thickness of 0.1 nm to 5.0 nm, preferably 0.5 nm to 3.0 nm, more preferably 1.0 nm to less than 3.0 nm. In this case, at least part of the insulator 252 may have a region with the thickness as described above. Further, the thickness of the insulator 252 is preferably thinner than the thickness of the insulator 250 . In this case, at least part of the insulator 252 may have a region thinner than the insulator 250 .
  • the ALD method includes a thermal ALD (thermal ALD) method in which a precursor and a reactant react with only thermal energy, a PEALD (plasma enhanced ALD) method using a plasma-excited reactant, and the like.
  • thermal ALD thermal ALD
  • PEALD plasma enhanced ALD
  • film formation can be performed at a lower temperature by using plasma, which is preferable in some cases.
  • the ALD method can deposit atoms one layer at a time, it is possible to form extremely thin films, to form structures with a high aspect ratio, to form films with few defects such as pinholes, and to improve coverage. There are effects such as excellent film formation and low temperature film formation. Therefore, the insulator 252 can be formed with a thin film thickness as described above with good coverage on the side surfaces of the opening formed in the insulator 280 or the like.
  • a film formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods.
  • quantification of impurities secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), or Auger electron spectroscopy (AES: Auger Electron Spectroscopy) can be performed using
  • the region 230bc can be formed. Oxygen vacancies and VOH that are formed can be reduced, and excessive oxidation of the regions 230ba and 230bb can be suppressed in some cases. In such a case, the structure without the insulator 252 can simplify the manufacturing process of the semiconductor device and improve productivity.
  • the insulator 250 functions as part of the gate insulator. Insulator 250 is preferably placed in contact with the top surface of insulator 252 .
  • the insulator 250 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 250 contains at least oxygen and silicon.
  • the insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen.
  • the thickness of the insulator 250 is preferably from 0.1 nm to 20 nm, more preferably from 0.5 nm to 15 nm.
  • the thickness of the insulator 250 is preferably 0.5 nm or more and 10 nm or less, more preferably 0.5 nm or more and 5 nm or less. is more preferred.
  • the insulator 250 may have at least a portion of the region with the film thickness as described above.
  • the insulator 250 may have a two-layer laminated structure of an insulator 250a and an insulator 250b on the insulator 250a.
  • the lower insulator 250a is formed using an insulator through which oxygen easily permeates
  • the upper insulator 250b is formed using an insulator through which oxygen diffuses.
  • the insulator 250a is preferably formed using the material that can be used for the insulator 250, and the insulator 250b is preferably an insulator containing an oxide of one or both of aluminum and hafnium.
  • the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used.
  • hafnium oxide is used for the insulator 250b.
  • the insulator 250b contains at least oxygen and hafnium.
  • the thickness of the insulator 250b is 0.5 nm to 5.0 nm, preferably 1.0 nm to 5.0 nm, more preferably 1.0 nm to 3.0 nm. In this case, at least a part of the insulator 250b may have a region with the thickness as described above.
  • an insulating material that is a high-k material with a high dielectric constant may be used for the insulator 250b.
  • the gate insulator has a stacked structure of the insulators 250a and 250b, the stacked structure can be stable against heat and have a high relative dielectric constant. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical film thickness of the gate insulator. Also, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced. Therefore, the withstand voltage of the insulator 250 can be increased.
  • EOT equivalent oxide thickness
  • the insulator 254 functions as part of the gate insulator.
  • a barrier insulating film against hydrogen is preferably used as the insulator 254 . Accordingly, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the insulator 250 and the oxide 230b.
  • an insulator that can be used for the insulator 283 described above may be used.
  • silicon nitride deposited by a PEALD method may be used as the insulator 254 .
  • insulator 254 comprises at least nitrogen and silicon.
  • the insulator 254 may further have a barrier property against oxygen. Accordingly, diffusion of oxygen contained in the insulator 250 to the conductor 260 can be suppressed.
  • the insulator 250 has a two-layer structure as illustrated in FIG. 2B
  • an insulator such as hafnium oxide which has a function of suppressing permeation of impurities such as hydrogen and oxygen, such as hafnium oxide
  • the insulator 250b can also have the function of the insulator 254 .
  • the structure without the insulator 254 can simplify the manufacturing process of the semiconductor device and improve productivity.
  • a conductor 260 functions as a first gate electrode of the transistor 200 .
  • the conductor 260 preferably has a conductor 260a and a conductor 260b disposed over the conductor 260a.
  • conductor 260a is preferably arranged to wrap the bottom and side surfaces of conductor 260b.
  • the top surface of conductor 260 is substantially aligned with the top surface of insulator 250 .
  • the conductor 260 has a two-layer structure of conductors 260a and 260b, but may have a single-layer structure or a laminated structure of three or more layers.
  • the conductor 260a preferably uses a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms.
  • a conductive material having a function of suppressing diffusion of oxygen eg, at least one of oxygen atoms and oxygen molecules is preferably used.
  • the conductor 260 since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity.
  • the conductor 260b can use a conductive material whose main component is tungsten, copper, or aluminum. Further, the conductor 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials.
  • the height of the bottom surface of the region of the conductor 260 where the conductor 260 and the oxide 230b do not overlap with each other is based on the bottom surface of the insulator 222 in the channel width direction of the transistor 200.
  • the height is preferably less than the height of the bottom surface of oxide 230b.
  • the conductor 260 functioning as a gate electrode covers the side surface and top surface of the channel formation region of the oxide 230b with the insulator 250 or the like interposed therebetween. Easier to work on the whole. Therefore, the on current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.
  • the insulator 280 is provided on the insulator 275, and openings are formed in regions where the insulator 250 and the conductor 260 are provided. Also, the upper surface of the insulator 280 may be flattened.
  • the insulator 280 functioning as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.
  • the insulator 280 is preferably provided using a material similar to that of the insulator 216, for example.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • a material such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies is preferable because a region containing oxygen that is released by heating can be easily formed.
  • the insulator 282 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 282 preferably functions as a barrier insulating film that suppresses permeation of oxygen.
  • an insulator such as a metal oxide having an amorphous structure such as aluminum oxide may be used. In this case, the insulator 282 contains at least oxygen and aluminum.
  • the insulator 282 having a function of trapping impurities such as hydrogen in contact with the insulator 280 in a region sandwiched between the insulator 212 and the insulator 283, hydrogen and the like contained in the insulator 280 and the like are provided. of impurities can be captured, and the amount of hydrogen in the region can be made constant.
  • the insulator 282 it is preferable to deposit aluminum oxide by a sputtering method, and it is more preferable to deposit aluminum oxide by a pulse DC sputtering method using an aluminum target in an atmosphere containing oxygen gas.
  • a pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • RF (Radio Frequency) power may be applied to the substrate.
  • the amount of oxygen injected into layers below the insulator 282 can be controlled by the amount of RF power applied to the substrate.
  • the smaller the RF power the smaller the amount of oxygen injected into a layer below the insulator 282, and the oxygen amount is likely to be saturated even if the thickness of the insulator 282 is thin. Also, the amount of oxygen injected into the layer below the insulator 282 increases as the RF power increases.
  • RF power is, for example, 0 W/cm 2 or more and 1.86 W/cm 2 or less.
  • the amount of oxygen suitable for the characteristics of the transistor can be changed and implanted depending on the RF power when the insulator 282 is formed. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be implanted.
  • the RF frequency is preferably 10 MHz or higher. It is typically 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate.
  • the insulator 282 may have a two-layer laminated structure of an insulator 282a and an insulator 282b on the insulator 282a.
  • the insulators 282a and 282b are preferably formed from the same material by different methods.
  • the RF power applied to the substrate when the insulator 282a is formed and the insulation It is preferable that the RF power applied to the substrate when depositing the insulator 282b is different. Lower than RF power is more preferred.
  • the insulator 282a is deposited with RF power applied to the substrate of 0 W/cm 2 or more and 0.62 W/cm 2 or less, and the RF power applied to the substrate of the insulator 282b is 1.86 W/cm 2 .
  • the RF power applied to the substrate when the insulator 282a is formed may be higher than the RF power applied to the substrate when the insulator 282b is formed.
  • the insulator 282a is deposited with RF power applied to the substrate of 1.86 W/cm 2 or less, and the insulator 282b is deposited with RF power applied to the substrate of 0 W/cm 2 or more and 0.62 W/cm 2 or more .
  • a film is formed as follows. More specifically, the insulator 282a is deposited with RF power applied to the substrate of 1.86 W/cm 2 , and the insulator 282b is deposited with RF power applied to the substrate of 0.62 W/cm 2 . With such a structure, the amount of oxygen supplied to the insulator 280 can be increased.
  • the thickness of the insulator 282a is 1 nm to 20 nm, preferably 1.5 nm to 15 nm, more preferably 2 nm to 10 nm, further preferably 3 nm to 8 nm.
  • the insulator 282a can have an amorphous structure regardless of RF power.
  • the insulator 282a has an amorphous structure
  • the insulator 282b can easily have an amorphous structure, and the insulator 282 can have an amorphous structure.
  • the insulator 282a and the insulator 282b have a laminated structure made of the same material, but the present invention is not limited to this.
  • the insulator 282a and the insulator 282b may be laminated structures made of different materials.
  • Insulator 283 contacts a portion of the top surface of insulator 214, the side surface of insulator 216, the side surface of insulator 222, the side surface of insulator 275, the side surface of insulator 280, and the side surface and top surface of insulator 282, respectively. .
  • the insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen into the insulator 280 from above. Insulator 283 is placed over insulator 282 .
  • a nitride containing silicon such as silicon nitride or silicon nitride oxide is preferably used.
  • silicon nitride deposited by a sputtering method may be used as the insulator 283 .
  • a silicon nitride film with high density can be formed.
  • silicon nitride deposited by a PEALD method or a CVD method may be stacked over silicon nitride deposited by a sputtering method.
  • the conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. Further, the conductor 240a and the conductor 240b may have a laminated structure.
  • the first conductor provided near the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271 includes:
  • a conductive material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used.
  • the conductive material having a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or stacked layers.
  • impurities such as water and hydrogen contained in a layer above the insulator 283 can be prevented from entering the oxide 230 through the conductors 240a and 240b.
  • a barrier insulating film that can be used for the insulator 275 or the like may be used as the insulator 241a and the insulator 241b.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used for the insulators 241a and 241b.
  • the insulators 241a and 241b are provided in contact with the insulators 283, 282, and 271; can be suppressed from being mixed into the oxide 230 through the
  • silicon nitride is suitable because it has a high blocking property against hydrogen.
  • oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.
  • the insulator 241a and the insulator 241b have a laminated structure as shown in FIG. It is preferable to use a combination of a barrier insulating film and a barrier insulating film against hydrogen.
  • aluminum oxide deposited by the ALD method may be used as the first insulator, and silicon nitride deposited by the PEALD method may be used as the second insulator.
  • oxidization of the conductor 240 can be suppressed, and moreover, entry of hydrogen into the conductor 240 can be reduced.
  • the conductors 246 (the conductors 246a and 246b) functioning as wirings may be arranged in contact with the top surface of the conductor 240a and the top surface of the conductor 240b.
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 246 .
  • the conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include a capacitor element, a resistance element, a switch element, a light emitting element, a memory element, and the like.
  • Insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. or nitrides with silicon and hafnium.
  • Insulators with a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and an empty silicon oxide. There are silicon oxide with pores, resin, and the like.
  • insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in stacks.
  • insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • Metal oxides such as tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from among the above, an alloy containing the above-described metal elements as a component, or an alloy or the like in which the above-described metal elements are combined.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like are used. is preferred. Also, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a conductive material or a material that maintains conductivity even after absorbing oxygen.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a stacked-layer structure in which the above-described material containing the metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductor functioning as a gate electrode it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed.
  • a conductive material containing the metal element and nitrogen described above may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may also be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, and the like are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.
  • the metal oxide is an In-M-Zn oxide having indium, the element M and zinc.
  • the element M is aluminum, gallium, yttrium, or tin.
  • Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.
  • the element M there are cases where a plurality of the above elements may be combined.
  • the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.
  • an oxide containing indium (In), gallium (Ga), and zinc (Zn) is preferably used for a semiconductor layer of a transistor.
  • an oxide containing indium (In), aluminum (Al), and zinc (Zn) also referred to as IAZO
  • IAZO indium (In), aluminum (Al), gallium (Ga), and zinc
  • IAGZO or IGAZO oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) may be used for the semiconductor layer.
  • nitrogen-containing metal oxides may also be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may also be referred to as a metal oxynitride.
  • Crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal. (poly crystal) and the like.
  • the shape of the peak of the XRD spectrum is almost bilaterally symmetrical.
  • the shape of the peak of the XRD spectrum is left-right asymmetric.
  • the asymmetric shape of the peaks in the XRD spectra demonstrates the presence of crystals in the film or substrate. In other words, the film or substrate cannot be said to be in an amorphous state unless the shape of the peaks in the XRD spectrum is symmetrical.
  • the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nano beam electron diffraction pattern) observed by nano beam electron diffraction (NBED).
  • a diffraction pattern also referred to as a nano beam electron diffraction pattern
  • NBED nano beam electron diffraction
  • a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state.
  • a spot-like pattern is observed instead of a halo. For this reason, it is presumed that it cannot be concluded that the In-Ga-Zn oxide deposited at room temperature is in an intermediate state, neither single crystal nor polycrystal, nor amorphous state, and is in an amorphous state. be done.
  • oxide semiconductors may be classified differently from the above when their structures are focused. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
  • CAAC-OS is an oxide semiconductor that includes a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the formation surface of the CAAC-OS film, or the normal direction to the surface of the CAAC-OS film.
  • a crystalline region is a region having periodicity in atomic arrangement. If the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement.
  • CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and has no obvious orientation in the ab plane direction.
  • the CAAC-OS includes a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (
  • In layer a layer containing indium (In) and oxygen
  • Ga gallium
  • Zn zinc
  • oxygen oxygen
  • it tends to have a layered crystal structure (also referred to as a layered structure) in which (Ga, Zn) layers are laminated.
  • the (Ga, Zn) layer may contain indium.
  • the In layer may contain gallium.
  • the In layer may contain zinc.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM (Transmission Electron Microscope) image.
  • a plurality of bright points are observed in the electron beam diffraction pattern of the CAAC-OS film.
  • a certain spot and another spot are observed at point-symmetrical positions with respect to the spot of the incident electron beam that has passed through the sample (also referred to as a direct spot) as the center of symmetry.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is less likely to occur in CAAC-OS.
  • CAAC-OS since the crystallinity of an oxide semiconductor may be deteriorated due to contamination of impurities, generation of defects, or the like, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS is resistant to heat and has high reliability.
  • CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for a transistor including a metal oxide in a channel formation region (sometimes referred to as an OS transistor), the degree of freedom in the manufacturing process can be increased.
  • an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than the nanocrystal size (for example, 1 nm or more and 30 nm or less)
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam with a probe diameter close to or smaller than the nanocrystal size for example, 1 nm or more and 30 nm or less
  • CAC-OS is, for example, one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called mosaic or patch.
  • the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In--Ga--Zn oxide are denoted by [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the CAC-OS in the In—Ga—Zn oxide means a region containing Ga as a main component and a region containing In as a main component in a material structure containing In, Ga, Zn, and O. Each region is a mosaic, and refers to a configuration in which these regions exist randomly. Therefore, CAC-OS is presumed to have a structure in which metal elements are unevenly distributed.
  • an EDX mapping obtained using energy dispersive X-ray spectroscopy shows that a region containing In as a main component It can be confirmed that the (first region) and the region (second region) containing Ga as the main component are unevenly distributed and have a mixed structure.
  • the first region is a region with higher conductivity than the second region. That is, when carriers flow through the first region, conductivity as a metal oxide is developed. Therefore, by distributing the first region in the form of a cloud in the metal oxide, a high field effect mobility ( ⁇ ) can be realized.
  • the second region is a region with higher insulation than the first region. That is, the distribution of the second region in the metal oxide can suppress the off current.
  • an oxide semiconductor with low carrier concentration is preferably used for a transistor.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm ⁇ 3 or less, preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less . 3 or less, more preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor with a low carrier concentration is sometimes referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.
  • the impurities in the oxide semiconductor refer to, for example, substances other than the main components of the oxide semiconductor. For example, an element whose concentration is less than 0.1 atomic percent can be said to be an impurity.
  • the concentration of silicon or carbon in the oxide semiconductor is 2 ⁇ 10 atoms/cm or less, preferably 2 ⁇ 10 17 atoms/cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms/cm 3 , preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less. , more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • the oxide semiconductor reacts with oxygen that bonds to a metal atom to form water, which may cause oxygen vacancies.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated.
  • part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, hydrogen in the oxide semiconductor is preferably reduced as much as possible.
  • the hydrogen concentration in the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • a layered substance is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds such as van der Waals forces that are weaker than covalent or ionic bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Layered substances include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds that contain chalcogens.
  • Chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides applicable as semiconductor layers include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), Tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (typically ZrSe 2 ), and the like.
  • a in each figure shows a top view.
  • B in each figure is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 in A in each figure, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in A in each figure, and is also a cross-sectional view of the transistor 200 in the channel width direction.
  • D in each figure is a cross-sectional view of a portion indicated by a dashed line A5-A6 in A in each figure.
  • some elements are omitted for clarity of the drawing.
  • an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. etc. can be used as appropriate for film formation.
  • Sputtering methods include an RF sputtering method using a high-frequency power source as a power source for sputtering, a DC sputtering method using a DC power source, and a pulse DC sputtering method in which the voltage applied to the electrodes is changed in a pulsed manner.
  • the RF sputtering method is mainly used for forming an insulating film
  • the DC sputtering method is mainly used for forming a metal conductive film.
  • the pulse DC sputtering method is mainly used when forming a film of a compound such as an oxide, a nitride, or a carbide by a reactive sputtering method.
  • the plasma CVD method can obtain high-quality films at relatively low temperatures.
  • the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed.
  • wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, and the like included in the semiconductor device.
  • a thermal CVD method that does not use plasma does not cause such plasma damage, so that the yield of semiconductor devices can be increased.
  • the thermal CVD method does not cause plasma damage during film formation, a film with few defects can be obtained.
  • the CVD method and ALD method are different from the sputtering method, in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method, such as the CVD method, which has a high film formation rate.
  • a film of any composition can be deposited depending on the flow rate ratio of the raw material gases.
  • the CVD method it is possible to form a film whose composition is continuously changed by changing the flow rate ratio of the source gas while forming the film.
  • the time required for film formation is reduced compared to the case where film is formed using multiple film formation chambers, because the time required for transportation or pressure adjustment is not required. can do. Therefore, productivity of semiconductor devices can be improved in some cases.
  • a film of any composition can be formed by simultaneously introducing different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles for each precursor.
  • a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 10A to 10D).
  • the insulator 212 is preferably deposited by a sputtering method.
  • the hydrogen concentration in the insulator 212 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • the film formation of the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
  • silicon nitride is deposited as the insulator 212 by a pulse DC sputtering method using a silicon target in an atmosphere containing nitrogen gas.
  • a pulse DC sputtering method it is possible to suppress the generation of particles due to arcing on the target surface, so that the film thickness distribution can be made more uniform.
  • the rise and fall of the discharge can be steeper than the high-frequency voltage. As a result, power can be supplied to the electrodes more efficiently, and the sputtering rate and film quality can be improved.
  • an insulator such as silicon nitride
  • impurities such as water and hydrogen
  • diffusion of impurities such as water and hydrogen contained in a layer below the insulator 212 can be suppressed.
  • an insulator such as silicon nitride through which copper is difficult to permeate as the insulator 212, even if a metal such as copper that is easily diffused is used as a conductor in a layer (not shown) below the insulator 212, the metal does not easily pass through. The upward diffusion through the insulator 212 can be suppressed.
  • an insulator 214 is formed over the insulator 212 (see FIGS. 10A to 10D).
  • the insulator 214 is preferably deposited by a sputtering method.
  • the hydrogen concentration in the insulator 214 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • the film formation of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
  • aluminum oxide is deposited as the insulator 214 by a pulse DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas.
  • the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • RF power may now be applied to the substrate.
  • the amount of oxygen injected into layers below the insulator 214 can be controlled by the amount of RF power applied to the substrate.
  • the RF power is 0 W/cm 2 or more and 1.86 W/cm 2 or less.
  • the amount of oxygen suitable for the characteristics of the transistor can be changed and implanted according to the RF power when the insulator 214 is formed. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be implanted.
  • the RF frequency is preferably 10 MHz or higher. It is typically 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate.
  • the insulator 214 it is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of trapping and fixing hydrogen. Accordingly, hydrogen contained in the insulator 216 or the like can be captured or fixed, and diffusion of the hydrogen to the oxide 230 can be prevented.
  • a metal oxide having an amorphous structure such as aluminum oxide
  • aluminum oxide having an amorphous structure aluminum oxide having an amorphous structure as the insulator 214 because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor 200 and the semiconductor device with favorable characteristics and high reliability can be manufactured.
  • a silicon oxide film is formed as the insulator 216 by a pulse DC sputtering method using a silicon target in an atmosphere containing oxygen gas.
  • the pulse DC sputtering method the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • the insulators 212, 214, and 216 are preferably formed continuously without being exposed to the atmosphere.
  • a multi-chamber film deposition apparatus may be used.
  • the insulator 212, the insulator 214, and the insulator 216 are formed with reduced hydrogen in the films, and the entry of hydrogen into the films between the film formation steps can be reduced. can be done.
  • Openings include, for example, grooves and slits. Also, an area in which an opening is formed may be referred to as an opening. Wet etching may be used to form the openings, but dry etching is preferable for fine processing.
  • the insulator 214 it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 forming the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator 214 .
  • a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as a dry etching device.
  • a capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency voltage to one electrode of the parallel plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel plate electrodes. Alternatively, a high-frequency voltage having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, high-frequency voltages having different frequencies may be applied to parallel plate electrodes.
  • a dry etching apparatus having a high density plasma source can be used.
  • a dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus.
  • ICP inductively coupled plasma
  • the conductive film preferably contains a conductor having a function of suppressing permeation of oxygen.
  • a conductor having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of a conductor having a function of suppressing permeation of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a titanium nitride film is formed as a conductive film to be the conductor 205a.
  • a metal nitride as a lower layer of the conductor 205b, oxidation of the conductor 205b by the insulator 216 or the like can be suppressed.
  • diffusion of the metal to the outside from the conductor 205a can be prevented.
  • a conductive film to be the conductor 205b is formed.
  • the conductive film tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used.
  • the conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, tungsten is deposited as the conductive film.
  • part of the conductive film to be the conductor 205a and the conductive film to be the conductor 205b are removed to expose the insulator 216 (see FIGS. 10A to 10D).
  • conductors 205a and 205b remain only in the openings. Note that part of the insulator 216 is removed by the CMP treatment in some cases.
  • an insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 11A to 11D).
  • an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited.
  • the insulator containing oxides of one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • hafnium-zirconium oxide is preferably used.
  • Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has barrier properties against hydrogen and water, diffusion of hydrogen and water contained in structures provided around the transistor 200 into the transistor 200 through the insulator 222 is suppressed. , the generation of oxygen vacancies in the oxide 230 can be suppressed.
  • the film formation of the insulator 222 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 222 is formed using hafnium oxide by an ALD method.
  • the heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • oxygen gas may be about 20%.
  • heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less.
  • the heat treatment after the insulator 222 is formed, treatment is performed at a temperature of 400° C. for 1 hour at a flow ratio of nitrogen gas to oxygen gas of 4:1. Impurities such as water and hydrogen contained in the insulator 222 can be removed by the heat treatment. In the case where an oxide containing hafnium is used as the insulator 222, the insulator 222 may be partly crystallized by the heat treatment. Further, the heat treatment can be performed at a timing such as after the insulator 224 is formed.
  • an insulating film 224A is formed over the insulator 222 (see FIGS. 11A to 11D).
  • the insulating film 224A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film is formed as the insulating film 224A by a sputtering method.
  • the hydrogen concentration in the insulating film 224A can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Since the insulating film 224A is in contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • an oxide film 230A and an oxide film 230B are formed in order on the insulating film 224A (see FIGS. 11A to 11D).
  • the oxide films 230A and 230B are preferably formed continuously without being exposed to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230A and 230B. can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A and the oxide film 230B are preferably formed by using the ALD method because films with uniform thickness can be formed even in trenches or openings with a large aspect ratio.
  • the use of the PEALD method is preferable because the oxide films 230A and 230B can be formed at a lower temperature than the thermal ALD method.
  • the sputtering method is used to form the oxide films 230A and 230B.
  • the oxide film 230A and the oxide film 230B are formed by sputtering
  • oxygen or a mixed gas of oxygen and noble gas is used as the sputtering gas.
  • the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased.
  • the above oxide film is formed by a sputtering method, the above In-M-Zn oxide target or the like can be used.
  • part of the oxygen contained in the sputtering gas may be supplied to the insulator 224 when forming the oxide film 230A. Therefore, the percentage of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230B is formed by a sputtering method, if the percentage of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, oxygen-excess oxidation occurs. A material semiconductor is formed. A transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region has relatively high reliability. However, one embodiment of the present invention is not limited to this.
  • an oxygen-deficient oxide semiconductor is formed by setting the oxygen content in the sputtering gas to 1% to 30%, preferably 5% to 20%. be.
  • a transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region has relatively high field-effect mobility.
  • the crystallinity of the oxide film can be improved by forming the film while heating the substrate.
  • a film is formed using Note that each oxide film may be formed in accordance with the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and the atomic ratio.
  • the insulating film 224A, the oxide film 230A, and the oxide film 230B are preferably formed by a sputtering method without being exposed to the atmosphere.
  • a multi-chamber film deposition apparatus may be used.
  • the insulating film 224A, the oxide film 230A, and the oxide film 230B can be prevented from being mixed with hydrogen between the film formation steps.
  • the heat treatment may be performed within a temperature range in which the oxide films 230A and 230B are not polycrystallized, and may be performed at 250° C. to 650° C., preferably 400° C. to 600° C.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • oxygen gas may be about 20%.
  • heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less.
  • the heat treatment is performed at a temperature of 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • Impurities such as carbon, water, and hydrogen in the oxide films 230A and 230B can be reduced by such heat treatment including oxygen gas.
  • the crystallinity of the oxide film 230B can be improved, and a denser structure can be obtained.
  • the crystal regions in the oxide films 230A and 230B can be increased, and the in-plane variations in the crystal regions in the oxide films 230A and 230B can be reduced. Therefore, in-plane variations in electrical characteristics of the transistor 200 can be reduced.
  • hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B moves to the insulator 222 and is absorbed into the insulator 222.
  • hydrogen in insulator 216 , insulating film 224 A, oxide film 230 A, and oxide film 230 B diffuses into insulator 222 . Therefore, although the hydrogen concentration in the insulator 222 increases, the hydrogen concentrations in the insulator 216, the insulating film 224A, the oxide films 230A, and the oxide films 230B decrease.
  • the insulating film 224A functions as a gate insulator of the transistor 200, and the oxide films 230A and 230B function as channel formation regions of the transistor 200. Therefore, the transistor 200 including the insulating film 224A, the oxide films 230A, and the oxide films 230B with reduced hydrogen concentration is preferable because it has high reliability.
  • a conductive film 242A is formed on the oxide film 230B (see FIGS. 11A to 11D).
  • the conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 242A may be formed using tantalum nitride by a sputtering method.
  • heat treatment may be performed before the conductive film 242A is formed. The heat treatment may be performed under reduced pressure to continuously form the conductive film 242A without exposure to the air.
  • the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment mode, the temperature of the heat treatment is set to 200.degree.
  • an insulating film 271A is formed over the conductive film 242A (see FIGS. 11A to 11D).
  • the insulating film 271A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 271A is preferably an insulating film having a function of suppressing permeation of oxygen.
  • an aluminum oxide film or a silicon nitride film may be formed by a sputtering method.
  • a silicon nitride film and a silicon oxide film over the silicon nitride film may be formed by sputtering as the insulating film 271A.
  • the conductive film 242A and the insulating film 271A are preferably formed by a sputtering method without being exposed to the air.
  • a multi-chamber film deposition apparatus may be used. Accordingly, the conductive film 242A and the insulating film 271A can be formed with reduced hydrogen in the films, and further, entry of hydrogen into the films between film formation steps can be reduced. Further, in the case of providing a hard mask over the insulating film 271A, a film to be the hard mask may be formed continuously without being exposed to the atmosphere.
  • the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A are processed into an island shape by a lithography method, so that the insulator 224, the oxide 230a, the oxide 230b, and the conductive film 224A are formed.
  • a layer 242B and an insulating layer 271B are formed (see FIGS. 12A-12D).
  • the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B are formed so as to overlap with the conductor 205 at least partially.
  • a dry etching method or a wet etching method can be used for the above processing. Processing by the dry etching method is suitable for fine processing.
  • the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A may be processed under different
  • the resist is first exposed through a mask.
  • the exposed regions are then removed or left behind using a developer to form a resist mask.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching treatment through the resist mask.
  • a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.
  • a hard mask made of an insulator or conductor may be used under the resist mask.
  • an insulating film or a conductive film that serves as a hard mask material is formed over the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do.
  • the etching of the conductive film 242A or the like may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the conductive film 242A or the like.
  • the insulating layer 271B is used as a hard mask.
  • the conductive layer 242B does not have curved surfaces between the side surfaces and the top surface, as shown in FIGS. 12B to 12D.
  • the conductors 242a and 242b shown in FIGS. 1B and 1D have angular ends where the side surface and the top surface intersect. Since the end portion where the side surface and the top surface of the conductor 242 intersect is angular, the cross-sectional area of the conductor 242 is larger than when the end portion has a curved surface. Accordingly, the resistance of the conductor 242 is reduced, so that the on current of the transistor 200 can be increased.
  • side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be tapered.
  • a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface.
  • the angle formed by the inclined side surface and the substrate surface (hereinafter sometimes referred to as taper angle) is preferably less than 90°.
  • the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may have a taper angle of, for example, 60° or more and less than 90°. By tapering the side surface in this manner, the coverage of the insulator 275 or the like is improved in subsequent steps, and defects such as voids can be reduced.
  • the structure is not limited to the above, and the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be substantially perpendicular to the top surface of the insulator 222.
  • the area can be reduced and the density can be increased.
  • a byproduct generated in the etching step is formed in layers on side surfaces of the insulator 224, the oxides 230a and 230b, the conductive layer 242B, and the insulating layer 271B.
  • the layered byproduct is formed between the insulator 224 , the oxide 230 a , the oxide 230 b , the conductive layer 242 B, the insulating layer 271 B, and the insulator 275 . Therefore, the layered byproduct formed in contact with the top surface of the insulator 222 is preferably removed.
  • an insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 13A to 13D).
  • insulator 275 is preferably in close contact with the top surface of insulator 222 and the side surface of insulator 224 .
  • the insulator 275 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • An insulating film having a function of suppressing permeation of oxygen is preferably used as the insulator 275 .
  • silicon nitride may be deposited by ALD.
  • aluminum oxide is deposited by a sputtering method, and silicon nitride is deposited thereover by a PEALD method.
  • the insulator 275 has such a stacked-layer structure, the function of suppressing diffusion of water, impurities such as hydrogen, and oxygen may be improved.
  • the oxides 230a, 230b, and the conductive layer 242B can be covered with the insulator 275 and the insulating layer 271B, which have a function of suppressing diffusion of oxygen. Accordingly, direct diffusion of oxygen from the insulator 280 or the like to the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B in a later step can be reduced.
  • an insulating film to be the insulator 280 is formed on the insulator 275 .
  • the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film may be formed by a sputtering method.
  • the insulator 280 containing excess oxygen can be formed.
  • the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Note that heat treatment may be performed before the insulating film is formed.
  • the heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the air.
  • moisture and hydrogen adsorbed to the surface of the insulator 275 or the like are removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b and the insulator 224 are reduced. be able to.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the insulating film to be the insulator 280 is subjected to CMP treatment to form the insulator 280 with a flat upper surface (see FIGS. 13A to 13D).
  • CMP treatment to form the insulator 280 with a flat upper surface.
  • a silicon nitride film may be formed over the insulator 280 by a sputtering method, for example, and CMP treatment may be performed until the silicon nitride reaches the insulator 280 .
  • part of the insulator 280, part of the insulator 275, part of the insulating layer 271B, and part of the conductive layer 242B are processed to form an opening reaching the oxide 230b.
  • the opening is preferably formed so as to overlap with the conductor 205 .
  • an insulator 271a, an insulator 271b, a conductor 242a, and a conductor 242b are formed (see FIGS. 14A to 14D).
  • the side surfaces of the insulator 280, the insulator 275, the insulator 271, and the conductor 242 may be tapered.
  • the taper angle of insulator 280 may be greater than the taper angle of conductor 242 .
  • the upper portion of oxide 230b may be removed when forming the opening.
  • a dry etching method or a wet etching method can be used for processing part of the insulator 280, part of the insulator 275, part of the insulating layer 271B, and part of the conductive layer 242B. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions. For example, part of the insulator 280 is processed by a dry etching method, part of the insulator 275 and part of the insulating layer 271B are processed by a wet etching method, and part of the conductive layer 242B is processed by a dry etching method. You may
  • the impurity adheres to the side surface of the oxide 230a, the top surface and side surface of the oxide 230b, the side surface of the conductor 242, the side surface of the insulator 280, or the like, or diffuses into these.
  • a step of removing such impurities may be performed.
  • the dry etching may form a damaged region on the surface of the oxide 230b. Such damaged areas may be removed.
  • the impurities include components contained in the insulator 280, the insulator 275, part of the insulating layer 271B, and the conductive layer 242B, components contained in a member used in an apparatus used for forming the opening, It may be caused by components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.
  • impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, impurities such as aluminum and silicon are preferably removed from the surface of oxide 230b and its vicinity. Further, it is preferable that the concentration of the impurity is reduced.
  • the concentration of aluminum atoms on and near the surface of the oxide 230b may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, and 1.0 atomic % or less. Atom % or less is more preferable, and less than 0.3 atomic % is even more preferable.
  • the regions with low crystallinity of the oxide 230b are preferably reduced or removed.
  • the oxide 230b have a layered CAAC structure.
  • the CAAC structure up to the lower end of the drain of the oxide 230b.
  • the conductor 242a or the conductor 242b and its vicinity function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain edge, which significantly affects the drain breakdown voltage, the low crystallinity region of the oxide 230b is removed, and the CAAC structure can further suppress variations in the electrical characteristics of the transistor 200. FIG. In addition, reliability of the transistor 200 can be improved.
  • a cleaning process is performed to remove impurities adhered to the surface of the oxide 230b in the etching process.
  • a cleaning method there are wet cleaning using a cleaning solution (which can also be referred to as wet etching treatment), plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate. Note that the cleaning process may deepen the groove.
  • Wet cleaning may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc. with carbonated water or pure water, pure water, carbonated water, or the like.
  • ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
  • these washings may be appropriately combined.
  • an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid
  • an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water.
  • concentration, temperature, and the like of the aqueous solution may be adjusted as appropriate depending on impurities to be removed, the configuration of the semiconductor device to be cleaned, and the like.
  • the ammonia concentration of the diluted ammonia water should be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less.
  • the concentration of hydrogen fluoride in the diluted hydrofluoric acid should be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.
  • a frequency of 200 kHz or higher is preferably used for ultrasonic cleaning, and a frequency of 900 kHz or higher is more preferably used. By using the frequency, damage to the oxide 230b and the like can be reduced.
  • the cleaning treatment may be performed multiple times, and the cleaning liquid may be changed for each cleaning treatment.
  • a treatment using diluted hydrofluoric acid or diluted ammonia water may be performed as the first cleaning treatment
  • a treatment using pure water or carbonated water may be performed as the second cleaning treatment.
  • wet cleaning is performed using diluted ammonia water.
  • impurities attached to the surfaces of the oxides 230a and 230b or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.
  • a heat treatment may be performed after the above etching or after the above cleaning.
  • the heat treatment may be performed at 100° C. or higher and 450° C. or lower, preferably 350° C. or higher and 400° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxides 230a and 230b, and oxygen vacancies can be reduced. Further, by performing such heat treatment, the crystallinity of the oxide 230b can be improved.
  • after heat treatment in an oxygen atmosphere heat treatment may be continuously performed in a nitrogen atmosphere without exposure to the air.
  • an insulating film 252A is formed (see FIGS. 15A to 15D).
  • the insulating film 252A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 252A is preferably formed using an ALD method.
  • the insulating film 252A is preferably formed with a thin film thickness, and it is necessary to reduce variations in film thickness.
  • the ALD method is a method of forming a film by alternately introducing a precursor and a reactant (for example, an oxidizing agent). Film thickness can be adjusted.
  • a precursor and a reactant for example, an oxidizing agent
  • the insulating film 252A needs to be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 280 and the like.
  • ozone (O 3 ), oxygen (O 2 ), water (H 2 O), or the like can be used as an oxidizing agent.
  • oxygen (O 2 ), or the like that does not contain hydrogen can be used as an oxidizing agent.
  • the insulating film 252A is formed by thermal ALD using aluminum oxide.
  • an insulating film 250A is formed (see FIGS. 15A to 15D).
  • Heat treatment may be performed before the insulating film 250A is formed, or the heat treatment may be performed under reduced pressure and the insulating film 250A may be formed continuously without exposure to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such treatment, moisture and hydrogen adsorbed to the surface of the insulating film 252A or the like can be removed, and the moisture concentration and hydrogen concentration in the oxides 230a and 230b can be reduced.
  • the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.
  • the insulating film 250A can be formed using a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes the insulator 250a facing the oxide 230b through the thin insulator 252 in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • silicon oxynitride is deposited by PECVD as the insulating film 250A.
  • microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • Dotted lines shown in FIGS. 15B to 15D indicate microwaves, high frequencies such as RF, oxygen plasma, oxygen radicals, or the like.
  • a microwave treatment apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • the frequency of the microwave processing device may be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz.
  • High-density oxygen radicals can be generated by using high-density plasma.
  • the power of the power source for applying microwaves in the microwave processing apparatus may be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less.
  • the microwave processing apparatus may have a power supply for applying RF to the substrate side. Further, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.
  • the above microwave treatment is preferably performed under reduced pressure, and the pressure should be 10 Pa or more and 1000 Pa or less, preferably 300 Pa or more and 700 Pa or less.
  • the treatment temperature may be 750°C or lower, preferably 500°C or lower, for example, about 250°C.
  • heat treatment may be continuously performed without exposure to the outside air.
  • the temperature may be 100° C. or higher and 750° C. or lower, preferably 300° C. or higher and 500° C. or lower.
  • the microwave treatment may be performed using oxygen gas and argon gas.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is greater than 0% and 100% or less, preferably greater than 0% and 50% or less, more preferably 10% or more and 40% or less, further preferably 10%. % or more and 30% or less.
  • microwave treatment is performed in an oxygen-containing atmosphere to turn oxygen gas into plasma using microwaves or high frequencies such as RF. It can act on the region between 242a and conductor 242b.
  • the region 230bc can also be irradiated with microwaves or high frequencies such as RF. That is, microwaves, high frequencies such as RF, oxygen plasma, or the like can be applied to the region 230bc shown in FIG. 2A.
  • the VOH in region 230bc can be disrupted and hydrogen can be removed from region 230bc. That is, VOH contained in the region 230bc can be reduced.
  • oxygen vacancies and VOH in the region 230bc can be reduced, and the carrier concentration can be lowered.
  • oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 are supplied to the oxygen vacancies formed in the region 230bc, thereby further reducing the oxygen vacancies in the region 230bc and increasing the carrier concentration. can be lowered.
  • conductors 242a and 242b are provided on the regions 230ba and 230bb shown in FIG. 2A.
  • the conductor 242 preferably functions as a shielding film against the action of microwaves, high frequencies such as RF, oxygen plasma, and the like when microwave treatment is performed in an oxygen-containing atmosphere. Therefore, the conductor 242 preferably has a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.
  • the conductors 242a and 242b block the effects of microwaves, high frequencies such as RF, and oxygen plasma, so that these effects do not reach the regions 230ba and 230bb. do not have.
  • reduction of V OH and supply of an excessive amount of oxygen do not occur in the regions 230ba and 230bb due to the microwave treatment, so that a decrease in carrier concentration can be prevented.
  • An insulator 252 having a barrier property against oxygen is provided in contact with side surfaces of the conductors 242a and 242b. Accordingly, formation of an oxide film on the side surfaces of the conductors 242a and 242b due to microwave treatment can be suppressed.
  • the film quality of the insulator 252 and the insulator 250a can be improved, the reliability of the transistor 200 is improved.
  • oxygen vacancies and V OH can be selectively removed from the oxide semiconductor region 230bc to make the region 230bc i-type or substantially i-type. Furthermore, excessive supply of oxygen to the regions 230ba and 230bb functioning as a source region or a drain region can be suppressed, and conductivity can be maintained. As a result, variations in the electrical characteristics of the transistor 200 can be suppressed, and variation in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.
  • heat energy may be directly transmitted to the oxide 230b due to the electromagnetic interaction between the microwave and the molecules in the oxide 230b. This thermal energy may heat the oxide 230b.
  • Such heat treatment is sometimes called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing may be obtained. Further, when hydrogen is contained in the oxide 230b, it is conceivable that this thermal energy is transmitted to hydrogen in the oxide 230b and thus activated hydrogen is released from the oxide 230b.
  • heat treatment may be performed while maintaining the reduced pressure.
  • hydrogen in the insulating film 252A, the insulating film 250A, the insulating film to be the insulator 250b, the oxide 230b, and the oxide 230a can be efficiently removed.
  • part of the hydrogen may be gettered by the conductors 242 (the conductors 242a and 242b).
  • the step of performing the heat treatment may be repeated a plurality of times while the reduced pressure state is maintained.
  • the diffusion of hydrogen, water, impurities, and the like can be suppressed by modifying the film quality of the insulating film 252A, the insulating film 250A, and the insulating film to be the insulator 250b by microwave treatment. Therefore, in a post-process such as formation of a conductive film to be the conductor 260 or a post-treatment such as heat treatment, hydrogen, water, impurities, or the like diffuse through the insulator 252 into the oxides 230b, 230a, and the like. can be suppressed.
  • heat treatment may be performed under the same conditions as the above heat treatment.
  • the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere.
  • the concentrations of moisture and hydrogen in the insulators 250 and 280 can be reduced.
  • the insulator 282 may be formed continuously without exposure to the air.
  • aluminum oxide is deposited as the insulator 282 by a pulse DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas.
  • the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • the RF power applied to the substrate is 1.86 W/cm 2 or less. Preferably, it is 0 W/cm 2 or more and 0.62 W/cm 2 or less. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed.
  • the insulator 282 may be formed to have a two-layer structure.
  • the volume of the insulator 280 for one transistor 200 may become excessively small.
  • the amount of oxygen that diffuses into the oxide 230 is significantly reduced in the above heat treatment. If the oxide 230 is heated in contact with an oxide insulator (eg, the insulator 250 or the like) that does not contain enough oxygen, oxygen in the oxide 230 might be released.
  • the insulator 252 is provided in contact with the top surface and side surfaces of the oxide 230 in a region of the oxide 230 overlapping with the conductor 260 . Since the insulator 252 has a barrier property against oxygen, release of oxygen from the oxide 230 can be reduced even in the above heat treatment. Thereby, oxygen vacancies and VOH formed in the region 230bc can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be improved.
  • a transistor having favorable electrical characteristics and favorable reliability can be formed regardless of whether the amount of oxygen supplied from the insulator 280 is large or small. can be done. Therefore, it is possible to provide a semiconductor device that suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.
  • an insulator 285 is formed over the insulator 274 and the insulator 283 (see FIGS. 20A to 20D).
  • the insulator 285 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 285 is preferably deposited by a sputtering method.
  • the concentration of hydrogen in the insulator 285 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • silicon oxide is deposited as the insulator 285 by a sputtering method.
  • openings reaching the conductors 242 are formed in the insulators 271, 275, 280, 282, 283, and 285 (see FIGS. 20A and 20B).
  • the formation of the opening may be performed using a lithography method.
  • the shape of the opening is circular when viewed from above, but the shape is not limited to this.
  • the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners when viewed from above.
  • the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing permeation of oxygen is preferably used.
  • the anisotropic etching of the insulating films to be the insulators 241a and 241b for example, a dry etching method or the like may be used.
  • a dry etching method or the like By providing the insulators 241a and 241b on the side walls of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed next can be prevented.
  • impurities such as water and hydrogen contained in the insulator 280 and the like can be prevented from diffusing into the conductors 240a and 240b.
  • the conductive film preferably has a stacked-layer structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen.
  • a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. can be used.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive films to be the conductors 246a and 246b are processed by a lithography method to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240b.
  • part of the insulator 285 in a region where the conductors 246a and 246b do not overlap with the insulator 285 may be removed.
  • ⁇ Microwave processing device> A microwave processing apparatus that can be used in the above method for manufacturing a semiconductor device is described below.
  • FIG. 21 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700.
  • the manufacturing apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 having a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning substrates, and an atmosphere-side substrate transfer chamber for transferring substrates from the atmosphere-side substrate supply chamber 2701 .
  • a chamber 2702 for loading a substrate and switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, and a substrate unloading chamber for carrying out the substrate and changing the pressure in the chamber from reduced pressure to atmospheric pressure, or It has an unload lock chamber 2703b for switching from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in vacuum, chambers 2706a, 2706b, 2706c, and 2706d.
  • the atmospheric side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the chamber 2706a. , chamber 2706b, chamber 2706c and chamber 2706d.
  • a gate valve GV is provided at the connecting portion of each chamber, and each chamber can be independently held in a vacuum state except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702 .
  • the atmosphere-side substrate transfer chamber 2702 is provided with a transfer robot 2763a
  • the transfer chamber 2704 is provided with a transfer robot 2763b. The substrate can be transported within the manufacturing apparatus 2700 by the transport robot 2763a and the transport robot 2763b.
  • the back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1 ⁇ 10 ⁇ 4 Pa or less, preferably 3 ⁇ 10 ⁇ 5 Pa or less, more preferably 1 ⁇ 10 ⁇ 5 Pa or less.
  • the partial pressure of gas molecules (atoms) having a mass-to-charge ratio (m/z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less. and more preferably 3 ⁇ 10 ⁇ 6 Pa or less.
  • the partial pressure of gas molecules (atoms) having an m/z of 28 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less, more preferably 3 ⁇ 10 ⁇ 5 Pa or less. ⁇ 10 ⁇ 6 Pa or less.
  • the partial pressure of gas molecules (atoms) with m/z of 44 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less, more preferably 3 ⁇ 10 ⁇ 5 Pa or less. ⁇ 10 ⁇ 6 Pa or less.
  • the total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using an ionization vacuum gauge, a mass spectrometer, or the like.
  • the leak rate can be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, mass spectrometer, or the like. For example, it may be derived from the total pressure 10 minutes after the start of vacuuming with a vacuum pump such as a turbo-molecular pump and the total pressure 10 minutes after the valve is closed.
  • the total pressure after 10 minutes from the start of the evacuation may be an average value obtained by measuring the total pressure a plurality of times.
  • aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits less gas containing impurities is used as a member constituting the manufacturing apparatus 2700 .
  • an alloy containing iron, chromium, nickel, or the like may be coated with the aforementioned metal containing impurities and emitting less gas. Alloys containing iron, chromium, nickel, and the like are rigid, heat resistant, and workable.
  • the surface unevenness of the member is reduced by polishing or the like in order to reduce the surface area, the emitted gas can be reduced.
  • the members of the manufacturing apparatus 2700 are made of only metal as much as possible. It is advisable to thinly coat with chromium or the like.
  • the desorption speed of water and the like which is difficult to desorb only by exhausting, can be further increased.
  • the desorption speed of the adsorbate can be further increased.
  • the pressure is preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less.
  • the transfer chamber 2704 and each chamber are evacuated for a period of 5 to 300 minutes, preferably 10 to 120 minutes.
  • the chamber 2706b and the chamber 2706c are, for example, chambers capable of subjecting an object to be processed to microwave processing. Note that the chamber 2706b and the chamber 2706c are different only in the atmosphere when the microwave treatment is performed. Since other configurations are common, they will be collectively described below.
  • the chamber 2706b and the chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812 and an exhaust port 2819. Further, outside the chambers 2706b and 2706c, etc., there are a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, and a waveguide 2807. , a matching box 2815 , a high frequency power supply 2816 , a vacuum pump 2817 and a valve 2818 are provided.
  • the substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically chucking or mechanically chucking the substrate 2811 . It also functions as an electrode to which power is supplied from the high frequency power supply 2816 . It also has a heating mechanism 2813 inside and has a function of heating the substrate 2811 .
  • the vacuum pump 2817 for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, a turbomolecular pump, or the like can be used. Also, in addition to the vacuum pump 2817, a cryotrap may be used. The use of a cryopump and a cryotrap is particularly preferable because water can be discharged efficiently.
  • the heating mechanism 2813 for example, a heating mechanism that heats using a resistance heating element or the like may be used.
  • a heating mechanism that heats by heat conduction or heat radiation from a medium such as heated gas may be used.
  • RTA Rapid Thermal Annealing
  • GRTA Gas Rapid Thermal Annealing
  • LRTA Low Rapid Thermal Annealing
  • GRTA performs heat treatment using high temperature gas.
  • An inert gas is used as the gas.
  • the gas supply source 2801 may be connected to the refiner via a mass flow controller. It is preferable to use a gas having a dew point of ⁇ 80° C. or lower, preferably ⁇ 100° C. or lower.
  • a gas having a dew point of ⁇ 80° C. or lower preferably ⁇ 100° C. or lower.
  • oxygen gas, nitrogen gas, and noble gas such as argon gas may be used.
  • dielectric plate 2809 for example, silicon oxide (quartz), aluminum oxide (alumina), yttrium oxide (yttria), or the like may be used. Further, another protective layer may be formed on the surface of dielectric plate 2809 . As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, or the like may be used. Since the dielectric plate 2809 will be exposed to a particularly high-density region of the high-density plasma 2810, which will be described later, damage can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.
  • the high-frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz.
  • a microwave generated by the high frequency generator 2803 is transmitted to the mode converter 2805 via the waveguide 2804 .
  • the microwave transmitted as TE mode is converted into TEM mode.
  • the microwave is transmitted to slot antenna plate 2808 via waveguide 2807 .
  • Slot antenna plate 2808 is provided with a plurality of slot holes, and microwaves pass through the slot holes and dielectric plate 2809 .
  • an electric field can be generated below the dielectric plate 2809 to generate high density plasma 2810 .
  • Ions and radicals according to the gas species supplied from the gas supply source 2801 are present in the high-density plasma 2810 . For example, there are oxygen radicals.
  • the ions and radicals generated by the high-density plasma 2810 can modify the film on the substrate 2811 .
  • the high-frequency power supply 2816 for example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz and 27.12 MHz may be used.
  • RF Radio Frequency
  • oxygen radical treatment using high-density plasma 2810 can be performed.
  • the chamber 2706a and the chamber 2706d are, for example, chambers capable of irradiating an object to be processed with electromagnetic waves.
  • the only difference between the chamber 2706a and the chamber 2706d is the type of electromagnetic wave. Since there are many common parts in other configurations, they will be collectively described below.
  • a gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822 .
  • Vacuum pump 2828 is connected to exhaust port 2830 through valve 2829 .
  • the lamp 2820 is arranged facing the substrate holder 2825 .
  • the substrate holder 2825 has the function of holding the substrate 2824 . Further, the substrate holder 2825 has a heating mechanism 2826 inside and has a function of heating the substrate 2824 .
  • a light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light
  • a light source having a function of emitting an electromagnetic wave having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.
  • a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp may be used.
  • electromagnetic waves radiated from the lamps 2820 may cause the substrate holder 2825 to generate heat to heat the substrate 2824 .
  • the heating mechanism 2826 may not be provided inside the substrate holder 2825 .
  • the vacuum pump 2828 refers to the description of the vacuum pump 2817.
  • the heating mechanism 2826 the description of the heating mechanism 2813 is referred to.
  • the gas supply source 2821 the description of the gas supply source 2801 is referred to.
  • the microwave processing device that can be used in this embodiment is not limited to the above.
  • a microwave processing apparatus 2900 shown in FIG. 24 can be used.
  • Microwave processing apparatus 2900 has quartz tube 2901 , exhaust port 2819 , gas supply source 2801 , valve 2802 , high frequency generator 2803 , waveguide 2804 , gas pipe 2806 , vacuum pump 2817 and valve 2818 .
  • the microwave processing apparatus 2900 also includes a substrate holder 2902 that holds a plurality of substrates (2811_1 to 2811_n, where n is an integer of 2 or more) inside the quartz tube 2901 . Further, the microwave processing apparatus 2900 may have heating means 2903 outside the quartz tube 2901 .
  • the microwave generated by the high-frequency generator 2803 is applied to the substrate provided inside the quartz tube 2901 via the waveguide 2804 .
  • a vacuum pump 2817 is connected to an exhaust port 2819 via a valve 2818 and can adjust the pressure inside the quartz tube 2901 .
  • a gas supply source 2801 is also connected to a gas pipe 2806 via a valve 2802 so that a desired gas can be introduced into the quartz pipe 2901 .
  • the plurality of substrates in the quartz tube 2901 can be heated to a desired temperature by the heating means 2903 .
  • the heating means 2903 may heat the gas supplied from the gas supply source 2801 .
  • All of the substrates 2811_1 to 2811_n may be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates.
  • the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n ⁇ 1 may be processing substrates.
  • the substrates 2811_1, 2811_2, 2811_n ⁇ 1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n ⁇ 2 may be processing substrates.
  • the use of a dummy substrate is preferable because a plurality of substrates to be processed can be uniformly processed during microwave treatment or heat treatment, and variations among the substrates to be processed can be reduced.
  • placing a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804 is preferable because direct exposure of the processing substrate to microwaves can be suppressed.
  • a in each figure shows a top view of the semiconductor device.
  • B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in A in each figure.
  • C in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in A in each figure.
  • D in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in A in each figure.
  • some elements are omitted for clarity of illustration.
  • the semiconductor device shown in FIGS. 6A to 6D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
  • the semiconductor devices shown in FIGS. 6A to 6D are different from the semiconductor devices shown in FIGS. 1A to 1D in that each of the insulators 271 and 283 has a two-layer structure.
  • the insulator 271a has an insulator 271a1 and an insulator 271a2 on the insulator 271a1.
  • the insulator 271b has an insulator 271b1 and an insulator 271b2 on the insulator 271b1.
  • the insulators 271a1 and 271b1 preferably function as barrier insulating films against at least oxygen. Therefore, the insulator 271a1 and the insulator 271b1 preferably have a function of suppressing diffusion of oxygen. Accordingly, oxygen contained in the insulator 280 can be prevented from diffusing into the conductors 242a and 242b. Therefore, the oxygen contained in the insulator 280 can prevent the conductors 242a and 242b from being oxidized to increase the resistivity and reduce the on-current.
  • the insulators 271a2 and 271b2 function as protective layers for leaving the insulators 271a1 and 271b1.
  • the insulating layer to be the insulators 271a1 and 271b1 is removed. There is fear. Therefore, insulating layers to be the insulators 271a1 and 271b1 are provided between the hard mask and the insulating layers to be the insulators 271a1 and 271b1. can be left.
  • silicon oxide or the like is preferably used for the insulators 271a2 and 271b2.
  • the insulator 283 has an insulator 283a and an insulator 283b on the insulator 283a.
  • the insulators 283a and 283b are preferably formed from the same material by different methods.
  • silicon nitride may be deposited as the insulator 283a by a sputtering method
  • silicon nitride may be deposited as the insulator 283b by an ALD method.
  • the hydrogen concentration in the insulator 282a can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • a film formed by an ALD method with good coverage is used to block the overlapping portion of the pinhole or discontinuity. be able to.
  • a part of the upper surface of the insulator 283b may be removed. Further, it may be difficult to clearly detect the boundary between the insulator 283a and the insulator 283b.
  • the insulator 283a and the insulator 283b are not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.
  • the semiconductor device shown in FIGS. 7A to 7D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
  • the semiconductor devices shown in FIGS. 7A to 7D are different from the semiconductor devices shown in FIGS. 1A to 1D in that the insulator 282 is not provided. Therefore, in the semiconductor device shown in FIGS. 7A to 7D, insulator 283 is the top surface of conductor 260 , the top surface of insulator 280 , the top of insulator 254 , the top of insulator 250 , and the top of insulator 252 . touch the top.
  • the semiconductor device shown in FIGS. 8A to 8D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
  • the semiconductor devices illustrated in FIGS. 8A to 8D are different from the semiconductor devices illustrated in FIGS. 1A to 1D in that oxides 243 (oxides 243a and 243b) are provided.
  • the oxide 243a is provided between the oxide 230b and the conductor 242a
  • the oxide 243b is provided between the oxide 230b and the conductor 242b.
  • oxide 243a preferably contacts the top surface of oxide 230b and the bottom surface of conductor 242a.
  • oxide 243b preferably contacts the top surface of oxide 230b and the bottom surface of conductor 242b.
  • the oxide 243 preferably has a function of suppressing permeation of oxygen.
  • the oxide 243 having a function of suppressing permeation of oxygen between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, an electric current between the conductor 242 and the oxide 230b is reduced. This is preferable because resistance is reduced. With such a structure, electrical characteristics, field-effect mobility, and reliability of the transistor 200 can be improved in some cases.
  • a metal oxide containing the element M may also be used as the oxide 243 .
  • the element M is preferably aluminum, gallium, yttrium, or tin.
  • the oxide 243 preferably has a higher concentration of the element M than the oxide 230b.
  • gallium oxide may be used as the oxide 243 .
  • a metal oxide such as an In-M-Zn oxide may be used as the oxide 243 .
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the thickness of the oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and still more preferably 1 nm to 2 nm. Further, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, release of oxygen from the oxide 230 can be suppressed favorably. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal structure, release of oxygen from the oxide 230 can be suppressed in some cases.
  • the semiconductor device shown in FIGS. 9A to 9D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
  • the semiconductor devices shown in FIGS. 9A to 9D are different from the semiconductor devices shown in FIGS. 1A to 1D in that the insulator 283 is in contact with part of the top surface of the insulator 212 .
  • Transistor 200 is thus disposed within the region encapsulated by insulator 283 and insulator 212 . With the above structure, hydrogen contained outside the sealed region can be prevented from entering the sealed region. Further, although the transistor 200 illustrated in FIGS.
  • an OS transistor such as the transistor 200 has little change in electrical characteristics due to radiation irradiation, that is, it has high resistance to radiation, so it can be suitably used in an environment where radiation may be incident.
  • an OS transistor can be suitably used when used in outer space.
  • the OS transistor can be used as a transistor included in a semiconductor device provided in a space shuttle, an artificial satellite, a space probe, or the like.
  • Radiation includes, for example, X-rays, neutron beams, and the like.
  • outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may include the thermosphere, the mesosphere, and the stratosphere.
  • 25A shows a top view of the semiconductor device 500.
  • FIG. The x-axis shown in FIG. 25A is parallel to the channel length direction of the transistor 200, and the y-axis is perpendicular to the x-axis.
  • 25B is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in FIG. 25A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 25C is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in FIG. 25A, and is also a cross-sectional view of the opening region 400 and its vicinity. Note that some elements are omitted in the top view of FIG. 25A for clarity of illustration.
  • the sealing portion 265 is provided so as to surround the plurality of transistors 200, the insulators 216, the insulators 222, the insulators 275, the insulators 280, and the insulators 282.
  • insulator 283 is provided to cover insulator 216 , insulator 222 , insulator 275 , insulator 280 , and insulator 282 .
  • the insulator 283 is in contact with the upper surface of the insulator 214 .
  • An insulator 274 is provided between the insulator 283 and the insulator 285 above the sealing portion 265 .
  • the top surface of the insulator 274 is approximately level with the top surface of the insulator 283 .
  • an insulator similar to the insulator 280 can be used.
  • Heat treatment is performed in a state where the opening region 400 is formed and the insulator 280 is exposed from the opening of the insulator 282 , whereby oxygen contained in the insulator 280 is removed while oxygen is supplied to the oxide 230 . can be diffused out of the open area 400 .
  • sufficient oxygen is supplied from the insulator 280 containing oxygen which is released by heating to the region functioning as a channel formation region in the oxide semiconductor layer and the vicinity thereof, and an excessive amount of oxygen is removed. can be prevented from being supplied.
  • the shape of the opening region 400 in top view is substantially rectangular, but the present invention is not limited to this.
  • the top view shape of the open area 400 may be a rectangle, an ellipse, a circle, a rhombus, or a combination thereof.
  • the area and arrangement intervals of the opening regions 400 can be appropriately set according to the design of the semiconductor device including the transistor 200 . For example, in a region where the density of the transistors 200 is low, the area of the opening regions 400 may be widened or the arrangement interval of the opening regions 400 may be narrowed. Further, for example, in a region where the density of the transistors 200 is high, the area of the opening regions 400 may be narrowed or the arrangement interval of the opening regions 400 may be widened.
  • the conductor 112 provided over the conductor 240 and the conductor 110 can be formed at the same time.
  • the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100 , the transistor 200 , or the transistor 300 .
  • the conductor 112 and the conductor 110 have a single-layer structure in FIG. 26, they are not limited to this structure, and may have a laminated structure of two or more layers. For example, between a conductor with a barrier property and a conductor with high conductivity, a conductor with a barrier property and a conductor with high adhesion to the conductor with high conductivity may be formed.
  • the insulator 130 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. etc., and can be provided as a laminate or a single layer.
  • the insulator 130 preferably has a laminated structure of a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material.
  • the capacitive element 100 includes an insulator with a high dielectric constant (high-k), so that a sufficient capacitance can be secured, and an insulator with a high dielectric strength improves the dielectric strength and increases the capacitance. Electrostatic breakdown of the element 100 can be suppressed.
  • high dielectric constant (high-k) materials examples include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, silicon and There are oxides with hafnium, oxynitrides with silicon and hafnium, and nitrides with silicon and hafnium.
  • materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and nitrogen. There are added silicon oxide, silicon oxide with holes, resin, and the like.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300 as interlayer films.
  • conductors 328, 330, and the like electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326, respectively. Note that the conductors 328 and 330 function as plugs or wirings.
  • the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape thereunder.
  • the top surface of the insulator 322 may be planarized by a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided over the insulator 326 and the conductor 330 .
  • an insulator 350, an insulator 352, and an insulator 354 are stacked in this order.
  • a conductor 356 is formed over the insulators 350 , 352 , and 354 .
  • Conductor 356 functions as a plug or wiring.
  • an insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug.
  • the insulator 217 is provided in contact with inner walls of openings formed in the insulators 210 , 212 , 214 , and 216 . That is, the insulator 217 is provided between the conductor 218 and the insulators 210 , 212 , 214 , and 216 . Note that since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 is formed in contact with the side surface of the conductor 205 in some cases.
  • an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride may be used. Since the insulator 217 is provided in contact with the insulator 210 , the insulator 212 , the insulator 214 , and the insulator 222 , impurities such as water or hydrogen from the insulator 210 or the insulator 216 are oxidized through the conductor 218 . It is possible to suppress mixing into the object 230 .
  • silicon nitride is suitable because it has a high blocking property against hydrogen.
  • oxygen contained in the insulator 210 or the insulator 216 can be prevented from being absorbed by the conductor 218 .
  • the insulator 217 can be formed by a method similar to that of the insulator 241 .
  • a PEALD method may be used to form a silicon nitride film, and anisotropic etching may be used to form an opening reaching the conductor 356 .
  • Insulators that can be used as interlayer films include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.
  • the material should be selected according to the function of the insulator.
  • the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like preferably have an insulator with a low dielectric constant.
  • the insulator preferably contains silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, resin, or the like.
  • the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. and resin.
  • silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained.
  • resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used for the insulators 214, 212, 350, and the like.
  • Examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or stacks.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium. , ruthenium and the like can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like are metal materials, alloy materials, metal nitride materials, metal oxide materials, or the like formed of any of the above materials.
  • conductive materials can be used in a single layer or in lamination. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.
  • an insulator having an excess oxygen region is provided near the oxide semiconductor in some cases.
  • an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • the insulator 241 may be provided between the insulator 280 containing excess oxygen and the conductor 240 .
  • the transistor 200 can be sealed with an insulator having a barrier property.
  • the provision of the insulator 241 can suppress excess oxygen in the insulator 280 from being absorbed by the conductor 240 .
  • the presence of the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240 .
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used as the insulator 241 .
  • silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like is preferably used.
  • silicon nitride is preferable because it has a high blocking property against hydrogen.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can also be used.
  • the transistor 200 may be sealed with the insulator 212, the insulator 214, the insulator 282, and the insulator 283 as described in the above embodiment. With such a structure, entry of hydrogen contained in the insulator 274, the insulator 150, and the like into the insulator 280 and the like can be reduced.
  • the conductor 240 penetrates through the insulators 283 and 282, and the conductor 218 penetrates through the insulators 214 and 212.
  • the insulator 241 is in contact with the conductor 240.
  • An insulator 217 is provided in contact with the conductor 218 . Accordingly, hydrogen entering inside the insulators 212 , 214 , 282 , and 283 through the conductors 240 and 218 can be reduced.
  • the transistor 200 is sealed with the insulator 212, the insulator 214, the insulator 282, the insulator 283, the insulator 241, and the insulator 217, and impurities such as hydrogen contained in the insulator 274 and the like are removed from the outside. It is possible to reduce contamination from
  • dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) provided when taking out a plurality of semiconductor devices in the form of chips by dividing a large-area substrate into individual semiconductor elements will be described.
  • a dividing method for example, grooves (dicing lines) for dividing the semiconductor elements are first formed in the substrate, and then cut along the dicing lines to divide (divide) into a plurality of semiconductor devices.
  • the region where the insulator 283 and the insulator 214 are in contact overlaps the dicing line. That is, openings are provided in the insulator 282 , the insulator 280 , the insulator 275 , the insulator 222 , and the insulator 216 in the vicinity of the dicing line region provided at the outer edge of the memory cell having the plurality of transistors 200 .
  • the insulator 214 and the insulator 283 are in contact with each other in the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216.
  • openings may be provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214.
  • the insulator 212 and the insulator 283 are in contact with each other in the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214.
  • the insulator 212 and the insulator 283 may be formed using the same material and the same method. By providing the insulator 212 and the insulator 283 using the same material and the same method, adhesion can be improved. For example, it is preferable to use silicon nitride.
  • the insulator 212 , the insulator 214 , the insulator 282 , and the insulator 283 can wrap the transistor 200 .
  • At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water; therefore, the semiconductor element described in this embodiment is formed.
  • this structure can prevent excess oxygen in the insulator 280 from diffusing to the outside. Excess oxygen in insulator 280 is therefore efficiently supplied to the oxide in which the channel in transistor 200 is formed. Oxygen vacancies in the oxide in which a channel is formed in the transistor 200 can be reduced by the oxygen. Accordingly, the oxide in which the channel of the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, it is possible to suppress variations in the electrical characteristics of the transistor 200 and improve its reliability.
  • the shape of the capacitor 100 is planar, but the storage device shown in this embodiment is not limited to this.
  • the shape of the capacitive element 100 may be cylindrical. Note that the configuration of the memory device shown in FIG. 27 below the insulator 150 is similar to that of the semiconductor device shown in FIG.
  • the capacitive element 100 shown in FIG. 27 includes an insulator 150 on the insulator 130, an insulator 142 on the insulator 150, and a conductor 115 arranged in an opening formed in the insulator 150 and the insulator 142. , an insulator 145 over the conductor 115 and the insulator 142 , a conductor 125 over the insulator 145 , and an insulator 152 over the conductor 125 and the insulator 145 .
  • conductor 115 , insulator 145 , and conductor 125 are placed in openings formed in insulator 150 and insulator 142 .
  • the conductor 115 functions as the lower electrode of the capacitor 100
  • the conductor 125 functions as the upper electrode of the capacitor 100
  • the insulator 145 functions as the dielectric of the capacitor 100 .
  • the capacitive element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched therebetween not only on the bottom surface but also on the side surfaces in the openings of the insulator 150 and the insulator 142. Capacity can be increased. Therefore, the capacitance of the capacitive element 100 can be increased as the depth of the opening is increased. By increasing the capacitance per unit area of the capacitive element 100 in this manner, miniaturization or high integration of the semiconductor device can be promoted.
  • An insulator that can be used for the insulator 280 may be used for the insulator 152 .
  • the insulator 142 preferably functions as an etching stopper when the opening of the insulator 150 is formed, and an insulator that can be used for the insulator 214 may be used.
  • the shape of the openings formed in the insulators 150 and 142 when viewed from above may be a quadrangle, a polygonal shape other than a quadrangle, or a polygonal shape with curved corners. , or a circular shape including an ellipse.
  • the conductor 115 is arranged in contact with the openings formed in the insulator 142 and the insulator 150 .
  • the top surface of the conductor 115 substantially coincides with the top surface of the insulator 142 .
  • the lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130 .
  • the conductor 115 is preferably formed by an ALD method, a CVD method, or the like.
  • a conductor that can be used for the conductor 205 may be used.
  • the insulator 145 is arranged to cover the conductor 115 and the insulator 142 .
  • the insulator 145 is preferably formed by an ALD method, a CVD method, or the like.
  • the insulator 145 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, nitridation. Hafnium or the like may be used, and a stacked layer or a single layer can be provided.
  • an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used.
  • a material with high dielectric strength such as silicon oxynitride or a high dielectric constant (high-k) material for the insulator 145 .
  • a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.
  • high dielectric constant (high-k) materials examples include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, silicon and There are oxides with hafnium, oxynitrides with silicon and hafnium, nitrides with silicon and hafnium, and the like.
  • high-k materials gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, silicon and There are oxides with hafnium, oxynitrides with silicon and hafnium, nitrides with silicon and hafnium, and the like.
  • materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. silicon oxide, resin, etc.
  • silicon nitride (SiN x ) deposited using the PEALD method silicon oxide (SiO x ) deposited using the PEALD method, and silicon nitride (SiN x ) deposited using the PEALD method are stacked in this order. can be used.
  • an insulating film in which zirconium oxide, silicon oxide deposited by an ALD method, and zirconium oxide are stacked in this order can be used.
  • an insulator with high dielectric strength dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.
  • the conductor 125 is arranged so as to fill the openings formed in the insulator 142 and the insulator 150 .
  • the conductor 125 is electrically connected to the wiring 1005 through the conductors 140 and 153 .
  • the conductor 125 is preferably formed by an ALD method, a CVD method, or the like.
  • a conductor that can be used for the conductor 205 may be used.
  • the conductor 153 is provided on the insulator 154 and covered with the insulator 156 .
  • a conductor that can be used for the conductor 112 may be used for the conductor 153
  • an insulator that can be used for the insulator 152 may be used for the insulator 156 .
  • the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100 , the transistor 200 , or the transistor 300 .
  • FIG. 2 An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.
  • ⁇ Configuration example of memory device> 28 is a cross-sectional view of a semiconductor device having a memory device 290.
  • FIG. The memory device 290 shown in FIG. 28 has a capacitive device 292 in addition to the transistor 200 shown in FIGS. 1A-1D.
  • FIG. 28 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.
  • the capacitor device 292 includes a conductor 242b, an insulator 271b provided over the conductor 242b, and an insulator 275 provided in contact with the top surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b. , and a conductor 294 on insulator 275 . That is, the capacitive device 292 constitutes an MIM (Metal-Insulator-Metal) capacity. Note that one of the pair of electrodes included in the capacitor device 292, that is, the conductor 242b can also serve as the source electrode of the transistor.
  • MIM Metal-Insulator-Metal
  • the dielectric layer included in the capacitive device 292 can also serve as protective layers provided for the transistor, that is, the insulator 271 and the insulator 275 . Therefore, part of the manufacturing process of the transistor can be shared in the manufacturing process of the capacitor device 292, so that the semiconductor device can be manufactured with high productivity. In addition, since one of the pair of electrodes of the capacitor device 292, that is, the conductor 242b also serves as the source electrode of the transistor, the area where the transistor and the capacitor device are arranged can be reduced.
  • conductor 294 for example, a material that can be used for the conductor 242 may be used.
  • An example of the device will be described. Note that in the semiconductor devices shown in FIGS. 29A, 29B, and 30, a structure having the same function as the structure constituting the semiconductor device (see FIG. 28) shown in the previous embodiment and ⁇ Configuration Example of Memory Device> is used. are marked with the same reference numerals. Note that in this item, the materials described in detail in the above embodiments and ⁇ Structure Example of Memory Device> can be used as materials for forming the transistor 200 and the capacitor device 292 . 29A, 29B, and 30 use the memory device shown in FIG. 28 as the memory device, but the present invention is not limited to this.
  • FIG. 29A is a cross-sectional view along the channel length of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitive device 292a, and a capacitive device 292b.
  • the capacitive device 292a includes the conductor 242a, the insulator 271a on the conductor 242a, the insulator 275 in contact with the top surface of the insulator 271a, the side surface of the insulator 271a, and the side surface of the conductor 242a, and the insulator 271a.
  • the capacitive device 292b includes a conductor 242b, an insulator 271b on the conductor 242b, an insulator 275 in contact with the top surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and the insulator 275b. and an upper conductor 294b.
  • the semiconductor device 600 has a symmetrical configuration with the dashed-dotted line A3-A4 as the axis of symmetry.
  • the conductor 242c serves also as one of the source electrode and the drain electrode of the transistor 200a and one of the source electrode and the drain electrode of the transistor 200b.
  • an insulator 271c is provided over the conductor 242c.
  • the conductor 246 functioning as a wiring and the conductor 240 functioning as plugs also serve as connections between the transistors 200a and 200b. In this way, by configuring the two transistors, the two capacitive devices, and the connection between the wiring and the plug as described above, it is possible to provide a semiconductor device that can be miniaturized or highly integrated.
  • the configuration example of the semiconductor device illustrated in FIG. 28 can be referred to for the configuration and effect of each of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b.
  • the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b are given as examples of the structure of the semiconductor device above, the semiconductor device described in this embodiment is not limited thereto.
  • a semiconductor device 600 and a semiconductor device having a configuration similar to that of the semiconductor device 600 may be connected via a capacitor.
  • a semiconductor device having transistor 200a, transistor 200b, capacitive device 292a, and capacitive device 292b is referred to herein as a cell.
  • the above description of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b can be referred to.
  • FIG. 29B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitive device 292a, and a capacitive device 292b, and a cell having a configuration similar to that of the semiconductor device 600 are connected via a capacitive portion.
  • a conductor 294b functioning as one electrode of a capacitive device 292b included in the semiconductor device 600 also serves as one electrode of a capacitive device included in a semiconductor device 601 having the same configuration as the semiconductor device 600. It has become. Also, although not shown, the conductor 294a functioning as one electrode of the capacitive device 292a of the semiconductor device 600 is located on the left side of the semiconductor device 600, i.e., in FIG. Also serves as an electrode. The right side of the semiconductor device 601, that is, the cells in the A2 direction in FIG. 29B have the same configuration. That is, a cell array (also called a memory device layer) can be configured.
  • the interval between adjacent cells can be reduced, so that the projected area of the cell array can be reduced and high integration can be achieved. Further, by arranging the structure of the cell array shown in FIG. 29B in a matrix, a matrix-like cell array can be formed.
  • the cell area can be reduced and a semiconductor device having a cell array can be miniaturized or sophisticated. Integration can be achieved.
  • FIG. 30 shows a sectional view of a configuration in which n layers of cell arrays 610 are stacked. As shown in FIG. 30, by stacking a plurality of cell arrays (cell arrays 610_1 to 610_n), cells can be integrated and arranged without increasing the area occupied by the cell arrays. That is, a 3D cell array can be constructed.
  • FIGS. 31A, 31B, and 32A to 32H are used to describe a transistor using an oxide as a semiconductor (hereinafter also referred to as an OS transistor) according to one embodiment of the present invention, and A memory device to which a capacitor is applied (hereinafter sometimes referred to as an OS memory device) will be described.
  • An OS memory device is a memory device that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.
  • FIG. 31A shows an example of the configuration of the OS memory device.
  • a memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470 .
  • Peripheral circuitry 1411 includes row circuitry 1420 , column circuitry 1430 , output circuitry 1440 and control logic circuitry 1460 .
  • the column circuit 1430 has, for example, a column decoder, precharge circuit, sense amplifier, write circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • a sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wirings are wirings connected to memory cells included in the memory cell array 1470, and will be described later in detail.
  • the amplified data signal is output to the outside of memory device 1400 via output circuit 1440 as data signal RDATA.
  • the row circuit 1420 has, for example, a row decoder, a word line driver circuit, etc., and can select a row to be accessed.
  • the storage device 1400 is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as power supply voltages.
  • Control signals (CE, WE, RES), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row and column decoders, and the data signal WDATA is input to the write circuit.
  • the control logic circuit 1460 processes externally input control signals (CE, WE, RES) to generate control signals for the row decoder and column decoder.
  • Control signal CE is a chip enable signal
  • control signal WE is a write enable signal
  • control signal RES is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
  • the memory cell array 1470 has a plurality of memory cells MC arranged in rows and columns and a plurality of wirings.
  • the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, and the like.
  • the number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.
  • FIG. 31A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this.
  • a memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411 .
  • a structure in which a sense amplifier is provided under the memory cell array 1470 may be employed.
  • FIGS. 32A to 32H A configuration example of a memory cell that can be applied to the memory cell MC described above will be described with reference to FIGS. 32A to 32H.
  • [DOSRAM] 32A to 32C show circuit configuration examples of memory cells of a DRAM.
  • a DRAM using a 1-OS-transistor-1-capacitor-type memory cell is sometimes referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • a memory cell 1471 illustrated in FIG. 32A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a top gate) and a back gate.
  • the transistor M1 has a first terminal connected to the first terminal of the capacitor CA, a second terminal connected to the wiring BIL, a gate connected to the wiring WOL, and a back gate of the transistor M1. are connected to the wiring BGL.
  • a second terminal of the capacitive element CA is connected to the wiring LL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA.
  • the wiring LL may be at a ground potential or a low-level potential when writing and reading data.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell 1471 shown in FIG. 32A corresponds to the memory device shown in FIG. That is, the transistor M1 corresponds to the transistor 200 and the capacitive element CA corresponds to the capacitive device 292.
  • FIG. 32A corresponds to the memory device shown in FIG. That is, the transistor M1 corresponds to the transistor 200 and the capacitive element CA corresponds to the capacitive device 292.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, like the memory cell 1472 shown in FIG. 32B.
  • the memory cell MC may be a memory cell configured with a single-gate transistor, that is, a transistor M1 having no back gate, like the memory cell 1473 shown in FIG. 32C.
  • the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA.
  • the off-state current of the transistor M1 can be significantly reduced. In other words, since written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cells can be made unnecessary. In addition, since the off current is very small, multilevel data or analog data can be held in the memory cells 1471 , 1472 , and 1473 .
  • the bit line can be shortened. As a result, the bit line capacity is reduced, and the storage capacity of the memory cell can be reduced.
  • [NOSRAM] 32D to 32G show a circuit configuration example of a gain cell type memory cell with two transistors and one capacitive element.
  • a memory cell 1474 illustrated in FIG. 32D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the transistor M2 has a first terminal connected to the first terminal of the capacitor CB, a second terminal connected to the wiring WBL, a gate connected to the wiring WOL, and a back gate of the transistor M2. are connected to the wiring BGL.
  • a second terminal of the capacitive element CB is connected to the wiring CAL.
  • a first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitor CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB.
  • a high-level potential is preferably applied to the wiring CAL when data is written and when data is read. Further, it is preferable to apply a low-level potential to the wiring CAL while data is being held.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell 1474 shown in FIG. 32D corresponds to the memory device shown in FIGS. That is, the transistor M2 is connected to the transistor 200, the capacitor CB is connected to the capacitor 100, the transistor M3 is connected to the transistor 300, the wiring WBL is connected to the wiring 1003, the wiring WOL is connected to the wiring 1004, the wiring BGL is connected to the wiring 1006, and the wiring CAL is connected to the wiring. 1005 , the wiring RBL corresponds to the wiring 1002 , and the wiring SL corresponds to the wiring 1001 .
  • the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, like the memory cell 1475 shown in FIG. 32E.
  • the memory cell MC may be a memory cell configured with a single-gate transistor, that is, a transistor M2 that does not have a back gate, like the memory cell 1476 shown in FIG. 32F.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into one wiring BIL, like the memory cell 1477 shown in FIG. 32G.
  • the transistor 200 can be used as the transistor M2
  • the transistor 300 can be used as the transistor M3
  • the capacitor 100 can be used as the capacitor CB.
  • an OS transistor as the transistor M2
  • the off-state current of the transistor M2 can be significantly reduced. Accordingly, written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cells can be made unnecessary.
  • the memory cell 1474 can hold multilevel data or analog data. The same applies to memory cells 1475 to 1477 .
  • the transistor M3 may be a transistor including silicon in a channel formation region (hereinafter sometimes referred to as a Si transistor).
  • the conductivity type of the Si transistor may be n-channel type or p-channel type.
  • a Si transistor may have higher field effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a read transistor.
  • the transistor M2 can be stacked over the transistor M3, so that the area occupied by the memory cell can be reduced and the memory device can be highly integrated.
  • the transistor M3 may be an OS transistor.
  • OS transistors are used for the transistors M2 and M3, the circuit of the memory cell array 1470 can be formed using only n-channel transistors.
  • FIG. 32H shows an example of a gain cell type memory cell with 3 transistors and 1 capacitive element.
  • a memory cell 1478 illustrated in FIG. 32H includes transistors M4 to M6 and a capacitor CC. Capacitive element CC is provided as appropriate.
  • a memory cell 1478 is electrically connected to a wiring BIL, a wiring RWL, a wiring WWL, a wiring BGL, and a wiring GNDL.
  • a wiring GNDL is a wiring for applying a low-level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. Note that the back gate and gate of the transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a backgate.
  • the transistor M5 and the transistor M6 may each be an n-channel Si transistor or a p-channel Si transistor.
  • the transistors M4 to M6 may be OS transistors.
  • memory cell array 1470 can be configured using only n-type transistors.
  • the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitor 100 can be used as the capacitor CC.
  • the off-state current of the transistor M4 can be significantly reduced.
  • peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to those described above. Arrangements or functions of these circuits and wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
  • FIGS. 33A and 33B An example of a chip 1200 on which the semiconductor device of the invention is mounted is shown with reference to FIGS. 33A and 33B.
  • a plurality of circuits (systems) are mounted on the chip 1200 .
  • SoC System on Chip
  • the chip 1200 has a CPU 1211, a GPU 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with bumps (not shown) to connect with the first surface of the package substrate 1201 as shown in FIG. 33B.
  • a plurality of bumps 1202 are provided on the rear surface of the first surface of the package substrate 1201 and connected to the motherboard 1203 .
  • the mother board 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222 .
  • storage devices such as a DRAM 1221 and a flash memory 1222 .
  • the DOSRAM shown in the previous embodiment can be used for the DRAM 1221 .
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222 .
  • the CPU 1211 preferably has multiple CPU cores.
  • the GPU 1212 preferably has multiple GPU cores.
  • the CPU 1211 and GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200 .
  • the above-mentioned NOSRAM or DOSRAM can be used for the memory.
  • the GPU 1212 is suitable for parallel computation of a large amount of data, and can be used for image processing or sum-of-products operations. By providing the image processing circuit or the product-sum operation circuit using the oxide semiconductor of the present invention in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.
  • the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened. And, after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.
  • the analog computation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation unit 1213 may be provided with the sum-of-products calculation circuit.
  • the memory controller 1214 has a circuit functioning as a controller for the DRAM 1221 and a circuit functioning as an interface for the flash memory 1222 .
  • the interface 1215 has an interface circuit with externally connected devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, game controllers, and the like. USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used as such an interface.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.
  • a package substrate 1201 provided with a chip 1200 having a GPU 1212 , a motherboard 1203 provided with a DRAM 1221 and a flash memory 1222 can be called a GPU module 1204 .
  • the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum operation circuit using the GPU 1212 enables a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network ( DBN), the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recurrent neural network
  • DBM deep Boltzmann machine
  • DBN deep belief network
  • This embodiment mode shows an example of an electronic component and an electronic device in which the storage device or the like described in the above embodiment mode is incorporated.
  • FIG. 34A shows a perspective view of an electronic component 700 and a board (mounting board 704) on which the electronic component 700 is mounted.
  • Electronic component 700 shown in FIG. 34A has storage device 720 in mold 711 .
  • FIG. 34A is partially omitted to show the inside of electronic component 700 .
  • Electronic component 700 has lands 712 outside mold 711 . Land 712 is electrically connected to electrode pad 713 , and electrode pad 713 is electrically connected to storage device 720 by wire 714 .
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed board 702 .
  • the memory device 720 has a drive circuit layer 721 and a memory circuit layer 722 .
  • FIG. 34B A perspective view of the electronic component 730 is shown in FIG. 34B.
  • Electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • An electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 provided on the interposer 731 .
  • the electronic component 730 shows an example of using the storage device 720 as a high bandwidth memory (HBM).
  • HBM high bandwidth memory
  • an integrated circuit semiconductor device
  • a CPU, GPU, or FPGA can be used.
  • a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 732 .
  • a silicon interposer, a resin interposer, or the like can be used as the interposer 731 .
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. A plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 731 also has a function of electrically connecting the integrated circuit provided over the interposer 731 to electrodes provided over the package substrate 732 . For these reasons, the interposer is sometimes called a "rewiring board" or an "intermediate board".
  • through electrodes are provided in the interposer 731 and the integrated circuit and the package substrate 732 are electrically connected using the through electrodes.
  • a TSV Through Silicon Via
  • HBM In HBM, it is necessary to connect many wires in order to achieve a wide memory bandwidth. Therefore, an interposer for mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts the HBM.
  • the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA.
  • a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) be able to.
  • the semiconductor devices described in the above embodiments are, for example, storage devices of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/reproducing devices, navigation systems, etc.).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor devices described in the above embodiments are applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives).
  • 35A to 35E schematically show some configuration examples of removable storage devices.
  • the semiconductor devices described in the previous embodiments are processed into packaged memory chips and used for various storage devices and removable memories.
  • FIG. 35B is a schematic diagram of the appearance of the SD card
  • FIG. 35C is a schematic diagram of the internal structure of the SD card.
  • SD card 1110 has housing 1111 , connector 1112 and substrate 1113 .
  • a substrate 1113 is housed in a housing 1111 .
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113 .
  • a wireless chip having a wireless communication function may be provided on the substrate 1113 .
  • data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110 .
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 or the like.
  • a semiconductor device can be used for a processor such as a CPU or a GPU, or a chip.
  • 36A to 36H illustrate specific examples of electronic devices that include processors such as CPUs and GPUs, or chips according to one embodiment of the present invention.
  • a GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
  • electronic devices include relatively large screens such as televisions, monitors for desktop or notebook information terminals, digital signage (digital signage), large game machines such as pachinko machines, etc. , digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproducing devices, and the like.
  • the electronic device can be equipped with artificial intelligence.
  • the electronic device of one embodiment of the present invention may have an antenna.
  • An image, information, or the like can be displayed on the display portion by receiving a signal with the antenna.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared).
  • An electronic device of one embodiment of the present invention can have various functions. For example, functions to display various information (still images, moving images, text images, etc.) on the display, touch panel functions, functions to display calendars, dates or times, functions to execute various software (programs), wireless communication function, a function of reading a program or data recorded on a recording medium, and the like. Examples of electronic devices are shown in FIGS. 36A to 36H.
  • FIG. 36A shows a mobile phone (smartphone), which is a type of information terminal.
  • the information terminal 5100 has a housing 5101 and a display unit 5102.
  • the display unit 5102 is provided with a touch panel
  • the housing 5101 is provided with buttons.
  • the information terminal 5100 can execute an application using artificial intelligence.
  • Applications using artificial intelligence include, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5102.
  • An application displayed on the display portion 5102, an application for performing biometric authentication such as a fingerprint or a voiceprint, and the like can be given.
  • a notebook information terminal 5200 is illustrated in FIG. 36B.
  • the notebook information terminal 5200 has an information terminal main body 5201 , a display section 5202 , and a keyboard 5203 .
  • the notebook information terminal 5200 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Also, by using the notebook information terminal 5200, it is possible to develop new artificial intelligence.
  • a smartphone and a notebook information terminal are shown as examples of electronic devices in FIGS. 36A and 36B, respectively, but information terminals other than smartphones and notebook information terminals can be applied.
  • Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.
  • FIG. 36C shows a portable game machine 5300, which is an example of a game machine.
  • a portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like.
  • Housing 5302 and housing 5303 can be removed from housing 5301 .
  • the connection portion 5305 provided in the housing 5301 to another housing (not shown)
  • the video output to the display portion 5304 can be output to another video device (not shown). can.
  • the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play the game at the same time.
  • the chips described in the above embodiments can be incorporated into the chips or the like provided in the substrates of the housings 5301, 5302, and 5303.
  • FIG. 36D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is wirelessly or wiredly connected to the stationary game machine 5400 .
  • a low power consumption game machine By applying the GPU or chip of one embodiment of the present invention to a game machine such as the portable game machine 5300 and the stationary game machine 5400, a low power consumption game machine can be realized.
  • the low power consumption can reduce the heat generated from the circuit, thereby reducing the influence of the heat on the circuit itself, the peripheral circuits, and the module.
  • the portable game machine 5300 having artificial intelligence can be realized.
  • the progress of the game, the speech and behavior of creatures appearing in the game, and the expressions that occur in the game are determined by the program of the game. , which enables expressions not limited to game programs. For example, it is possible to express changes in the content of questions asked by the player, the progress of the game, the time, and the speech and behavior of characters appearing in the game.
  • the game players can be anthropomorphically configured by artificial intelligence. can play games.
  • FIGS. 36C and 36D illustrate a portable game machine and a stationary game machine as examples of game machines
  • game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these.
  • Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in amusement facilities (game arcades, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like. is mentioned.
  • a GPU or chip of one aspect of the present invention can be applied to large-scale computers.
  • FIG. 36E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • FIG. 36F is a diagram showing a rack-mounted computer 5502 that the supercomputer 5500 has.
  • a supercomputer 5500 has a rack 5501 and a plurality of rack-mount computers 5502 .
  • a plurality of computers 5502 are stored in the rack 5501 .
  • the computer 5502 is provided with a plurality of substrates 5504, and the GPUs or chips described in the above embodiments can be mounted over the substrates.
  • the supercomputer 5500 is a large computer mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous amounts of computation, resulting in high power consumption and high chip heat generation.
  • a low power consumption supercomputer can be realized.
  • the low power consumption can reduce the heat generated from the circuit, thereby reducing the influence of the heat on the circuit itself, the peripheral circuits, and the module.
  • FIGS. 36E and 36F illustrate a supercomputer as an example of a large computer
  • the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Large computers to which the GPU or chip of one aspect of the present invention is applied include, for example, computers that provide services (servers), large general-purpose computers (mainframes), and the like.
  • a GPU or chip of one embodiment of the present invention can be applied to automobiles, which are mobile objects, and to the vicinity of the driver's seat of automobiles.
  • FIG. 36G is a diagram showing the vicinity of the windshield in the interior of an automobile, which is an example of a mobile object.
  • FIG. 36G illustrates display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to the pillar.
  • the display panels 5701 to 5703 can provide various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, and the like. In addition, the display items and layout displayed on the display panel can be appropriately changed according to user's preference, and the design can be improved.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 can complement the field of view (blind spot) blocked by the pillars by displaying an image from an imaging device (not shown) provided in the automobile. That is, by displaying an image from an imaging device provided outside the automobile, blind spots can be compensated for and safety can be enhanced. In addition, by projecting an image that supplements the invisible part, safety confirmation can be performed more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
  • the chip can be used, for example, in an automatic driving system for automobiles.
  • the chip can be used in a system for road guidance, danger prediction, and the like.
  • the display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like, and the chip of one embodiment of the present invention can be applied to these moving objects. It is possible to give a system using artificial intelligence.
  • FIG. 36H shows an electric refrigerator-freezer 5800, which is an example of an appliance.
  • the electric freezer-refrigerator 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
  • the electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric freezer-refrigerator 5800 has a function of automatically generating a menu based on the ingredients stored in the electric freezer-refrigerator 5800, the expiration date of the ingredients, etc. It can have a function of automatically adjusting the temperature according to the temperature.
  • Electric refrigerators and freezers have been described as an example of electrical appliances, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
  • the electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, the effects thereof, and the like described in the present embodiment can be appropriately combined with the descriptions of other electronic devices.
  • FIGS. 6A to 6D can be referred to for the structure of the transistor included in the sample. Note that the designed values of the transistor included in the sample were a channel length of 20 nm and a channel width of 20 nm.
  • Embodiment Mode 1 can be referred to for details of the manufacturing method.
  • the insulator 212 used silicon nitride with a film thickness of 60 nm.
  • the insulator 212 was deposited by a pulse DC sputtering method using a silicon target.
  • the insulator 214 used aluminum oxide with a film thickness of 40 nm.
  • the insulator 214 was deposited by a pulsed DC sputtering method using an aluminum target.
  • the insulator 216 used silicon oxide with a film thickness of 130 nm.
  • the insulator 216 was deposited by a pulse DC sputtering method using a silicon target.
  • the insulator 212, the insulator 214, and the insulator 216 were formed continuously using a multi-chamber sputtering apparatus without being exposed to the outside air.
  • the conductor 205a was formed using a titanium nitride film formed by a metal CVD method.
  • the conductor 205b was formed using a tungsten film formed by a metal CVD method.
  • the insulator 222 used hafnium oxide with a film thickness of 20 nm deposited by the ALD method.
  • the insulator 224 was formed using silicon oxide with a film thickness of 20 nm formed by a sputtering method.
  • the conductors 242a and 242b were formed using a tantalum nitride film with a thickness of 20 nm formed by a sputtering method. Note that the conductive films to be the conductors 242a and 242b were formed using a metal tantalum target in an atmosphere containing nitrogen.
  • the insulators 271a1 and 271b1 were formed using a silicon nitride film with a thickness of 5 nm.
  • the insulators 271a2 and 271b2 were formed using a silicon oxide film. Note that the silicon nitride film and the silicon oxide film were continuously formed using a multi-chamber sputtering apparatus without exposure to the outside air.
  • the insulator 275 used silicon nitride with a film thickness of 5 nm formed by the ALD method.
  • the insulator 280 uses silicon oxide deposited by a sputtering method.
  • the insulator 252 was formed using an aluminum oxide film with a thickness of 1 nm deposited by the ALD method.
  • the insulator 250 was formed using a 3-nm-thick silicon oxide film formed by an ALD method.
  • the insulator 254 was formed using a 3-nm-thick silicon nitride film formed by an ALD method.
  • the conductor 260a was formed using a titanium nitride film with a film thickness of 5 nm, which was deposited by a metal CVD method.
  • the conductor 260b was formed using a tungsten film formed by a metal CVD method.
  • Aluminum oxide was used for the insulator 282 .
  • the insulator 282 was deposited by a pulsed DC sputtering method using an aluminum target.
  • the insulator 283a used silicon nitride with a film thickness of 20 nm formed by a sputtering method.
  • silicon nitride with a thickness of 5 nm deposited by an ALD method was used.
  • the insulator 274 uses silicon oxynitride deposited by the CVD method.
  • silicon oxide with a thickness of 50 nm formed by a sputtering method was used.
  • a laminate of a first insulator and a second insulator is used for each of the insulators 241a and 241b.
  • the first insulator was formed using an aluminum oxide film formed by an ALD method
  • the second insulator was formed using a silicon nitride film formed by an ALD method.
  • Each of the conductors 240a and 240b was formed using a laminated film of a titanium nitride film and a tungsten film on the titanium nitride film. Note that the titanium nitride film and the tungsten film were formed by a CVD method.
  • a sample including a transistor was produced as described above.
  • FIG. 37A to 37C are schematic diagrams showing the structures of prototype transistors.
  • 37A is a bird's-eye view of the transistor
  • FIG. 37B is a cross-sectional view of the transistor in the channel length direction
  • FIG. 37C is a cross-sectional view of the transistor in the channel width direction.
  • the transistor has a structure similar to that of the transistor 200 described in the above embodiment, and includes a top gate electrode (TGE), a top gate insulating layer (TGI), a back gate electrode (BGE), and a back gate electrode (BGE). )), a back gate insulator (BGI), an electrode (S/Electrode) functioning as a source or a drain, and the like.
  • TGE top gate electrode
  • TGI top gate insulating layer
  • BGE back gate electrode
  • BGE back gate electrode
  • the transistor includes an In--Ga--Zn oxide (CAAC-IGZO) having a CAAC structure in a channel formation region.
  • CAAC-IGZO In--Ga--Zn oxide
  • the laminated structure of the In--Ga--Zn oxide and the electrode functioning as the source or drain is processed into an island shape.
  • top gate electrode shown in FIGS. 37A to 37C corresponds to the conductors 260a and 260b
  • the back gate electrode corresponds to the conductor 205, providing back gate insulation.
  • the layer (back gate insulator) corresponds to the insulator 222 and the insulator 224
  • the electrode (S/D electrode) that functions as the source or drain corresponds to the conductor 242a or the conductor 242b and includes CAAC-IGZO.
  • the active layer also called semiconductor layer
  • a top gate insulating layer corresponds to insulator 252 , insulator 250 , and insulator 254 .
  • the thickness of the active layer containing CAAC-IGZO is 25 nm, and the physical thickness of the top gate insulating layer is 7 nm.
  • FIG. 38A A photographed planar SEM image is shown in FIG. 38A. Note that part of the planar SEM image corresponds to the top view shown in FIG. 14A. Further, FIG. 38B shows an enlarged view of a planar SEM image of the area indicated by a solid-line rectangle in FIG. 38A.
  • the top gate is indicated by an arrow.
  • the region indicated by the arrow in FIG. 38A can also be said to be an opening (Gate Trench Etching) provided by etching. Also, the region indicated by the arrow in FIG. 38B is the channel formation region (Channel).
  • FIG. 39A shows a cross-sectional STEM image of the fabricated sample in the channel length direction
  • FIG. 39B shows a cross-sectional STEM image of the fabricated sample in the channel width direction
  • 39A is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in FIG. 38B
  • FIG. 39B is a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in FIG. 38B. Note that in FIGS. 39A and 39B, some components (for example, the insulator 271 and the insulator 275) are not labeled.
  • the length of each component was measured based on the observation results of cross-sectional STEM images.
  • the gate length in the channel length direction (width Lg shown in FIG. 4A) of the transistor included in the sample was 6.7 nm.
  • the length in the channel width direction of the interface between the oxides 230a and 230b contained in the sample was 29.3 nm.
  • FIG. 39C A cross-sectional STEM image of the channel formation region of the oxide 230b and its vicinity is shown in FIG. 39C. Note that FIG. 39C is also an enlarged view of FIG. 39A. A lattice image was observed in the cross-sectional STEM image shown in FIG. 39C.
  • an FFT pattern was obtained by performing fast Fourier transform (FFT) processing.
  • FFT fast Fourier transform
  • the FFT pattern obtained by performing the FFT processing has a pattern reflecting reciprocal lattice space information similar to the electron beam diffraction pattern.
  • a cross-sectional STEM image of the CAAC-OS taken in a direction perpendicular to the c-axis two high-intensity spots may be observed in the FFT pattern.
  • the intensity of these two spots represents the degree of crystallinity of the CAAC-OS, and the angle of the line connecting the two spots represents the crystal orientation of the CAAC-OS.
  • the acquired FFT pattern is shown in FIG. 39D.
  • two spots with high intensity spots indicated by arrows in Figure 39D
  • the oxide 230b was CAAC-OS.
  • Id-Vg characteristics were measured as electrical characteristics.
  • the Id-Vg characteristics were measured by setting the drain voltage Vd to 0.1 V or 1.2 V, the source voltage Vs and the back gate voltage Vbg to 0 V, and sweeping the top gate voltage Vg from ⁇ 4 V to +4 V in steps of 0.1 V. bottom. Moreover, the said measurement was performed in a room temperature environment.
  • FIG. 40A shows the Id-Vg characteristics of the transistor included in the manufactured sample.
  • the first and second vertical axes represent the drain current per 1 ⁇ m channel width, and the horizontal axis represents the gate-source voltage (Vg) [V].
  • the vertical axis on the left side (first vertical axis) is shown in logarithmic scale (Log), and the unit is [A/ ⁇ m].
  • the vertical axis on the right side (second vertical axis) is indicated by a linear scale (Linear), and the unit is [ ⁇ A/ ⁇ m].
  • the solid line indicates the drain current Id (logarithmic scale) when the drain voltage Vd is 1.2 V
  • the dotted line indicates the drain current Id (linear scale) when the drain voltage Vd is 1.2 V. show.
  • Vth is defined as the gate-source voltage Vg when the drain current Id is 1 pA.
  • SS is a sub-threshold slope.
  • gm is the mutual conductance.
  • FIG. 40B shows Id-Vg characteristics of a transistor different from the transistor whose Id-Vg characteristics are shown in FIG. 40A.
  • the left vertical axis (first vertical axis) represents drain current (Id) [A]
  • the right vertical axis (second vertical axis) represents field effect mobility ( ⁇ FE) [cm 2 /Vs].
  • the horizontal axis represents Vg [V].
  • the solid line indicates the drain current Id when the drain voltage Vd is 1.2 V
  • the dashed line indicates the drain current Id when the drain voltage Vd is 0.1 V
  • the dashed line indicates the field effect. shows mobility.
  • the field-effect mobility was calculated from the value measured with the drain voltage Vd set to 1.2V.
  • Vth A normal probability plot diagram of Vth is shown in FIG. In FIG. 41, the horizontal axis is Vth [V] and the vertical axis is the estimated cumulative probability (%).
  • Methods for calculating the estimated cumulative probability include the median rank method, the average rank method, the symmetric sample cumulative distribution method, and the Kaplan-Meier method. In this example, the estimated cumulative probability was calculated using the median rank method.
  • the standard deviation ( ⁇ ) of Vth of 34 transistors excluding two outliers was about 134 mV.
  • the Id-Vd characteristics were measured as electrical characteristics.
  • the Id-Vd characteristics were measured with the top gate voltage Vg set to 1.0 V, 1.2 V, 1.4 V, 1.6 V, 1.8 V, or 2.0 V, and the source voltage Vs and the back gate voltage Vbg set to 0 V.
  • the drain voltage Vd was swept from 0V to 2.5V in steps of 0.05V.
  • the said measurement was performed in a room temperature environment.
  • FIG. 47 shows the Id-Vd characteristics of the transistor included in the manufactured sample.
  • the vertical axis represents drain current per 1 ⁇ m channel width ( ⁇ A/ ⁇ m), and the horizontal axis represents drain-source voltage (Vd) [V].
  • sample A1 has a gate length of 9.9 nm in the channel length direction.
  • sample A2 has a gate length of 14.3 nm in the channel length direction.
  • Sample A3 has a gate length of 17.9 nm in the channel length direction. Note that the above sample (a sample having a gate length in the channel length direction of 9.9 nm and a length in the channel width direction of 32.6 nm) is referred to as sample A0.
  • the structures of the transistors are the same in the samples A0 to A3.
  • FIG. 42 shows plots of Vth of transistors included in each of the samples A0 to A3.
  • the vertical axis represents Vth [V]
  • the horizontal axis represents the gate length (Gate Length) [nm] in the channel length direction.
  • a wiring 2000 is electrically connected to one of the source and drain of the transistor M30, a wiring 2001 is electrically connected to the gate of the transistor M30, and a wiring 2002 is electrically connected to one of the reading circuit R10. It is connected to the.
  • the other of the source and the drain of the transistor M30 is electrically connected to the node FN, the other of the reading circuit is electrically connected to the node FN, and one of the source and the drain of the transistor M22 is electrically connected to the node FN.
  • a wiring 2003 is electrically connected to the gate of the transistor M22, a wiring 2004 is electrically connected to the other of the source and the drain of the transistor M22, and a wiring 2005 is electrically connected to the back gate of the transistor M22. .
  • the transistor M30 is a write transistor, and the transistor M22 is a transistor whose retention characteristics are to be measured. Although the transistor M22 is illustrated as one transistor in FIG. 43A, the transistor M22 is a transistor in which 20000 transistors (transistors with a channel length of 9.9 nm and a channel width of 32.6 nm) included in the sample A1 are connected in parallel. is.
  • a potential of the wiring 2001 was set so that the transistor M30 was turned on, a potential of 1.2 V was applied to the wiring 2000, and charges were accumulated in the node FN so that the potential of 1.2 V was set. After that, a potential of ⁇ 3 V was applied to the wiring 2001 to turn off the transistor M30.
  • the potential of the wiring 2004 was set to 0 V and the potential of the wiring 2005 was set to -3 V so that the transistor M22 was turned off.
  • the potential of the wiring 2003 electrically connected to the gate of the transistor M22 was -1.5V.
  • the above state was held for a certain period of time, the change in the potential of the node FN over time was read by the reading circuit R10, and the leakage current value was derived from the read value.
  • the value of the off current can be known.
  • FIG. 43B shows the measurement results of the off current Ioff measured under temperature environments of 85°C, 100°C, and 125°C.
  • the horizontal axis of FIG. 43B indicates the value obtained by multiplying the reciprocal of the temperature by 1000 (1000/T) [1/K], and the vertical axis indicates the off current Ioff [A/FET] per transistor in logarithm.
  • the frequency characteristics of the transistor included in the manufactured sample were measured. Specifically, the cutoff frequency and the maximum oscillation frequency with respect to the channel length of the transistor were measured. In the measurement of the frequency characteristics, the drain voltage Vd was set to 2.5V and the top gate voltage Vg was set to 1.5V. Moreover, the measurement was performed under a room temperature environment (here, under a temperature environment of 27°C). Further, the measurement was performed by connecting 1000 transistors in parallel. Here, frequency characteristics were measured for two transistors. In the first transistor, the gate length in the channel length direction is 6.7 nm and the length in the channel width direction is 29.3 nm. In the second transistor, the gate length in the channel length direction is 9.9 nm and the length in the channel width direction is 32.6 nm.
  • Fig. 44A shows the environment for measuring frequency characteristics.
  • the measurement equipment shown in FIG. 44A includes a network analyzer, a DC power supply, and a prober.
  • N5247A manufactured by Keysight was prepared as a network analyzer.
  • DC power supplies a first DC power supply (6242 manufactured by ADCMT), a second DC power supply (6241A manufactured by ADCMT), and a third DC power supply (PW18-1.8AQ manufactured by Kenwood) are used.
  • I67-A-GSG-100 manufactured by FORMFACTOR was prepared as a probe head (PROBE HEAD) of the prober. The two probe heads are connected to ports (port1, port2) of the network analyzer, respectively.
  • a first DC power supply for supplying power to port 1 is connected to port 1 of the network analyzer via the network analyzer, and a second DC power supply for supplying power to port 2 is connected to port 2 of the network analyzer.
  • a DC power supply is connected through a network analyzer.
  • one probe needle connected to a third DC power supply (BackGate) is applied to a TEG, which will be described later.
  • FIG. 44B shows the circuit diagrams of each of the three types of TEGs, the plan view of the DUT, and its enlarged view.
  • the S-parameters were measured by a network analyzer, and the cut-off frequency f T and the maximum oscillation frequency f max were obtained from the obtained S-parameters.
  • the cut-off frequency f T is defined as the frequency at which the current gain, or extrapolated value of the current gain, is unity.
  • the current amplification factor is a non-diagonal component of the H matrix, and is represented by the following formula (1) using S parameters.
  • the maximum oscillation frequency f max is defined as the frequency at which the power amplification factor or the extrapolated value of the power amplification factor is 1.
  • the power amplification factor can be the maximum available power gain or the maximum unidirectional power gain (also called unitary power gain).
  • the maximum available power gain MAG is represented by the following formula (2).
  • K is a stabilization factor (also referred to as a K factor) and is represented by formula (3) below.
  • Equation (2) the maximum available power gain MAG represented by Equation (2) can be used when K is greater than one. In other words, if K is less than 1, the maximum available power gain MAG cannot be defined by equation (2). If K is less than 1, the maximum stable gain MSG can be used.
  • the maximum stable gain MSG is represented by Equation (4) below.
  • the maximum unidirectional power gain Ug is represented by the following formula (5).
  • the maximum oscillation frequency f max was calculated using the maximum available power gain MAG and the maximum stable gain MSG.
  • 45A and 48A show measurement results of the cutoff frequency of the first transistor (the gate length in the channel length direction is 6.7 nm and the length in the channel width direction is 29.3 nm).
  • 45A and 48A the vertical axis indicates the current gain (
  • the solid lines shown in FIGS. 45A and 48A indicate the actual measurement of current gain with respect to frequency, and the dashed lines shown in FIGS. 45A and 48A indicate the extrapolation of the actual measurement of current gain with respect to frequency.
  • 45A and 48A differ from each other in plot ranges of actual measurement of current gain with respect to frequency.
  • FIG. 48B shows the measurement results of the maximum oscillation frequency.
  • the vertical axis indicates current gain (Gain) [dB]
  • the horizontal axis indicates frequency (Frequency) [GHz].
  • values of maximum stable gain MSG are given, and at frequencies above 22 GHz, values of maximum available power gain MAG are given.
  • the cutoff frequency f T of the first transistor (having a gate length in the channel length direction of 6.7 nm and a length in the channel width direction of 29.3 nm) was estimated to be 119 GHz. was estimated to be 14.7 GHz .
  • the cutoff frequency f T of the second transistor (having a gate length in the channel length direction of 9.9 nm and a length in the channel width direction of 32.6 nm) was estimated to be 124 GHz.
  • the transistors included in the manufactured samples were fine and exhibited good electrical characteristics.
  • the transistor was shown to have excellent frequency characteristics.
  • FIG. 46 shows a graph in which the reported year is plotted on the horizontal axis and the gate length (nm) [nm] is plotted on the vertical axis.
  • the plot indicated by square marks in FIG. 46 is the gate length of the transistor manufactured in this example (this work). Note that the plots indicated by the circles in FIG. 46 are plotted with reference to the gate lengths of transistors that have been prototyped by the company in the past or that have been reported.
  • the configuration of the transistor included in the fabricated sample is the same as the configuration of the transistor described in [Fabrication of sample] above, except for the gate length and channel width. In this section, eight transistors (transistors 901 to 908) are manufactured.
  • the transistors 901, 902, 903, and 904 had channel lengths of 6 nm, 11 nm, 16 nm, and 21 nm, respectively, and a channel width (design value) of 20 nm.
  • the transistors 905, 906, 907, and 908 had channel lengths of 36 nm, 41 nm, 56 nm, and 66 nm, respectively, and a channel width (design value) of 60 nm.
  • Id-Vg characteristics were measured as electrical characteristics.
  • the Id-Vg characteristic is measured by setting the drain voltage Vd to 0.1 V or 1.2 V, the source voltage Vs and the back gate voltage Vbg to 0 V, and sweeping the top gate voltage Vg from ⁇ 4 V to +4 V in steps of 0.1 V. bottom. Moreover, the said measurement was performed in a room temperature environment.
  • 49A to 49D show the Id-Vg characteristics of the transistors 901 to 904, respectively, and FIGS. 50A to 50D show the Id-Vg characteristics of the transistors 905 to 908, respectively. 49A to 49D and FIGS. 50A to 50D, it was found that good switching characteristics were obtained in any of the manufactured transistors.
  • OS transistors As described in Embodiment 2, cell arrays including OS transistors can be stacked. That is, OS transistors (also referred to as OSFETs) can be stacked. In this section, a sample in which an OSFET is stacked was manufactured, and electrical characteristics of an OS transistor included in each layer were evaluated.
  • Fig. 51 shows a schematic diagram showing the structure of the prepared sample. As shown in FIG. 51, the sample has a structure in which two layers including an MOSFET are stacked. A relay layer is provided between the first layer (1st-layer) and the second layer (2nd-layer).
  • a relay wiring is provided in the relay layer, and the relay wiring is electrically connected to one of the source electrode and the drain electrode of the first-layer OSFET through a plug (Via).
  • Id-Vg characteristics were measured as electrical characteristics.
  • the Id-Vg characteristics were measured by setting the drain voltage Vd to 0.1 V or 1.2 V, the source voltage Vs and the back gate voltage Vbg to 0 V, and sweeping the top gate voltage Vg from ⁇ 4 V to +4 V in steps of 0.1 V. bottom. Moreover, the said measurement was performed in a room temperature environment. Note that the Id-Vg characteristics were measured after forming the second layer.

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  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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