WO2019171205A1 - 積層体、及び半導体装置 - Google Patents
積層体、及び半導体装置 Download PDFInfo
- Publication number
- WO2019171205A1 WO2019171205A1 PCT/IB2019/051516 IB2019051516W WO2019171205A1 WO 2019171205 A1 WO2019171205 A1 WO 2019171205A1 IB 2019051516 W IB2019051516 W IB 2019051516W WO 2019171205 A1 WO2019171205 A1 WO 2019171205A1
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- WIPO (PCT)
- Prior art keywords
- oxide
- insulator
- conductor
- film
- oxygen
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 347
- 239000013078 crystal Substances 0.000 claims abstract description 126
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- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
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- 229910052754 neon Inorganic materials 0.000 description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000001151 other effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
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- 230000001681 protective effect Effects 0.000 description 2
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- 241000894007 species Species 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- 239000011593 sulfur Substances 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000004627 transmission electron microscopy Methods 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 208000003464 asthenopia Diseases 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 229910000416 bismuth oxide Inorganic materials 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
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- TYIXMATWDRGMPF-UHFFFAOYSA-N dibismuth;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Bi+3].[Bi+3] TYIXMATWDRGMPF-UHFFFAOYSA-N 0.000 description 1
- 238000002050 diffraction method Methods 0.000 description 1
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- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000002524 electron diffraction data Methods 0.000 description 1
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
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- 238000009616 inductively coupled plasma Methods 0.000 description 1
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- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
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- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
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- 239000010453 quartz Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 229910002076 stabilized zirconia Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 238000012916 structural analysis Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 229910001233 yttria-stabilized zirconia Inorganic materials 0.000 description 1
Images
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
Definitions
- One embodiment of the present invention relates to a stacked body, a semiconductor device, and a manufacturing method thereof.
- One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
- a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
- a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device.
- a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may have a semiconductor device. .
- one embodiment of the present invention is not limited to the above technical field.
- One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
- one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
- oxide semiconductor As a material for a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor has attracted attention as another material.
- oxide semiconductors for example, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known.
- IGZO In—Ga—Zn oxide
- Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, Non-Patent Document 4 and Non-Patent Document 5 show that even an oxide semiconductor having lower crystallinity than the CAAC structure and the nc structure has a minute crystal.
- Non-Patent Document 6 a transistor using IGZO as an active layer has extremely low off-state current (see Non-Patent Document 6), and an LSI and a display using the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8). .
- An object of one embodiment of the present invention is to provide a stacked body with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a stacked body with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.
- An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time.
- An object of one embodiment of the present invention is to provide a semiconductor device with high data writing speed.
- An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.
- An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption.
- An object of one embodiment of the present invention is to provide a novel semiconductor device.
- One embodiment of the present invention includes an insulator, a conductor, and a first oxide between the insulator and the conductor, and the first oxide is a c-axis-aligned first crystal.
- the c-axis of the first crystal region is a stacked body that is substantially perpendicular to the surface of the first oxide on the insulator side.
- One embodiment of the present invention includes an insulator, a conductor, a first oxide between the insulator and the conductor, and a second oxide that faces the first oxide across the insulator.
- the first oxide has a c-axis oriented first crystal region, and the c axis of the first crystal region is roughly the same as the surface of the first oxide on the insulator side.
- Another embodiment of the present invention is the first oxide, the second oxide, the third oxide, the first insulator, the first conductor, and the second conductor.
- a first conductor covering a side surface and a lower surface of the first conductor; a first insulator covering a side surface and a lower surface of the first oxide;
- the second oxide covers the side surface and the lower surface of the first insulator, the third oxide is in contact with the lower surface of the second oxide, and the first oxide is c-axis oriented first
- the first crystal region has a c-axis substantially perpendicular to the surface of the first oxide on the first insulator side, and the second conductor and the third conductor are third
- the semiconductor device is located opposite to the other oxide via the second oxide.
- the second oxide has a c-axis oriented second crystal region, and the c axis of the second crystal region corresponds to the surface of the second oxide on the first insulator side. It is preferable that it is substantially vertical.
- the third oxide has a c-axis-oriented third crystal region, and the second crystal region has a c-axis in a direction different from the c-axis of the third crystal region. preferable.
- the first crystal region preferably has a c-axis in a direction different from the c-axis of the third crystal region.
- the height of the upper surface of the conductor is preferably substantially the same as the height of the upper surface of the first oxide, the upper surface of the second oxide, and the upper surface of the first insulator.
- the above-described semiconductor device further includes a second insulator in contact with the side surface of the second oxide.
- the second insulator has an opening, and the first oxide and the second oxide are formed in the opening.
- the height of the upper surface of the second insulator is substantially the same as the height of the upper surface of the conductor.
- One embodiment of the present invention includes a first oxide, a second oxide, a third oxide, a first insulator, and a conductor.
- the first oxide includes: Covering the side and bottom surfaces of the conductor, the first insulator covers the side and bottom surfaces of the first oxide, the second oxide covers the side and bottom surfaces of the first insulator, and the third oxide
- the oxide is in contact with the lower surface of the second oxide, the first oxide has a c-axis oriented first crystal region, and the c axis of the first crystal region is on the first insulator side.
- the semiconductor device is substantially perpendicular to the surface of the first oxide.
- the second oxide has a c-axis oriented second crystal region, and the c axis of the second crystal region corresponds to the surface of the second oxide on the first insulator side. It is preferable that it is substantially vertical.
- the third oxide has a c-axis-oriented third crystal region, and the second crystal region has a c-axis in a direction different from the c-axis of the third crystal region. preferable.
- the first crystal region preferably has a c-axis in a direction different from the c-axis of the third crystal region.
- the third oxide includes a first region, a second region and a third region sandwiching the first region, and the first region overlaps with the conductor. It has a region, and it is preferable that the second region and the third region have one or more selected from phosphorus, boron, aluminum, or magnesium.
- the height of the upper surface of the conductor is preferably substantially the same as the height of the upper surface of the first oxide, the upper surface of the second oxide, and the upper surface of the first insulator.
- the above-described semiconductor device further includes a second insulator in contact with the side surface of the second oxide.
- the second insulator has an opening, and the first oxide and the second oxide are formed in the opening.
- the height of the upper surface of the second insulator is substantially the same as the height of the upper surface of the conductor.
- the second oxide overlap with part of the second region and part of the third region.
- One embodiment of the present invention includes a first oxide, a second oxide, a third oxide, a first insulator, a second insulator, and a first conductor.
- the first oxide is in contact with the lower surface of the first conductor
- the first insulator is in contact with the lower surface of the first oxide
- the second oxide is in contact with the lower surface of the first insulator.
- the third oxide is in contact with the lower surface, the third oxide is in contact with the lower surface of the second oxide, the first oxide has a c-axis oriented first crystal region, and the c-axis of the first crystal region is , Substantially perpendicular to the surface of the first oxide on the first insulator side, the second oxide has a second crystal region with c-axis orientation, and the c-axis of the second crystal region is The second insulator is substantially perpendicular to the surface of the second oxide on the first insulator side, the second insulator is located above the third oxide, and the second insulator is formed of the second oxide.
- the third oxide in contact with the end portion includes the first region and the first region.
- the first region has a region overlapping with the first conductor, and the second region and the third region are phosphorous, boron, and aluminum.
- the semiconductor device includes one or more selected from magnesium.
- the above-described semiconductor device further includes a third insulator having an opening, and the third insulator is a part of the lower surface of the second oxide and a part and a side surface of the upper surface of the third oxide. It is preferable that the second oxide and the third oxide are in contact with each other through the opening.
- One embodiment of the present invention includes a first oxide, a second oxide, a third oxide, a first insulator, a second insulator, a first conductor, And the first oxide is in contact with the lower surface of the first conductor, and the first insulator is in contact with the lower surface of the first oxide.
- the second oxide is in contact with the lower surface of the first insulator, the third oxide is in contact with the lower surface of the second oxide, and the first oxide is a c-axis oriented first crystal.
- the c-axis of the first crystal region is substantially perpendicular to the surface of the first oxide on the first insulator side
- the second oxide is a c-axis oriented second crystal region
- the c-axis of the second crystal region is substantially perpendicular to the surface of the second oxide on the first insulator side
- the second insulator is located above the third oxide.
- the second insulator is in contact with the end of the second oxide and the second conductor.
- Body and the third conductor is a semiconductor device located opposite through a second oxide in the third on-oxide.
- the semiconductor device further includes a third insulator having an opening, and the third insulator is a part of the lower surface of the second oxide, a part of the upper surface and the side surface of the second conductor, It is preferable that the second oxide and the third oxide are in contact with part of the upper surface and the side surface of the third conductor and the side surface of the third oxide and through the opening.
- the third oxide has a c-axis-oriented third crystal region, and the second crystal region has a c-axis in a direction different from the c-axis of the third crystal region. preferable.
- the first crystal region preferably has a c-axis in a direction different from the c-axis of the third crystal region.
- a stacked body with favorable electrical characteristics can be provided.
- a stacked body with favorable reliability can be provided.
- a semiconductor device with high on-state current can be provided.
- a semiconductor device having high frequency characteristics can be provided.
- a semiconductor device with favorable reliability can be provided.
- a semiconductor device that can be miniaturized or highly integrated can be provided.
- a semiconductor device having favorable electrical characteristics can be provided.
- a highly productive semiconductor device can be provided.
- a semiconductor device capable of retaining data for a long time can be provided.
- a semiconductor device with high data writing speed can be provided.
- a semiconductor device with a high degree of design freedom can be provided.
- a semiconductor device that can reduce power consumption can be provided.
- a novel semiconductor device can be provided.
- Sectional drawing of the laminated body which concerns on 1 aspect of this invention illustrates a movement path of oxygen in an In—Ga—Zn oxide.
- 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
- FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
- FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention.
- FIG. 10 is a schematic view of a semiconductor device according to one embodiment of the present invention.
- FIG. 3 is a schematic diagram of a memory device according to one embodiment of the present invention.
- FIG. 14 illustrates an electronic device according to one embodiment of the present invention. The calculation result of the diffusion coefficient and diffusion length of 18 O in a metal oxide film based on an Example.
- a top view also referred to as a “plan view”
- a perspective view a perspective view, and the like
- some components may be omitted in order to facilitate understanding of the invention.
- description of some hidden lines may be omitted.
- the ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.
- the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
- X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
- the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
- the channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) and the channel width shown in the top view of the transistor (Hereinafter also referred to as “apparent channel width”) may be different.
- the effective channel width when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible.
- the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.
- channel width when it is simply described as a channel width, it may indicate an apparent channel width.
- channel width in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
- the impurity of a semiconductor means the thing other than the main component which comprises a semiconductor, for example.
- an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
- the impurities are included, for example, DOS (Density of States) of the semiconductor may increase or crystallinity may decrease.
- examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor.
- water may also function as an impurity.
- oxygen vacancies may be formed, for example, by mixing impurities.
- impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
- silicon oxynitride has a higher oxygen content than nitrogen.
- silicon nitride oxide has a composition containing more nitrogen than oxygen.
- the term “insulator” can be referred to as an insulating film or an insulating layer.
- the term “conductor” can be restated as a conductive film or a conductive layer.
- the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
- the barrier film is a film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, and when the barrier film has conductivity, Sometimes called.
- a metal oxide is a metal oxide in a broad sense.
- Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS).
- oxide semiconductors also referred to as oxide semiconductors or simply OS.
- the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET or an OS transistor, it can be said to be a transistor including an oxide or an oxide semiconductor.
- normally-off means that when a potential is not applied to the gate or a ground potential is applied to the gate, a current per channel width of 1 ⁇ m flowing through the transistor is 1 ⁇ 10 ⁇ 20 at room temperature. A or lower, 1 ⁇ 10 ⁇ 18 A or lower at 85 ° C., or 1 ⁇ 10 ⁇ 16 A or lower at 125 ° C.
- FIG. 1A is a cross-sectional view of a stack 10 according to one embodiment of the present invention.
- the stacked body 10 includes an insulator 11, a conductor 15, and an oxide 13 between the insulator 11 and the conductor 15.
- the oxide 13 is an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium) It is preferable to use a metal oxide such as neodymium, hafnium, tantalum, tungsten, or magnesium.
- the element M may be aluminum, gallium, yttrium, or tin.
- an In—Ga oxide or an In—Zn oxide may be used as the oxide 13.
- the oxide 13 preferably has crystallinity.
- the oxide 13 it is preferable to use a CAAC-OS (c-axis aligned crystal oxide semiconductor).
- the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and has a strain.
- the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
- Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
- a lattice arrangement such as a pentagon and a heptagon in the distortion.
- it is difficult to check a clear crystal grain boundary also referred to as a grain boundary
- the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Because.
- the CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
- In layer a layer containing indium and oxygen
- M, Zn elements M, zinc, and oxygen
- indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
- CAAC-OS is a metal oxide with high crystallinity.
- CAAC-OS impurities and defects oxygen deficiency (V O:. Oxygen vacancy also referred) etc.) with less metal It can be said that it is an oxide. Therefore, the physical properties of the metal oxide including a CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.
- CAAC-OS analyzed by X-ray diffraction X-ray Diffraction
- XRD X-Ray Diffraction
- a peak may appear when the diffraction angle (2 ⁇ ) is in the vicinity of 31 °. Since this peak is attributed to the (009) plane of the InGaZnO 4 crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis is oriented substantially perpendicular to the formation surface or the top surface.
- CAAC-OS analyzed by electron diffraction An example of a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO 4 crystal in parallel with a sample surface, a diffraction pattern (also referred to as a limited-field transmission electron diffraction pattern) may appear. This diffraction pattern includes spots caused by the (009) plane of the InGaZnO 4 crystal. Therefore, electron diffraction reveals that crystals included in the CAAC-OS have c-axis alignment and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface.
- a diffraction pattern also referred to as a limited-field transmission electron diffraction pattern
- crystallography it is common to take a unit cell having a specific axis as the c-axis among the three axes (crystal axis) of the a-axis, b-axis, and c-axis constituting the unit cell.
- a crystal having a layered structure two axes parallel to the plane direction of the layer are generally defined as an a axis and a b axis, and an axis intersecting the layer is generally defined as a c axis.
- a crystal having such a layered structure there is graphite classified as a hexagonal system, the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is orthogonal to the cleavage plane.
- graphite classified as a hexagonal system the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is orthogonal to the cleavage plane.
- an InGaZnO 4 crystal having a layered structure of YbFe 2 O 4 type crystal structure can be classified into a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layer, and the c-axis Is orthogonal to the layer (ie, the a-axis and b-axis).
- the oxide 13 has a c-axis oriented crystal region. As shown in FIG. 1A, the oxide 13 includes a crystal layer 13P extending in the ab plane direction and a c-axis 13X perpendicular to the ab plane.
- the oxide 13 has a plurality of layers 13P and a plurality of c-axes 13X.
- the c-axis 13X of the crystal region is substantially perpendicular to the surface of the oxide 13 on the insulator 11 side. Being substantially perpendicular to the surface is synonymous with being substantially parallel to the normal of the surface. That is, in the oxide 13, the c-axis 13X of the crystal region can be said to be substantially parallel to the normal line of the surface of the oxide 13 on the insulator 11 side.
- the insulator 11 and the oxide 13 are preferably provided in contact with each other. By providing the insulator 11 and the oxide 13 in contact with each other, it becomes easy to form a region having a c-axis 13X that is substantially perpendicular to the surface of the oxide 13 on the insulator 11 side.
- the ab plane of the oxide 13 can be confirmed, for example, by observing a crystal lattice image of atoms arranged in a layered manner in observation of a cross section using transmission electron microscopy (TEM: Transmission Electron Microscopy).
- the surface A and the straight line B are substantially perpendicular means a state where the angle formed by the surface A and the straight line B is 60 ° or more and 90 ° or less.
- the plane A and the straight line B are substantially parallel means a state where the angle formed by the normal line of the plane A and the straight line B is 60 ° or more and 90 ° or less.
- the straight line C and the straight line D being substantially vertical means a state in which the angle formed by the straight line C and the straight line D is 60 ° or more and 90 ° or less.
- the straight line C and the straight line D being substantially parallel means a state in which the angle formed by the straight line C and the straight line D is 0 ° or more and 30 ° or less.
- the film thickness of the oxide 13 is, for example, 2 nm or more, preferably 3 nm or more, more preferably 5 nm or more.
- a region can be formed in which the c-axis 13 ⁇ / b> X is oriented so as to be substantially perpendicular to the surface of the oxide 13 on the insulator 11 side.
- CAAC-OS has a property that oxygen is less likely to diffuse in the c-axis direction than in the ab plane direction. Therefore, the oxide 13 is provided below the insulator 11 or the insulator 11 by having a crystal region that is c-axis oriented so as to be substantially perpendicular to the surface of the oxide 13 on the insulator 11 side. It is possible to suppress diffusion of oxygen from the insulator containing oxygen into the conductor 15. Thereby, it can suppress that the conductor 15 is oxidized, and can suppress that the resistance of the conductor 15 becomes high.
- the average surface roughness (Ra) of the formation surface of the insulator 11 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less.
- the average surface roughness (Ra) is obtained by extending the arithmetic average roughness defined in JIS B0601: 2001 (ISO4287: 1997) to three dimensions so that it can be applied to curved surfaces. Yes, expressed as an average of the absolute values of deviations from the reference plane to the specified plane.
- the average surface roughness (Ra) can be measured with an atomic force microscope (AFM).
- an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, resin, or the like can be used.
- a plurality of insulating layers formed using the above materials may be stacked.
- the oxide 13 includes a region in which the c-axis 13X is oriented so as to be substantially perpendicular to the surface of the oxide 13 on the insulator 11 side. 11 or oxygen diffused from the insulator containing oxygen provided under the insulator 11 into the oxide 13 is likely to diffuse in the ab plane direction in the oxide 13 (the diffusion path shown in FIG. 1A). Route 2).
- oxygen diffused in the oxide 13 is difficult to diffuse in the c-axis direction in the oxide 13. Since oxygen is difficult to diffuse in the c-axis direction, oxygen can be prevented from diffusing into the conductor 15 from the insulator 11 or the insulator containing oxygen provided under the insulator 11 (FIG. 1A). Diffusion route Route 1) shown in FIG. Thereby, it can suppress that the conductor 15 is oxidized, and can suppress that the resistance of the conductor 15 becomes high.
- FIG. 1A illustrates an example in which the c-axis 13X is in the vertical direction on the paper surface; however, one embodiment of the present invention is not limited thereto.
- the c-axis 13X may be in the left-right direction on the paper surface.
- the c-axis 13X can be at an arbitrary angle with respect to the paper surface.
- FIG. 2A is a cross-sectional view of a stacked body 10A according to one embodiment of the present invention.
- the stacked body 10A includes an insulator 11, a conductor 15, an oxide 13 between the insulator 11 and the conductor 15, and an oxide sandwiching the insulator 11. 13 and an oxide 17 opposite to each other.
- the stacked body 10 ⁇ / b> A differs from the stacked body 10 in that it includes an oxide 17.
- the oxide 17 is preferably a metal oxide. Since the description of the oxide 13 can be referred to for the metal oxide to be the oxide 17, detailed description thereof is omitted.
- the oxide 17 preferably has crystallinity. In particular, as the oxide 17, a CAAC-OS is preferably used.
- the oxide 17 has crystallinity, and includes a crystal layer 17P extending in the ab plane direction and a c-axis 17X perpendicular to the ab plane direction.
- the oxide 17 has a region including a c-axis 17X that is substantially perpendicular to the surface of the oxide 17 on the insulator 11 side. It can also be said that the oxide 17 has a region including the c-axis 17X that is approximately parallel to the normal line of the surface of the oxide 17 on the insulator 11 side.
- the film thickness of the oxide 17 is, for example, 2 nm or more, preferably 3 nm or more, more preferably 5 nm or more.
- a region can be formed in which the c-axis 17 ⁇ / b> X is oriented so as to be substantially perpendicular to the surface of the oxide 17 on the insulator 11 side.
- the c-axis 17 ⁇ / b> X includes a region oriented so as to be substantially perpendicular to the surface of the oxide 17 on the insulator 11 side, thereby including oxygen provided under the oxide 17. Oxygen can be prevented from diffusing from the insulator into the conductor 15. Thereby, it can suppress that the conductor 15 is oxidized, and can suppress that the resistance of the conductor 15 becomes high.
- Oxygen may be desorbed from an oxygen-containing insulator provided under the oxide 17.
- the oxide 13 includes a region in which the c-axis 13X is oriented so as to be substantially perpendicular to the surface of the oxide 13 on the insulator 11 side.
- Oxygen diffused into the oxide 17 from the insulator containing oxygen provided under the oxide 17 is likely to diffuse in the ab plane direction in the oxide 17 (diffusion path Route 4 shown in FIG. 2A).
- oxygen diffused in the oxide 17 is difficult to diffuse in the c-axis direction in the oxide 17.
- oxygen can be prevented from diffusing from the insulator containing oxygen provided under the oxide 17 into the conductor 15 (a diffusion path Route shown in FIG. 2A). 3). Thereby, it can suppress that the conductor 15 is oxidized, and can suppress that the resistance of the conductor 15 becomes high.
- FIG. 2A illustrates an example in which the c-axis 13X and the c-axis 17X are in the vertical direction on the paper surface
- one embodiment of the present invention is not limited thereto.
- the c-axis 13X and the c-axis 17X may be in the left-right direction on the paper surface.
- the c-axis 17X can be at an arbitrary angle with respect to the paper surface. Further, the c-axis 13X and the c-axis 17X may be in different directions.
- a stacked body with favorable electrical characteristics can be obtained.
- a highly reliable stacked body can be obtained.
- FIG. 3A and FIG. 3B are schematic views of region divisions in single crystal InGaZnO 4 (c-InGaZnO 4 ) in which the oxygen atom migration path is examined.
- FIG. 3B is a schematic diagram in which the schematic diagram of FIG. 3A is rotated 90 degrees about the c-axis as a rotation axis.
- the evaluation of the activation barrier uses the first principle electronic state calculation package VASP (Vienna ab initio simulation package), and the NEB (Nudged Elastic Band) method, which is a chemical reaction transfer route search method, is used for the atomic relaxation calculation.
- VASP Vehicle Ab initio simulation package
- NEB Nudged Elastic Band
- the NEB method is a technique for finding a state where the required energy is the lowest among the states connecting the two states from the initial state and the final state.
- Table 1 shows the calculation results of activation barriers for each movement route.
- the movement path A has a large activation barrier, so that oxygen hardly moves in the c-axis direction, and oxygen easily moves in a direction parallel to the layer. That is, the CAAC-OS has a property that oxygen is less likely to diffuse in the c-axis direction than in the ab plane direction. Therefore, the oxide 13 has a region in which the c-axis 13X is oriented so as to be substantially perpendicular to the surface of the oxide 13 on the insulator 11 side, so that the insulator 11 or the insulator 11 is located below. Oxygen can be prevented from diffusing from the provided insulator containing oxygen into the conductor 15 (diffusion path Route 1 shown in FIG.
- a substrate is prepared, and an oxide 17 is formed on the substrate.
- the oxide 17 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that when the stacked body 10 is manufactured, the oxide 17 is not formed.
- the oxide 17 is formed by a sputtering method
- oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
- excess oxygen in the oxide film can be increased.
- the oxide is formed by a sputtering method
- the above In-M-Zn oxide target or the like can be used.
- a direct current (DC) power source or an alternating current (AC) power source such as a radio frequency (RF) power source is connected to the target, and necessary power can be applied according to the electric conductivity of the target.
- DC direct current
- AC alternating current
- RF radio frequency
- the crystallinity of the oxide 17 can be improved by performing film formation while heating the substrate.
- the temperature of the substrate is preferably from room temperature to 250 ° C., more preferably from room temperature to 200 ° C., and further preferably from room temperature to 150 ° C. Note that one embodiment of the present invention is not limited to this.
- the oxide 17 is formed by a sputtering method, when the film is formed so that the proportion of oxygen contained in the sputtering gas exceeds 30% and is 100% or less, preferably 70% or more and 100% or less, the crystallinity of the oxide 17 is increased. Can be improved.
- a target can be formed. Note that the film formation conditions and the atomic ratio may be selected as appropriate in accordance with characteristics required for the oxide 17.
- heat treatment is preferably performed before the insulator 11 is formed.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Or it is preferable to carry out at the same temperature as the film formation temperature of the insulator 11.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably 350 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- the insulator 11 is formed.
- the insulator 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a stacked film of silicon oxide and gallium oxide over silicon oxide may be used as the insulator 11.
- the film formation temperature at the time of forming the insulator 11 is preferably 300 ° C. or higher and lower than 450 ° C., preferably 300 ° C. or higher and lower than 400 ° C., particularly around 350 ° C.
- an insulator with few impurities can be formed.
- an oxide 13 is formed. Regarding the formation of the oxide 13, the description of the oxide 17 can be referred to, and thus detailed description thereof is omitted.
- the oxide 13 may be formed using a target similar to the target used for forming the oxide 17.
- the oxide 13 is preferably formed while heating the substrate. At this time, oxygen vacancies in the oxide 13 and the oxide 17 can be reduced by setting the substrate temperature to 300 ° C. or higher. By forming the film while heating the substrate, the crystallinity of the oxide 13 and the oxide 17 can be improved.
- the proportion of oxygen contained in the sputtering gas of the oxide 13 may be 70% or more, preferably 80% or more, more preferably 100%. Further, by performing film formation while heating the substrate, the crystallinity of the oxide can be improved.
- the conductor 15 is formed.
- the conductor 15 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
- ALD method a thermal ALD method, a plasma ALD method, a PEALD method, or the like can be used.
- the conductor 15 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum It is preferable to use a metal element selected from the above, an alloy including the above-described metal element as a component, an alloy combining the above-described metal elements, or the like.
- tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. It is preferable. Also, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are not easily oxidized.
- a conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.
- a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
- a plurality of conductive layers formed of the above materials may be stacked.
- a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined.
- a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
- a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
- a stacked body with favorable electrical characteristics can be provided.
- a stacked body with favorable reliability can be provided.
- a novel semiconductor device using the stacked body of one embodiment of the present invention can be provided.
- 4A, 4B, and 4C are a top view and a cross-sectional view of the transistor 200 and the periphery of the transistor 200 according to one embodiment of the present invention.
- FIG. 4A is a top view of the semiconductor device including the transistor 200.
- FIG. 4B and 4C are cross-sectional views of the semiconductor device.
- FIG. 4B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 4A and also a cross-sectional view in the channel length direction of the transistor 200.
- FIG. 4C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 4A and is a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 4A, some elements are omitted for clarity.
- the transistor 200 includes an oxide 230a disposed on a substrate (not shown), an oxide 230b disposed on the oxide 230a, and an upper surface of the oxide 230b.
- An oxide 230c disposed in the opening, an insulator 250 on the oxide 230c, an oxide 230d on the insulator 250, and a conductor 260 on the oxide 230d.
- the top surface of the conductor 260 is preferably substantially coincident with the top surfaces of the insulator 250, the oxide 230c, the oxide 230d, and the insulator 280. .
- the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may be collectively referred to as the oxide 230.
- the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242.
- the insulator 254 and the insulator 244 are preferably provided between the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 280.
- the insulator 254 includes an upper surface and a side surface of the conductor 242a, an upper surface and a side surface of the conductor 242b, a side surface of the oxide 230a and the oxide 230b, In addition, it is preferable to be in contact with the upper surface of the insulator 224.
- the transistor 200 a structure in which a layer where a channel is formed (hereinafter also referred to as a channel formation region) and three layers of an oxide 230a, an oxide 230b, and an oxide 230c are stacked is shown.
- the present invention is not limited to this.
- a structure in which a two-layer structure of the oxide 230b and the oxide 230c or a stacked structure of four or more layers may be provided may be employed.
- each of the oxide 230a, the oxide 230b, and the oxide 230c may have a stacked structure of two or more layers.
- the conductor 260 is illustrated as a two-layer structure, but the present invention is not limited to this.
- the conductor 260 may have a single layer structure or a stacked structure of three or more layers.
- the oxide 230c when the oxide 230c has a stacked structure including a first oxide and a second oxide over the first oxide, the first oxide has a composition similar to that of the oxide 230b.
- the second oxide preferably has a composition similar to that of the oxide 230a.
- the oxide 230d preferably has a composition similar to that of the second oxide.
- the oxide 230d may have a stacked structure of two or more layers.
- the conductor 260 functions as a gate electrode of the transistor, and the conductor 242a and the conductor 242b function as a source electrode or a drain electrode, respectively.
- the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and the region sandwiched between the conductors 242a and 242b.
- the arrangement of the conductor 260, the conductor 242a, and the conductor 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 200, the gate electrode can be disposed in a self-aligned manner between the source electrode and the drain electrode. Accordingly, the conductor 260 can be formed without providing a margin for alignment, so that the area occupied by the transistor 200 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.
- the insulator 250 functions as a gate insulator of the transistor.
- the oxide 230d may also function as a gate insulating layer of the transistor.
- the oxide 230d is not a semiconductor but an insulator or a property close thereto, and thus can function as a gate insulating layer.
- the oxide 230d is a conductor or has properties close to that of the oxide 230d, and thus can function as a gate electrode.
- the conductor 260 includes a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a. preferable.
- the conductor 260 corresponds to the conductor 10 of the stacked body 10 and the stacked body 10A described in the previous embodiment.
- the oxide 230d corresponds to the stacked body 10 and the oxide 13 of the stacked body 10A described in the above embodiment.
- the insulator 250 corresponds to the insulator 10 of the stacked body 10 and the stacked body 10A described in the previous embodiment.
- the oxide 230c corresponds to the oxide 17 of the stacked body 10A described in the above embodiment.
- FIG. 6 shows an enlarged view of the oxide 230 and its vicinity in FIG.
- a crystal layer extending in the ab plane direction is indicated by a broken line.
- the oxygen included in the insulator 280 diffuses in the oxide 230c, and then diffuses in the ab plane direction of the oxide 230c.
- the oxygen diffused in the ab plane direction of the oxide 230c reaches the oxide 230b, it is combined with oxygen vacancies in the oxide 230b to reduce oxygen vacancies (Route shown in FIGS. 5 and 6).
- the oxygen bonded to the oxygen vacancy in the oxide 230b moves to another oxygen vacancy and is bonded to the oxygen vacancy.
- the oxygen vacancies generated by the movement of oxygen are combined with oxygen diffused from the insulator 280 to the oxide 230b through the oxide 230c.
- oxygen contained in the insulator 280 passes through the oxide 230c and is successively diffused into the oxide 230b, and is combined with oxygen vacancies in the oxide 230b. Accordingly, oxygen vacancies in the oxide 230b can be reduced, and the transistor can be prevented from being normally on.
- the insulator 280 in contact with the oxide 230c may be an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 280.
- an insulator containing excess oxygen in contact with the oxide 230c oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.
- the insulator 280 containing oxygen in excess of the stoichiometric composition can be referred to as an OST (Oxygen Storage Tank or Oxygen Stock Tank).
- Oxygen included in the insulator 250 diffuses in the ab plane direction of the oxide 230d after diffusing into the oxide 230d.
- the oxygen diffuses into the oxide 230b through the insulator 250 and the oxide 230c (Route C shown in FIGS. 5 and 6). Accordingly, oxygen vacancies in the oxide 230b can be reduced, and the transistor can be prevented from being normally on.
- oxygen included in the insulator 250 is difficult to diffuse in the c-axis 230cX direction of the oxide 230c and the c-axis 230dX direction of the oxide 230d, oxygen can be prevented from diffusing into the conductor 260 (see FIG. 5 and FIG. 5). Route D shown in FIG.
- the conductor 260 can be prevented from being oxidized, and the deterioration of the electrical characteristics of the transistor can be suppressed.
- the electrical characteristics of the transistor can be stabilized and the reliability can be improved.
- oxygen included in the insulator 250 may diffuse into the oxide 230b through the oxide 230c after diffusing through the insulator 250.
- FIG. 7 shows an enlarged view of the oxide 230 and its vicinity when the oxide 230c has a stacked structure including the first oxide 230c1 and the second oxide 230c2 on the first oxide.
- FIG. 7 is an enlarged view of the oxide 230 in FIG. 4B and the vicinity thereof.
- a crystal layer extending in the ab plane direction is indicated by a broken line.
- the first oxide 230c1 and the second oxide 230c2 preferably have a c-axis aligned crystal region.
- the c-axis 230c1X of the first oxide 230c1 and the c-axis 230c2X of the second oxide 230c2 are illustrated.
- the c-axis 230c1X and the c-axis 230c2X are preferably substantially perpendicular to the interface between the oxide 230c and the insulator 250, respectively.
- FIG. 8 is an enlarged view of the oxide 230 in FIG. 4C and the vicinity thereof.
- a crystal layer extending in the ab plane direction is indicated by a broken line.
- the c-axis 230aX included in the oxide 230a is substantially perpendicular to the interface between the insulator 224, which is a formation surface of the oxide 230a, and the oxide 230a.
- the oxide 230a has a plurality of c-axes 230aX, and the c-axes 230aX are substantially parallel to each other.
- the c-axis 230bX included in the oxide 230b is substantially perpendicular to the interface between the oxide 230a and the oxide 230b, which is a formation surface of the oxide 230b.
- the oxide 230b has a plurality of c-axes 230bX, and each c-axis 230bX is substantially parallel to each other.
- the c-axis 230cX of the oxide 230c is substantially perpendicular to the interface between the oxide 230b, which is a surface on which the oxide 230c is formed, and the oxide 230c.
- c-axis 230cX1 to c-axis 230cX5 are shown as examples of the c-axis 230cX.
- the c-axis 230cX1 to c-axis 230cX5 are each substantially perpendicular to the nearest oxide 230b and oxide 230c interface.
- the oxide 230c includes a region including the c-axis 230aX and the c-axis 230cX that is not parallel to the c-axis 230bX.
- the oxide 230c has a region including the c-axis 230cX in a direction different from the c-axis 230aX and the c-axis 230bX.
- oxygen desorbed in the oxide 230a or the oxide 230b diffuses in the ab plane direction of the oxide 230a or the oxide 230b and diffuses out of the oxide 230a or the oxide 230b.
- the c-axis 230cX1 and the c-axis 230cX5 of the oxide 230c are substantially parallel to the c-axis 230aX and the c-axis 230bX, whereas the c-axis 230cX2 to the c-axis 230cX4 of the oxide 230c are c
- shaft 230aX and the c-axis 230bX is shown.
- the oxide 230c preferably has a c-axis 230cX whose angle formed with the c-axis 230bX is greater than 30 ° and equal to or less than 90 °.
- the oxide 230c has a c-axis 230cX having an angle of 40 ° or more and 90 ° or less with the c-axis 230bX. It is more preferable that the oxide 230c has a c-axis 230cX whose angle with the c-axis 230bX is 45 ° or more and 90 ° or less.
- the straight line E and the straight line F being not parallel means the state where the angle
- the directions of the straight line E and the straight line F being different indicate that the straight line E and the straight line F are not parallel.
- the c-axis 230dX included in the oxide 230d is substantially perpendicular to the interface between the insulator 250d and the oxide 230d, which is a surface on which the oxide 230d is formed.
- c-axis 230dX1 to c-axis 230dX5 are shown as examples of the c-axis 230dX.
- the c-axis 230dX1 to c-axis 230dX5 are each substantially perpendicular to the interface between the nearest insulator 250 and the oxide 230c.
- the oxide 230d includes a region including the c-axis 230aX and the c-axis 230dX that is not parallel to the c-axis 230bX.
- the oxide 230d has a region including the c-axis 230dX in a direction different from the c-axis 230aX and the c-axis 230bX.
- oxygen desorbed in the oxide 230a or the oxide 230b diffuses in the ab plane direction of the oxide 230a or the oxide 230b and diffuses out of the oxide 230a or the oxide 230b.
- the c-axis 230dX1 and the c-axis 230dX5 of the oxide 230d are substantially parallel to the c-axis 230aX and the c-axis 230bX, whereas the c-axis 230dX2 to the c-axis 230dX4 of the oxide 230d are c
- shaft 230aX and the c-axis 230bX is shown.
- the oxide 230d preferably has a c-axis 230dX that has an angle formed with the c-axis 230bX of greater than 30 ° and equal to or less than 90 °.
- the oxide 230d has a c-axis 230dX having an angle of 40 ° or more and 90 ° or less with the c-axis 230bX. More preferably, the oxide 230d has a c-axis 230dX having an angle of 45 ° or more and 90 ° or less with respect to the c-axis 230bX.
- the transistor 200 includes an insulator 214 disposed over a substrate (not shown), an insulator 216 disposed over the insulator 214, and a conductor 205 disposed so as to be embedded in the insulator 216.
- the insulator 216 and the insulator 222 disposed on the conductor 205 and the insulator 224 disposed on the insulator 222 are preferably included. It is preferable that the oxide 230 a be disposed over the insulator 224.
- an insulator 274 that functions as an interlayer film and an insulator 281 are preferably provided over the transistor 200.
- the insulator 274 is preferably provided in contact with the top surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280.
- the insulator 222, the insulator 254, and the insulator 274 preferably have a function of suppressing diffusion of hydrogen (eg, hydrogen atoms and hydrogen molecules).
- the insulator 222, the insulator 254, and the insulator 274 preferably have lower hydrogen permeability than the insulator 224, the insulator 250, and the insulator 280.
- the insulator 222 and the insulator 254 preferably have a function of suppressing diffusion of oxygen (eg, oxygen atoms and oxygen molecules).
- the insulator 222 and the insulator 254 preferably have lower oxygen permeability than the insulator 224, the insulator 250, and the insulator 280.
- the insulator 224, the oxide 230a, the oxide 230b, and the insulator 250 are separated from the insulator 280 and the insulator 281 by the insulator 254, the oxide 230c, and the insulator 274.
- impurities such as hydrogen contained in the insulator 280 and the insulator 281 and excess oxygen can be prevented from entering the insulator 224, the oxide 230a, the oxide 230b, and the insulator 250.
- a conductor 240 (a conductor 240a and a conductor 240b) that is electrically connected to the transistor 200 and functions as a plug is provided.
- an insulator 241 (the insulator 241a and the insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug. That is, the insulator 241 is provided in contact with the inner walls of the openings of the insulator 254, the insulator 280, the insulator 274, and the insulator 281.
- the first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and the second conductor of the conductor 240 may be further provided inside.
- the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be approximately the same.
- the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this.
- the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.
- a metal oxide that functions as an oxide semiconductor is preferably used for the oxides 230a, 230b, and 230c including a channel formation region.
- an oxide semiconductor a metal oxide that functions as an oxide semiconductor
- a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used as the metal oxide serving as the channel formation region of the oxide 230. In this manner, by using a metal oxide having a large band gap, leakage current (off-state current) in a non-conducting state of a transistor can be extremely reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.
- the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium) It is preferable to use a metal oxide such as neodymium, hafnium, tantalum, tungsten, or magnesium.
- the element M may be aluminum, gallium, yttrium, or tin.
- indium oxide, zinc oxide, In—Ga oxide, In—Zn oxide, Ga—Zn oxide, or gallium oxide may be used as the oxide 230.
- the thickness of a region that does not overlap with the conductor 242 may be smaller than the thickness of a region that overlaps with the conductor 242. This is formed by removing a part of the upper surface of the oxide 230b when forming the conductor 242a and the conductor 242b.
- a region with low resistance may be formed in the vicinity of the interface with the conductive film. In this manner, by removing the low resistance region located between the conductors 242a and 242b on the top surface of the oxide 230b, formation of a channel in the region can be prevented.
- a semiconductor device including a transistor with high on-state current can be provided.
- a semiconductor device including a transistor having high frequency characteristics can be provided.
- a semiconductor device including a transistor with low off-state current can be provided.
- the conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260.
- the conductor 205 is preferably provided so as to be embedded in the insulator 216.
- the flatness of the upper surface of the conductor 205 is preferably improved.
- the average surface roughness (Ra) of the upper surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, the flatness of the insulator 224 formed over the conductor 205 can be improved, and the crystallinity of the oxide 230a, the oxide 230b, and the oxide 230c can be improved.
- the conductor 260 may function as a first gate (also referred to as a top gate) electrode.
- the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode.
- Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being interlocked.
- Vth of the transistor 200 can be made higher than 0 V and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when a negative potential is not applied.
- the conductor 205 is preferably provided larger than the channel formation region in the oxide 230.
- the conductor 205 is preferably extended also in a region outside the end portion intersecting with the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with an insulator outside the side surface in the channel width direction of the oxide 230.
- the channel formation region of the oxide 230 is electrically isolated by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. Can be surrounded.
- the conductor 205 is extended to function as wiring.
- the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 205.
- One conductor 205 is not necessarily provided for each transistor.
- the conductor 205 may be shared by a plurality of transistors.
- the conductor 205 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that although the conductor 205 has an example of a stacked structure including three layers of the conductor 205a, the conductor 205b, and the conductor 205c, this embodiment is not limited thereto.
- the conductor 205 may be a single layer or may have a stacked structure of two layers or four or more layers.
- the conductor 205a and the conductor 205b include a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, and a nitrogen oxide molecule (N 2 O, NO, NO 2 ), and has a function of suppressing diffusion of at least one of impurities such as copper atoms and oxygen (for example, oxygen atoms and oxygen molecules) (at least one of the impurities and oxygen is not easily transmitted).
- a conductive material selected from titanium, titanium nitride, tantalum, and tantalum nitride can be used.
- a conductive material containing tungsten, copper, or aluminum as a main component can be used.
- the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.
- the conductor having a function of suppressing oxygen diffusion By using a conductor having a function of suppressing oxygen diffusion as the conductor 205a or the conductor 205b, it is possible to prevent the conductivity of the conductor 205c from being reduced.
- the conductor having a function of suppressing oxygen diffusion for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, the conductive material may be a single layer or a stacked layer as the conductor 205a or the conductor 205b.
- the insulator 214 preferably functions as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, the insulator 214 has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, and the like) and copper atoms. It is preferable to use an insulating material (which is difficult for the impurities to pass through). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).
- oxygen for example, at least one of oxygen atoms and oxygen molecules
- the insulator 214 it is preferable to use aluminum oxide or silicon nitride as the insulator 214.
- impurities such as water or hydrogen from the substrate side to the transistor 200 side with respect to the insulator 214 can be suppressed.
- diffusion of oxygen contained in the insulator 224 and the like to the substrate side with respect to the insulator 214 can be suppressed.
- the insulator 216, the insulator 280, and the insulator 281 that function as an interlayer film preferably have a lower dielectric constant than that of the insulator 214.
- parasitic capacitance generated between the wirings can be reduced.
- silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and nitrogen were added. Silicon oxide, silicon oxide having holes, or the like may be used as appropriate.
- the insulator 216 may have a laminated structure.
- an insulator similar to the insulator 214 may be provided at least in a portion in contact with the side surface of the conductor 205.
- the conductor 205 can be prevented from being oxidized by oxygen contained in the insulator 216.
- the conductor 205 can suppress absorption of oxygen contained in the insulator 216.
- the insulator 222 and the insulator 224 have a function as a gate insulator.
- the insulator 224 in contact with the oxide 230 desorbs oxygen by heating.
- oxygen released by heating may be referred to as excess oxygen.
- the insulator 224 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate.
- an oxide material from which part of oxygen is released by heating is preferably used as the insulator 224.
- the oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
- the oxide film is 0.0 ⁇ 10 19 atoms / cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms / cm 3 or more, or 3.0 ⁇ 10 20 atoms / cm 3 or more.
- the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C.
- the insulator 224 preferably has a smaller thickness in a region that does not overlap with the oxide 230b than in other regions.
- the lower end portion of the conductor 260 can be positioned on the lower side, so that the electric field of the conductor 260 functioning as the first gate electrode is applied to the side surface of the oxide 230. It becomes easy.
- the insulator 224 may be provided in an island shape so as to overlap with the oxide 230b and the oxide 230a.
- the insulator 222 preferably functions as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side, like the insulator 214.
- the insulator 222 preferably has lower hydrogen permeability than the insulator 224.
- the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is difficult to permeate).
- the insulator 222 preferably has lower oxygen permeability than the insulator 224.
- the insulator 222 has a function of suppressing diffusion of oxygen and impurities, which is preferable because oxygen included in the oxide 230 can be prevented from diffusing to the substrate side.
- the conductor 205 can be prevented from reacting with the oxygen included in the insulator 224 and the oxide 230.
- an insulator containing one or both oxides of aluminum and hafnium which are insulating materials may be used.
- the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Acts as a layer.
- aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
- these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
- the insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST).
- An insulator including a so-called high-k material may be used as a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.
- the insulator 222 it is particularly preferable to use hafnium oxide among the materials described above.
- the interface state density may be reduced by using hafnium oxide for the insulator 222 as compared with the case of using aluminum oxide.
- the insulator 222 and the insulator 224 may have a stacked structure of two or more layers.
- the present invention is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.
- an insulator similar to the insulator 224 may be provided below the insulator 222.
- the transistor 200 includes an oxide 230a, an oxide 230b on the oxide 230a, an oxide 230c on the oxide 230b, and an oxide 230d on the oxide 230c.
- the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed.
- the oxide 230c over the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.
- the oxide 230 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 230b. It is preferable. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used. As the oxide 230d, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
- the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d preferably have crystallinity, and in particular, a CAAC-OS is preferably used.
- An oxide having crystallinity such as a CAAC-OS has a dense structure with few impurities and defects (such as oxygen vacancies) and high crystallinity. With such an oxide 230, the transistor 200 becomes stable against a high temperature (so-called thermal budget) in the manufacturing process.
- the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is higher than the energy at the lower end of the conduction band of the oxide 230b.
- the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity of the oxide 230b.
- the oxide 230c is preferably a metal oxide that can be used for the oxide 230a.
- the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 230b. It is preferable.
- the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
- the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230c.
- the energy level at the lower end of the conduction band changes gently.
- the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously joined.
- the defect state density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c is preferably low.
- the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states is formed. can do.
- the oxide 230b is an In—Ga—Zn oxide
- an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 230a and the oxide 230c.
- the oxide 230c may have a stacked structure.
- a stacked structure of gallium oxide can be used.
- a stacked structure of an In—Ga—Zn oxide and an oxide containing no In may be used as the oxide 230c.
- the main path of the carrier is the oxide 230b.
- the oxide 230a and the oxide 230c have the above structure, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 200 can obtain a high on-state current and a high frequency characteristic. Note that in the case where the oxide 230c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the oxide 230b and the oxide 230c, the constituent element of the oxide 230c is It is expected to suppress diffusion.
- the oxide 230c has a stacked structure and an oxide not containing In is positioned above the stacked structure, In that can be diffused to the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, when In is diffused, transistor characteristics are deteriorated. Therefore, with the stacked structure of the oxide 230c, a highly reliable semiconductor device can be provided.
- Ga: Zn 1: 3: 4 [atomic ratio]
- Ga: Zn 4: 2: 3 [atomic ratio]
- Ga: Zn 2: 1 [atomic ratio]
- a conductor 242 (conductor 242a and conductor 242b) functioning as a source electrode and a drain electrode is provided over the oxide 230b.
- the conductor 242 include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above metal element as a component, or an alloy combining the above metal elements.
- tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. It is preferable. Also, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. A conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.
- the oxygen concentration may be reduced in the vicinity of the conductor 242 of the oxide 230.
- a metal compound layer including a metal contained in the conductor 242 and a component of the oxide 230 may be formed in the vicinity of the conductor 242 of the oxide 230. In such a case, the carrier density increases in a region near the conductor 242 of the oxide 230, and the region becomes a low-resistance region.
- the region between the conductors 242a and 242b is formed so as to overlap with the opening of the insulator 280. Accordingly, the conductor 260 can be disposed in a self-aligned manner between the conductor 242a and the conductor 242b.
- the insulator 250 functions as a gate insulator.
- the insulator 250 is preferably provided in contact with the upper surface of the oxide 230c.
- silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole is used. be able to.
- silicon oxide and silicon oxynitride are preferable because they are stable against heat.
- the concentration of impurities such as water or hydrogen in the insulator 250 is reduced.
- the thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
- a metal oxide may be provided between the insulator 250 and the conductor 260.
- the metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. Thus, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.
- the metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a metal oxide that is a high-k material with a high relative dielectric constant.
- the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure having high relative dielectric constant and stability against heat can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulator.
- EOT equivalent oxide thickness
- a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. it can.
- the conductor 260 is shown as a two-layer structure in FIG. 4, but may have a single-layer structure or a laminated structure of three or more layers.
- the conductor 260a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, etc.) and copper atoms. It is preferable to use a conductor having the same. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).
- the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductivity of the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered.
- tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material having a function of suppressing oxygen diffusion.
- the conductor 260b be made of a conductive material mainly containing tungsten, copper, or aluminum.
- a conductor having high conductivity is preferably used.
- a conductive material containing tungsten, copper, or aluminum as a main component can be used.
- the conductor 260b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the conductive material.
- a metal oxide that can be used as the oxide 230 may be provided between the insulator 250 and the conductor 260a. At this time, the metal oxide functions as a gate electrode similarly to the conductor 260.
- oxygen can be supplied to at least one of the insulator 250 and the oxide 230, which is preferable.
- the conductor 260 is prevented from being oxidized by oxygen contained in the insulator 250 or the insulator 280. Can do.
- oxygen contained in the insulator 250 can be suppressed from being absorbed by the conductor 260.
- a side surface of the oxide 230 is a conductor in a region where the conductor 2302 of the oxide 230b does not overlap, in other words, in a channel formation region of the oxide 230. It is arranged so as to be covered with 260. Accordingly, the electric field of the conductor 260 functioning as the first gate electrode is easily applied to the side surface of the oxide 230. Thus, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.
- the insulator 254 preferably functions as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor 200 from the insulator 280 side, like the insulator 214 and the like.
- the insulator 254 preferably has lower hydrogen permeability than the insulator 224.
- the insulator 254 includes a part of a side surface of the oxide 230c, an upper surface and a side surface of the conductor 242a, and an upper surface and a side surface of the conductor 242b.
- the oxide 230b be in contact with part of the top surface, part of the side surface, the side surface of the oxide 230a, and the top surface of the insulator 224.
- hydrogen contained in the insulator 280 can be prevented from entering the oxide 230 from the top surfaces or side surfaces of the oxide 230a, the oxide 230b, and the insulator 224.
- the insulator 254 preferably has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).
- the insulator 254 preferably has lower oxygen permeability than the insulator 280 or the insulator 224.
- the insulator 254 is preferably formed using a sputtering method.
- oxygen can be added in the vicinity of the region of the insulator 224 that is in contact with the insulator 254. Accordingly, oxygen can be supplied from the region into the oxide 230 through the insulator 224.
- the insulator 254 has a function of suppressing diffusion of oxygen upward, whereby oxygen can be prevented from diffusing from the oxide 230 to the insulator 280.
- the insulator 222 has a function of suppressing diffusion of oxygen downward, whereby oxygen can be prevented from diffusing from the oxide 230 to the substrate side. In this manner, oxygen is supplied to the channel formation region of the oxide 230. Accordingly, oxygen vacancies in the oxide 230 can be reduced, and the transistor can be prevented from being normally on.
- an insulator containing one or both of aluminum and hafnium may be formed.
- the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- the insulator 254 may have a stacked structure.
- the second insulator may be formed using the ALD method over the first insulator formed using the sputtering method.
- the first insulator and the second insulator may be made of the same material selected from the materials described above, or may be made of different materials.
- aluminum oxide formed by a sputtering method may be used as the first insulator
- aluminum oxide formed by an ALD method may be used as the second insulator.
- a film formed by the ALD method has high coverage, and a film having high uniformity can be formed even on a step portion formed of a structure such as the oxide 230.
- the insulator 280 is separated from the insulator 224 and the oxide 230 by covering the insulator 224 and the oxide 230 with the insulator 254 having a barrier property against hydrogen. Accordingly, intrusion of impurities such as hydrogen from the outside of the transistor 200 can be suppressed, so that favorable electrical characteristics and reliability can be given to the transistor 200.
- an insulator containing aluminum nitride may be used.
- a nitride insulator satisfying the composition formula of AlNx x is a real number greater than 0 and less than or equal to 2, preferably x is greater than 0.5 and less than or equal to 1.5
- the insulator 254 can be formed using aluminum titanium nitride, titanium nitride, or the like.
- the film by using a sputtering method because the film can be formed without using a highly oxidizing gas such as oxygen or ozone as the film forming gas.
- a highly oxidizing gas such as oxygen or ozone as the film forming gas.
- silicon nitride, silicon nitride oxide, or the like can be used.
- an insulator containing one or both of aluminum and hafnium may be formed.
- the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- the insulator 244 preferably functions as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor 200 from the insulator 280 side, like the insulator 214 and the like.
- the insulator 244 preferably has lower hydrogen permeability than the insulator 224.
- the insulator 244 is preferably disposed so as to be in contact with the insulator 254. With such a structure, hydrogen contained in the insulator 280 can be prevented from entering the oxide 230 from the side surfaces of the conductor 260, the oxide 230c, and the insulator 250.
- the insulator 280 can be formed using the insulator 254 and the insulator 244.
- the insulator 224, the oxide 230, and the insulator 250 are separated from the insulator 224, the oxide 230, and the insulator 250. Accordingly, intrusion of impurities such as hydrogen from the outside of the transistor 200 can be suppressed, so that favorable electrical characteristics and reliability can be given to the transistor 200.
- the insulator 244 preferably has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (the above-described oxygen hardly transmits).
- the insulator 244 preferably has lower oxygen permeability than the insulator 224.
- an insulator containing aluminum nitride may be used.
- a nitride insulator satisfying a composition formula of AlNx (x is a real number greater than 0 and equal to or less than 2, preferably x is greater than 0.5 and equal to or less than 1.5) is preferably used.
- a film having excellent insulating properties and excellent thermal conductivity can be obtained, so that heat dissipation of heat generated when the transistor 200 is driven can be improved.
- the insulator 244 can be formed using aluminum titanium nitride, titanium nitride, or the like.
- the film by using a sputtering method because the film can be formed without using a highly oxidizing gas such as oxygen or ozone as the film forming gas.
- a highly oxidizing gas such as oxygen or ozone as the film forming gas.
- silicon nitride, silicon nitride oxide, or the like can be used.
- an insulator containing one or both of aluminum and hafnium may be formed.
- the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- the insulator 244 is preferably formed using an ALD method. Since the ALD method is a film-forming method with good coverage, it is possible to prevent step breakage and the like from being formed due to the unevenness of the insulator 244.
- the insulator 280 is provided over the insulator 224 and the oxide 230 with the insulator 244 and the insulator 254 interposed therebetween.
- the insulator 280 silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having a hole, or the like is used. It is preferable to have.
- silicon oxide and silicon oxynitride are preferable because they are thermally stable.
- a material such as silicon oxide, silicon oxynitride, or silicon oxide having a hole is preferable because a region containing oxygen that is released by heating can be easily formed.
- the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Further, the upper surface of the insulator 280 may be planarized.
- the insulator 274 preferably functions as a barrier insulating film that suppresses entry of impurities such as water or hydrogen into the insulator 280 from above, like the insulator 214.
- an insulator that can be used for the insulator 214, the insulator 254, and the like may be used, for example.
- an insulator 281 that functions as an interlayer film is preferably provided over the insulator 274.
- the insulator 281 preferably has reduced concentration of impurities such as water or hydrogen in the film.
- the conductor 240a and the conductor 240b are disposed in openings formed in the insulator 281, the insulator 274, the insulator 280, the insulator 244, and the insulator 254.
- the conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 281.
- an insulator 241a is provided in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, the insulator 244, and the insulator 254, and a first conductor of the conductor 240a is in contact with the side surface thereof. Is formed.
- a conductor 242a is located at least at a part of the bottom of the opening, and the conductor 242a is in contact with the conductor 240a.
- the insulator 241b is provided in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, the insulator 244, and the insulator 254, and the first conductor of the conductor 240b is in contact with the side surface thereof.
- the body is formed.
- a conductor 242b is located at least at a part of the bottom of the opening, and the conductor 242b is in contact with the conductor 240b.
- the conductive material 240a and the conductive material 240b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
- the conductor 240a and the conductor 240b may have a stacked structure.
- the conductor in contact with the oxide 230a, the oxide 230b, the insulator 254, the insulator 280, the insulator 274, and the insulator 281 includes the above-described water or hydrogen. It is preferable to use a conductor having a function of suppressing diffusion of impurities.
- a conductor having a function of suppressing diffusion of impurities For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used.
- the conductive material having a function of suppressing diffusion of impurities such as water or hydrogen may be used in a single layer or a stacked layer.
- oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.
- impurities such as water or hydrogen from an upper layer than the insulator 281 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.
- an insulator that can be used for the insulator 214 or the like for example, aluminum oxide or silicon nitride may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254, impurities such as water or hydrogen from the insulator 280 and the like are prevented from entering the oxide 230 through the conductor 240a and the conductor 240b. be able to. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.
- an ALD method or a CVD method can be used for the formation of the insulator 241a and the insulator 241b.
- a conductor functioning as a wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b.
- a conductive material containing tungsten, copper, or aluminum as a main component is preferably used.
- the conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the conductive material.
- the conductor may be formed so as to be embedded in an opening provided in the insulator.
- the resistivity is 1.0 ⁇ 10 13 ⁇ cm or more and 1.0 ⁇ 10 15 ⁇ cm or less, preferably 5.0 ⁇ 10 13 ⁇ cm or more and 5.0 ⁇ 10 14 so as to cover the conductor. It is preferable to provide an insulator of ⁇ cm or less. By providing an insulator having the above-described resistivity on the conductor, the insulator disperses charges accumulated between the wiring of the transistor 200 and the conductor while maintaining insulation. It is preferable because it can suppress poor characteristics and electrostatic breakdown of the transistor due to the charge and an electronic device including the transistor.
- 9A, 9B, and 9C are a top view and a cross-sectional view of the transistor 200A and the periphery of the transistor 200A according to one embodiment of the present invention.
- FIG. 9A is a top view of a semiconductor device having a transistor 200A.
- 9B and 9C are cross-sectional views of the semiconductor device.
- FIG. 9B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 9A and also a cross-sectional view in the channel length direction of the transistor 200A.
- FIG. 9C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 9A and is a cross-sectional view in the channel width direction of the transistor 200A. Note that in the top view of FIG. 9A, some elements are omitted for clarity.
- the transistor 200A illustrated in FIGS. 9A, 9B, and 9C does not include the conductor 242a and the conductor 242b but includes the layer 253a and the layer 253b as described above. This is mainly different from the transistor 200 (see FIG. 4) shown in the device configuration example 1>. Note that the same components as those of the transistor 200 are denoted by the same reference numerals, and detailed description thereof may be omitted.
- the transistor 200A is separated from the oxide 230a disposed on a substrate (not shown), the oxide 230b disposed on the oxide 230a, and the oxide 230b.
- the insulator 280 which is disposed over the oxide 253b and overlaps between the layer 253a and the layer 253b, and the oxide disposed in the opening.
- the layer 253a and the layer 253b may be collectively referred to as a layer 253.
- the insulator 254 is preferably disposed between the insulator 224, the oxide 230a, the oxide 230b, and the insulator 280.
- the insulator 254 includes an upper surface and a side surface of the layer 253a, an upper surface and a side surface of the layer 253b, a side surface of the oxide 230a and the oxide 230b, and an insulating material. It is preferable to contact the upper surface of the body 224.
- the conductor 260 functions as a gate electrode of the transistor, and the layers 253a and 253b function as a source region or a drain region, respectively.
- the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and the insulator 254 and the region sandwiched between the layers 253a and 253b.
- the arrangement of the conductor 260, the layers 253a, and 253b is selected in a self-aligned manner with respect to the openings of the insulator 280 and the insulator 254. That is, in the transistor 200A, the gate electrode can be disposed in a self-aligned manner between the source region and the drain region. Therefore, since the conductor 260 can be formed without providing an alignment margin, the area occupied by the transistor 200A can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.
- FIG. 10 shows an enlarged view of the oxide 230 in FIG. 9B and the vicinity thereof.
- An enlarged view of the oxide 230 in FIG. 9C and the vicinity thereof is shown in FIG.
- a crystal layer extending in the ab plane direction is indicated by a broken line.
- the description of the transistor 200 described above can be referred to for the route of oxygen diffused from the insulator 280 into the oxide 230b, and thus detailed description thereof is omitted.
- FIG. 12 shows an enlarged view of the oxide 230 and its vicinity when the oxide 230c has a stacked structure including the first oxide 230c1 and the second oxide 230c2 on the first oxide.
- FIG. 12 is an enlarged view of the oxide 230 in FIG. 9B and the vicinity thereof.
- a crystal layer extending in the ab plane direction is indicated by a broken line.
- the description of the transistor 200 can be referred to for the c-axis directions of the oxides 230a to 230d, and thus a detailed description thereof is omitted (see FIG. 8).
- the oxide 230 will be described.
- the oxide 230 may be added with an element that forms oxygen vacancies or an element that combines with oxygen vacancies, whereby the carrier density may increase and the resistance may be reduced.
- Typical examples of such an element include boron and phosphorus.
- hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, and the like can be used.
- rare gases include helium, neon, argon, krypton, and xenon.
- the oxide 230 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, and strontium. Any one or more metal elements selected from metal elements such as lanthanum may be added. Among the elements described above, boron and phosphorus are preferable as the added element. For the addition of boron and phosphorus, equipment of an amorphous silicon or low-temperature polysilicon production line can be used, so that capital investment can be suppressed. The concentration of the element may be measured by using secondary ion mass spectrometry (SIMS) or the like.
- SIMS secondary ion mass spectrometry
- the layer 253 is a layer formed by adding the above element to the oxide 230.
- the layers 253a and 253b are formed so as to face each other with the conductor 260 interposed therebetween, and the top surface thereof is preferably in contact with the insulator 254 and the oxide 230c.
- the side surfaces of the layers 253a and 253b on the conductor 260 side coincide with the side surfaces of the conductor 260, or a part of the layers 253a and 253b overlap with the conductor 260.
- the concentration of the element in the layer 253 is preferably equal to or higher than the concentration of the element in a portion where the layer 253 of the oxide 230 is not formed.
- the amount of oxygen vacancies included in the layer 253 is preferably equal to or higher than the amount of oxygen vacancies in the portion where the layer 253 of the oxide 230 is not formed.
- the layer 253 has a higher carrier density and lower resistance than a portion of the oxide 230 where the layer 253 is not formed.
- the oxide 230 includes a first region overlapping with the conductor 260, a pair of second regions not overlapping with either the conductor 260 or the insulator 254, and a pair of third regions overlapping with the insulating layer 254.
- the first region is located between the pair of second regions, and the first region and the pair of second regions are located between the pair of third regions.
- the third region (for example, the region 231b in FIG. 10) has a higher carrier density and a lower resistance than the first region (the region 234 in FIG. 10).
- the second region (for example, the region 232b in FIG. 10) has a higher carrier density and lower resistance than the first region, and has a carrier density higher than that of the third region.
- the second region may have a carrier density equivalent to that of the third region and may have equivalent resistance. Therefore, the first region functions as a channel formation region of the transistor 200A, the third region functions as a source region or a drain region, and the second region functions as a junction region.
- an offset region is prevented from being formed between the channel formation region of the oxide 230 and the source or drain region, and the effective channel length is larger than the width of the conductor 260. It can be suppressed. Accordingly, the on-state current of the transistor 200A can be increased, the S value can be improved, and the frequency characteristics can be improved.
- the conductor 240 functioning as a plug can be connected to the region 231 without providing a source electrode and a drain electrode formed of metal. it can.
- the source electrode and the drain electrode formed using a metal are provided in contact with the oxide 230, the source electrode and the drain electrode formed using the metal are oxidized when high-temperature heat treatment is performed in the manufacturing process or the later process of the transistor 200A.
- the on-current, S value, and frequency characteristics of the transistor 200A may be deteriorated.
- a semiconductor device that exhibits favorable on-state current, S value, and frequency characteristics can be provided even when high-temperature heat treatment is performed in a manufacturing process or a post-process of the transistor 200A.
- a process in which a high temperature of about 750 ° C. to 800 ° C. is applied can be performed.
- an element that forms an oxygen vacancy is added to the layer 253 and heat treatment is performed, so that hydrogen contained in the region 234 functioning as a channel formation region is captured by the oxygen vacancy contained in the layer 253.
- it is possible Accordingly, stable electrical characteristics can be given to the transistor 200A, and reliability can be improved.
- the region 232 may not function as a bonding region.
- the region 232 has a carrier density equivalent to that of the region 234, an equivalent resistance value, or an equivalent property.
- the region 232 functions as a so-called offset region.
- the channel length is reduced (for example, when the channel length is 60 nm or less or the channel length is 30 nm or less), the influence of the offset region may be negligible.
- the layer 253 is formed in the vicinity of the surfaces of the oxide 230b, the insulator 254, and the oxide 230c in the film thickness direction of the oxide 230b, but the present invention is not limited thereto.
- the layer 253 may have substantially the same thickness as the oxide 230b, or may be formed on the oxide 230a.
- the layer 253 is formed in the region 231 and the region 232, but is not limited thereto. For example, it may be formed only in the region 231, may be formed in the region 231 and a part of the region 232, or may be formed in the region 231, the region 232, and a part of the region 234. It may be formed.
- concentrations of metal elements detected in each region and impurity elements such as hydrogen and nitrogen are not limited to stepwise changes in each region, but also continuously change in each region (also referred to as gradation). May be. That is, the closer to the channel formation region, the lower the concentration of the metal element and impurity elements such as hydrogen and nitrogen.
- a semiconductor device including a transistor with high on-state current can be provided.
- a semiconductor device including a transistor having high frequency characteristics can be provided.
- a semiconductor device including a transistor with low off-state current can be provided.
- the region between the layer 253a and the layer 253b is formed so as to overlap with the opening of the insulator 280. Accordingly, the conductor 260 can be disposed in a self-aligned manner between the layers 253a and 253b.
- the side surface of the oxide 230 is disposed so as to be covered with the conductor 260. Accordingly, the electric field of the conductor 260 functioning as the first gate electrode is easily applied to the side surface of the oxide 230. Thus, the on-state current of the transistor 200A can be increased and the frequency characteristics can be improved.
- the insulator 254 functioning as a barrier insulating film includes a part of a side surface of the oxide 230c, a top surface and a side surface of the layer 253a, a top surface and a side surface of the layer 253b, that is, a part of the top surface of the oxide 230b and a part of the side surface.
- hydrogen contained in the insulator 280 can be prevented from entering the oxide 230 from the top surfaces or side surfaces of the oxide 230a, the oxide 230b, and the insulator 224.
- the insulator 254 may have a function as a protective film when the layers 253a and 253b are formed.
- the insulator 254 as a protective film, the surface of the oxide 230 is not directly exposed to ions or plasma, and the layer 253a And damage to the oxide 230 in forming the layer 253b can be suppressed, which is preferable.
- the damage to the oxide 230 refers to the formation of excessive oxygen vacancies in the oxide 230, excessive decrease in crystallinity of the oxide 230, or the like.
- silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or oxide having a void Silicon or the like can be used as the insulator 254.
- the insulator 280 is provided over the insulator 224 and the oxide 230 with the insulator 254 interposed therebetween.
- the conductor 240a and the conductor 240b are disposed in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254.
- the conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 281.
- an insulator 241a is provided in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of the conductor 240a is formed in contact with a side surface thereof.
- the layer 253a is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the layer 253a.
- the insulator 241b is provided in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and the first conductor of the conductor 240b is formed in contact with the side surface thereof.
- the layer 253b is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the layer 253b.
- 13A, 13B, and 13C are a top view and a cross-sectional view of the transistor 200B and the periphery of the transistor 200B according to one embodiment of the present invention.
- FIG. 13A is a top view of a semiconductor device having a transistor 200B.
- 13B and 13C are cross-sectional views of the semiconductor device.
- FIG. 13B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 13A and also a cross-sectional view in the channel length direction of the transistor 200B.
- FIG. 13C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 13A and also a cross-sectional view in the channel width direction of the transistor 200B.
- FIG. 13A some elements are omitted for clarity. Note that the same components as those of the transistor 200 and the transistor 200A described above are denoted by the same reference numerals, and detailed description thereof may be omitted.
- the transistor 200B includes an oxide 230a disposed over a substrate (a substrate is not shown) provided with an insulator 224, and an oxide 230b disposed over the oxide 230a.
- layers 253a and 253b formed separately from each other and the insulator 224 and the oxide 230b are formed over the top surface of the oxide 230b, and an opening is formed so as to overlap between the layers 253a and 253b.
- the insulator 254 may have a stacked structure of two or more layers.
- an insulator 254 is preferably disposed between the insulator 224, the oxide 230 a, the oxide 230 b, and the insulator 280.
- the insulator 254 includes an upper surface and a side surface of the layer 253a, an upper surface and a side surface of the layer 253b, a side surface of the oxide 230a and the oxide 230b, and an insulating material. It is preferable to contact the upper surface of the body 224.
- an insulator 270 is disposed between the conductor 260 and the insulator 280.
- the insulator 270 is in contact with the side surface of the conductor 260a, the upper surface and the side surface of the conductor 260b, and part of the upper surface of the oxide 230d. Is preferred.
- the conductor 260 functions as a gate electrode of the transistor, and the layer 253a and the layer 253b function as a source region or a drain region, respectively.
- the layers 253a and 253b are regions where the resistance is reduced by adding a dopant to at least part of the oxide 230b of the oxide 230a and the oxide 230b. Further, the layer 253a and the layer 253b are preferably overlapped with the insulator 254 in a top view.
- FIG. 14 shows an enlarged view of the oxide 230 and its vicinity in FIG.
- the description of the transistor 200 described above can be referred to for the route of oxygen diffused from the insulator 280 into the oxide 230b, and thus detailed description thereof is omitted.
- Route C and Route D are omitted.
- FIG. 15 shows an enlarged view of the oxide 230 and the vicinity thereof when the oxide 230c has a stacked structure including the first oxide 230c1 and the second oxide 230c2 on the first oxide.
- FIG. 15 is an enlarged view of the oxide 230 in FIG. 13B and the vicinity thereof.
- Route C and Route D are omitted.
- the description of the transistor 200 can be referred to for the c-axis directions of the oxides 230a to 230d, and thus a detailed description thereof is omitted (see FIG. 8).
- an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition is preferably used as the insulator 280 in contact with the oxide 230c. Furthermore, the insulator 280 is preferably in contact with the end surface of the oxide 230c. The insulator 280 is preferably in contact with the end surface of the oxide 230d. The insulator 280 is preferably in contact with the end surface of the insulator 250. With such a structure, oxygen can be efficiently supplied from the insulator 280 to the oxide 230, and oxygen vacancies can be reduced.
- an insulator 274 that functions as an interlayer film and an insulator 281 are preferably provided over the transistor 200B.
- the insulator 274 is preferably disposed in contact with the upper surface of the insulator 280.
- 16A, 16B, and 16C are a top view and a cross-sectional view of the transistor 200C according to one embodiment of the present invention and the periphery of the transistor 200C.
- FIG. 16A is a top view of the transistor 200C.
- FIG. 16B is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in FIG. 16A and also a cross-sectional view in the channel length direction of the transistor 200C.
- FIG. 16C is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in FIG. 16A, and is also a cross-sectional view in the channel width direction of the transistor 200C.
- some elements are omitted for clarity.
- a transistor 200C illustrated in FIGS. 16A, 16B, and 16C does not include the layer 253a and the layer 253b, and the conductor 242a which is disposed separately from each other over the oxide 230b.
- the transistor 200B is different from the transistor 200B illustrated in FIGS. Note that the same components as those of the transistor 200B are denoted by the same reference numerals, and detailed description thereof may be omitted.
- the transistor 200C is provided over the conductor 242a and the conductor 242b, and includes an insulator 254 in which an opening is formed so as to overlap between the conductor 242a and the conductor 242b, and an oxide 230c disposed in the opening.
- An insulator 250, an oxide 230d, and a conductor 260 are included.
- a substrate over which the transistor 200 is formed for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
- the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
- the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
- a semiconductor substrate having an insulator region inside the above-described semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
- the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
- a substrate in which a conductor or a semiconductor is provided on an insulator substrate a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
- a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
- Insulator examples include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
- the transistor when the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to thinning of the gate insulator.
- a high-k material for the insulator functioning as a gate insulator the voltage during transistor operation can be reduced while maintaining the physical film thickness.
- a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant for the insulator functioning as an interlayer film. Therefore, the material may be selected according to the function of the insulator.
- Insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium.
- an oxynitride having silicon, or a nitride having silicon and hafnium are examples of gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium.
- Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, For example, silicon oxide having a hole or resin may be used.
- a transistor including an oxide semiconductor is surrounded by an insulator (such as the insulator 214, the insulator 222, the insulator 254, and the insulator 274) having a function of suppressing transmission of impurities such as hydrogen and oxygen.
- an insulator such as the insulator 214, the insulator 222, the insulator 254, and the insulator 2704.
- the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
- An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.
- an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
- a metal oxide such as tantalum oxide, or a metal nitride such as aluminum nitride, aluminum nitride titanium, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
- the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating.
- the oxide 230 By using a structure in which silicon oxide or silicon oxynitride including a region containing oxygen which is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
- Conductor a material used for the conductor 15 described in the above embodiment can be used.
- the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred.
- a conductive material containing oxygen is preferably provided on the channel formation region side.
- a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode.
- the above-described conductive material containing a metal element and nitrogen may be used.
- a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
- Indium tin oxide may be used.
- indium gallium zinc oxide containing nitrogen may be used.
- a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
- an oxide semiconductor a metal oxide functioning as an oxide semiconductor
- the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.
- the oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one kind or plural kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.
- the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc is considered.
- the element M is aluminum, gallium, yttrium, tin, or the like.
- Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
- the element M may be a combination of a plurality of the aforementioned elements.
- metal oxides containing nitrogen may be collectively referred to as metal oxides.
- a metal oxide containing nitrogen may be referred to as a metal oxynitride.
- An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor.
- a non-single-crystal oxide semiconductor for example, a polycrystalline oxide semiconductor and an amorphous oxide semiconductor are known.
- a thin film with high crystallinity is preferably used as the oxide semiconductor used for the semiconductor of the transistor.
- the stability or reliability of the transistor can be improved.
- the thin film include a single crystal oxide semiconductor thin film and a polycrystalline oxide semiconductor thin film.
- a high temperature or laser heating step is required in order to form a single crystal oxide semiconductor thin film or a polycrystalline oxide semiconductor thin film on a substrate. Therefore, the cost of the manufacturing process increases and the throughput also decreases.
- Non-Patent Document 1 and Non-Patent Document 2 an In—Ga—Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009.
- CAAC-IGZO In—Ga—Zn oxide having a CAAC structure
- CAAC-IGZO can be formed on a substrate at a low temperature with c-axis orientation, crystal grain boundaries are not clearly confirmed.
- a transistor using CAAC-IGZO has excellent electrical characteristics and reliability.
- nc-IGZO In 2013, an In—Ga—Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and regularity is not observed in crystal orientation between different regions. Yes.
- Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size due to the electron beam irradiation on the thin films of CAAC-IGZO, nc-IGZO, and IGZO having low crystallinity.
- a CAAC-IGZO thin film or an nc-IGZO thin film is preferably used as a semiconductor of the transistor.
- a transistor including an oxide semiconductor has a very small leakage current in a non-conducting state. Specifically, an off-current per 1 ⁇ m channel width of the transistor is on the order of yA / ⁇ m (10 ⁇ 24 A / ⁇ m).
- yA / ⁇ m 10 ⁇ 24 A / ⁇ m.
- Non-Patent Document 8 an application of a transistor using an oxide semiconductor to a display device using a characteristic of low leakage current of the transistor has been reported (see Non-Patent Document 8).
- the display device the displayed image is switched several tens of times per second. The number of switching of images per second is called a refresh rate.
- the refresh rate may be referred to as a drive frequency.
- Such high-speed screen switching that is difficult for human eyes to perceive is considered as a cause of eye fatigue.
- it has been proposed to reduce the number of times of image rewriting by lowering the refresh rate of the display device.
- power consumption of the display device can be reduced by driving at a reduced refresh rate.
- Such a driving method is called idling stop (IDS) driving.
- IDS idling stop
- the discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of the transistor using the oxide semiconductor having the CAAC structure or the nc structure, and the cost reduction and the throughput of the manufacturing process.
- research on application of the transistor to a display device and an LSI utilizing the characteristic that the leakage current of the transistor is low is underway.
- composition of metal oxide A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.
- CAAC c-axis aligned crystal
- CAC Cloud-Aligned Composite
- CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor.
- the conductive function is a function of flowing electrons (or holes) serving as carriers
- the insulating function is an electron serving as carriers. It is a function that does not flow.
- a function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
- CAC-OS or CAC-metal oxide has a conductive region and an insulating region.
- the conductive region has the above-described conductive function
- the insulating region has the above-described insulating function.
- the conductive region and the insulating region may be separated at the nanoparticle level.
- the conductive region and the insulating region may be unevenly distributed in the material, respectively.
- the conductive region may be observed with the periphery blurred and connected in a cloud shape.
- the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
- CAC-OS or CAC-metal oxide is composed of components having different band gaps.
- CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
- the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
- the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
- CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
- An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
- the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor).
- OS amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
- the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and has a strain.
- the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
- Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
- a lattice arrangement such as a pentagon and a heptagon in the distortion.
- a clear crystal grain boundary also referred to as a grain boundary
- the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.
- the CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
- In layer a layer containing indium and oxygen
- M, Zn elements M, zinc, and oxygen
- indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
- CAAC-OS is an oxide semiconductor with high crystallinity.
- CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs.
- the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.
- Nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
- the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
- the a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.
- the a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
- Oxide semiconductors have various structures and have different characteristics.
- the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
- the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.
- an oxide semiconductor with low carrier density is preferably used.
- the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased.
- a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
- the oxide semiconductor has a carrier density of less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 ⁇ 9 / What is necessary is just to be cm 3 or more.
- a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low defect level density and thus may have a low trap level density.
- the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
- Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
- the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
- the oxide semiconductor contains an alkali metal or an alkaline earth metal
- a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor.
- the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
- the nitrogen concentration in the oxide semiconductor is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 in SIMS. atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and even more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
- the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
- an oxygen vacancy may be formed in some cases.
- electrons serving as carriers may be generated.
- a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible.
- the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
- Stable electrical characteristics can be provided by using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor.
- oxygen deficiency is an example of a defect that leads to poor electrical characteristics of the transistor.
- the threshold voltage is likely to fluctuate in the negative direction, which tends to be normally on. This is because donors due to oxygen vacancies contained in the metal oxide are generated and the carrier concentration increases.
- various problems such as an operation failure easily occurring during operation or a high power consumption during non-operation occur.
- the metal oxide there are oxygen atoms that are weakly bonded to metal atoms and tend to be oxygen deficient.
- the metal oxide is an In—Ga—Zn oxide
- a zinc atom and an oxygen atom tend to form a weak bond (also referred to as a weak Zn—O bond).
- the weak Zn—O bond is a bond between a zinc atom and an oxygen atom that is bonded at such a high strength as to be broken by a high-temperature treatment performed during the manufacturing process or an electrical stress applied during a stress test. The resulting bond.
- the bond is cut by heat treatment or current stress, and oxygen vacancies are formed. Formation of oxygen vacancies lowers the stability of the transistor, such as resistance to heat treatment and resistance in stress tests.
- impurities in the metal oxide when impurities are present in the metal oxide, it is presumed that a weak Zn—O bond is likely to be formed.
- impurities in the metal oxide include water molecules and hydrogen. The presence of water molecules or hydrogen in the metal oxide may cause a hydrogen atom to bond with an oxygen atom constituting the metal oxide (also referred to as OH bond).
- an oxygen atom bonded to a hydrogen atom When the In—Ga—Zn oxide is a single crystal, the oxygen atoms constituting the metal oxide are bonded to four metal atoms constituting the metal oxide.
- an oxygen atom bonded to a hydrogen atom may be bonded to two or three metal atoms. By reducing the number of metal atoms bonded to oxygen atoms, the oxygen atoms are easily lost. Note that when a zinc atom is bonded to an oxygen atom forming an OH bond, the bond between the oxygen atom and the zinc atom is presumed to be weak.
- weak Zn—O bonds may be formed in a strain existing in a region where a plurality of nanocrystals are connected. Nanocrystals are based on hexagons but have lattice arrangements such as pentagons and heptagons in the strain. In this strain, since the bond distance between atoms is not uniform, it is estimated that a weak Zn—O bond is formed.
- the oxygen atoms and zinc atoms constituting the weak Zn—O bond By reducing the oxygen atoms and zinc atoms constituting the weak Zn—O bond, formation of oxygen vacancies due to heat treatment or current stress can be suppressed, and the stability of the transistor can be improved. Note that when only the oxygen atoms constituting the weak Zn—O bond are reduced and the zinc atoms constituting the weak Zn—O bond are not reduced, supplying the oxygen atom in the vicinity of the zinc atom causes the weak Zn—O bond to regenerate. May be formed. Therefore, it is preferable to reduce zinc atoms and oxygen atoms constituting weak Zn—O bonds.
- Vacuum baking is a heat treatment performed in a vacuum atmosphere.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the treatment chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- the temperature of the substrate at the time of heat treatment may be 300 ° C. or higher, preferably 400 ° C. or higher.
- oxygen atoms and zinc atoms constituting weak Zn-O bonds can be reduced.
- the atoms constituting the metal oxide are rearranged so that four metals are rearranged. More oxygen atoms are bonded to the atoms. Accordingly, oxygen atoms and zinc atoms constituting the weak Zn—O bond can be reduced, and the weak Zn—O bond can be prevented from being re-formed.
- (A) in each figure shows a top view.
- (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200.
- (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.
- a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate.
- the insulator 214 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD method. (Atomic Layer Deposition) method or the like can be used.
- the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
- PECVD Plasma Enhanced CVD
- TCVD Thermal CVD
- Photo CVD Photo CVD
- MCVD Metal CVD
- MOCVD Metal Organic CVD
- the plasma CVD method can obtain a high-quality film at a relatively low temperature.
- the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
- a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
- a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
- plasma damage during film formation does not occur, so that a film with few defects can be obtained.
- the ALD method utilizes the self-controllability that is the nature of atoms and can deposit atoms one layer at a time, so it is possible to form a very thin film, and to form a structure with a high aspect ratio. There are effects such as film formation with few defects such as holes, film formation with excellent coverage, and film formation at low temperature.
- the ALD method also includes a film forming method PEALD (Plasma Enhanced ALD) method using plasma. Use of plasma may be preferable because it enables film formation at a lower temperature.
- some precursors used in the ALD method include impurities such as carbon. Therefore, a film provided by the ALD method may contain a larger amount of impurities such as carbon than a film provided by another film formation method.
- the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
- the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
- the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
- the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
- the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
- a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
- a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
- an aluminum oxide film is formed as the insulator 214 by a sputtering method.
- the insulator 214 may have a multilayer structure.
- an aluminum oxide film may be formed by a sputtering method, and the aluminum oxide film may be formed on the aluminum oxide by an ALD method.
- an aluminum oxide film may be formed by an ALD method, and an aluminum oxide film may be formed on the aluminum oxide by a sputtering method.
- silicon nitride or silicon nitride oxide may be formed by a plasma CVD method.
- an insulator 216 is formed over the insulator 214.
- the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- silicon oxide is formed as the insulator 216 by a CVD method.
- an opening reaching the insulator 214 is formed in the insulator 216 by using a lithography method.
- the opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed.
- a wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing.
- As the insulator 214 an insulator that functions as an etching stopper when the insulator 216 is etched to form an opening is preferably selected. For example, in the case where silicon oxide is used for the insulator 216 that forms the opening, silicon nitride, aluminum oxide, or hafnium oxide is preferably used as the insulator 214 that functions as an etching stopper.
- a resist is exposed through a mask.
- a resist mask is formed by removing or leaving the exposed region using a developer.
- a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
- the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
- an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens.
- an electron beam or an ion beam may be used.
- a mask is not necessary when an electron beam or an ion beam is used.
- the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
- a hard mask made of an insulator or a conductor may be used instead of the resist mask.
- an insulating film or a conductive film to be a hard mask material is formed over the insulating film to be the insulator 216, a resist mask is formed thereover, and the hard mask material is etched to have a desired shape.
- a hard mask can be formed. Etching of the insulating film to be the insulator 216 may be performed after removing the resist mask, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the insulating film to be the insulator 216 is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.
- a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
- the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes.
- a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed.
- mold electrode may be sufficient.
- mold electrode may be sufficient.
- a dry etching apparatus having a high-density plasma source can be used.
- an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high-density plasma source.
- a conductive film to be the conductor 205a is formed.
- a conductive barrier film having a function of suppressing permeation of impurities and oxygen is preferably used.
- tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
- a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
- the conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the conductive film to be the conductor 205a tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method.
- a metal nitride as the conductor 205a, diffusion of the metal from the conductor 205a to the outside can be suppressed even when a metal that easily diffuses such as copper is used in the conductor 205c described later.
- a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a.
- the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a conductive barrier film having a function of suppressing permeation of impurities and oxygen is preferably used as in the conductor 205a.
- titanium nitride is formed using an ALD method as the conductive film to be the conductor 205b.
- a conductive film to be the conductor 205c is formed over the conductive film to be the conductor 205b.
- the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a low-resistance conductive material such as tungsten, copper, or aluminum is formed as the conductive film to be the conductor 205c.
- the conductive film to be the conductor 205a, the conductive film to be the conductor 205b, and a part of the conductive film to be the conductor 205c are removed by polishing, so that the insulator 216 is exposed.
- the conductive film to be the conductor 205a, the conductive film to be the conductor 205b, and the conductive film to be the conductor 205c remain only in the opening.
- the conductor 205 including the conductor 205a, the conductor 205b, and the conductor 205c with a flat upper surface can be formed (see FIG. 17).
- part of the insulator 216 may be removed by the CMP treatment.
- the method for manufacturing the insulator 216 and the conductor 205 is not limited to the above.
- a conductive film to be the conductor 205 is formed over the insulator 214, and the conductive film 205 is formed by lithography using a lithography method.
- an insulating film to be the insulator 216 is provided so as to cover the conductor 205, and a part of the insulating film is removed by CMP treatment until a part of the conductor 205 is exposed.
- An insulator 216 may be formed.
- the planarity of the upper surfaces of the conductor 205 and the insulator 216 can be improved, and the oxide 230b and The crystallinity of the CAAC-OS included in one or both of the oxides 230c can be improved.
- the insulator 222 is formed over the insulator 216 and the conductor 205.
- an insulator including one or both of aluminum and hafnium may be formed.
- the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- An insulator including one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 200 to the inside of the transistor 200 through the insulator 222 is suppressed. In addition, generation of oxygen vacancies in the oxide 230 can be suppressed.
- the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulator 224 is formed over the insulator 222.
- the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- heat treatment is preferably performed.
- the heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.
- the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
- the heat treatment may be performed in a reduced pressure state.
- the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in a nitrogen or inert gas atmosphere. Good.
- the heat treatment after the insulator 224 is formed, treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.
- impurities such as water and hydrogen contained in the insulator 224 can be removed.
- the heat treatment can also be performed at a timing after the insulator 222 is formed.
- plasma treatment including oxygen may be performed in a reduced pressure state.
- an apparatus having a power source that generates high-density plasma using microwaves for example.
- a power source for applying RF Radio Frequency
- high-density plasma high-density oxygen radicals can be generated.
- RF Radio Frequency
- oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. it can.
- plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment may not be performed.
- an oxide film 230A to be the oxide 230a, an oxide film 230B to be the oxide 230b, and a conductive film 242A are sequentially formed over the insulator 224 (see FIG. 17).
- the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
- the oxide film 230A, the oxide film 230B, and the conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the oxide film 230A and the oxide film 230B are formed by a sputtering method
- oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
- excess oxygen in the oxide film to be formed can be increased.
- the above oxide film is formed by a sputtering method
- the above In-M-Zn oxide target or the like can be used.
- a direct current (DC) power source or an alternating current (AC) power source such as a radio frequency (RF) power source is connected to the target, and necessary power can be applied according to the electric conductivity of the target.
- DC direct current
- AC alternating current
- RF radio frequency
- part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, more preferably 100%.
- an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. It is formed.
- a transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have a relatively high field-effect mobility. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved. Note that one embodiment of the present invention is not limited to this.
- an oxygen-excess type is formed by forming the film so that the proportion of oxygen contained in the sputtering gas exceeds 30% and is 100% or less, preferably 70% or more and 100% or less.
- An oxide semiconductor is formed.
- a transistor using an oxygen-excess type oxide semiconductor for a channel formation region can have relatively high reliability.
- the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B are preferably formed without being exposed to the atmosphere.
- a multi-chamber film deposition apparatus may be used.
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment.
- impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed.
- the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.
- the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into island shapes to form the oxide 230a, the oxide 230b, and the conductive film 242B. Note that in this step, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may be reduced (see FIG. 18).
- the oxide 230 a and the oxide 230 b are formed so that at least a part thereof overlaps with the conductor 205.
- the angle formed by the side surfaces of the oxides 230a and 230b and the upper surface of the insulator 222 may be a low angle.
- the angle formed between the side surfaces of the oxides 230a and 230b and the upper surface of the insulator 222 is preferably greater than or equal to 60 ° and less than 70 °.
- the side surface of the oxide 230 b may be substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased.
- a curved surface is provided between the side surface of the oxide 230b and the upper surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape).
- the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the oxide 230b.
- the conductive film to be the oxide film 230A, the oxide film 230B, and the conductive film 242A may be processed by a lithography method.
- a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.
- impurities due to an etching gas or the like may adhere to or diffuse on the surface or inside of the oxide 230a and the oxide 230b.
- impurities include fluorine and chlorine.
- ⁇ Clean to remove the above impurities.
- the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleanings may be combined as appropriate.
- cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water.
- aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water.
- ultrasonic cleaning using pure water or carbonated water may be performed.
- ultrasonic cleaning using pure water or carbonated water is performed.
- heat treatment may be performed.
- the above-described heat treatment conditions can be used.
- heat treatment is preferably performed before the insulating film 254A is formed.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C.
- it is preferably performed at the same temperature as the deposition temperature of the insulating film 254A.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 200 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an insulating film 254A is formed over the insulator 224, the oxide 230a, the oxide 230b, and the conductive film 242B.
- the insulating film 254A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film 254A is preferably an insulating film having a function of suppressing diffusion of impurities such as hydrogen and oxygen.
- an aluminum oxide film is preferably formed by a sputtering method. By forming an aluminum oxide film with a gas containing oxygen by a sputtering method, oxygen can be injected into the insulator 224. That is, the insulator 224 can have excess oxygen.
- the insulating film 254A aluminum oxide may be deposited while heating the substrate at a high temperature.
- the substrate heating temperature at the time of forming the insulating film 254A may be 200 ° C. or higher, preferably 250 ° C. or higher, more preferably 350 ° C. or higher.
- the insulating film 254A may have a stacked structure.
- an insulating film 244A may be formed over the insulating film 254A (see FIG. 19).
- the insulating film 244A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an insulating film having a function of suppressing diffusion of impurities such as hydrogen and oxygen is preferably used.
- the insulating film 244A having a uniform thickness can be formed even in the step portion formed by the dummy gate layer 262A or the like.
- a dense thin film can be formed by using the ALD method. Since a dense thin film having excellent coverage can be formed in this manner, for example, even if a defect such as a void or a pinhole occurs in the insulating film 254A, it can be covered with the insulating film 244A.
- the insulating film 244A may be formed as the insulating film 244A.
- the flow rate of nitrogen gas with respect to the total flow rate of the deposition gas is 30% to 100%, preferably 40% or more. 100% or less, more preferably 50% or more and 100% or less.
- the insulating film 244A aluminum oxide may be formed while heating the substrate at a high temperature.
- the substrate heating temperature at the time of forming the insulating film 244A may be 200 ° C. or higher, preferably 250 ° C. or higher, more preferably 350 ° C. or higher.
- the insulating film 254A by forming an aluminum oxide film using the ALD method as the insulating film 254A, it is possible to prevent the dummy gate layer 262A from being deformed when the insulating film 244A is formed at the above temperature. .
- fluorine may be added after formation of one or both of the insulating film 244A and the insulating film 254A. Fluorine is added to one or both of the insulating film 244A and the insulating film 254A by performing plasma treatment in an atmosphere containing a fluorine-based gas (for example, CF 4 ) or by doping a gas containing fluorine. ,It can be carried out.
- a fluorine-based gas for example, CF 4
- excess oxygen contained in the insulator 224 can be prevented from diffusing outward, and impurities such as water and hydrogen can be prevented from entering the insulator 224 from the outside. Note that the formation of the insulating film 244A can be omitted.
- a dummy gate layer 262A is formed (see FIG. 19).
- the dummy gate film to be the dummy gate layer 262A is processed and used as a dummy gate.
- a dummy gate is a temporary gate electrode. That is, a dummy gate film to be the dummy gate layer 262A is processed to form a temporary gate electrode, and the dummy gate is removed in a later process, and a gate electrode made of a conductive film or the like is formed instead. Therefore, it is preferable to use a film that can be easily processed and removed easily as the dummy gate film to be the dummy gate layer 262A.
- the dummy gate film to be the dummy gate layer 262A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
- an insulator, a semiconductor, or a conductor can be used.
- silicon such as polysilicon, microcrystalline silicon, or amorphous silicon, or a metal film such as aluminum, titanium, or tungsten may be used.
- a film containing carbon, SOG (Spin On Glass), a resin film, or the like may be formed using a coating method.
- the resin include photoresist, polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
- the dummy gate film to be the dummy gate layer 262A can be a multilayer film using different film types.
- the dummy gate film serving as the dummy gate layer 262A can be a film having a two-layer structure in which a conductive film and a resin film are formed over the conductive film.
- the conductive film may function as a stopper film for CMP processing.
- the end point of the CMP process may be detected, and processing variations may be reduced.
- the dummy gate layer 262A is formed by etching the dummy gate film to be the dummy gate layer 262A by lithography (see FIG. 19).
- the dummy gate layer 262A is formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.
- an insulating film to be the insulator 280 is formed over the dummy gate layer 262A and the insulating film 244A.
- the insulating film to be the insulator 280 and part of the dummy gate layer 262A are removed until part of the dummy gate layer 262A is exposed, so that the insulator 280 and the dummy gate 262 are formed (see FIG. 20).
- a CMP process is preferably used to form the insulator 280 and the dummy gate 262. As shown in FIG. 20B, the upper surface of the dummy gate 262 and the upper surface of the insulator 280 substantially coincide with each other.
- the dummy gate 262 and part of the insulating film 254A and the insulating film 244A overlapping with the dummy gate 262 are removed to form an opening 263 (see FIG. 21).
- the dummy gate 262 can be removed by wet etching, dry etching, ashing, or the like. Alternatively, a combination of a plurality of the above processes may be performed as appropriate. For example, a wet etching process is performed after the ashing process. By removing the dummy gate 262, a part of the surface of the conductive film 242B is exposed from the opening 263.
- the removal can be performed using wet etching or dry etching. In this embodiment mode, dry etching is used. Use of dry etching is preferable because fine processing can be performed.
- part of the top surface of the oxide 230b exposed from between the conductors 242a and 242b may be removed.
- the conductor 242a and the conductor 242b are formed using the insulator 280, the insulator 244, and the insulator 254 as a mask. Accordingly, the insulator 280, the insulator 244, and the opening 263 formed in the insulator 254 overlap with a region between the conductor 242a and the conductor 242b. Thereby, the conductor 260 can be disposed in a self-aligned manner between the conductors 242a and 242b in a later step.
- heat treatment is preferably performed before the formation of the oxide film 230C.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Alternatively, it is preferably performed at the same temperature as the deposition temperature of the oxide film 230C.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 300 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an oxide film 230 ⁇ / b> C is formed so as to be embedded in the opening 263. Further, it is preferable that the oxide film 230C be continuously formed after the heat treatment without being exposed to the atmosphere. For example, it is preferable to perform the heat treatment and the film formation process continuously in different chambers using a multi-chamber film formation apparatus or the like. By performing such treatment, impurities such as moisture, hydrogen, and carbon adsorbed on the surfaces of the oxide 230a and the oxide 230b are removed, and the moisture concentration and hydrogen in the oxide 230a and the oxide 230b are removed. The concentration can be reduced.
- the impurity removed by the heat treatment includes an impurity having a bond of hydrogen and carbon, an impurity having a bond of hydrogen and oxygen, and the like. Further, by performing heat treatment and film formation continuously without exposure to the outside air, impurities such as hydrogen can be prevented from re-entering the oxide 230.
- the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the oxide film 230C to be the oxide 230c may be formed using a film formation method similar to that for the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c.
- As the oxide film 230C an In—Ga—Zn oxide or an oxide containing no In can be used.
- As the oxide not containing In a Ga—Zn oxide, gallium oxide, or the like can be used.
- a stacked structure of an In—Ga—Zn oxide and an oxide containing no In may be used as the oxide film 230C.
- an oxide film to be the oxide 230c is formed by a sputtering method using a 1: 3: 4 [atomic ratio] target.
- the oxide film 230C may have a stacked structure including a first oxide film and a second oxide film on the first oxide film, and is similar to the target used for forming the oxide film 230B.
- the first oxide film may be formed using a target
- the second oxide film may be formed using a target similar to the target used for forming the oxide film 230A.
- the oxide film 230C is preferably formed while heating the substrate. At this time, oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced by setting the substrate temperature to 300 ° C. or higher. Further, for example, the film may be formed at the same temperature as that of an insulating film 250A described later. In addition, by forming the film while heating the substrate in this manner, the crystallinity of the oxide 230a, the oxide 230b, and the oxide film 230C can be improved.
- the oxide film 230C when the oxide film 230C is formed, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, more preferably 100%. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.
- heat treatment is preferably performed before the formation of the insulating film 250A.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Alternatively, it is preferably performed at the same temperature as the deposition temperature of the insulating film 250A.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 350 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an insulating film 250A is formed.
- the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- As the insulating film 250A it is preferable to form silicon oxide, hafnium oxide, gallium oxide, or the like by an ALD method.
- a stacked film of silicon oxide and gallium oxide over silicon oxide may be used as the insulating film 250A.
- the film formation temperature at the time of forming the insulating film 250A is 300 ° C. or higher and lower than 450 ° C., preferably 300 ° C. or higher and lower than 400 ° C., particularly preferably around 350 ° C.
- an insulator with few impurities can be formed.
- oxygen can be introduced into the insulating film 250A by exciting oxygen with a microwave to generate high-density oxygen plasma and exposing the insulating film 250A to the oxygen plasma.
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.
- an oxide film 230D is formed. Further, it is preferable that the oxide film 230D be continuously formed after the heat treatment without being exposed to the atmosphere. For example, it is preferable to perform the heat treatment and the film formation process continuously in different chambers using a multi-chamber film formation apparatus or the like. By performing such treatment, impurities such as moisture, hydrogen, and carbon adsorbed on the surface of the insulating film 250A and the like can be removed, and the moisture concentration and the hydrogen concentration in the insulating film 250A can be reduced.
- the impurity removed by the heat treatment includes an impurity having a bond of hydrogen and carbon, an impurity having a bond of hydrogen and oxygen, and the like. Further, by performing heat treatment and film formation continuously without exposure to the outside air, impurities such as hydrogen can be prevented from re-entering the oxide 230.
- the oxide film 230D may be formed using a target similar to the target used for forming the oxide film 230C.
- the oxide film 230D is preferably formed while heating the substrate. At this time, by setting the substrate temperature to 300 ° C. or higher, oxygen vacancies in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. By forming the film while heating the substrate, the crystallinity of the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be improved.
- the oxide film 230D when the oxide film 230D is formed, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a, the oxide 230b, and the oxide film 230C through the insulating film 250A. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, more preferably 100%. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.
- a conductive film 260A and a conductive film 260B are formed.
- the conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a CVD method it is preferable to use a CVD method.
- the conductive film 260A is formed using an ALD method
- the conductive film 260B is formed using a CVD method (see FIG. 22).
- the oxide film 230C, the insulator 250, and the oxide 230d are polished by polishing the oxide film 230C, the insulating film 250A, the oxide film 230D, the conductive film 260A, and the conductive film 260B until the insulator 280 is exposed. Then, a conductor 260 (conductor 260a and conductor 260b) is formed (see FIG. 23).
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment.
- the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced.
- heat treatment is preferably performed before the formation of the insulating film to be the insulator 274.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Or it is preferable to carry out at the same temperature as the film-forming temperature of this insulating film.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 250 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an insulating film to be the insulator 274 is formed over the insulator 280.
- the insulating film to be the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an aluminum oxide film is preferably formed by a sputtering method, for example. By forming an aluminum oxide film by a sputtering method, diffusion of hydrogen included in the insulator 280 to the oxide 230 may be suppressed in some cases.
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment.
- the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced.
- an insulating film to be the insulator 281 may be formed over the insulator 274 (see FIG. 23).
- the insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- openings that reach the conductor 242a and the conductor 242b are formed in the insulator 254, the insulator 244, the insulator 280, the insulator 274, and the insulator 281.
- the opening may be formed using a lithography method.
- an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
- the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an insulating film having a function of suppressing permeation of oxygen is preferably used.
- a silicon nitride film may be formed by using an ALD method or a CVD method.
- a precursor containing silicon and halogen or a precursor of aminosilanes can be used.
- a precursor containing silicon and halogen SiCl 4 , SiH 2 Cl 2 , Si 2 Cl 6 , Si 3 Cl 8, or the like can be used.
- monovalent, divalent, or trivalent aminosilanes can be used as precursors for aminosilanes.
- ammonia or hydrazine can be used as the nitriding gas.
- the anisotropic etching may be performed by, for example, a dry etching method.
- the conductive film to be the conductor 240a and the conductor 240b preferably has a stacked structure including a conductor having a function of suppressing diffusion of impurities such as water and hydrogen.
- a stack of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used.
- the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 281 is exposed.
- the conductive film remains only in the opening, whereby the conductor 240a and the conductor 240b having a flat upper surface can be formed (see FIG. 23).
- part of the insulator 281 may be removed by the CMP treatment.
- a semiconductor device including the transistor 200 illustrated in FIG. 4 can be manufactured. As illustrated in FIGS. 17 to 23, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
- ⁇ Method for Manufacturing Semiconductor Device 1-2> A method for manufacturing a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from that described in ⁇ Method 1-1 for Manufacturing Semiconductor Device>, will be described with reference to FIGS.
- (A) in each figure shows a top view.
- (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200.
- (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.
- the manufacturing method is the same as that described in ⁇ Semiconductor Device Manufacturing Method 1-1>. Therefore, the method for manufacturing the semiconductor device according to FIGS. 17 to 21 can be referred to.
- an oxide film 230 ⁇ / b> C is formed so as to be embedded in the opening 263.
- a dopant 258 is added to the oxide film 230C (see FIG. 24).
- the dopant 258 is preferably oxygen.
- oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide 230c can be reduced.
- a method for adding the dopant 258 an ion implantation method in which an ionized source gas is added after mass separation, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. be able to.
- the ionic species to be added and the concentration thereof can be strictly controlled.
- high-concentration ions can be added in a short time.
- an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.
- an insulating layer to be the insulator 250, an oxide film to be the oxide 230d, and a conductive film to be the conductor 260 (the conductors 260a and 260b) are formed over the oxide film 230C.
- the oxide 230c is polished by polishing the oxide film 230C, the insulating layer to be the insulator 250, the oxide film to be the oxide 230d, and the conductive film to be the conductor 260 by CMP treatment until the insulator 280 is exposed.
- the insulator 250, the oxide 230d, and the conductor 260 are formed.
- a dopant 259 is added to the insulator 280 (see FIG. 25). As the dopant 259, oxygen is preferable.
- oxygen can be supplied to the oxide 230a, the oxide 230b, and the oxide 230c through the insulator 280, and oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide 230c are reduced. it can. Since the description of the dopant 258 can be referred to for the addition method of the dopant 259, detailed description is omitted.
- an insulating film 275 is formed over the insulator 280 (see FIG. 26).
- the insulating film 275 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an aluminum oxide film is preferably formed by a sputtering method, for example. By forming an aluminum oxide film by a sputtering method, diffusion of hydrogen included in the insulator 280 to the oxide 230 may be suppressed in some cases.
- heat treatment may be performed.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 350 ° C. for 4 hours.
- oxygen included in the insulating film 275 is supplied to the insulator 280, and oxygen can be supplied to the oxide 230a, the oxide 230b, and the oxide 230c through the insulator 280, and the oxide 230a, the oxide 230b, and Oxygen vacancies in the oxide 230c can be reduced.
- the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced.
- the insulating film 275 is removed, and the insulator 280, the oxide 230c, the insulator 250, the oxide 230d, the conductor 260a, and the conductor 260b are exposed.
- an insulating film to be the insulator 274 is formed over the insulator 280.
- An insulating film to be the insulator 281 may be formed over the insulator 274 (see FIG. 23).
- openings that reach the conductor 242a and the conductor 242b are formed in the insulator 254, the insulator 244, the insulator 280, the insulator 274, and the insulator 281.
- an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
- conductive films to be the conductors 240a and 240b are formed. Subsequently, by performing CMP treatment, part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 281 is exposed. As a result, the conductive film remains only in the opening, whereby the conductor 240a and the conductor 240b having a flat upper surface can be formed (see FIG. 4).
- a semiconductor device including the transistor 200 illustrated in FIG. 4 can be manufactured. As illustrated in FIGS. 24 to 26, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
- (A) in each figure shows a top view.
- (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200A.
- (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200A. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.
- the manufacturing method is the same as that described in ⁇ Semiconductor Device Manufacturing Method 1-1> (see FIG. 27). Accordingly, the description of ⁇ Method 1-1 for Manufacturing Semiconductor Device> can be referred to, and thus detailed description thereof is omitted.
- heat treatment may be performed.
- impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed.
- the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b. Note that in this step, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may be reduced (see FIG. 28).
- the oxide film 230A and the oxide film 230B may be processed by a lithography method.
- a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.
- Cleaning is performed in order to remove impurities during the processing of the oxide film 230A and the oxide film 230B.
- the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleanings may be combined as appropriate.
- heat treatment may be performed.
- the above-described heat treatment conditions can be used.
- heat treatment is preferably performed before the insulating film 254A is formed.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Alternatively, it is preferably performed at the same temperature as the deposition temperature of the insulating film 254A.
- an insulating film 254A is formed to cover the oxide 230a and the oxide 230b (see FIG. 28).
- the insulating film 254A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a dummy gate film to be a dummy gate layer 262A is formed on the insulating film 254A.
- the dummy gate film to be the dummy gate layer 262A is processed and used as a dummy gate.
- a dummy gate is a temporary gate electrode. That is, a dummy gate film to be the dummy gate layer 262A is processed to form a temporary gate electrode, and the dummy gate is removed in a later process, and a gate electrode made of a conductive film or the like is formed instead. Therefore, it is preferable to use a film that can be easily processed and removed easily as the dummy gate film to be the dummy gate layer 262A.
- the dummy gate film to be the dummy gate layer 262A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
- an insulator, a semiconductor, or a conductor can be used.
- silicon such as polysilicon, microcrystalline silicon, or amorphous silicon, or a metal film such as aluminum, titanium, or tungsten may be used.
- a film containing carbon, SOG (Spin On Glass), a resin film, or the like may be formed using a coating method.
- the resin include photoresist, polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
- the dummy gate film to be the dummy gate layer 262A can be a multilayer film using different film types.
- the dummy gate film serving as the dummy gate layer 262A can be a film having a two-layer structure in which a conductive film and a resin film are formed over the conductive film.
- the conductive film may function as a stopper film for CMP processing.
- the end point of the CMP process may be detected, and processing variations may be reduced.
- the dummy gate layer 262A is formed by etching the dummy gate film to be the dummy gate layer 262A by lithography (see FIG. 28).
- the dummy gate layer 262A is formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.
- a dopant 257 is added to the oxide 230b using the dummy gate layer 262A as a mask (see FIG. 29).
- the layer 253a and the layer 253b including the dopant 257 are formed in a region of the oxide 230b that does not overlap with the dummy gate layer 262A.
- FIG. 29 illustrates a state where the dopant 257 is diffused and added to a region overlapping with the dummy gate layer 262A of the oxide 230b.
- part of the layers 253a and 253b is also formed in a region overlapping with the dummy gate layer 262A.
- the distance between the layer 253a and the layer 253b, that is, the channel length can be controlled by the length of the dummy gate layer 262A in the channel length direction.
- an ion implantation method in which an ionized source gas is added by mass separation an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. be able to.
- mass separation the ionic species to be added and the concentration thereof can be strictly controlled.
- mass separation is not performed, high-concentration ions can be added in a short time.
- an ion doping method in which atomic or molecular clusters are generated and ionized may be used.
- the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.
- an element that forms the above-described oxygen vacancies or an element that binds to oxygen vacancies may be used.
- an element typically, boron or phosphorus can be given.
- hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, or the like may be used.
- rare gases include helium, neon, argon, krypton, and xenon.
- metals such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc. Any one or more metal elements selected from the elements may be added.
- boron and phosphorus are preferable as the dopant 257. When boron or phosphorus is used as the dopant 257, equipment for an amorphous silicon or low-temperature polysilicon production line can be used, so that capital investment can be suppressed.
- the dopant 257 is added substantially perpendicularly to the upper surface of the insulator 214.
- the present invention is not limited to this, and the dopant 257 may be added while being inclined with respect to the upper surface of the insulator 214.
- the layers 253a and 253b can be easily formed in part of a region overlapping with the dummy gate layer 262A.
- the dopant 257 is added to the oxide 230 through the insulating film 254A.
- the dopant 257 is also added to the insulating film 254A. That is, both the oxide 230 and the insulating film 254A have an element contained in the dopant 257.
- the dopant 257 may be able to suppress the diffusion of excess oxygen to the outside.
- the conductor 260 formed in a later step can be disposed in a self-aligned manner between the layers 253a and 253b.
- an insulating film 280A is formed over the insulating film 254A and the dummy gate layer 262A (see FIG. 30).
- the insulating film 280A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film 280A and a part of the dummy gate layer 262A are removed until a part of the dummy gate layer 262A is exposed to form the insulator 280 and the dummy gate 262 (see FIG. 31).
- a CMP process is preferably used for forming the insulator 280 and the dummy gate 262.
- the dummy gate layer 262A is, for example, a film having a two-layer structure in which a conductive film and a resin film are formed over the conductive film. May function as.
- the end point of the CMP process may be detected by the conductive film, and variation in height of the dummy gate 262 may be reduced.
- the upper surface of the dummy gate 262 and the upper surface of the insulator 280 substantially coincide with each other.
- the dummy gate 262 and a part of the insulating film 254A overlapping with the dummy gate 262 are removed to form an opening 263 (see FIG. 32).
- the removal of the dummy gate 262 and the insulating film 254A can be performed by wet etching, dry etching, ashing, or the like. Alternatively, a combination of a plurality of the above processes may be performed as appropriate. For example, a wet etching process is performed after the ashing process.
- the insulator 254 is formed by removing part of the insulating film 254A. By removing the dummy gate 262 and the insulating film 254A, part of the surface of the oxide 230b is exposed from the opening 263. At this time, part of the surface of the layer 253 may be exposed from the opening 263.
- heat treatment is preferably performed before the formation of the oxide film 230C.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Alternatively, it is preferably performed at the same temperature as the deposition temperature of the oxide film 230C.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 300 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an oxide film 230 ⁇ / b> C is formed so as to be embedded in the opening 263. Further, it is preferable that the oxide film 230C be continuously formed after the heat treatment without being exposed to the atmosphere. For example, it is preferable to perform the heat treatment and the film formation process continuously in different chambers using a multi-chamber film formation apparatus or the like.
- the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the oxide film 230C to be the oxide 230c may be formed using a film formation method similar to that for the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c.
- As the oxide film 230C an In—Ga—Zn oxide or an oxide containing no In can be used.
- As the oxide not containing In a Ga—Zn oxide, gallium oxide, or the like can be used.
- a stacked structure of an In—Ga—Zn oxide and an oxide containing no In may be used as the oxide film 230C.
- the oxide film 230C may have a stacked structure including a first oxide film and a second oxide film on the first oxide film, and is similar to the target used for forming the oxide film 230B.
- the first oxide film may be formed using a target
- the second oxide film may be formed using a target similar to the target used for forming the oxide film 230A.
- the oxide film 230C is preferably formed while heating the substrate. At this time, oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced by setting the substrate temperature to 300 ° C. or higher. Further, for example, the film may be formed at the same temperature as that of an insulating film 250A described later. In addition, by forming the film while heating the substrate in this manner, the crystallinity of the oxide 230a, the oxide 230b, and the oxide film 230C can be improved.
- the oxide film 230C when the oxide film 230C is formed, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, more preferably 100%. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.
- heat treatment is preferably performed before the formation of the insulating film 250A.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Alternatively, it is preferably performed at the same temperature as the deposition temperature of the insulating film 250A.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 350 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an insulating film 250A is formed.
- the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- As the insulating film 250A it is preferable to form silicon oxide, hafnium oxide, gallium oxide, or the like by an ALD method.
- a stacked film of silicon oxide and gallium oxide over silicon oxide may be used as the insulating film 250A.
- the film formation temperature at the time of forming the insulating film 250A is 300 ° C. or higher and lower than 450 ° C., preferably 300 ° C. or higher and lower than 400 ° C., particularly preferably around 350 ° C.
- an insulator with few impurities can be formed.
- oxygen can be introduced into the insulating film 250A by exciting oxygen with a microwave to generate high-density oxygen plasma and exposing the insulating film 250A to the oxygen plasma.
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.
- an oxide film 230D is formed. Further, it is preferable that the oxide film 230D be continuously formed after the heat treatment without being exposed to the atmosphere. For example, it is preferable to perform the heat treatment and the film formation process continuously in different chambers using a multi-chamber film formation apparatus or the like.
- the oxide film 230D may be formed using a target similar to the target used for forming the oxide film 230C.
- the oxide film 230D is preferably formed while heating the substrate. At this time, by setting the substrate temperature to 300 ° C. or higher, oxygen vacancies in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. By forming the film while heating the substrate, the crystallinity of the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be improved.
- the oxide film 230D when the oxide film 230D is formed, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a, the oxide 230b, and the oxide film 230C through the insulating film 250A. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, more preferably 100%. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.
- a conductive film 260A and a conductive film 260B are formed.
- the conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a CVD method it is preferable to use a CVD method.
- the conductive film 260A is formed using an ALD method
- the conductive film 260B is formed using a CVD method (see FIG. 33).
- the oxide film 230C, the insulator 250, and the oxide 230d are polished by polishing the oxide film 230C, the insulating film 250A, the oxide film 230D, the conductive film 260A, and the conductive film 260B until the insulator 280 is exposed. Then, a conductor 260 (conductor 260a and conductor 260b) is formed (see FIG. 34).
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment.
- the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced.
- heat treatment is preferably performed before the formation of the insulating film to be the insulator 274.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Or it is preferable to carry out at the same temperature as the film-forming temperature of this insulating film.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 250 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an insulating film to be the insulator 274 is formed over the insulator 280 (see FIG. 34).
- the insulating film to be the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an aluminum oxide film is preferably formed by a sputtering method, for example. By forming an aluminum oxide film by a sputtering method, diffusion of hydrogen included in the insulator 280 to the oxide 230 may be suppressed in some cases.
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment.
- the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced.
- an insulating film to be the insulator 281 may be formed over the insulator 274.
- the insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 34).
- openings reaching the layers 253a and 253b are formed in the insulator 254, the insulator 280, the insulator 274, and the insulator 281.
- the opening may be formed using a lithography method.
- an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
- the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an insulating film having a function of suppressing permeation of oxygen is preferably used.
- a silicon nitride film may be formed by using an ALD method or a CVD method.
- a precursor containing silicon and halogen or a precursor of aminosilanes can be used.
- a precursor containing silicon and halogen SiCl 4 , SiH 2 Cl 2 , Si 2 Cl 6 , Si 3 Cl 8, or the like can be used.
- monovalent, divalent, or trivalent aminosilanes can be used as precursors for aminosilanes.
- ammonia or hydrazine can be used as the nitriding gas.
- the anisotropic etching may be performed by, for example, a dry etching method.
- the conductive film to be the conductor 240a and the conductor 240b preferably has a stacked structure including a conductor having a function of suppressing diffusion of impurities such as water and hydrogen.
- a stack of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used.
- the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 281 is exposed.
- the conductive film remains only in the opening, whereby the conductor 240a and the conductor 240b having a flat upper surface can be formed (see FIG. 9).
- part of the insulator 281 may be removed by the CMP treatment.
- a semiconductor device including the transistor 200A illustrated in FIG. 9 can be manufactured.
- the transistor 200A can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
- ⁇ Method for Manufacturing Semiconductor Device 2-2> A method for manufacturing a semiconductor device including the transistor 200A according to one embodiment of the present invention, which is different from that described in ⁇ Method 2-1 for manufacturing a semiconductor device>, is described with reference to FIGS.
- (A) in each figure shows a top view.
- (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200A.
- (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200A. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.
- the manufacturing method is the same as that described in ⁇ Method for Manufacturing Semiconductor Device 2-1>. Therefore, the method for manufacturing the semiconductor device according to FIGS. 27 to 32 can be referred to.
- an oxide film 230 ⁇ / b> C is formed so as to be embedded in the opening 263.
- a dopant 258 is added to the oxide film 230C (see FIG. 35).
- the dopant 258 is preferably oxygen.
- oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide 230c can be reduced. Since the description of the dopant 257 can be referred to for the addition method of the dopant 258, detailed description thereof is omitted.
- an insulating layer to be the insulator 250, an oxide film to be the oxide 230d, and a conductive film to be the conductor 260 (the conductors 260a and 260b) are formed over the oxide film 230C.
- the oxide 230c is polished by polishing the oxide film 230C, the insulating layer to be the insulator 250, the oxide film to be the oxide 230d, and the conductive film to be the conductor 260 by CMP treatment until the insulator 280 is exposed.
- the insulator 250, the oxide 230d, and the conductor 260 are formed.
- a dopant 259 is added to the insulator 280 (see FIG. 36). As the dopant 259, oxygen is preferable.
- oxygen can be supplied to the oxide 230a, the oxide 230b, and the oxide 230c through the insulator 280, and oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide 230c are reduced. it can. Since the description of the dopant 257 can be referred to for the addition method of the dopant 259, detailed description thereof is omitted.
- an insulating film 275 is formed over the insulator 280 (see FIG. 37).
- the insulating film 275 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an aluminum oxide film is preferably formed by a sputtering method, for example. By forming an aluminum oxide film by a sputtering method, diffusion of hydrogen included in the insulator 280 to the oxide 230 may be suppressed in some cases.
- heat treatment may be performed.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 350 ° C. for 4 hours.
- oxygen included in the insulating film 275 is supplied to the insulator 280, and oxygen can be supplied to the oxide 230a, the oxide 230b, and the oxide 230c through the insulator 280, and the oxide 230a, the oxide 230b, and Oxygen vacancies in the oxide 230c can be reduced.
- the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced.
- the insulating film 275 is removed, and the insulator 280, the oxide 230c, the insulator 250, the oxide 230d, the conductor 260a, and the conductor 260b are exposed.
- an insulating film to be the insulator 274 is formed over the insulator 280.
- An insulator to be the insulator 281 may be formed over the insulator 274 (see FIG. 34).
- openings that reach the layers 253a and 253b are formed in the insulator 254, the insulator 244, the insulator 280, the insulator 274, and the insulator 281.
- an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
- conductive films to be the conductors 240a and 240b are formed. Subsequently, by performing CMP treatment, part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 281 is exposed. As a result, the conductive film remains only in the opening, whereby the conductor 240a and the conductor 240b having a flat upper surface can be formed (see FIG. 9).
- a semiconductor device including the transistor 200A illustrated in FIG. 9 can be manufactured. As illustrated in FIGS. 35 to 37, the transistor 200A can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
- (A) in each figure shows a top view.
- (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200B.
- (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200B. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.
- the manufacturing method is the same as that described in ⁇ Semiconductor device manufacturing method 1-1> (see FIG. 38). Accordingly, the description of ⁇ Method 1-1 for Manufacturing Semiconductor Device> can be referred to, and thus detailed description thereof is omitted.
- heat treatment may be performed.
- impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed.
- the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b. Note that in this step, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may be reduced (see FIG. 39).
- the oxide film 230A and the oxide film 230B may be processed by a lithography method.
- a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.
- Cleaning is performed in order to remove impurities during the processing of the oxide film 230A and the oxide film 230B.
- the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleanings may be combined as appropriate.
- heat treatment may be performed.
- the above-described heat treatment conditions can be used.
- heat treatment is preferably performed before the insulating film 254A is formed.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Alternatively, it is preferably performed at the same temperature as the deposition temperature of the insulating film 254A.
- an insulating film 254A is formed to cover the oxide 230a and the oxide 230b (see FIG. 39).
- the insulating film 254A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film 254A is preferably an insulating film having a function of suppressing diffusion of impurities such as hydrogen and oxygen.
- an aluminum oxide film is preferably formed by a sputtering method. By forming an aluminum oxide film with a gas containing oxygen by a sputtering method, oxygen can be injected into the insulator 224. That is, the insulator 224 can have excess oxygen.
- the insulating film 254A aluminum oxide may be deposited while heating the substrate at a high temperature.
- the substrate heating temperature at the time of forming the insulating film 254A may be 200 ° C. or higher, preferably 250 ° C. or higher, more preferably 350 ° C. or higher.
- the insulating film 254A may have a stacked structure.
- a dummy gate film to be a dummy gate layer 262A is formed on the insulating film 254A.
- the dummy gate film to be the dummy gate layer 262A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
- an insulator, a semiconductor, or a conductor can be used.
- silicon such as polysilicon, microcrystalline silicon, or amorphous silicon, or a metal film such as aluminum, titanium, or tungsten may be used.
- a film containing carbon, SOG (Spin On Glass), a resin film, or the like may be formed using a coating method.
- the dummy gate film to be the dummy gate layer 262A can be a multilayer film using different film types.
- the dummy gate layer 262A is formed by etching the dummy gate film to be the dummy gate layer 262A by lithography (see FIG. 39).
- the dummy gate layer 262A is formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.
- a dopant 257 is added to the oxide 230b (see FIG. 40).
- the layer 253a and the layer 253b including the dopant 257 are formed in a region of the oxide 230b that does not overlap with the dummy gate layer 262A.
- FIG. 40 illustrates a state where the dopant 257 is diffused and added to a region overlapping with the dummy gate layer 262A of the oxide 230b.
- part of the layers 253a and 253b is also formed in a region overlapping with the dummy gate layer 262A.
- the distance between the layer 253a and the layer 253b, that is, the channel length can be controlled by the length of the dummy gate layer 262A in the channel length direction.
- the addition method of the dopant 257 and the element that can be used as the dopant 257 can refer to the description of ⁇ Method for manufacturing semiconductor device 2-1>, detailed description thereof is omitted.
- the dopant 257 is added substantially perpendicularly to the upper surface of the insulator 214.
- the present invention is not limited to this, and the dopant 257 may be added while being inclined with respect to the upper surface of the insulator 214.
- the layers 253a and 253b can be easily formed in part of a region overlapping with the dummy gate layer 262A.
- the dopant 257 is added to the oxide 230 through the insulating film 254A.
- the dopant 257 is also added to the insulating film 254A. That is, both the oxide 230 and the insulating film 254A have an element contained in the dopant 257.
- the dopant 257 may be able to suppress the diffusion of excess oxygen to the outside.
- the conductor 260 formed in a later step can be disposed in a self-aligned manner between the layers 253a and 253b.
- an insulating film 279A is formed over the insulating film 254A and the dummy gate layer 262A (see FIG. 41).
- the insulating film 279A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film 279A and a part of the dummy gate layer 262A are removed until a part of the dummy gate layer 262A is exposed to form the insulator 279 and the dummy gate 262 (see FIG. 42).
- a CMP process is preferably used for forming the insulator 279 and the dummy gate 262.
- the dummy gate layer 262A is, for example, a film having a two-layer structure in which a conductive film and a resin film are formed over the conductive film. May function as.
- the end point of the CMP process may be detected by the conductive film, and variation in height of the dummy gate 262 may be reduced.
- the upper surface of the dummy gate 262 and the upper surface of the insulator 279 substantially coincide with each other.
- the dummy gate 262 and a part of the insulating film 254A overlapping with the dummy gate 262 are removed to form an opening 263 (see FIG. 43).
- the removal of the dummy gate 262 and the insulating film 254A can be performed by wet etching, dry etching, ashing, or the like. Alternatively, a combination of a plurality of the above processes may be performed as appropriate. For example, a wet etching process is performed after the ashing process.
- the insulator 254 is formed by removing part of the insulating film 254A. By removing the dummy gate 262 and the insulating film 254A, part of the surface of the oxide 230b is exposed from the opening 263.
- the insulator 279 is removed.
- the insulator 279 can be removed by wet etching, dry etching, or the like.
- heat treatment is preferably performed before the formation of the oxide film 230C.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Alternatively, it is preferably performed at the same temperature as the deposition temperature of the oxide film 230C.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 300 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an oxide film 230C is formed over the insulator 254 and the oxide 230b. Further, it is preferable that the oxide film 230C be continuously formed after the heat treatment without being exposed to the atmosphere. For example, it is preferable to perform the heat treatment and the film formation process continuously in different chambers using a multi-chamber film formation apparatus or the like.
- the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the oxide film 230C to be the oxide 230c may be formed using a film formation method similar to that for the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c.
- As the oxide film 230C an In—Ga—Zn oxide or an oxide containing no In can be used.
- As the oxide not containing In a Ga—Zn oxide, gallium oxide, or the like can be used.
- a stacked structure of an In—Ga—Zn oxide and an oxide containing no In may be used as the oxide film 230C.
- the oxide film 230C may have a stacked structure including a first oxide film and a second oxide film on the first oxide film, and is similar to the target used for forming the oxide film 230B.
- the first oxide film may be formed using a target
- the second oxide film may be formed using a target similar to the target used for forming the oxide film 230A.
- the oxide film 230C is preferably formed while heating the substrate. At this time, oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced by setting the substrate temperature to 300 ° C. or higher. Further, for example, the film may be formed at the same temperature as that of an insulating film 250A described later. In addition, by forming the film while heating the substrate in this manner, the crystallinity of the oxide 230a, the oxide 230b, and the oxide film 230C can be improved.
- the oxide film 230C when the oxide film 230C is formed, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, more preferably 100%. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.
- heat treatment is preferably performed before the formation of the insulating film 250A.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Alternatively, it is preferably performed at the same temperature as the deposition temperature of the insulating film 250A.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 350 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an insulating film 250A is formed.
- the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- As the insulating film 250A it is preferable to form silicon oxide, hafnium oxide, gallium oxide, or the like by an ALD method.
- a stacked film of silicon oxide and gallium oxide over silicon oxide may be used as the insulating film 250A.
- the film formation temperature at the time of forming the insulating film 250A is 300 ° C. or higher and lower than 450 ° C., preferably 300 ° C. or higher and lower than 400 ° C., particularly preferably around 350 ° C.
- an insulator with few impurities can be formed.
- oxygen can be introduced into the insulating film 250A by exciting oxygen with a microwave to generate high-density oxygen plasma and exposing the insulating film 250A to the oxygen plasma.
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.
- an oxide film 230D is formed. Further, it is preferable that the oxide film 230D be continuously formed after the heat treatment without being exposed to the atmosphere. For example, it is preferable to perform the heat treatment and the film formation process continuously in different chambers using a multi-chamber film formation apparatus or the like.
- the oxide film 230D may be formed using a target similar to the target used for forming the oxide film 230C.
- the oxide film 230D is preferably formed while heating the substrate. At this time, by setting the substrate temperature to 300 ° C. or higher, oxygen vacancies in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. By forming the film while heating the substrate, the crystallinity of the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be improved.
- the oxide film 230D when the oxide film 230D is formed, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a, the oxide 230b, and the oxide film 230C through the insulating film 250A. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, more preferably 100%. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.
- a conductive film 260A and a conductive film 260B are formed.
- the conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a CVD method it is preferable to use a CVD method.
- the conductive film 260A is formed using the ALD method
- the conductive film 260B is formed using the CVD method (see FIG. 44).
- the conductive film 260A and the conductive film 260B are processed to form the conductor 260 (the conductor 260a and the conductor 260b).
- an insulating film 270A to be the insulator 270 is formed so as to cover the conductor 260 and the oxide film 230D.
- an insulating film having a function of suppressing diffusion of impurities such as hydrogen and oxygen is preferably used as in the material used for the insulator 254.
- aluminum oxide may be formed by a sputtering method (see FIG. 45).
- the insulator 270, the oxide film 230D, the insulating film 250A, and the oxide film 230C are processed to form the insulator 270, the oxide 230d, the insulator 250, and the oxide 230c (see FIG. 46).
- the processing of the insulating film 250A and the oxide film 230C may be performed continuously with the processing of the conductive film 260A and the conductive film 260B.
- the side end of the conductor 260, the side end of the insulator 250, and the side end of the oxide 230c may be located in the same plane.
- the insulator 270, the oxide 230d, the insulator 250, and the oxide 230c form the conductor 260 as illustrated in a top view in FIG.
- the insulator 270, the oxide film 230D, the insulating film 250A, and the oxide film 230C may be processed so as to include them.
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment.
- the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced.
- heat treatment is preferably performed before the formation of the insulating film to be the insulator 274.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 200 ° C. Or it is preferable to carry out at the same temperature as the film-forming temperature of this insulating film.
- the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus.
- the heat treatment is preferably performed at 250 ° C.
- the heat treatment is preferably performed under reduced pressure, and may be performed in a vacuum atmosphere, for example.
- the vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like.
- the pressure in the processing chamber may be 1 ⁇ 10 ⁇ 2 Pa or less, preferably 1 ⁇ 10 ⁇ 3 Pa or less.
- an insulator 280 is formed on the insulator 270.
- the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an insulating film to be the insulator 274 is formed over the insulator 280 (see FIG. 46).
- the insulating film to be the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an aluminum oxide film is preferably formed by a sputtering method, for example.
- oxygen may be supplied to the insulator 280 when the insulator 274 is formed. In some cases, diffusion of oxygen included in the insulator 280 to the insulator 281 side can be suppressed. Further, in some cases, diffusion of hydrogen included in the insulator 281 to the oxide 230 side can be suppressed.
- heat treatment may be performed.
- the heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and the hydrogen concentration of the insulator 280 and the insulator 274 can be reduced.
- an insulating film to be the insulator 281 may be formed over the insulator 274.
- the insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 46).
- openings reaching the layers 253a and 253b are formed in the insulator 254, the insulator 280, the insulator 274, and the insulator 281.
- the opening may be formed using a lithography method.
- an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
- the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an insulating film having a function of suppressing permeation of oxygen is preferably used.
- a silicon nitride film may be formed by using an ALD method or a CVD method.
- a precursor containing silicon and halogen or a precursor of aminosilanes can be used.
- a precursor containing silicon and halogen SiCl 4 , SiH 2 Cl 2 , Si 2 Cl 6 , Si 3 Cl 8, or the like can be used.
- monovalent, divalent, or trivalent aminosilanes can be used as precursors for aminosilanes.
- ammonia or hydrazine can be used as the nitriding gas.
- the anisotropic etching may be performed by, for example, a dry etching method.
- the conductive film to be the conductor 240a and the conductor 240b preferably has a stacked structure including a conductor having a function of suppressing diffusion of impurities such as water and hydrogen.
- a stack of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used.
- the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 281 is exposed.
- the conductive film remains only in the opening, whereby the conductor 240a and the conductor 240b having a flat upper surface can be formed (see FIG. 13).
- part of the insulator 281 may be removed by the CMP treatment.
- a semiconductor device including the transistor 200B illustrated in FIG. 13 can be manufactured. As illustrated in FIGS. 38 to 46, the transistor 200B can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
- ⁇ Method for Manufacturing Semiconductor Device 3-2> A method for manufacturing a semiconductor device including the transistor 200B according to one embodiment of the present invention, which is different from that described in ⁇ Method 3-1 for manufacturing a semiconductor device>, is described with reference to FIGS.
- (A) in each figure shows a top view.
- (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200B.
- (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200B. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.
- the manufacturing method is the same as that described in ⁇ Method for Manufacturing Semiconductor Device 3-1>. Therefore, the method for manufacturing the semiconductor device according to FIGS. 38 to 43 can be referred to.
- the insulator 279 is removed.
- the insulator 279 can be removed by wet etching, dry etching, or the like.
- heat treatment is preferably performed before the formation of the oxide film 230C.
- an oxide film 230C is formed over the insulator 254 and the oxide 230b.
- a dopant 258 is added to the oxide film 230C (see FIG. 47).
- the dopant 258 is preferably oxygen.
- oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide 230c can be reduced. Since the description of the dopant 257 can be referred to for the addition method of the dopant 258, detailed description thereof is omitted.
- an insulating film 250A, an oxide film 230D, a conductive film 260A, and a conductive film 260B are formed over the oxide film 230C.
- the conductive film 260A and the conductive film 260B are processed to form the conductor 260a and the conductor 260b.
- an insulating film 270A is formed.
- the insulator 270A, the oxide film 230D, the insulating film 250A, and the oxide film 230C are processed to form the insulator 270, the oxide 230d, the insulator 250, and the oxide 230c (see FIGS. 44 and 45). . Since the above description can be referred to for formation of the insulator 270, the conductor 260, the oxide 230d, the insulator 250, and the oxide 230c, detailed description thereof is omitted.
- the insulator 280 is formed over the insulator 254, the insulator 270, the conductor 260, the oxide 230d, the insulator 250, and the oxide 230c.
- a dopant 259 is added to the insulator 280 (see FIG. 48).
- oxygen is preferable.
- oxygen can be supplied to the oxide 230a, the oxide 230b, and the oxide 230c through the insulator 280, and oxygen vacancies in the oxide 230a, the oxide 230b, and the oxide 230c are reduced. it can. Since the description of the dopant 257 can be referred to for the addition method of the dopant 259, detailed description thereof is omitted.
- an insulating film 275 is formed over the insulator 280 (see FIG. 49).
- the insulating film 275 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an aluminum oxide film is preferably formed by a sputtering method, for example. By forming an aluminum oxide film by a sputtering method, diffusion of hydrogen included in the insulator 280 to the oxide 230 may be suppressed in some cases.
- heat treatment may be performed.
- the heat treatment may be performed at 100 ° C. or more and 400 ° C. or less, for example, 350 ° C. for 4 hours.
- oxygen included in the insulating film 275 is supplied to the insulator 280, and oxygen can be supplied to the oxide 230a, the oxide 230b, and the oxide 230c through the insulator 280, and the oxide 230a, the oxide 230b, and Oxygen vacancies in the oxide 230c can be reduced.
- the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced.
- the insulating film 275 is removed, and the insulator 280, the oxide 230c, the insulator 250, the oxide 230d, the conductor 260a, and the conductor 260b are exposed.
- an insulating film to be the insulator 274 is formed over the insulator 280.
- An insulating film to be the insulator 281 may be formed over the insulator 274 (see FIG. 46).
- openings that reach the layers 253a and 253b are formed in the insulator 254, the insulator 244, the insulator 280, the insulator 274, and the insulator 281.
- an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
- conductive films to be the conductors 240a and 240b are formed. Subsequently, by performing CMP treatment, part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 281 is exposed. As a result, the conductive film remains only in the opening, whereby the conductor 240a and the conductor 240b having a flat upper surface can be formed (see FIG. 13).
- a semiconductor device including the transistor 200B illustrated in FIG. 13 can be manufactured. As illustrated in FIGS. 47 to 49, the transistor 200B can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
- (A) in each figure shows a top view.
- (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200C.
- (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200C. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.
- the manufacturing method is the same as that described in ⁇ Semiconductor device manufacturing method 1-1> (see FIG. 17). Accordingly, the description of ⁇ Method 1-1 for Manufacturing Semiconductor Device> can be referred to, and thus detailed description thereof is omitted.
- the conductive film 242B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the conductive film to be the oxide film 230A, the oxide film 230B, and the conductive film 242B is processed into an island shape, so that the oxide 230a, the oxide 230b, and the conductive film 242B are formed. Note that in this step, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may be reduced (see FIG. 50).
- an insulating film 254A is formed so as to cover the oxide 230a, the oxide 230b, and the conductive film 242B (see FIG. 50).
- the insulating film 254A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film 254A and the conductive film 242B are processed to form the insulator 254, the conductor 242a, and the conductor 242b (see FIG. 51).
- heat treatment is preferably performed before the formation of the oxide film 230C.
- an oxide film 230C is formed over the insulator 254 and the oxide 230b.
- An insulating film 250A, an oxide film 230D, a conductive film 260A, and a conductive film 260B are formed over the oxide film 230C (see FIG. 52). Since the above description can be referred to for the formation of the oxide film 230C, the insulating film 250A, the oxide film 230D, the conductive film 260A, and the conductive film 260B, detailed description thereof is omitted.
- the conductive film 260A and the conductive film 260B are processed to form the conductor 260a and the conductor 260b.
- an insulating film 270A is formed.
- the insulating film 270A, the oxide film 230D, the insulating film 250A, and the oxide film 230C are processed to form the insulator 270, the oxide 230d, the insulator 250, and the oxide 230c (see FIG. 53). Since the above description can be referred to for formation of the insulator 270, the conductor 260, the oxide 230d, the insulator 250, and the oxide 230c, detailed description thereof is omitted.
- heat treatment may be performed.
- an insulator 280 is formed on the insulator 270.
- an insulating film to be the insulator 274 is formed over the insulator 280 (see FIG. 54).
- heat treatment may be performed.
- an insulating film to be the insulator 281 may be formed over the insulator 274 (see FIG. 54).
- openings that reach the conductors 242a and 242b are formed in the insulator 254, the insulator 280, the insulator 274, and the insulator 281.
- the opening may be formed using a lithography method.
- the insulator 241 is formed. Subsequently, the conductor 240a and the conductor 240b can be formed (see FIG. 16).
- a semiconductor device including the transistor 200C illustrated in FIG. 16 can be manufactured. As illustrated in FIGS. 50 to 54, the transistor 200C can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
- a semiconductor device with high on-state current can be provided.
- a semiconductor device having high frequency characteristics can be provided.
- a semiconductor device with favorable reliability can be provided.
- a semiconductor device that can be miniaturized or highly integrated can be provided.
- a semiconductor device having favorable electrical characteristics can be provided.
- a semiconductor device with low off-state current can be provided.
- a semiconductor device with reduced power consumption can be provided.
- a highly productive semiconductor device can be provided.
- FIGS. 1 One example of a semiconductor device (memory device) using a transistor which is one embodiment of the present invention is illustrated in FIGS.
- the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.
- the transistor 200 the transistor 200 described in the above embodiment can be used.
- the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
- the wiring 1001 is electrically connected to the source of the transistor 300
- the wiring 1002 is electrically connected to the drain of the transistor 300.
- the wiring 1003 is electrically connected to one of a source and a drain of the transistor 200
- the wiring 1004 is electrically connected to the first gate of the transistor 200
- the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
- the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100
- the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
- the memory device shown in FIG. 55 can be arranged in a matrix to constitute a memory cell array.
- the transistor 300 is provided over the substrate 311 and functions as a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including a part of the substrate 311, and a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b.
- the transistor 300 may be either a p-channel type or an n-channel type.
- a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape.
- a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween.
- the conductor 316 may be formed using a material that adjusts a work function.
- Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate.
- an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion.
- transistor 300 illustrated in FIGS. 55A and 55B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
- the capacitor 100 is provided above the transistor 200.
- the capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.
- the conductor 112 provided on the conductor 240 and the conductor 110 can be formed at the same time.
- the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
- the conductor 112 and the conductor 110 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used.
- a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.
- the insulator 130 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. Or the like may be used, and may be provided as a stacked layer or a single layer.
- the insulator 130 is preferably formed using a stacked structure of a material having a high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material.
- the capacitor 100 has an insulator with a high dielectric constant (high-k), so that a sufficient capacitance can be secured, and the insulator having a high dielectric strength can improve the dielectric strength, The electrostatic breakdown of the element 100 can be suppressed.
- an insulator of a high dielectric constant (high-k) material (a material having a high relative dielectric constant)
- high-k high dielectric constant
- gallium oxide, hafnium oxide, zirconium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium And an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, or a nitride having silicon and hafnium gallium oxide, hafnium oxide, zirconium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium And an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, or a nitride having silicon and hafnium.
- silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon and nitrogen are used.
- silicon oxide added, silicon oxide having holes, or resin examples include silicon oxide added, silicon oxide having holes, or resin.
- a wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided. Further, a plurality of wiring layers can be provided depending on the design.
- a conductor having a function as a plug or a wiring may be provided with the same reference numeral by collecting a plurality of structures.
- the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
- an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film.
- the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.
- the insulator that functions as an interlayer film may function as a planarizing film that covers the concave and convex shapes below the insulator.
- the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
- CMP chemical mechanical polishing
- a wiring layer may be provided over the insulator 326 and the conductor 330.
- an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
- a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354.
- the conductor 356 functions as a plug or a wiring.
- a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216.
- the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300.
- an insulator 150 is provided over the conductor 120 and the insulator 130.
- Examples of the insulator that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.
- a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant for an insulator functioning as an interlayer film. Therefore, the material may be selected according to the function of the insulator.
- the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or it is preferable to have resin etc.
- the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole And a laminated structure of resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon.
- the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
- one or both of the conductor 112 and the insulator 130 and the insulator 150 provided over the conductor 120 have a resistivity of 1.0 ⁇ 10 12 ⁇ cm or more and 1.0 ⁇ 10 15 ⁇ cm or less, preferably It is preferable that the insulator be 5.0 ⁇ 10 12 ⁇ cm to 1.0 ⁇ 10 14 ⁇ cm, more preferably 1.0 ⁇ 10 13 ⁇ cm to 5.0 ⁇ 10 13 ⁇ cm.
- the insulator 130 and the insulator 150 maintains the insulating property, and the transistor 200, the transistor 300, and the capacitor 100 are maintained.
- charge accumulated between the wirings such as the conductor 112 and the conductor 120 can be dispersed, so that the characteristic failure and electrostatic breakdown of the transistor and the memory device including the transistor due to the charge can be suppressed.
- silicon nitride or silicon nitride oxide can be used as such an insulator.
- the insulator 140 may be provided below the conductor 112 as an insulator having the above-described resistivity.
- the insulator 140 is formed over the insulator 281, and openings are formed in the insulator 140, the insulator 281, the insulator 274, the insulator 280, the insulator 244, the insulator 254, and the like, and the opening is formed in the opening.
- the insulator 241 and the conductor 240 that is electrically connected to the transistor 200, the conductor 218, and the like may be formed.
- the insulator 140 can be formed using the same material as the insulator 130 or the insulator 150.
- a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. Therefore, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used for the insulator 210, the insulator 350, and the like.
- Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
- An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
- an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
- a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
- Conductors that can be used for wiring and plugs are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium
- a material containing one or more metal elements selected from ruthenium and the like can be used.
- a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
- a metal material, an alloy material, a metal nitride material, a metal oxide material, or the like formed using the above materials can be used as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like.
- These conductive materials can be used as a single layer or stacked layers. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.
- an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor.
- an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
- an insulator 241 may be provided between the insulator 224 and the conductor 240.
- the insulator 241 is preferably provided in contact with the insulator 222 and the insulator 254 which sandwich the insulator 224 having an excess oxygen region.
- the insulator 224 can be sealed with an insulator having a barrier property.
- the insulator 241 is preferably in contact with the insulator 280 and part of the insulator 281. When the insulator 241 extends to the insulator 280 and the insulator 281, diffusion of oxygen and impurities can be further suppressed.
- the insulator 241 it is possible to suppress excess oxygen included in the insulator 224 from being absorbed by the conductor 240. Further, with the insulator 241, diffusion of hydrogen as an impurity to the transistor 200 through the conductor 240 can be suppressed.
- an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used.
- aluminum oxide or hafnium oxide is preferably used.
- a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
- a semiconductor device having a structure different from that of the semiconductor device illustrated in FIG. 55 will be described.
- the transistor 200A is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200A.
- the transistor 200A the transistor 200A described in the above embodiment can be used.
- the transistor 200B is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200B.
- the transistor 200B the transistor 200B described in the above embodiment can be used. Since the above description can be referred to for the structure of the semiconductor device (memory device), detailed description thereof is omitted.
- FIGS. 1 One example of a memory device using a semiconductor device which is one embodiment of the present invention is illustrated in FIGS.
- the memory device illustrated in FIG. 58 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.
- the transistor 400 can control the second gate voltage of the transistor 200.
- the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 and the second gate of the transistor 200 are connected.
- the negative potential of the second gate of the transistor 200 is held with this structure, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source are 0V.
- the transistor 400 since the drain current when the second gate voltage and the first gate voltage are 0 V is very small, the power supply to the transistor 200 and the transistor 400 is not supplied. Negative potential can be maintained for a long time. Accordingly, the memory device including the transistor 200 and the transistor 400 can hold stored data for a long time.
- the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
- the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200.
- the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
- the wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is connected to the drain of the transistor 400. And are electrically connected.
- the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
- the transistor 400 can form a memory cell array by arranging in a matrix like the storage device shown in FIG. Note that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, the transistor 400 is preferably provided in a smaller number than the transistor 200.
- the transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel.
- the transistor 400 includes a conductor 460 functioning as a first gate electrode (a conductor 460a and a conductor 460b), a conductor 405 functioning as a second gate electrode, an insulator 222 functioning as a gate insulating layer,
- the functional layer 453b, the oxide 432a, the oxide 432b, and the conductor 440 are included.
- the conductor 405 is the same layer as the conductor 205.
- the oxide 431a and the oxide 432a are the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are the same layer as the oxide 230b.
- the conductors 453a and 453b are the same layer as the conductor 242.
- the oxide 430c is the same layer as the oxide 230c.
- the insulator 450 is the same layer as the insulator 250.
- the conductor 460 is the same layer as the conductor 260.
- the oxide 430c can be formed by processing an oxide film to be the oxide 230c.
- the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be extremely reduced.
- a dicing line (which may be referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing the large-area substrate into semiconductor elements will be described.
- a dividing method for example, a groove (dicing line) for dividing a semiconductor element may first be formed on a substrate, and then cut in the dicing line to be divided (divided) into a plurality of semiconductor devices.
- the region where the insulator 254 and the insulator 222 are in contact with each other is a dicing line. That is, an opening is provided in the insulator 224 in the vicinity of a memory cell including the plurality of transistors 200 and a region serving as a dicing line provided on the outer edge of the transistor 400.
- An insulator 254 is provided so as to cover the side surface of the insulator 224.
- the insulator 222 and the insulator 254 are in contact with each other in the opening provided in the insulator 224.
- the insulator 222 and the insulator 254 may be formed using the same material and the same method.
- adhesion can be improved. For example, it is preferable to use aluminum oxide.
- the insulator 224, the transistor 200, and the transistor 400 can be wrapped with the insulator 222 and the insulator 254. Since the insulator 222 and the insulator 254 have a function of suppressing diffusion of oxygen, hydrogen, and water, the substrate is divided for each circuit region in which the semiconductor element described in this embodiment is formed. Thus, even when processed into a plurality of chips, impurities such as hydrogen or water can be prevented from being mixed into the transistor 200 and the transistor 400 from the side surface direction of the divided substrate.
- excess oxygen in the insulator 224 can be prevented from diffusing outside the insulator 254 and the insulator 222. Accordingly, excess oxygen in the insulator 224 is efficiently supplied to the oxide in which the channel in the transistor 200 or the transistor 400 is formed. With the oxygen, oxygen vacancies in the oxide in which a channel in the transistor 200 or the transistor 400 is formed can be reduced. Accordingly, an oxide in which a channel is formed in the transistor 200 or the transistor 400 can be an oxide semiconductor having low density of defect states and stable characteristics. That is, variation in electrical characteristics of the transistor 200 or the transistor 400 can be suppressed and reliability can be improved.
- the memory device illustrated in FIG. 59 includes a transistor 400A in addition to the semiconductor device including the transistor 200A, the transistor 300, and the capacitor 100 illustrated in FIG.
- the transistor 400A is formed in the same layer as the transistor 200A and can be manufactured in parallel.
- the memory device illustrated in FIG. 60 includes a transistor 400B in addition to the semiconductor device including the transistor 200B, the transistor 300, and the capacitor 100 illustrated in FIG.
- the transistor 400B is formed in the same layer as the transistor 200B and can be manufactured in parallel. Since the above description can be referred to for the configuration of the storage device, detailed description thereof is omitted.
- an OS transistor a transistor using an oxide as a semiconductor
- a capacitor according to one embodiment of the present invention
- the storage device (hereinafter sometimes referred to as an OS memory device) is described.
- An OS memory device is a storage device that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.
- FIG. 61A shows an example of a structure of the OS memory device.
- the memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
- the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
- the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like.
- the precharge circuit has a function of precharging the wiring.
- the sense amplifier has a function of amplifying a data signal read from the memory cell.
- the wiring is a wiring connected to a memory cell included in the memory cell array 1470, which will be described in detail later.
- the amplified data signal is output to the outside of the storage device 1400 through the output circuit 1440 as the data signal RDATA.
- the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
- the storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as power supply voltages from the outside.
- control signals CE, WE, RE
- an address signal ADDR and a data signal WDATA are input to the storage device 1400 from the outside.
- the address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.
- the control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and the column decoder.
- CE is a chip enable signal
- WE is a write enable signal
- RE is a read enable signal.
- the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as necessary.
- the memory cell array 1470 includes a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC included in one column, and the like. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.
- the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane is shown in FIG. 61A, this embodiment is not limited to this.
- the memory cell array 1470 may be provided over part of the peripheral circuit 1411.
- a sense amplifier may be provided so as to overlap below the memory cell array 1470.
- FIG. 62 illustrates a configuration example of a memory cell applicable to the above-described memory cell MC.
- [DOSRAM] 62A to 62C show circuit configuration examples of DRAM memory cells.
- a DRAM using a memory cell of 1 OS transistor and 1 capacitor element type is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
- a memory cell 1471 illustrated in FIG. 62A includes a transistor M1 and a capacitor CA.
- the transistor M1 includes a gate (sometimes referred to as a front gate) and a back gate.
- the first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 Is connected to the wiring BGL.
- a second terminal of the capacitor element CA is connected to the wiring CAL.
- the wiring BIL functions as a bit line
- the wiring WOL functions as a word line.
- the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA.
- a low level potential is preferably applied to the wiring CAL at the time of writing and reading of data.
- the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
- the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
- the memory cell MC may have a structure in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1472 illustrated in FIG.
- the memory cell MC may be a single-gate transistor, that is, a memory cell including a transistor M1 having no back gate as in the memory cell 1473 illustrated in FIG.
- the transistor 200 can be used as the transistor M1
- the capacitor 100 can be used as the capacitor CA.
- the leakage current of the transistor M1 can be very low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cells can be reduced. Also, the refresh operation of the memory cell can be made unnecessary.
- the leakage current is very low, multi-value data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
- the bit line can be shortened. As a result, the bit line capacitance is reduced, and the storage capacity of the memory cell can be reduced.
- [NOSRAM] 62D to 62H show circuit configuration examples of a gain cell type memory cell having a two-transistor one-capacitance element.
- a memory cell 1474 illustrated in FIG. 62D includes a transistor M2, a transistor M3, and a capacitor CB.
- the transistor M2 includes a front gate (sometimes simply referred to as a gate) and a back gate.
- NOSRAM Nonvolatile Oxide Semiconductor RAM
- the first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 Is connected to the wiring BGL.
- a second terminal of the capacitor CB is connected to the wiring CAL.
- the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.
- the wiring WBL functions as a write bit line
- the wiring RBL functions as a read bit line
- the wiring WOL functions as a word line.
- the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable to apply a low-level potential to the wiring CAL during data writing, during data holding, and during data reading.
- the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
- the memory cell MC is not limited to the memory cell 1474, and the configuration of the circuit can be changed as appropriate.
- the memory cell MC may have a structure in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1475 illustrated in FIG.
- the memory cell MC may be a memory cell including a single-gate transistor, that is, a transistor M2 having no back gate, like the memory cell 1476 illustrated in FIG.
- the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL as in the memory cell 1477 illustrated in FIG.
- the transistor 200 can be used as the transistor M2
- the transistor 300 can be used as the transistor M3
- the capacitor 100 can be used as the capacitor CB.
- an OS transistor as the transistor M2
- the leakage current of the transistor M2 can be very low.
- the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced.
- the refresh operation of the memory cell can be made unnecessary.
- the leakage current is very low, multi-value data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
- the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter sometimes referred to as a Si transistor).
- the conductivity type of the Si transistor may be an n-channel type or a p-channel type.
- the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a reading transistor. Further, by using a Si transistor as the transistor M3, the transistor M2 can be provided over the transistor M3, so that the area occupied by the memory cells can be reduced and the storage device can be highly integrated.
- the transistor M3 may be an OS transistor.
- OS transistors are used as the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.
- FIG. 62H shows an example of a gain cell type memory cell having three transistors and one capacitor.
- a memory cell 1478 illustrated in FIG. 62H includes transistors M4 to M6 and a capacitor CC.
- the capacitor element CC is provided as appropriate.
- the memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL.
- the wiring GNDL is a wiring that applies a low level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.
- the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
- the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively.
- the transistors M4 to M6 may be OS transistors.
- the memory cell array 1470 can be configured using only n-type transistors.
- the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC.
- the leakage current of the transistor M4 can be very low.
- peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to the above.
- the arrangement or function of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary.
- FIGS. 5 an example of a chip 1200 on which the semiconductor device of one embodiment of the present invention is mounted is described with reference to FIGS.
- a plurality of circuits (systems) are mounted on the chip 1200.
- SoC system on chip
- a chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more. Interface 1215, one or a plurality of network circuits 1216, and the like.
- CPU Central Processing Unit
- GPU Graphics Processing Unit
- Interface 1215 one or a plurality of network circuits 1216, and the like.
- the chip 1200 is provided with bumps (not shown), and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG.
- a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and connected to the motherboard 1203.
- the motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222.
- storage devices such as a DRAM 1221 and a flash memory 1222.
- the DOSRAM described in the above embodiment can be used as the DRAM 1221.
- the NOSRAM described in the above embodiment can be used for the flash memory 1222.
- the CPU 1211 preferably has a plurality of CPU cores.
- the GPU 1212 preferably has a plurality of GPU cores. Further, each of the CPU 1211 and the GPU 1212 may have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. As the memory, the above-described NOSRAM or DOSRAM can be used.
- the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of one embodiment of the present invention or a product-sum operation circuit, image processing and product-sum operation can be performed with low power consumption.
- the wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, After the calculation in the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
- the analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum operation circuit may be provided in the analog operation unit 1213.
- the memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
- the interface 1215 has an interface circuit with external devices such as a display device, a speaker, a microphone, a camera, and a controller.
- the controller includes a mouse, a keyboard, a game controller, and the like.
- USB Universal Serial Bus
- HDMI registered trademark
- High-Definition Multimedia Interface or the like can be used.
- the network circuit 1216 has a network circuit such as a LAN (Local Area Network).
- a network security circuit may be included.
- the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits necessary for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
- the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.
- the GPU module 1204 includes the chip 1200 using the SoC technology, the size of the GPU module 1204 can be reduced. In addition, since it is excellent in image processing, it is preferably used for portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (carry-out) game machines.
- a product-sum operation circuit using the GPU 1212 allows a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (
- DNN deep neural network
- CNN convolutional neural network
- RNN recursive neural network
- DBM deep Boltzmann machine
- the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
- the semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording / playback device, a navigation system, and the like).
- the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
- the semiconductor device described in any of the above embodiments is applied to various types of removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
- FIG. 64 schematically shows some configuration examples of the removable storage device.
- the semiconductor device described in any of the above embodiments is processed into a packaged memory chip and used for various storage devices and removable memories.
- FIG. 64A is a schematic diagram of a USB memory.
- the USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104.
- the substrate 1104 is housed in the housing 1101.
- a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
- the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 or the like of the substrate 1104.
- FIG. 64B is a schematic diagram of the appearance of the SD card
- FIG. 64C is a schematic diagram of the internal structure of the SD card.
- the SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113.
- the substrate 1113 is housed in the housing 1111.
- a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
- a wireless chip having a wireless communication function may be provided on the substrate 1113.
- data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110.
- the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 of the substrate 1113 or the like.
- FIG. 64D is a schematic diagram of the external appearance of the SSD
- FIG. 64E is a schematic diagram of the internal structure of the SSD.
- the SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153.
- the substrate 1153 is housed in the housing 1151.
- a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
- the memory chip 1155 is a work memory of the controller chip 1156.
- a DOSRAM chip may be used.
- the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 or the like of the substrate 1153.
- the semiconductor device can be used for a processor such as a CPU or a GPU, or a chip.
- FIG. 65 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU or a chip according to one embodiment of the present invention.
- the GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices.
- electronic devices include relatively large game machines such as television devices, desktop or notebook personal computers, monitors for computers, digital signage (digital signage), and pachinko machines.
- electronic devices including a screen, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproducing device, and the like can be given.
- artificial intelligence can be mounted on the electronic device.
- the electronic device of one embodiment of the present invention may have an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit.
- the antenna may be used for non-contact power transmission.
- the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).
- the electronic device of one embodiment of the present invention can have various functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication A function, a function of reading a program or data recorded on a recording medium, and the like can be provided.
- FIG. 65 illustrates an example of an electronic device.
- FIG. 65A illustrates a mobile phone (smart phone) which is a kind of information terminal.
- the information terminal 5500 includes a housing 5510 and a display portion 5511. As an input interface, a touch panel is provided in the display portion 5511 and a button is provided in the housing 5510.
- the information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
- an application using artificial intelligence for example, an application for recognizing a conversation and displaying the content of the conversation on the display unit 5511, a character or a figure input by the user on the touch panel provided in the display unit 5511, Examples thereof include an application displayed on the display unit 5511 and an application for performing biometric authentication such as a fingerprint and a voiceprint.
- FIG. 65B shows a desktop information terminal 5300.
- the desktop information terminal 5300 includes an information terminal main body 5301, a display 5302, and a keyboard 5303.
- the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention, similarly to the information terminal 5500 described above.
- Examples of the application using artificial intelligence include design support software, sentence correction software, menu automatic generation software, and the like. Further, by using the desktop information terminal 5300, new artificial intelligence can be developed.
- a smartphone and a desktop information terminal are illustrated as examples of electronic devices in FIGS. 65A and 65B, respectively, but an information terminal other than the smartphone and the desktop information terminal is applied. be able to.
- Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.
- FIG. 65C illustrates an electric refrigerator-freezer 5800 that is an example of an electrical appliance.
- An electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator compartment door 5802, a refrigerator compartment door 5803, and the like.
- an electric refrigerator-freezer 5800 having artificial intelligence can be realized.
- the electric refrigerator-freezer 5800 is stored in the electric refrigerator-freezer 5800, a function for automatically generating menus based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, and the like. It can have a function of automatically adjusting the temperature to the food material.
- an electric refrigerator-freezer has been described as an electrical appliance.
- other electrical appliances include, for example, a vacuum cleaner, microwave oven, microwave oven, rice cooker, water heater, IH cooker, water server, and air conditioner. Examples include appliances, washing machines, dryers, and audiovisual equipment.
- FIG. 65D illustrates a portable game machine 5200 which is an example of a game machine.
- the portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.
- the portable game machine 5200 By applying the GPU or chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. Further, since heat generation from the circuit can be reduced with low power consumption, the influence of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
- the portable game machine 5200 having artificial intelligence can be realized.
- expressions such as the progress of the game, the behavior of the creatures appearing in the game, and the phenomenon occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game machine 5200
- Expressions that are not limited to game programs are possible. For example, it is possible to express that the content that the player asks, the progress of the game, the time, and the behavior of the person appearing on the game change.
- a game player when a game that requires a plurality of players is played on the portable game machine 5200, a game player can be formed artificially by artificial intelligence. Therefore, even if one player is made a game player using artificial intelligence, Can play games.
- FIG. 65D illustrates a portable game machine as an example of a game machine, but a game machine to which the GPU or the chip of one embodiment of the present invention is applied is not limited thereto.
- a game machine to which the GPU or the chip of one embodiment of the present invention is applied for example, a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), and a sports facility are installed. Pitching machine for batting practice.
- the GPU or the chip of one embodiment of the present invention can be applied to an automobile that is a moving body and the vicinity of a driver's seat of the automobile.
- FIG. 65 (E1) shows an automobile 5700 which is an example of a moving body
- FIG. 65 (E2) is a view showing the periphery of the windshield in the interior of the automobile.
- FIG. 65E2 illustrates a display panel 5704 attached to a pillar in addition to the display panel 5701, the display panel 5702, and the display panel 5703 attached to the dashboard.
- Display panels 5701 to 5703 can provide various other information by displaying speedometers, tachometers, travel distances, fuel gauges, gear states, air conditioner settings, and the like.
- the display items, layout, and the like displayed on the display panel can be changed as appropriate according to the user's preference, and the design can be improved.
- the display panels 5701 to 5703 can also be used as lighting devices.
- the field of view (dead angle) blocked by the pillar can be complemented. That is, by displaying an image from an imaging device provided outside the automobile 5700, the blind spot can be compensated for and safety can be improved. Also, by displaying a video that complements the invisible part, it is possible to confirm the safety more naturally and without a sense of incongruity.
- the display panel 5704 can also be used as a lighting device.
- the GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of an automobile 5700. Moreover, the chip can be used in a system for performing road guidance, risk prediction, and the like.
- the display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.
- the automobile is described as an example of the moving body, but the moving body is not limited to the automobile.
- the moving object include a train, a monorail, a ship, and a flying object (helicopter, unmanned aerial vehicle (drone), airplane, rocket).
- the chip of one embodiment of the present invention is applied to these moving objects.
- a system using artificial intelligence can be provided.
- the GPU or the chip of one embodiment of the present invention can be applied to a broadcasting system.
- FIG. 65 (F) schematically shows data transmission in the broadcasting system. Specifically, FIG. 65F shows a route through which a radio wave (broadcast signal) transmitted from the broadcasting station 5680 reaches the television receiver (TV) 5600 in each home.
- the TV 5600 includes a receiving device (not shown), and a broadcast signal received by the antenna 5650 is transmitted to the TV 5600 through the receiving device.
- the antenna 5650 is a UHF (Ultra High Frequency) antenna.
- a BS / 110 ° CS antenna, a CS antenna, or the like can also be applied.
- Radio wave 5675A and radio wave 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 amplifies received radio wave 5675A and transmits radio wave 5675B.
- the terrestrial TV broadcast can be viewed on the TV 5600 by receiving the radio wave 5675B with the antenna 5650.
- the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 65F, and may be satellite broadcasting using an artificial satellite, data broadcasting using an optical line, or the like.
- the above-described broadcasting system may be a broadcasting system using artificial intelligence by applying the chip of one embodiment of the present invention.
- the broadcast data is transmitted from the broadcast station 5680 to the TV 5600 of each home, the broadcast data is compressed by the encoder.
- the decoder of the receiving device included in the TV 5600 stores the broadcast data. Restoration is performed.
- artificial intelligence for example, in motion compensated prediction, which is one of encoder compression methods, a display pattern included in a display image can be recognized.
- intra-frame prediction using artificial intelligence can also be performed. For example, when broadcast data with a low resolution is received and the broadcast data is displayed on the TV 5600 with a high resolution, an image interpolation process such as up-conversion can be performed in the restoration of the broadcast data by the decoder.
- the above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcast data increases.
- a TV 5600 may be provided with a recording device having artificial intelligence.
- a recording device having artificial intelligence By adopting such a configuration, it is possible to automatically record a program that meets the user's preference by causing the recording device to learn the user's preference using artificial intelligence.
- the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, the effect, and the like can be combined with the description of other electronic devices as appropriate.
- a thermal oxide film having a thickness of about 100 nm was formed on a single crystal silicon wafer.
- the thermal oxide film was formed by oxidizing the surface of a single crystal silicon wafer at a temperature of 950 ° C. in an oxygen atmosphere containing 3% by volume of HCl.
- a silicon oxide film having a thickness of about 300 nm was formed on the thermal oxide film by a sputtering method.
- the silicon oxide film was formed using an oxygen gas containing 18 O as a film forming gas.
- an oxide film having a thickness of about 50 nm was formed on the silicon oxide film by a sputtering method.
- the oxide film was formed using an In—Ga—Zn oxide target, a substrate temperature of 200 ° C., and oxygen gas as a deposition gas. By forming the film under such conditions, an oxide film having c-axis aligned crystallinity can be formed.
- heat treatment was performed at 400 ° C. for 1 hour in a nitrogen atmosphere.
- the temperature increase rate from 40 ° C. to 400 ° C. was 7.2 ° C./min
- the temperature decrease rate from 400 ° C. to 40 ° C. was 3.6 ° C./min.
- FIG. 66A shows the diffusion coefficient D of 18 O in the oxide film calculated for the sample A1 and the sample A2. From this result, it was confirmed that the sample A2 was easier to diffuse oxygen than the sample A1.
- FIG. 66B shows the result of the estimated value of the diffusion length of 18 O in the oxide film calculated from FIG. 66A.
- the diffusion length As for the diffusion length, the diffusion length at 400 ° C. was estimated without considering the temperature increase period and the temperature decrease period in the heat treatment.
- FIG. 66B shows a case where the heat treatment time is 1 hour and a case where the heat treatment time is 4 hours, respectively. As shown in FIG. 66B, it was confirmed that the diffusion length of the sample A2 was twice or more than that of the sample A1.
- the ease of oxygen diffusion in the oxide film can be controlled by changing the composition even under the same film formation conditions.
- the composition of the oxide film and the film formation conditions can be selected as appropriate.
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Abstract
Description
本実施の形態では、本発明の一態様に係る積層体について説明する。
図1(A)は、本発明の一態様に係る積層体10の断面図である。図1(A)に示すように、積層体10は、絶縁体11と、導電体15と、絶縁体11と導電体15との間の酸化物13と、を有する。
InGaZnO4結晶における酸素原子の移動の起こりやすさを、酸素の移動経路上の活性化障壁の観点から説明する。
本発明の一態様に係る積層体10及び積層体10Aについて、作製方法を説明する。
以下では、先の実施の形態に示した積層体を適用したトランジスタを有する半導体装置の具体的な構成例について、説明する。
図4(A)、図4(B)及び図4(C)は、本発明の一態様に係るトランジスタ200、およびトランジスタ200周辺の上面図および断面図である。
図9(A)、図9(B)及び図9(C)は、本発明の一態様に係るトランジスタ200A、およびトランジスタ200A周辺の上面図および断面図である。
図13(A)、図13(B)及び図13(C)は、本発明の一態様に係るトランジスタ200B、およびトランジスタ200B周辺の上面図および断面図である。
図16(A)、図16(B)及び図16(C)は、本発明の一態様に係るトランジスタ200C、およびトランジスタ200C周辺の上面図および断面図である。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、SOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、先の実施の形態に示した導電体15に用いることが材料を用いることができる。
酸化物230として、酸化物半導体として機能する金属酸化物(以下、酸化物半導体ともいう)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud−Aligned Composite)−OSの構成について説明する。
酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC−OS(c−axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc−OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
ここでは、金属酸化物に含まれる、弱いZn−O結合について説明し、該結合を構成する酸素原子および亜鉛原子を低減する方法の一例について示す。
図4に示す、本発明の一態様に係るトランジスタ200を有する半導体装置について、作製方法を図17乃至図23を用いて説明する。
先の<半導体装置の作製方法1−1>に示したものとは異なる、本発明の一態様に係るトランジスタ200を有する半導体装置の作製方法について、図24乃至図26を用いて説明する。
図9に示す、本発明の一態様に係るトランジスタ200Aを有する半導体装置について、作製方法を図27乃至図34を用いて説明する。
先の<半導体装置の作製方法2−1>に示したものとは異なる、本発明の一態様に係るトランジスタ200Aを有する半導体装置の作製方法について、図35乃至図37を用いて説明する。
図13に示す、本発明の一態様に係るトランジスタ200Bを有する半導体装置について、作製方法を図38乃至図46を用いて説明する。
先の<半導体装置の作製方法3−1>に示したものとは異なる、本発明の一態様に係るトランジスタ200Bを有する半導体装置の作製方法について、図47乃至図49を用いて説明する。
図16に示す、本発明の一態様に係るトランジスタ200Cを有する半導体装置について、作製方法を図50乃至図54を用いて説明する。
本実施の形態では、半導体装置の一形態を、図55乃至図60を用いて説明する。
本発明の一態様であるトランジスタを使用した、半導体装置(記憶装置)の一例を図55乃至図57に示す。
トランジスタ300は、基板311上に設けられ、ゲート電極として機能する導電体316、ゲート絶縁体として機能する絶縁体315、基板311の一部からなる半導体領域313、およびソース領域またはドレイン領域として機能する低抵抗領域314a、および低抵抗領域314bを有する。トランジスタ300は、pチャネル型、あるいはnチャネル型のいずれでもよい。
容量素子100は、トランジスタ200の上方に設けられる。容量素子100は、第1の電極として機能する導電体110と、第2の電極として機能する導電体120、および誘電体として機能する絶縁体130とを有する。
各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線としての機能を有する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。
なお、トランジスタ200に、酸化物半導体を用いる場合、酸化物半導体の近傍に過剰酸素領域を有する絶縁体が設けることがある。その場合、該過剰酸素領域を有する絶縁体と、該過剰酸素領域を有する絶縁体に設ける導電体との間に、バリア性を有する絶縁体を設けることが好ましい。
本発明の一態様である半導体装置を使用した、記憶装置の一例を図58乃至図60に示す。
トランジスタ400は、トランジスタ200と、同じ層に形成されており、並行して作製することができるトランジスタである。トランジスタ400は、第1のゲート電極として機能する導電体460(導電体460a、および導電体460b)と、第2のゲート電極として機能する導電体405と、ゲート絶縁層として機能する絶縁体222、絶縁体224、および絶縁体450と、チャネルが形成される領域を有する酸化物430cと、ソースまたはドレインの一方として機能する層453a、酸化物431a、および酸化物431bと、ソースまたはドレインの他方として機能する層453b、酸化物432a、および酸化物432bと、導電体440(導電体440a、および導電体440b)と、を有する。
以下では、大面積基板を半導体素子ごとに分断することによって、複数の半導体装置をチップ状で取り出す場合に設けられるダイシングライン(スクライブライン、分断ライン、又は切断ラインと呼ぶ場合がある)について説明する。分断方法としては、例えば、まず、基板に半導体素子を分断するための溝(ダイシングライン)を形成した後、ダイシングラインにおいて切断し、複数の半導体装置に分断(分割)する場合がある。
本実施の形態では、図61及び図62を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ場合がある。)、および容量素子が適用されている記憶装置(以下、OSメモリ装置と呼ぶ場合がある。)について説明する。OSメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するOSトランジスタを有する記憶装置である。OSトランジスタのオフ電流は極めて小さいので、OSメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。
図61(A)にOSメモリ装置の構成の一例を示す。記憶装置1400は、周辺回路1411、およびメモリセルアレイ1470を有する。周辺回路1411は、行回路1420、列回路1430、出力回路1440、コントロールロジック回路1460を有する。
図62(A)乃至図62(C)に、DRAMのメモリセルの回路構成例を示す。本明細書等において、1OSトランジスタ1容量素子型のメモリセルを用いたDRAMを、DOSRAM(Dynamic Oxide Semiconductor Random Access Memory)と呼ぶ場合がある。図62(A)に示す、メモリセル1471は、トランジスタM1と、容量素子CAと、を有する。なお、トランジスタM1は、ゲート(フロントゲートと呼ぶ場合がある。)、及びバックゲートを有する。
図62(D)乃至図62(H)に、2トランジスタ1容量素子のゲインセル型のメモリセルの回路構成例を示す。図62(D)に示す、メモリセル1474は、トランジスタM2と、トランジスタM3と、容量素子CBと、を有する。なお、トランジスタM2は、フロントゲート(単にゲートと呼ぶ場合がある。)、及びバックゲートを有する。本明細書等において、トランジスタM2にOSトランジスタを用いたゲインセル型のメモリセルを有する記憶装置を、NOSRAM(Nonvolatile Oxide Semiconductor RAM)と呼ぶ場合がある。
本実施の形態では、図63を用いて、本発明の一態様の半導体装置が実装されたチップ1200の一例を示す。チップ1200には、複数の回路(システム)が実装されている。このように、複数の回路(システム)を一つのチップに集積する技術を、システムオンチップ(System on Chip:SoC)と呼ぶ場合がある。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータや、ノート型のコンピュータや、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード(例えば、SDカード)、USBメモリ、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用される。図64にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。
本発明の一態様に係る半導体装置は、CPUやGPUなどのプロセッサ、またはチップに用いることができる。図65に、本発明の一態様に係るCPUやGPUなどのプロセッサ、またはチップを備えた電子機器の具体例を示す。
本発明の一態様に係るGPU又はチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型もしくはノート型のパーソナルコンピュータ、コンピュータ用などのモニタ、デジタルサイネージ(Digital Signage:電子看板)、パチンコ機などの大型ゲーム機などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係る集積回路又はチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。
図65(A)には、情報端末の一種である携帯電話(スマートフォン)が図示されている。情報端末5500は、筐体5510と、表示部5511と、を有しており、入力用インターフェースとして、タッチパネルが表示部5511に備えられ、ボタンが筐体5510に備えられている。
図65(B)には、デスクトップ型情報端末5300が図示されている。デスクトップ型情報端末5300は、情報端末の本体5301と、ディスプレイ5302と、キーボード5303と、を有する。
図65(C)は、電化製品の一例である電気冷凍冷蔵庫5800を示している。電気冷凍冷蔵庫5800は、筐体5801、冷蔵室用扉5802、冷凍室用扉5803等を有する。
本発明の一態様のGPU又はチップは、移動体である自動車、及び自動車の運転席周辺に適用することができる。
本発明の一態様のGPU又はチップは、放送システムに適用することができる。
まず、単結晶シリコンウェハ上に、厚さ約100nmの熱酸化膜を形成した。熱酸化膜は、3体積%のHClを含む酸素雰囲気にて、950℃の温度で単結晶シリコンウェハの表面を酸化させることで形成した。
続いて、試料A1及び試料A2について、二次イオン質量分析法(SIMS:Secondary Ion Mass Spectrometry)を用いて、酸化物膜中の18Oの深さ方向のプロファイルを測定し、その結果から18Oの拡散係数Dを算出した。なお、拡散係数Dは、上記熱処理の履歴を考慮して計算した。
Claims (12)
- 第1の酸化物と、第2の酸化物と、第3の酸化物と、第1の絶縁体と、第2の絶縁体と、第1の導電体と、第2の導電体と、第3の導電体と、を有し、
前記第1の酸化物は、前記第1の導電体の下面と接し、
前記第1の絶縁体は、前記第1の酸化物の下面と接し、
前記第2の酸化物は、前記第1の絶縁体の下面と接し、
前記第3の酸化物は、前記第2の酸化物の下面と接し、
前記第1の酸化物は、c軸配向した第1の結晶領域を有し、
前記第1の結晶領域のc軸は、前記第1の絶縁体側の前記第1の酸化物の面と概略垂直であり、
前記第2の酸化物は、c軸配向した第2の結晶領域を有し、
前記第2の結晶領域のc軸は、前記第1の絶縁体側の前記第2の酸化物の面と概略垂直であり、
前記第2の絶縁体は、前記第3の酸化物の上方に位置し、
前記第2の絶縁体は、前記第2の酸化物の端部と接し、
前記第2の導電体及び前記第3の導電体は、前記第3の酸化物上で前記第2の酸化物を介して対向して位置する半導体装置。 - 請求項1において、
さらに開口を有する第3の絶縁体を有し、
前記第3の絶縁体は、前記第2の酸化物の下面の一部、前記第2の導電体の上面の一部及び側面、前記第3の導電体の上面の一部及び側面、ならびに前記第3の酸化物の側面と接し、
前記開口を介して、前記第2の酸化物と前記第3の酸化物が接する半導体装置。 - 第1の酸化物と、第2の酸化物と、第3の酸化物と、第1の絶縁体と、第2の絶縁体と、第1の導電体と、を有し、
前記第1の酸化物は、前記第1の導電体の下面と接し、
前記第1の絶縁体は、前記第1の酸化物の下面と接し、
前記第2の酸化物は、前記第1の絶縁体の下面と接し、
前記第3の酸化物は、前記第2の酸化物の下面と接し、
前記第1の酸化物は、c軸配向した第1の結晶領域を有し、
前記第1の結晶領域のc軸は、前記第1の絶縁体側の前記第1の酸化物の面と概略垂直であり、
前記第2の酸化物は、c軸配向した第2の結晶領域を有し、
前記第2の結晶領域のc軸は、前記第1の絶縁体側の前記第2の酸化物の面と概略垂直であり、
前記第2の絶縁体は、前記第3の酸化物の上方に位置し、
前記第2の絶縁体は、前記第2の酸化物の端部と接し、
前記第3の酸化物は、第1の領域と、前記第1の領域を挟む第2の領域及び第3の領域と、を有し、
前記第1の領域は、前記第1の導電体と重なる領域を有し、
前記第2の領域及び前記第3の領域は、リン、ホウ素、アルミニウムまたはマグネシウムから選ばれる一以上を有する半導体装置。 - 請求項3において、
さらに開口を有する第3の絶縁体を有し、
前記第3の絶縁体は、前記第2の酸化物の下面の一部、ならびに前記第3の酸化物の上面の一部及び側面と接し、
前記開口を介して、前記第2の酸化物と前記第3の酸化物が接する半導体装置。 - 第1の酸化物と、第2の酸化物と、第3の酸化物と、第1の絶縁体と、導電体と、を有し、
前記第1の酸化物は、前記導電体の側面及び下面を覆い、
前記第1の絶縁体は、前記第1の酸化物の側面及び下面を覆い、
前記第2の酸化物は、前記第1の絶縁体の側面及び下面を覆い、
前記第3の酸化物は、前記第2の酸化物の下面と接し、
前記第1の酸化物は、c軸配向した第1の結晶領域を有し、
前記第1の結晶領域のc軸は、前記第1の絶縁体側の前記第1の酸化物の面と概略垂直である半導体装置。 - 請求項5において、
前記第3の酸化物は、第1の領域と、前記第1の領域を挟む第2の領域及び第3の領域と、を有し、
前記第1の領域は、前記導電体と重なる領域を有し、
前記第2の領域及び前記第3の領域は、リン、ホウ素、アルミニウムまたはマグネシウムから選ばれる一以上を有する半導体装置。 - 第1の酸化物と、第2の酸化物と、第3の酸化物と、第1の絶縁体と、第1の導電体と、第2の導電体と、第3の導電体と、を有し、
前記第1の酸化物は、前記第1の導電体の側面及び下面を覆い、
前記第1の絶縁体は、前記第1の酸化物の側面及び下面を覆い、
前記第2の酸化物は、前記第1の絶縁体の側面及び下面を覆い、
前記第3の酸化物は、前記第2の酸化物の下面と接し、
前記第1の酸化物は、c軸配向した第1の結晶領域を有し、
前記第1の結晶領域のc軸は、前記第1の絶縁体側の前記第1の酸化物の面と概略垂直であり、
前記第2の導電体及び前記第3の導電体は、前記第3の酸化物上で前記第2の酸化物を介して対向して位置する半導体装置。 - 請求項5乃至請求項7のいずれか一において、
前記第2の酸化物は、c軸配向した第2の結晶領域を有し、
前記第2の結晶領域のc軸は、前記第1の絶縁体側の前記第2の酸化物の面と概略垂直である半導体装置。 - 請求項8において、
前記第3の酸化物は、c軸配向した第3の結晶領域を有し、
前記第2の結晶領域は、前記第3の結晶領域のc軸と異なる方向にc軸を有する半導体装置。 - 請求項9において、
前記第1の結晶領域は、前記第3の結晶領域のc軸と異なる方向にc軸を有する半導体装置。 - 絶縁体と、導電体と、前記絶縁体と前記導電体との間の第1の酸化物と、を有し、
前記第1の酸化物は、c軸配向した第1の結晶領域を有し、
前記第1の結晶領域のc軸は、前記絶縁体側の前記第1の酸化物の面と概略垂直である積層体。 - 絶縁体と、導電体と、前記絶縁体と前記導電体との間の第1の酸化物と、前記絶縁体をはさんで前記第1の酸化物と対向する第2の酸化物と、を有し、
前記第1の酸化物は、c軸配向した第1の結晶領域を有し、
前記第1の結晶領域のc軸は、前記絶縁体側の前記第1の酸化物の面と概略垂直であり、
前記第2の酸化物は、c軸配向した第2の結晶領域を有し、
前記第2の結晶領域のc軸は、前記絶縁体側の前記第2の酸化物の面と概略垂直である積層体。
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