WO2023040193A1 - 半导体结构、存储器及裂纹测试方法 - Google Patents

半导体结构、存储器及裂纹测试方法 Download PDF

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Publication number
WO2023040193A1
WO2023040193A1 PCT/CN2022/077073 CN2022077073W WO2023040193A1 WO 2023040193 A1 WO2023040193 A1 WO 2023040193A1 CN 2022077073 W CN2022077073 W CN 2022077073W WO 2023040193 A1 WO2023040193 A1 WO 2023040193A1
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test ring
test
tsv
contact
ring
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PCT/CN2022/077073
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English (en)
French (fr)
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吴双双
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长鑫存储技术有限公司
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Priority to US17/810,588 priority Critical patent/US20230077851A1/en
Publication of WO2023040193A1 publication Critical patent/WO2023040193A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

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  • the present disclosure relates to the technical field of semiconductors, and relates to but not limited to a semiconductor structure, a memory and a crack testing method.
  • TSV Through Silicon Via
  • the TSV runs through the entire wafer, the TSV will affect the structures disposed on the wafer and located near the TSV, and may reduce the performance of the formed device. Moreover, there is currently no effective way to test the impact of TSVs on nearby structures.
  • the embodiments of the present disclosure provide a semiconductor structure, a memory and a crack testing method.
  • a semiconductor structure comprising:
  • a conductive first test ring and a conductive second test ring are both disposed around the TSV and are electrically insulated from the TSV;
  • a first dielectric layer located between the first test ring and the second test ring, for electrically isolating the first test ring and the second test ring;
  • the first connection layer is located in the first dielectric layer and electrically connects the first test ring and the second test ring.
  • the protection structure also includes:
  • a conductive third test ring vertically penetrates the substrate, is arranged around the TSV, and is located between the second test ring and the TSV, and the end of the third test ring includes third contact;
  • a second connection layer located between the second test ring and the third test ring, electrically connects the second test ring and the third test ring; wherein, in a direction perpendicular to the substrate, The second connection layer is located between the third contact and the first connection layer.
  • the protection structure includes N third test rings and N second connection layers; wherein, the 1st third test ring to the (N-1)th said The third test ring is located between the second test ring and the Nth third test ring, where N is a positive integer greater than 1;
  • the first second connection layer is electrically connected to the second test ring and the first third test ring;
  • the Kth second connection layer is electrically connected to the Kth third test ring and the (K+1)th third test ring; wherein, K is a positive integer less than N.
  • the first connection layer is electrically connected to the first test ring, the second test ring and the third test ring.
  • the cross-sectional shape of the first test ring includes: a regular polygon or a circular ring;
  • the cross-sectional shape of the second test ring includes: a regular polygon or a circular ring; wherein, the center of symmetry of the cross-sectional shape of the first test ring coincides with the center of symmetry of the cross-sectional shape of the second test ring;
  • the cross-sectional center of the TSV covers the symmetrical center of the first test ring cross-sectional shape.
  • a memory including:
  • the base includes a substrate and an insulating layer covering the substrate;
  • the storage element is arranged in the insulating layer.
  • the memory also includes:
  • the interconnection structure and the protection structure are formed simultaneously.
  • the memory also includes:
  • One end of the protection structure is electrically connected to the gate of the transistor, and the other end of the protection structure is used to receive an external electrical signal.
  • the other end of the protection structure is grounded.
  • the substrate includes:
  • the dicing line is located between two adjacent memory chip regions
  • a plurality of the semiconductor structures are equidistantly arranged in the scribe line.
  • a crack test method which is applied to test the semiconductor structure according to any one of the first aspects of the embodiments of the present disclosure, the crack test method comprising:
  • the first electrical parameter indicates that the first path is not conducted, it is determined that a crack occurs in the TSV.
  • the protection structure further includes a conductive third test ring and a second connection layer, and the second connection layer electrically connects the second test ring and the third test ring;
  • the crack test method also includes:
  • the first electrical parameter indicates that the first path is not conducted, it is determined that a crack occurs in a first region relatively close to the first connection layer in the TSV;
  • the second electrical parameter indicates that the second path is not conducted, it is determined that the TSV has a crack in a second region relatively close to the second connection layer.
  • the protection structure further includes a conductive third test ring and a second connection layer, and the first connection layer electrically connects the first test ring, the second test ring and the third test ring. test ring;
  • the crack test method also includes:
  • the first electrical parameter indicates that the first path is not conducting
  • the second electrical parameter indicates that the second path is conducting
  • the first electrical parameter indicates that the first path is conducting
  • the second electrical parameter indicates that the second path is not conducting
  • the first electrical parameter and the second electrical parameter include at least one of the following: resistance; current; voltage difference.
  • the protection structure can play a role of locally releasing stress on the through-silicon via.
  • the protection structure can also play the role of isolating stress.
  • the protection structure can isolate the stress transmission between the TSV and the surrounding structure of the protection structure, and reduce the stress interaction between the TSV and the surrounding structure. Influenced by the TSV and the surrounding structure, it plays a certain protective role, which is beneficial to ensure that the quality of the formed device is better.
  • the conductive first test ring and the second test ring in the protective structure are both electrically insulated from the TSV, and the first connection layer in the first dielectric layer is electrically connected to the first test ring and the second test ring , by providing a first electrical signal to the first contact at the end of the first test ring and the second contact at the end of the second test ring, it can be determined which part of the protection structure is electrically connected to the first contact and the second contact.
  • the first electrical parameter of the first path, and according to the first electrical parameter it is determined whether a crack occurs in the TSV, and the measurement method is simple and fast.
  • first test ring and the second test ring included in the protective structure are electrically conductive, when the first test ring and the second test ring are grounded, the first test ring and the second test ring can also connect the TSVs. Conduct electromagnetic shielding.
  • Fig. 1a is a top view of a semiconductor structure according to an exemplary embodiment
  • Fig. 1b is a schematic partial cross-sectional view of a semiconductor structure according to an exemplary embodiment
  • Fig. 2a is a top view of another semiconductor structure according to an exemplary embodiment
  • Fig. 2b is a schematic partial cross-sectional view of another semiconductor structure according to an exemplary embodiment
  • Fig. 3 is a schematic diagram of a memory according to an exemplary embodiment
  • Fig. 4 is a flowchart of a crack testing method according to an exemplary embodiment
  • Fig. 5 is a schematic diagram of a crack testing method according to an exemplary embodiment
  • Figure 6a and Figure 6b are schematic diagrams showing another crack testing method according to an exemplary embodiment
  • Fig. 7a and Fig. 7b are schematic diagrams showing another crack testing method according to an exemplary embodiment
  • Fig. 8 is a schematic diagram showing another crack testing method according to an exemplary embodiment.
  • the term "A is connected to B" includes the situation that A and B are connected to each other and A and B are in contact with each other, or there are other components interposed between A and B and A is connected to each other in a non-contact manner. The case where B is connected.
  • the term "layer" refers to a portion of material comprising a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure.
  • a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of the continuous structure.
  • Layers may extend horizontally, vertically and/or along sloped surfaces.
  • Layers can include multiple sublayers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • through-silicon vias can be set through the substrate to realize the electrical connection between the upper and lower chips.
  • the through-silicon vias are filled with conductive metals, such as metal copper or metal tungsten.
  • the stress and electric field generated by the TSV will adversely affect the performance of devices disposed near the TSV, especially when the size of the TSV is large.
  • the TSV filled with copper when the temperature of the silicon substrate changes, due to the thermal expansion coefficient mismatch between the silicon substrate and copper, it is easy to cause the TSV to affect the surrounding silicon substrate.
  • tensile or compressive stress The magnitude of the tensile stress or compressive stress is inversely proportional to the distance from the TSV, and the tensile stress or compressive stress will make at least some structures of the devices (for example, MOS transistors) disposed around the TSV
  • the lattice constant of the channel region changes, thereby changing the mobility of carriers and adversely affecting the electrical properties of the device.
  • the conductive material included in the TSVs may diffuse through the cracks, and even the TSVs may diffuse through the cracks to electrically connect with the surrounding devices. In this case, the memory will be short-circuited and the quality and reliability of the memory will be reduced.
  • an embodiment of the present disclosure provides a semiconductor structure 100 .
  • the semiconductor structure 100 includes:
  • TSV 110 penetrating through substrate 120 ;
  • Protective structure 130 comprising:
  • the conductive first test ring 131 and the conductive second test ring 132 are arranged around the TSV 110 and are electrically insulated from the TSV 110 ;
  • the first dielectric layer 133 is located between the first test ring 131 and the second test ring 132, and is used for electrically isolating the first test ring 131 and the second test ring 132;
  • the first connection layer 134 is located in the first dielectric layer 133 and is electrically connected to the first test ring 131 and the second test ring 132 .
  • the TSV 110 may penetrate the substrate 120 along a first direction.
  • the first direction may include a direction parallel to the Z axis.
  • the constituent material of the TSV 110 may include a conductive material, such as copper or tungsten.
  • the constituent material of the TSV 110 further includes a barrier layer disposed between the conductive material and the substrate 120 for blocking the diffusion of the conductive material to the substrate 120 .
  • the constituent materials of the barrier layer may include metal nitrides, such as titanium nitride and/or tantalum nitride.
  • the constituent materials of the barrier layer may also include oxides, such as silicon oxide and/or silicon oxynitride.
  • the constituent material of the base 120 may include: a semiconductor substrate, and the constituent material of the semiconductor substrate may include: silicon, silicon-on-insulator (SOI) or silicon-on-insulator (SSOI) and the like. As shown in FIG. 1b, an active area (Active Area, AA) can be defined on the semiconductor substrate.
  • an active area Active Area, AA
  • the constituent materials of the substrate 120 may also include: dielectric materials, for example, silicon dioxide or tetraethyl orthosilicate (TEOS) and the like.
  • dielectric materials for example, silicon dioxide or tetraethyl orthosilicate (TEOS) and the like.
  • composition material of the first test ring 131 and the composition material of the second test ring 132 may be the same.
  • the constituent materials of the first test ring 131 and the second test ring 132 may include: copper or tungsten.
  • the end of the first test ring 131 may include: a first contact 1311 for receiving an electrical signal applied to the first test ring 131 .
  • An end of the second test ring 132 may include: a second contact 1321 for receiving an electrical signal applied to the second test ring 132 .
  • the second test ring 132 may be disposed between the first test ring 131 and the TSV 110 . It should be emphasized that there is a certain gap between the second test ring 132 and the TSV 110 , and the gap is filled with a dielectric material to electrically isolate the second test ring 132 and the TSV 110 .
  • the crack when a crack occurs between the TSV 110 and the protective structure 130 due to stress or the like, the crack may be along the first direction, the second direction or the third direction.
  • the second direction may include a direction parallel to the X-axis
  • the third direction may include a direction parallel to the Y-axis.
  • the second test ring 132 can prevent the crack from further extending along the second test ring 132. direction or the third direction, so that the protective structure 130 can control the crack near the TSV 110 in the area between the protective structure 130 and the TSV 110, and reduce the crack further away from the TSV to the protective structure 130
  • the protection structure 130 can also prevent cracks generated from outside the TSV 110 from extending to the TSV 110 , that is, the protection structure 130 also plays a role of stress protection for the TSV 110 .
  • the cross-sectional shape of the protective structure 130 is a closed figure (for example, rectangle, octagon, dodecagon, ellipse or circle, etc.), and the first test ring 131 and the second test ring 132 are also closed figures, the TSV 110 is completely surrounded by the first test ring 131, and the TSV 110 is completely surrounded by the second test ring 132, so that the protective structure 130 can It plays a better role in stress protection, and crack detection can be performed in all directions around the TSV 110 in the plane, which is beneficial to improve the comprehensiveness and accuracy of crack detection.
  • the constituent material of the first dielectric layer 133 may include a material with a low dielectric constant, for example, silicon dioxide or tetraethyl orthosilicate, and the like.
  • the constituent material of the first connection layer 134 is a conductive material, which may include a conductive metal, such as copper or tungsten. Referring to FIG. 1b, the first connection layer 134 may be substantially parallel to the plane where the substrate 120 is located. In some embodiments, the first connection layer 134 may also have a certain angle with the substrate 120 .
  • the protection structure 130 can locally release the stress of the TSV 110 .
  • the protection structure 130 can also play a role of isolating stress.
  • the protection structure 130 can isolate the stress transmission between the TSV 110 and the surrounding structures of the protection structure 130, reducing the stress between the TSV 110 and the surrounding structures. The stresses among them interact with each other, and play a certain protective role for the TSV 110 and the surrounding structure, which is beneficial to ensure that the quality of the formed device is better.
  • the conductive first test ring 131 and the second test ring 132 in the protection structure 130 are electrically insulated from the TSV 110 through the dielectric material, and the first connection layer 134 located in the first dielectric layer 133 is electrically connected to The first test ring 131 and the second test ring 132 can provide a first electrical signal to the first contact 1311 at the end of the first test ring 131 and the second contact 1321 at the end of the second test ring 132 to determine the protection
  • the first electrical parameter of the first path electrically connected to the first contact 1311 and the second contact 1321 in the structure 130, and determine whether there is a crack in the TSV 110 according to the first electrical parameter, so as to realize stress detection (that is, crack detection), the measurement method is simple and quick.
  • first test ring 131 and the second test ring 132 included in the protective structure 130 are electrically conductive, when the first test ring 131 and the second test ring 132 are grounded, the first test ring 131 and the second test ring 132 Electromagnetic shielding can also be performed on the TSV 110 .
  • the protection structure 130 further includes:
  • the conductive third test ring 135 vertically penetrates the substrate 120, is arranged around the TSV 110, and is located between the second test ring 132 and the TSV 110, and the end of the third test ring 135 includes a third contact 1351;
  • the second connection layer 136 located between the second test ring 132 and the third test ring 135, electrically connects the second test ring 132 and the third test ring 135; wherein, in the direction perpendicular to the substrate 120, the second connection layer 136 is located between the third contact 1351 and the first connection layer 134 .
  • the constituent material of the third test ring 135 may include: copper or tungsten.
  • the third contact 1351 is used for receiving the electrical signal applied to the third test ring 135 .
  • the third contact 1351, the first contact 1311, and the second contact 1321 can use the same material, such as aluminum, for example.
  • the composition material of the second connection layer 136 is a conductive material, which may include a conductive metal, such as copper or tungsten. Referring to FIG. 2b, the second connection layer 136 may be substantially parallel to the plane where the substrate 120 is located. In some embodiments, the second connection layer 136 may also have a certain angle with the substrate 120 . It can be understood that, in the direction perpendicular to the substrate 120, the second connection layer 136 only needs to be disposed between the plane where the third contact 1351 is located and the plane where the first connection layer 134 is located.
  • a second dielectric layer (not shown in the figure) may also be provided between the third test ring 135 and the second test ring 132 for electrically isolating the third test ring 135 and the second test ring 132 .
  • the composition material of the second dielectric layer may be the same as that of the first dielectric layer 133 .
  • the second connection layer 136 is located in the second dielectric layer. It should be emphasized that the second test ring 132 is electrically connected to the third test ring 135 through the second connection layer 136 .
  • the first connection layer 134 electrically connects the first test ring 131 , the second test ring 132 and the third test ring 135 .
  • the first connection layer 134 only electrically connects the first test ring 131 and the second test ring 132 , but cannot electrically connect the second test ring 132 and the third test ring 135 .
  • the protection structure 130 includes N third test rings 135 and N second connection layers 136; wherein, the 1st third test ring 135 to the (N-1)th third test ring 135, Located between the second test ring 132 and the Nth third test ring 135, N is a positive integer greater than 1;
  • the first second connection layer 136 is electrically connected to the second test ring 132 and the first third test ring 135;
  • the Kth second connection layer 136 is electrically connected to the Kth third test ring 135 and the (K+1)th third test ring 135 ; wherein, K is a positive integer less than N.
  • the number of third test rings 135 and second connection layers 136 are, the larger the area occupied by the protective structure 130 will be. Therefore, the number of third test rings 135 can be determined according to actual needs. And the setting quantity of the second connection layer 136 .
  • the analysis can be performed layer by layer to determine which two adjacent second connection layers 136 the crack exists between. And/or, determining whether a crack exists between the first connecting layer 134 and the nearest adjacent second connecting layer 136 is beneficial to further accurately locate the location of the crack and further improve the accuracy of crack detection.
  • the cross-sectional shape of the first test ring 131 includes: a regular polygon or a circular ring;
  • the cross-sectional shape of the second test ring 132 includes: a regular polygon or a circular ring; wherein, the center of symmetry of the cross-sectional shape of the first test ring 131 coincides with the center of symmetry of the cross-sectional shape of the second test ring 132;
  • the cross-sectional center of the TSV 110 covers the symmetrical center of the cross-sectional shape of the first test ring 131 .
  • the cross-sectional shape of the first test ring 131 when the cross-sectional shape of the first test ring 131 is a regular polygon and the cross-sectional shape of the second test ring 132 is also a regular polygon, the cross-sectional shape of the first test ring 131
  • the cross-sectional shape of the second test ring 132 may be different or different.
  • the cross-sectional shape of the first test ring 131 may be a square
  • the cross-sectional shape of the second test ring 132 may be an equilateral triangle, square, regular hexagon, regular octagon, regular dodecagon, or circle.
  • the cross-sectional shape of the first test ring 131 is the same as that of the second test ring 132 . Since the center of symmetry of the cross-sectional shape of the first test ring 131 coincides with the center of symmetry of the cross-sectional shape of the second test ring 132 , the distances between the first test ring 131 and the second test ring 132 are the same everywhere.
  • the cross-sectional shape of the TSV 110 may include a circle, a square, or a rectangle.
  • the TSV 110 is cylindrical, and in a direction parallel to the plane of the substrate 120, the cross-sectional shape of the TSV 110 is circular, so that the difficulty of forming the through hole by etching can be reduced, and the direction to the substrate 120 can be reduced. It is difficult to fill the via hole with conductive material to form the TSV 110 .
  • the cross-sectional center of the TSV 110 covers the symmetrical center of the cross-sectional shape of the first test ring 131, that is, the cross-sectional center of the TSV 110 and the cross-sectional shape of the first test ring 131
  • the symmetrical centers are overlapped, so that the layout of the protection structure 130 can be optimized, and the occupation of the area of the substrate 120 by the protection structure 130 can be reduced.
  • the cross-sectional shape of the third test ring 135 in a direction parallel to the plane where the base 120 is located, includes: a regular polygon or a circular ring; wherein, the center of symmetry of the cross-sectional shape of the third test ring 135 is the same as that of the second test ring.
  • the center of symmetry of the cross-sectional shape of TSV 132 is coincident, and the center of cross-section of the TSV 110 is coincident with the center of symmetry of the cross-sectional shape of the third test ring 135 .
  • the cross-sectional shape of the third test ring 135 may be different from the cross-sectional shape of the first test ring 131 and/or the cross-sectional shape of the second test ring 132 . It should be emphasized that, in the direction parallel to the plane where the substrate 120 is located, the cross-sectional shape of the third test ring 135 has no intersection point with the cross-sectional shape of the first test ring 131, and the cross-sectional shape of the third test ring 135 and the second test ring 132 The cross-sectional shape of has no intersection points.
  • the cross-sectional shape of the first test ring 131, the cross-sectional shape of the second test ring 132 and the cross-sectional shape of the third test ring 135 are the same, and the first test ring 131, the second test ring
  • the centers of symmetry of the test ring 132 and the third test ring 135 coincide, so that the distances between the third test ring 135 and the first test ring 131 are the same, and the distances between the third test ring 135 and the second test ring 132 are the same. The distance is the same.
  • Fig. 3 is a schematic diagram of a memory 200 according to an exemplary embodiment.
  • the memory 200 includes:
  • a semiconductor structure 100 wherein the base 120 includes a substrate 121 and an insulating layer 122 covering the substrate 121;
  • the storage element 210 is disposed in the insulating layer 122 .
  • the memory 200 includes, but is not limited to: Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), three-dimensional NAND memory, or phase change memory.
  • DRAM Dynamic Random Access Memory
  • three-dimensional NAND memory three-dimensional NAND memory
  • phase change memory phase change memory
  • the TSV 110 in the semiconductor structure 100 can electrically connect functional structures disposed on both sides of the substrate 120 , and/or the TSV 110 in the semiconductor structure 100 can be used for crack testing.
  • the semiconductor structure 100 is a test structure, and the TSV 110 therein does not serve as an electrical connection function structure.
  • the storage element 210 is disposed outside the protection structure 130 away from the TSV 110 , and the protection structure 130 is located between the storage element 210 and the TSV 110 .
  • the protection structure 130 in the semiconductor structure 100 can play a role of locally releasing stress on the through-silicon via 110 .
  • the protective structure 130 can also play a role of isolating stress.
  • the protective structure 130 can isolate the stress transmission between the TSV 110 and the surrounding structure (for example, the storage element 210 ) of the protective structure 130, reducing the stress transmission between
  • the stress interaction between the through hole 110 and the surrounding structure plays a certain protective role for the TSV 110 and the surrounding structure, which is beneficial to ensure the quality of the memory 200 is better.
  • the conductive first test ring 131 and the second test ring 132 in the protection structure 130 are both electrically insulated from the TSV 110 , and the first connection layer 134 located in the first dielectric layer 133 is electrically connected to the first The test ring 131 and the second test ring 132 can determine the protection structure 130 by providing the first electrical signal to the first contact 1311 at the end of the first test ring 131 and the second contact 1321 at the end of the second test ring 132.
  • the first electrical parameter of the first path electrically connected to the first contact 1311 and the second contact 1321 in the middle, and determine whether there is a crack in the TSV 110 according to the first electrical parameter, the measurement method is simple and fast.
  • the memory 200 may also include other preset structures that have the same structure as the semiconductor structure 100 and are used for electrically connecting stacked structures, The preset structure and the test semiconductor structure 100 can be formed simultaneously, so that the quality of the preset structure can be reflected according to the test result of the test semiconductor structure 100 . Further, according to the test result of the semiconductor structure 100 as the test, the subsequent manufacturing process of the preset structure can be adjusted to improve the quality of the formed preset structure, thereby improving the quality of the memory 200 .
  • the protection structure 130 can also conduct TSV.
  • the hole 110 performs electromagnetic shielding.
  • memory 200 also includes:
  • the interconnection structure and the protection structure 130 are formed simultaneously.
  • the conductive interconnection structure may include: a stacked first conductive contact (PC), an initial metal layer (M0), a second conductive contact (CT), a first metal layer (M1), a first conductive A via (V1), a second metal layer (M2), a second conductive via (V2), and a third metal layer (M3).
  • the first test ring 131 may include a first conductive contact, a second conductive contact, a first metal layer, a first conductive via, a second metal layer, a second The conductive vias and the third metal layer (namely the first contact 1311), the second test ring 132 may include the first conductive contact, the second conductive contact, the first metal layer, the first conductive via, the second The second metal layer, the second conductive via, and the third metal layer (ie, the second contact 1321 ).
  • the interconnection structure, the same structures in the first test ring 131 and the second test ring 132 are formed at the same time.
  • the first conductive contact in the interconnection structure, the first conductive contact in the first test ring 131 and the first conductive contact in the second test ring 132 are formed simultaneously
  • the second conductive contact in the interconnection structure, the first The second conductive contact in the test ring 131 and the second conductive contact in the second test ring 132 are formed simultaneously, the first metal layer in the interconnection structure, the first metal layer in the first test ring 131 and the second test ring
  • the first metal layer in 132 is formed at the same time, and by analogy, the third metal layer in the interconnection structure, the third metal layer in the first test ring 131 and the third metal layer in the second test ring 132 are formed at the same time.
  • the first connection layer 134 may be formed simultaneously with the initial metal layer in the interconnect structure.
  • one end of the first connection layer 134 may be disposed between the first conductive contact and the second conductive contact of the first test ring 131; the other end of the first connection layer 134 may be disposed Between the first conductive contact and the second conductive contact of the second test ring 132 .
  • the first conductive contact of the first test ring 131 is in direct contact with the second conductive contact
  • the first conductive contact of the second test ring 132 is in direct contact with the second conductive contact
  • the first connection layer 134 One end of the first connection layer 134 is in contact with the first conductive contact and/or the second conductive contact of the first test ring 131, and the other end of the first connection layer 134 is in contact with the first conductive contact and/or the second conductive contact of the second test ring 132.
  • the second connection layer 136 is formed simultaneously with the first metal layer in the interconnect structure.
  • the second connection layer 136, the first metal layer in the first test ring 131 and the first metal layer in the second test ring 132 are formed simultaneously, and the second connection layer 136, the second connection layer 136, the first The first metal layer in the test ring 131 and the first metal layer in the second test ring 132 may be of an integral structure.
  • the protection structure 130 can be formed while forming the interconnection structure. Compared with separately forming the interconnection structure and the protection structure 130 in terms of timing, by forming the interconnection structure and the protection structure 130 at the same time, the process steps can be optimized and the efficiency can be improved.
  • memory 200 also includes:
  • a transistor located on the surface of the substrate 121;
  • One end of the protection structure 130 is electrically connected to the gate of the transistor, and the other end of the protection structure 130 is used to receive an external electrical signal.
  • the gate (PG) of the transistor may be located on the surface of the substrate 121 .
  • An ion implantation well (Well IMP) can be formed by performing ion implantation on the active region of the substrate 121 .
  • the other end of the protection structure 130 is the end provided with the first contact 1311 and the second contact 1321 .
  • the protection structure 130 includes the third test ring 135, the first contact 1311, the second contact 1321 and the third contact 1351 are located at the same end of the protection structure 130, therefore, the other end of the protection structure 130 is also provided with One end of the third contact 1351 .
  • the other end of the protection structure 130 is grounded.
  • the substrate 121 includes: a dicing line located between two adjacent memory chip regions; and a plurality of semiconductor structures 100 arranged at equal intervals in the dicing line.
  • the semiconductor structure 100 when the semiconductor structure 100 is disposed in the dicing line, the semiconductor structure 100 is only used as a test structure for crack testing.
  • the occupation of the effective area on the surface of the substrate 120 for the storage element 210 can be reduced without affecting the integration of the memory 200 .
  • Fig. 4 is a flowchart of a crack testing method according to an exemplary embodiment.
  • the crack test method can be applied to test the semiconductor structure 100 provided by the embodiment of the present disclosure, so as to test whether there is a crack in the semiconductor structure 100 .
  • this crack testing method comprises the following steps:
  • S110 Provide a first electrical signal to the first contact at the end of the first test ring and the second contact at the end of the second test ring, and determine the first contact electrically connected to the first contact and the second contact in the protection structure a first electrical parameter of a path;
  • the first path may include the path L1 shown in FIG. 5
  • the first electrical signal may include a voltage signal or a current signal.
  • S110 may include: providing a preset voltage signal to the first contact and the second contact, and there is a voltage difference between the first contact and the second contact, so as to control the voltage between the first contact and the second contact path provides a current signal.
  • S110 may include providing a current signal to the first contact and the second contact.
  • the first electrical parameter may include: voltage difference, current or resistance.
  • the first electrical parameter is resistance as an example for description.
  • S110 may further include: measuring a voltage difference between the first contact and the second contact. Further, according to the current signal provided to the first contact and the second contact, and the measured voltage difference between the first contact and the second contact, the difference between the first contact and the second contact can be determined. resistance between. It can be understood that when the first contact and the second contact are only connected through the first path, the determined resistance is the resistance of the first path.
  • the first preset condition may include: the first electrical parameter is less than or equal to the first voltage difference threshold.
  • the first preset condition may include: the first electrical parameter is less than or equal to a first resistance threshold.
  • the resistance between the first contact and the second contact is within a certain range (for example, less than or equal to the first resistance threshold).
  • the crack will extend to the protection structure 130 , resulting in at least one test ring (for example, the first test ring 131 , the second test ring 132 or the third test ring 135 ) in the protection structure 130 .
  • the at least partial fracture results in a measured resistance of the first contact and the second contact that is greater (eg, greater than a first resistance threshold).
  • the crack when a crack occurs in the TSV 110, the crack extends to the second test ring 132 in a direction parallel to the substrate 121, so that the second test ring 132 breaks.
  • the first path between the first contact 1311 and the second contact 1321 is partially or completely disconnected, and at this time the resistance of the first path is very large and is greater than the first resistance threshold.
  • the current can flow along the first test ring 131 , the first connection layer 134 and The direction of the second test ring 132 is flow through.
  • the protection structure 130 can be determined by providing the first electrical signal to the first contact 1311 at the end of the first test ring 131 and the second contact 1321 at the end of the second test ring 132.
  • the first electrical parameter of the first path electrically connected to the first contact 1311 and the second contact 1321 in the middle, and determine whether there is a crack in the TSV 110 according to the first electrical parameter, the measurement method is simple and fast.
  • the protection structure 130 further includes a conductive third test ring 135 and a second connection layer 136, and the second connection layer 136 electrically connects the second test ring 132 and the third test ring 135;
  • the crack test method also includes:
  • the second electrical parameter includes at least one of the following: resistance; current; voltage difference.
  • the second preset condition includes: the resistance is smaller than a second resistance threshold.
  • the first region includes: the region of the semiconductor structure 100 located between the first plane where the first connection layer 134 is located and the second plane where the second connection layer 136 is located.
  • the second region includes: the region of the semiconductor structure 100 between the second plane where the second connection layer 136 is located and the third plane where the first contact 1311 and the second contact 1321 are located.
  • the first connection layer 134 is not in direct contact with the third test ring 135, the first connection layer 134 electrically connects the first test ring 131 and the second test ring 132, and the second test The ring 132 and the third test ring 135 are not electrically connected through the first connection layer 134 . However, when the electrical connection path between the first connection layer 134 and the second connection layer 136 is not broken, the first connection layer 134 can still be connected to the third test ring 135 through the second test ring 132 and the second connection layer 136 . electrical connection.
  • the second connection layer 136 is not in direct contact with the first test ring 131, and when the electrical connection path between the first connection layer 134 and the second connection layer 136 is not broken, the second connection layer 136 can still be electrically connected to the first test ring 131 through the second test ring 132 and the first connection layer 134 .
  • test method can analyze layer by layer to further determine the area where cracks exist, thereby further improving the accuracy of crack detection.
  • the protection structure 130 further includes a conductive third test ring 135 and a second connection layer 136, and the first connection layer 134 is electrically connected to the first test ring 131, the second test ring 131 and the second test ring 131.
  • Ring 132 and the third test ring 135; the crack test method also includes:
  • the TSV 110 is close to the first connection between the first test ring 131 and the second test ring 132 Areas of layer 134 are cracked.
  • the crack testing method may further include:
  • the third preset condition includes: the resistance is smaller than a third resistance threshold.
  • first resistance threshold the second resistance threshold and the third resistance threshold can all be set according to actual conditions.
  • the first resistance threshold, the second resistance threshold and the third resistance threshold may be at least partially the same or each may be different.
  • the protection structure can play a role of locally releasing stress on the through-silicon via.
  • the protection structure can also play the role of isolating stress.
  • the protection structure can isolate the stress transmission between the TSV and the surrounding structure of the protection structure, and reduce the stress interaction between the TSV and the surrounding structure. Influenced by the TSV and the surrounding structure, it plays a certain protective role, which is beneficial to ensure that the quality of the formed device is better.

Abstract

本公开实施例提供一种半导体结构、存储器及裂纹测试方法，所述半导体结构包括：穿硅通孔，贯穿基底；保护结构，包括：导电的第一测试环和导电的第二测试环，均围绕所述穿硅通孔设置，且与所述穿硅通孔电绝缘；第一介质层，位于所述第一测试环和所述第二测试环之间，用于电隔离所述第一测试环和所述第二测试环；第一连接层，位于所述第一介质层内，电连接所述第一测试环和所述第二测试环。

Description

半导体结构、存储器及裂纹测试方法
相关申请的交叉引用
本公开基于申请号为202111084056.6、申请日为2021年09月14日、发明名称为“半导体结构、存储器及裂纹测试方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构、存储器及裂纹测试方法。
背景技术
随着半导体技术的发展，集成电路的特征尺寸不断缩小，器件互连密度不断提高。传统的二维封装已经不能满足业界的需求，因此基于穿硅通孔(Through Silicon Via，TSV)技术的垂直互连叠层封装方式，以其短距离互连和高密度集成的关键技术优势，逐渐引领了封装技术发展的趋势。
由于穿硅通孔贯穿整个晶圆，因此，穿硅通孔会对设置在该晶圆上、且位于该穿硅通孔附近的结构造成影响，可能会降低形成的器件性能。并且，目前并没有能有效测试穿硅通孔对附近的结构造成影响的方式。
发明内容
有鉴于此，本公开实施例提供一种半导体结构、存储器及裂纹测试方法。
根据本公开实施例的第一方面，提供一种半导体结构，包括：
穿硅通孔，贯穿基底；
保护结构，包括：
导电的第一测试环和导电的第二测试环，均围绕所述穿硅通孔设置，且与所述穿硅通孔电绝缘；
第一介质层，位于所述第一测试环和所述第二测试环之间，用于电隔离所述第一测试环和所述第二测试环；
第一连接层，位于所述第一介质层内，电连接所述第一测试环和所述第二测试环。
在一些实施例中，所述保护结构还包括：
导电的第三测试环，垂直贯穿所述基底，围绕所述穿硅通孔设置，且位于所述第二测试环和所述穿硅通孔之间，所述第三测试环的端部包括第三触点；
第二连接层，位于所述第二测试环和所述第三测试环之间，电连接所述第二测试环和所述第三测试环；其中，在垂直于所述基底的方向上，所述第二连接层位于所述第三触点与所述第一连接层之间。
在一些实施例中，所述保护结构包括N个所述第三测试环和N个所述第二连接层；其中，第1个所述第三测试环至第(N-1)个所述第三测试环，位于所述第二测试环与第N个所述第三测试环之间，N为大于1的正整数；
第1个所述第二连接层，电连接所述第二测试环和第1个第三测试环；
第K个所述第二连接层，电连接第K个所述第三测试环和第(K+1)个所述第三测试环；其中，K为小于N的正整数。
在一些实施例中，所述第一连接层，电连接所述第一测试环、所述第二测试环和所述第三测试环。
在一些实施例中，在平行于所述基底所在平面的方向，
所述第一测试环的截面形状包括：正多边形或者圆环形；
所述第二测试环的截面形状包括：正多边形或者圆环形；其中，所述第一测试环的截面形状对称中心与所述第二测试环的截面形状对称中心重合；
所述穿硅通孔的截面中心覆盖所述第一测试环截面形状的对称中心。
根据本公开实施例的第二方面，提供一种存储器，包括：
如本公开实施例第一方面任一项所述的半导体结构；其中，所述基底包括衬底和覆盖所述衬底的绝缘层；
存储元件，设置于所述绝缘层中。
在一些实施例中，所述存储器还包括：
导电的互连结构，与所述存储元件电连接；
其中，所述互连结构与所述保护结构同时形成。
在一些实施例中，所述存储器还包括：
晶体管，位于所述衬底表面；
所述保护结构的一端与所述晶体管的栅极电连接，所述保护结构的另一端用于接收外部电信号。
在一些实施例中，所述保护结构的另一端接地。
在一些实施例中，所述衬底包括：
切割道，位于相邻的两个存储芯片区域之间；
多个所述半导体结构，等间距设置在所述切割道内。
根据本公开实施例的第三方面，提供一种裂纹测试方法，应用于测试如本公开实施例第一方面任一项所述的半导体结构，所述裂纹测试方法包括：
提供所述半导体结构；
向所述第一测试环端部的第一触点和所述第二测试环端部的第二触点提供第一电信号，确定所述保护结构中与所述第一触点及所述第二触点电 连接的第一路径的第一电学参数；
当所述第一电学参数指示所述第一路径导通时，确定所述穿硅通孔没有出现裂纹；
当所述第一电学参数指示所述第一路径未导通时，确定所述穿硅通孔出现裂纹。
在一些实施例中，所述保护结构还包括导电的第三测试环和第二连接层，所述第二连接层电连接所述第二测试环和所述第三测试环；
所述裂纹测试方法还包括：
向所述第二触点和所述第三测试环端部的第三触点提供第二电信号，确定所述保护结构中与所述第二触点及所述第三触点电连接的第二路径的第二电学参数；
当所述第一电学参数指示所述第一路径导通，且所述第二电学参数指示所述第二路径导通时，确定所述穿硅通孔没有出现裂纹；
当所述第一电学参数指示所述第一路径未导通时，确定所述穿硅通孔在相对靠近所述第一连接层的第一区域出现裂纹；
当所述第二电学参数指示所述第二路径未导通时，确定所述穿硅通孔在相对靠近所述第二连接层的第二区域出现裂纹。
在一些实施例中，所述保护结构还包括导电的第三测试环和第二连接层，所述第一连接层电连接所述第一测试环、所述第二测试环以及所述第三测试环；
所述裂纹测试方法还包括：
向所述第二触点和所述第三测试环端部的第三触点提供第二电信号，确定所述保护结构中与所述第二触点及所述第三触点电连接的第二路径的第二电学参数；
当所述第一电学参数指示所述第一路径导通，且所述第二电学参数指 示所述第二路径导通时，确定所述穿硅通孔没有出现裂纹；
当所述第一电学参数指示所述第一路径未导通，且所述第二电学参数指示所述第二路径导通时，确定所述穿硅通孔靠近所述第一测试环和所述第二测试环之间的第一连接层的区域出现裂纹；
当所述第一电学参数指示所述第一路径导通，且所述第二电学参数指示所述第二路径未导通时，确定所述穿硅通孔靠近所述第一测试环和所述第二测试环之间的第一连接层的区域出现裂纹。
在一些实施例中，所述第一电学参数和所述第二电学参数包括以下至少之一：电阻；电流；电压差。
本公开实施例提供的半导体结构，通过设置围绕穿硅通孔的保护结构，保护结构能够起到对穿硅通孔局部进行应力释放的作用。而且，保护结构还能起到隔绝应力的作用，具体地，保护结构能够隔绝穿硅通孔与保护结构外围的结构之间的应力传递，减少穿硅通孔与外围的结构之间的应力相互影响，对于穿硅通孔和该外围的结构起到一定的保护作用，有利于保证形成的器件质量较好。
此外，由于保护结构中导电的第一测试环以及第二测试环，均与穿硅通孔电绝缘，且位于第一介质层中的第一连接层电连接第一测试环和第二测试环，可通过向第一测试环端部的第一触点和第二测试环端部的第二触点提供第一电信号，确定保护结构中与第一触点及第二触点电连接的第一路径的第一电学参数，并根据第一电学参数确定穿硅通孔是否出现裂纹，测量方式简单快捷。
再者，由于保护结构包括的第一测试环和第二测试环导电，因此，当第一测试环和第二测试环接地时，第一测试环和第二测试环还能对穿硅通孔进行电磁屏蔽。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1a是根据一示例性实施例示出的一种半导体结构的俯视图；
图1b是根据一示例性实施例示出的一种半导体结构的局部截面示意图；
图2a是根据一示例性实施例示出的另一种半导体结构的俯视图；
图2b是根据一示例性实施例示出的另一种半导体结构的局部截面示意图；
图3是根据一示例性实施例示出的一种存储器的示意图；
图4是根据一示例性实施例示出的一种裂纹测试方法的流程图；
图5是根据一示例性实施例示出的一种裂纹测试方法的示意图；
图6a和图6b是根据一示例性实施例示出的另一种裂纹测试方法的示意图；
图7a和图7b是根据一示例性实施例示出的又一种裂纹测试方法的示意图；
图8是根据一示例性实施例示出的又一种裂纹测试方法的示意图。
具体实施方式
下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能将本公开的范围完整的传达给 本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
在本公开实施例中，术语“A与B相连”包含A、B两者相互接触地A与B相连的情形，或者A、B两者之间还间插有其他部件而A非接触地与B相连的情形。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。层可以包括多个子层。例如，互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
需要说明的是，本公开实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
相关技术中，为了实现芯片的三维堆叠，可设置贯穿衬底的穿硅通孔 来实现上下两个芯片之间的电连接。通常，穿硅通孔中填充的为导电金属，例如，金属铜或者金属钨等。但是，穿硅通孔所产生的应力和电场会对设置在该穿硅通孔附近的器件性能产生不利影响，尤其是当穿硅通孔的尺寸较大时。
例如，以穿硅通孔中填充的是铜为例，当硅衬底的温度发生变化时，由于硅衬底和铜的热膨胀系数不匹配，容易使得穿硅通孔对周围的硅衬底产生拉伸应力或者压缩应力。该拉伸应力或者压缩应力的大小，与离穿硅通孔之间的距离成反比，该拉伸应力或者压缩应力会使得设置在穿硅通孔周围的器件的至少部分结构(例如，MOS晶体管沟道区)的晶格常数发生变化，从而改变载流子的迁移率，对器件的电学性能产生不利影响。
并且，当由于该应力导致穿硅通孔周围的绝缘材料产生裂纹时，穿硅通孔包括的导电材料可能通过裂纹发生扩散，甚至出现穿硅通孔通过裂纹扩散至与周围的器件电连接的情况，导致存储器发生短路，降低存储器质量与可靠性。
有鉴于此，本公开实施例提供一种半导体结构100。参照图1a和图1b所示，半导体结构100包括：
穿硅通孔110，贯穿基底120；
保护结构130，包括：
导电的第一测试环131和导电的第二测试环132，均围绕穿硅通孔110设置，且与穿硅通孔110电绝缘；
第一介质层133，位于第一测试环131和第二测试环132之间，用于电隔离第一测试环131和第二测试环132；
第一连接层134，位于第一介质层133内，电连接第一测试环131和第二测试环132。
示例性地，穿硅通孔110可沿第一方向贯穿基底120。参照图1b所示， 第一方向可包括平行于Z轴的方向。穿硅通孔110的组成材料可包括导电材料，例如，铜或钨等。
在一些实施例中，穿硅通孔110的组成材料还包括阻挡层，设置于导电材料与基底120之间，用于阻挡导电材料向基底120扩散。所述阻挡层的组成材料可以包括金属氮化物，例如氮化钛和/或氮化钽。所述阻挡层的组成材料也可以包括氧化物，例如氧化硅和/或氮氧化硅。
基底120的组成材料可包括：半导体衬底，该半导体衬底的组成材料可包括：硅、绝缘体上硅(SOI)或者绝缘体上层叠硅(SSOI)等。如图1b所示，该半导体衬底上可以被定义有源区(Active Area，AA)。
基底120的组成材料也可包括：介质材料，例如，二氧化硅或者正硅酸乙酯(TEOS)等。
第一测试环131的组成材料与第二测试环132的组成材料可相同。例如，第一测试环131和第二测试环132的组成材料可包括：铜或者钨。
参照图1b所示，第一测试环131的端部可包括：第一触点1311，用于接收向第一测试环131施加的电信号。第二测试环132的端部可包括：第二触点1321，用于接收向第二测试环132施加的电信号。
参照图1a所示，第二测试环132可设置于第一测试环131与穿硅通孔110之间。需要强调的是，第二测试环132与穿硅通孔110之间存在一定的间隙，该间隙内填充有介质材料，以电隔离第二测试环132与穿硅通孔110。
结合图1a和图1b所示，在半导体结构100中，当穿硅通孔110与保护结构130之间因为应力等原因产生裂纹时，裂纹可能沿着第一方向、第二方向或者第三方向进行延伸，第二方向可包括平行于X轴的方向，第三方向可包括平行于Y轴的方向。
当裂纹沿第二方向或第三方向延伸至第二测试环132时，由于第二测试环132的组成材料不同于基底120的组成材料，因此，第二测试环132 可以阻挡裂纹进一步沿第二方向或第三方向延伸，如此，保护结构130可以将穿硅通孔110附近的裂纹控制在保护结构130与穿硅通孔110之间的区域内，降低裂纹进一步向保护结构130远离穿硅通孔110的外侧延伸的几率，即对位于保护结构130远离穿硅通孔110的外侧的器件，保护结构130起到了应力保护的作用。
类似地，保护结构130也可以阻挡从远离穿硅通孔110的外侧产生的裂纹向穿硅通孔110进行延伸，即保护结构130也对穿硅通孔110起到了应力保护的作用。
需要强调的是，在垂直于第一方向的平面内，保护结构130的截面形状为闭合图形(例如，矩形、八边形、十二边形、椭圆形或者圆形等)，第一测试环131与第二测试环132的截面形状也为闭合图形，穿硅通孔110被第一测试环131完全围绕，且穿硅通孔110被第二测试环132完全围绕，如此，保护结构130可以起到较好的应力保护作用，并且，能够在该平面内对围绕穿硅通孔110的所有方向均进行裂纹检测，有利于提升裂纹检测的全面性和准确性。
第一介质层133的组成材料可以包括低介电常数的材料，例如，二氧化硅或者正硅酸乙酯等。
第一连接层134的组成材料为导电材料，可包括导电金属，例如，铜或者钨等。参照图1b所示，第一连接层134可基本平行于基底120所在的平面。在一些实施例中，第一连接层134也可与基底120存在一定的夹角。
本公开实施例提供的半导体结构100，通过设置围绕穿硅通孔110的保护结构130，保护结构130能够对穿硅通孔110局部进行应力释放。而且，保护结构130还能起到隔绝应力的作用，具体地，保护结构130能够隔绝穿硅通孔110与保护结构130外围的结构之间的应力传递，减少穿硅通孔110与外围的结构之间的应力相互影响，对于穿硅通孔110和该外围的结构 均起到一定的保护作用，有利于保证形成的器件的质量较好。
此外，由于保护结构130中导电的第一测试环131以及第二测试环132分别经介质材料均与穿硅通孔110电绝缘，且位于第一介质层133中的第一连接层134电连接第一测试环131和第二测试环132，可通过向第一测试环131端部的第一触点1311和第二测试环132端部的第二触点1321提供第一电信号，确定保护结构130中与第一触点1311及第二触点1321电连接的第一路径的第一电学参数，并根据第一电学参数确定穿硅通孔110是否出现裂纹，以实现应力检测(即裂纹检测)，测量方式简单快捷。
再者，由于保护结构130包括的第一测试环131和第二测试环132导电，因此，当第一测试环131和第二测试环132接地时，第一测试环131和第二测试环132还能对穿硅通孔110进行电磁屏蔽。
在一些实施例中，参照图2a和图2b所示，保护结构130还包括：
导电的第三测试环135，垂直贯穿基底120，围绕穿硅通孔110设置，且位于第二测试环132和穿硅通孔110之间，第三测试环135的端部包括第三触点1351；
第二连接层136，位于第二测试环132和第三测试环135之间，电连接第二测试环132和第三测试环135；其中，在垂直于基底120的方向上，第二连接层136位于第三触点1351与第一连接层134之间。
第三测试环135的组成材料可包括：铜或者钨。第三触点1351，用于接收向第三测试环135施加的电信号。第三触点1351和第一触点1311，以及第二触点1321例如可以使用相同的材料，例如铝。
第二连接层136的组成材料为导电材料，可包括导电金属，例如，铜或者钨等。参照图2b所示，第二连接层136可基本平行于基底120所在的平面。在一些实施例中，第二连接层136也可与基底120存在一定的夹角。可以理解的是，在垂直于基底120的方向上，第二连接层136只要设置第 三触点1351所在平面与第一连接层134所在平面之间即可。
可以理解的是，第三测试环135与第二测试环132之间还可设置有第二介质层(图中未示出)，用于电隔离第三测试环135与第二测试环132。第二介质层的组成材料与第一介质层133的组成材料可相同。
第二连接层136，位于第二介质层中。需要强调的是，第二测试环132与第三测试环135通过第二连接层136电连接。
在一些实施例中，参照图2b所示，第一连接层134，电连接第一测试环131、第二测试环132和第三测试环135。
在另一些实施例中，第一连接层134仅电连接第一测试环131与第二测试环132，而不能电连接第二测试环132与第三测试环135。
需要强调的是，当第一连接层134的设置方式不同时，在第一触点1311、第二触点1321和第三触点1351之间可形成的导电路径不同，因此，利用该半导体结构100进行应力检测(即裂纹检测)的时候，具体的判断条件可能存在差异，本公开会在后续实施例提供的测试方法中进行具体描述。
本公开实施例中，通过设置第三测试环135和第二连接层136，有利于准确定位裂纹产生位置，可提高裂纹测试的准确性。
在一些实施例中，保护结构130包括N个第三测试环135和N个第二连接层136；其中，第1个第三测试环135至第(N-1)个第三测试环135，位于第二测试环132与第N个第三测试环135之间，N为大于1的正整数；
第1个第二连接层136，电连接第二测试环132和第1个第三测试环135；
第K个第二连接层136，电连接第K个第三测试环135和第(K+1)个第三测试环135；其中，K为小于N的正整数。
可以理解的是，当第三测试环135和第二连接层136设置的数量越多，保护结构130所占用的面积就会越大，因此，可根据实际需求确定第三测 试环135的设置数量以及第二连接层136的设置数量。
本公开实施例中，通过设置多个第三测试环135和多个第二连接层136，可逐层进行分析，确定出裂纹具体存在于哪两个相邻的第二连接层136之间，和/或，确定出裂纹是否存在于第一连接层134和最近邻的第二连接层136之间，有利于进一步准确定位裂纹产生位置，进一步提高裂纹检测的准确性。
在一些实施例中，在平行于基底120所在平面的方向，
第一测试环131的截面形状包括：正多边形或者圆环形；
第二测试环132的截面形状包括：正多边形或者圆环形；其中，第一测试环131的截面形状对称中心与第二测试环132的截面形状对称中心重合；
穿硅通孔110的截面中心覆盖第一测试环131截面形状的对称中心。
示例性地，在平行于基底120所在平面的方向，当第一测试环131的截面形状为正多边形，且第二测试环132的截面形状也为正多边形时，第一测试环131的截面形状与第二测试环132的截面形状可以不同或者不同。例如，第一测试环131的截面形状可为正方形，第二测试环132的截面形状可为正三角形、正方形、正六边形、正八边形、正十二边形或者圆形等。
需要强调的是，在平行于基底120所在平面的方向，第一测试环131的截面形状与第二测试环132的截面形状没有交点。
优选地，在平行于基底120所在平面的方向，第一测试环131的截面形状与第二测试环132的截面形状相同。由于第一测试环131的截面形状对称中心与第二测试环132的截面形状对称中心重合，如此，第一测试环131与第二测试环132之间各处距离相同。
示例性地，在平行于基底120所在平面的方向，穿硅通孔110的截面形状可包括圆形、正方形或者长方形等。优选地，穿硅通孔110为圆柱形， 在平行于基底120所在平面的方向，穿硅通孔110的截面形状为圆形，如此，可降低刻蚀形成该通孔的难度，以及降低向该通孔中填充导电材料形成穿硅通孔110的难度。
在平行于基底120所在平面的方向，由于穿硅通孔110的截面中心覆盖第一测试环131截面形状的对称中心，即穿硅通孔110的截面中心与第一测试环131的截面形状的对称中心重叠，如此，可优化保护结构130布局，减少保护结构130对于基底120面积的占用。
在一些实施例中，在平行于基底120所在平面的方向，第三测试环135的截面形状包括：正多边形或者圆环形；其中，第三测试环135的截面形状对称中心与第二测试环132的截面形状对称中心重合，穿硅通孔110的截面中心与第三测试环135截面形状的对称中心重合。
示例性地，在平行于基底120所在平面的方向，第三测试环135的截面形状，可以不同于第一测试环131的截面形状和/或第二测试环132的截面形状。需要强调的是，在平行于基底120所在平面的方向，第三测试环135的截面形状与第一测试环131的截面形状没有交点，且第三测试环135的截面形状与第二测试环132的截面形状没有交点。
优选地，在平行于基底120所在平面的方向，第一测试环131的截面形状、第二测试环132的截面形状以及第三测试环135的截面形状相同，且第一测试环131、第二测试环132以及第三测试环135的对称中心重合，如此，第三测试环135与第一测试环131之间各处距离相同，且第三测试环135与第二测试环132之间各处距离相同。
图3是根据一示例性实施例示出的一种存储器200的示意图。参照图3所示，存储器200包括：
半导体结构100；其中，基底120包括衬底121和覆盖衬底121的绝缘层122；
存储元件210，设置于绝缘层122中。
示例性地，存储器200包括但不限于：动态随机存取存储器(Dynamic Random Access Memory，DRAM)、三维NAND存储器或者相变存储器等。
在存储器200中，半导体结构100中的穿硅通孔110可电连接设置在基底120两侧的功能结构，和/或，半导体结构100中的穿硅通孔110可用于进行裂纹测试。
可以理解的是，当半导体结构100中的穿硅通孔110用于进行裂纹测试时，该半导体结构100为测试结构，其中的穿硅通孔110不起到电连接功能结构的作用。
需要强调的是，存储元件210设置在保护结构130远离穿硅通孔110的外侧，保护结构130位于存储元件210和穿硅通孔110之间。
本公开实施例提供的存储器200，通过设置半导体结构100，半导体结构100中的保护结构130能够起到对穿硅通孔110局部进行应力释放的作用。而且，保护结构130还能起到隔绝应力的作用，具体地，保护结构130能够隔绝穿硅通孔110与保护结构130外围的结构(例如，存储元件210)之间的应力传递，减少穿硅通孔110与外围的结构之间的应力相互影响，对于穿硅通孔110和该外围的结构起到一定的保护作用，有利于保证存储器200的质量较好。
此外，由于保护结构130中的导电的第一测试环131以及第二测试环132，均与穿硅通孔110电绝缘，且位于第一介质层133中的第一连接层134电连接第一测试环131和第二测试环132，可通过向第一测试环131端部的第一触点1311和第二测试环132端部的第二触点1321提供第一电信号，确定保护结构130中与第一触点1311及第二触点1321电连接的第一路径的第一电学参数，并根据第一电学参数确定穿硅通孔110是否出现裂纹，测量方式简单快捷。
需要强调的是，当半导体结构100仅用于进行裂纹测试时，存储器200中还可包括起到与半导体结构100具有相同结构、且用于电连接堆叠设置的结构之间的其他预设结构，该预设结构与作为测试的半导体结构100可以是同时形成的，如此，可根据对该作为测试的半导体结构100的测试结果，反应该预设结构的质量。进一步地，还可根据作为测试的半导体结构100的测试结果，调整后续对该预设结构的制作工艺，以提高形成的上述预设结构的质量，进而提高存储器200的质量。
再者，由于保护结构130包括的第一测试环131和第二测试环132导电，因此，当第一测试环131和/或第二测试环132接地时，保护结构130还能对穿硅通孔110进行电磁屏蔽。
在一些实施例中，存储器200还包括：
导电的互连结构，与存储元件210电连接；
其中，互连结构与保护结构130同时形成。
沿第一方向，导电的互连结构可包括：层叠设置的第一导电接触(PC)、初始金属层(M0)、第二导电接触(CT)、第一金属层(M1)、第一导电通孔(V1)、第二金属层(M2)、第二导电通孔(V2)以及第三金属层(M3)。
参照图1b所示，沿第一方向，第一测试环131可包括依次层叠设置的第一导电接触、第二导电接触、第一金属层、第一导电通孔、第二金属层、第二导电通孔以及第三金属层(即第一触点1311)，第二测试环132可包括依次层叠设置的第一导电接触、第二导电接触、第一金属层、第一导电通孔、第二金属层、第二导电通孔以及第三金属层(即第二触点1321)。
需要强调的是，互连结构、第一测试环131以及第二测试环132中相同的结构同时形成。例如，互连结构中的第一导电接触、第一测试环131中的第一导电接触以及第二测试环132中的第一导电接触同时形成，互连结构中的第二导电接触、第一测试环131中的第二导电接触以及第二测试 环132中的第二导电接触同时形成，互连结构中的第一金属层、第一测试环131中的第一金属层以及第二测试环132中的第一金属层同时形成，依次类推，互连结构中的第三金属层、第一测试环131中的第三金属层以及第二测试环132中的第三金属层同时形成。第一连接层134可与互连结构中的初始金属层同时形成。
示例性地，如图1b所示，第一连接层134的一端，可设置于第一测试环131的第一导电接触和第二导电接触之间；第一连接层134的另一端，可设置于第二测试环132的第一导电接触和第二导电接触之间。
在另一些实施例中，第一测试环131的第一导电接触和第二导电接触之间直接接触，第二测试环132的第一导电接触和第二导电接触直接接触，第一连接层134的一端与第一测试环131的第一导电接触和/或第二导电接触接触，第一连接层134的另一端接触与第二测试环132的第一导电接触和/或第二导电接触接触。
在半导体结构100包括第二连接层136时，第二连接层136与互连结构中的第一金属层同时形成。此时，第二连接层136、第一测试环131中的第一金属层以及第二测试环132中的第一金属层同时形成，且第二连接层136、第二连接层136、第一测试环131中的第一金属层以及第二测试环132中的第一金属层可为一体结构。
如此，可在形成互连结构的同时形成保护结构130，相较于在时序上分开形成互连结构和保护结构130，通过同时形成互连结构和保护结构130，可优化工艺步骤，提高效率。
在一些实施例中，存储器200还包括：
晶体管，位于衬底121表面；
保护结构130的一端与晶体管的栅极电连接，保护结构130的另一端用于接收外部电信号。
参照图1b所示，晶体管的栅极(PG)可位于衬底121表面。可通过对衬底121的有源区进行离子注入，形成离子注入阱(Well IMP)。
可以理解的是，上述保护结构130的另一端即为设置有第一触点1311和第二触点1321的一端。当保护结构130包括第三测试环135时，第一触点1311、第二触点1321和第三触点1351位于保护结构130的同一端，因此，上述保护结构130的另一端也为设置有第三触点1351的一端。
在一些实施例中，上述保护结构130的另一端接地。
在一些实施例中，衬底121包括：切割道，位于相邻的两个存储芯片区域之间；多个半导体结构100，等间距设置在切割道内。
可以理解的是，当半导体结构100设置在切割道内时，该半导体结构100仅作为裂纹测试的测试结构。
本公开实施例中，通过将作为裂纹测试的半导体结构100设置在切割道内，可以减少对于基底120表面用于设置存储元件210的有效面积的占用，不会影响存储器200的集成度。
此外，通过在切割道内等间距设置多个半导体结构100，可通过对多个半导体结构100进行测试，获得更为精确的应力检测结果。
图4是根据一示例性实施例示出的一种裂纹测试方法的流程图。该裂纹测试方法可应用于测试如本公开实施例提供的半导体结构100，以测试该半导体结构100中是否存在裂纹。参照图4所示，该裂纹测试方法包括以下步骤：
S100：提供半导体结构；
S110：向第一测试环端部的第一触点和第二测试环端部的第二触点提供第一电信号，确定保护结构中与第一触点及第二触点电连接的第一路径的第一电学参数；
S120：当第一电学参数满足第一预设条件时，确定穿硅通孔没有出现 裂纹；
S130：当第一电学参数不满足第一预设条件时，确定穿硅通孔出现裂纹。
S110中，第一路径可包括图5中示出的路径L1，第一电信号可包括电压信号或者电流信号。
S110可包括：向第一触点和第二触点提供预设电压信号，且第一触点和第二触点之间存在电压差，以对第一触点和第二触点之间的路径提供电流信号。或者，S110可包括向第一触点和第二触点提供电流信号。
示例性地，第一电学参数可包括：电压差、电流或者电阻。下面以第一电学参数为电阻为例，进行说明。
S110还可包括：测量第一触点和第二触点之间的电压差。进一步地，可根据提供给第一触点和第二触点的电流信号，以及测量出来的第一触点和第二触点之间的电压差，确定第一触点和第二触点之间的电阻。可以理解的是，当第一触点和第二触点仅通过第一路径连接时，确定出的电阻即为第一路径的电阻。
S120和S130中，以第一电学参数为电压差为例，第一预设条件可包括：第一电学参数小于或等于第一电压差阈值。
以第一电学参数为电阻为例，第一预设条件可包括：第一电学参数小于或等于第一电阻阈值。实际应用中，当穿硅通孔100周围无裂纹时，第一触点和第二触点间的电阻处于某个范围(例如，小于或等于第一电阻阈值)。当穿硅通孔110出现裂纹时，通常裂纹会延伸至保护结构130，导致保护结构130中的至少一个测试环(例如，第一测试环131、第二测试环132或第三测试环135)至少部分断裂，导致测量得到的第一触点和第二触点的电阻变大(例如，大于第一电阻阈值)。
具体地，以图1a示出的半导体结构100为例，当穿硅通孔110出现裂 纹时，在平行于衬底121的方向，裂纹延伸至第二测试环132，使得第二测试环132断裂，第一触点1311及第二触点1321之间的第一路径部分或全部断开，此时第一路径的电阻很大，且大于第一电阻阈值。示例性地，当通过电源向第一触点1311提供正电压，向第二触点1321提供负电压，且第一路径导通时，电流可沿第一测试环131、第一连接层134和第二测试环132的方向流通。当第一路径部分断开时，电流依旧可沿第一测试环131、第一连接层134和第二测试环132的方向流通，但此时第一路径的电阻大于第一电阻阈值。当第一路径完全断开时，沿第一测试环131、第一连接层134和第二测试环132无法形成电流通路。
本公开实施例提供的裂纹测试方法，可通过向第一测试环131端部的第一触点1311和第二测试环132端部的第二触点1321提供第一电信号，确定保护结构130中与第一触点1311及第二触点1321电连接的第一路径的第一电学参数，并根据第一电学参数确定穿硅通孔110是否出现裂纹，测量方式简单快捷。
在一些实施例中，保护结构130还包括导电的第三测试环135和第二连接层136，第二连接层136电连接第二测试环132和第三测试环135；
所述裂纹测试方法还包括：
向第二触点1321和第三测试环135端部的第三触点1351提供第二电信号，确定保护结构130中与第二触点1321及第三触点1351电连接的第二路径(例如，图6a中示出的路径L2)的第二电学参数；
当第一电学参数满足第一预设条件，且第二电学参数满足第二预设条件时，确定穿硅通孔110没有出现裂纹；
当第一电学参数不满足第一预设条件时，确定穿硅通孔110在相对靠近第一连接层134的第一区域出现裂纹；
当第二电学参数不满足第二预设条件时，确定穿硅通孔110在相对靠 近第二连接层136的第二区域出现裂纹。
示例性地，第二电学参数包括以下至少之一：电阻；电流；电压差。
以第二电学参数是电阻为例，第二预设条件包括：电阻小于第二电阻阈值。
参照图6a和图6b所示，第一区域，包括：半导体结构100位于第一连接层134所在的第一平面与第二连接层136所在的第二平面之间的区域。
第二区域，包括：半导体结构100位于第二连接层136所在的第二平面与第一触点1311和第二触点1321所在的第三平面之间的区域。
可以理解的是，本公开实施例中，第一连接层134并未直接与第三测试环135接触，第一连接层134电连接第一测试环131和第二测试环132，且第二测试环132和第三测试环135并未通过第一连接层134电连接。但是，当第一连接层134与第二连接层136的电连接路径并未断裂时，第一连接层134依旧可以通过第二测试环132以及第二连接层136，实现与第三测试环135的电连接。
类似地，本公开实施例中，第二连接层136并未直接与第一测试环131接触，当第一连接层134与第二连接层136的电连接路径并未断裂时，第二连接层136依旧可以通过第二测试环132和第一连接层134，实现与第一测试环131电连接。
本公开实施例提供的测试方法，可逐层进行分析，进一步确定出裂纹存在的区域，进而进一步提高裂纹检测的准确性。
在一些实施例中，参照图7a和图7b所示，保护结构130还包括导电的第三测试环135和第二连接层136，第一连接层134电连接第一测试环131、第二测试环132以及第三测试环135；所述裂纹测试方法还包括：
向第二触点1321和第三测试环135端部的第三触点1351提供第二电信号，确定保护结构130中与第二触点1321及第三触点1351电连接的第 二路径的第二电学参数；
当第一电学参数满足第一预设条件，且第二电学满足第二预设条件时，确定穿硅通孔110没有出现裂纹；
当第一电学参数不满足第一预设条件，且第二电学参数满足第二预设条件时，确定穿硅通孔110靠近第一测试环131和第二测试环132之间的第一连接层134的区域出现裂纹；
当第一电学参数满足第一预设条件，且第二电学参数不满足第二预设条件时，确定穿硅通孔110靠近第一测试环131和第二测试环132之间的第一连接层134的区域出现裂纹。
在一些实施例中，参照图8所示，所述裂纹测试方法还可包括：
向第一触点1311和第三触点1351提供第三电信号，确定保护结构130中与第一触点1311及第二触点1321电连接的第三路径(例如，路径L3)的第三电学参数；
当第三电学参数满足第三预设条件时，确定穿硅通孔110没有出现裂纹；
当第三电学参数不满足第三预设条件时，确定穿硅通孔110出现裂纹。
以第三电学参数是电阻为例，第三预设条件包括：电阻小于第三电阻阈值。
需要强调的是，第一电阻阈值、第二电阻阈值以及第三电阻阈值的取值都可以根据实际情况进行设置。第一电阻阈值、第二电阻阈值以及第三电阻阈值可至少部分相同或者各自不同。
在本公开所提供的实施例中，应该理解到，所揭露的装置、系统与方法，可以通过其他的方式实现。以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开 的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供的半导体结构，通过设置围绕穿硅通孔的保护结构，保护结构能够起到对穿硅通孔局部进行应力释放的作用。而且，保护结构还能起到隔绝应力的作用，具体地，保护结构能够隔绝穿硅通孔与保护结构外围的结构之间的应力传递，减少穿硅通孔与外围的结构之间的应力相互影响，对于穿硅通孔和该外围的结构起到一定的保护作用，有利于保证形成的器件质量较好。

Claims (14)

  1. 一种半导体结构，包括：
    穿硅通孔，贯穿基底；
    保护结构，包括：
    导电的第一测试环和导电的第二测试环，均围绕所述穿硅通孔设置，且与所述穿硅通孔电绝缘；
    第一介质层，位于所述第一测试环和所述第二测试环之间，用于电隔离所述第一测试环和所述第二测试环；
    第一连接层，位于所述第一介质层内，电连接所述第一测试环和所述第二测试环。
  2. 根据权利要求1所述的半导体结构，其中，所述保护结构还包括：
    导电的第三测试环，垂直贯穿所述基底，围绕所述穿硅通孔设置，且位于所述第二测试环和所述穿硅通孔之间，所述第三测试环的端部包括第三触点；
    第二连接层，位于所述第二测试环和所述第三测试环之间，电连接所述第二测试环和所述第三测试环；其中，在垂直于所述基底的方向上，所述第二连接层位于所述第三触点与所述第一连接层之间。
  3. 根据权利要求2所述的半导体结构，其中，
    所述保护结构包括N个所述第三测试环和N个所述第二连接层；其中，第1个所述第三测试环至第(N-1)个所述第三测试环，位于所述第二测试环与第N个所述第三测试环之间，N为大于1的正整数；
    第1个所述第二连接层，电连接所述第二测试环和第1个第三测试环；
    第K个所述第二连接层，电连接第K个所述第三测试环和第(K+1)个所述第三测试环；其中，K为小于N的正整数。
  4. 根据权利要求2所述的半导体结构，其中，
    所述第一连接层，电连接所述第一测试环、所述第二测试环和所述第三测试环。
  5. 根据权利要求1所述的半导体结构，其中，在平行于所述基底所在平面的方向，
    所述第一测试环的截面形状包括：正多边形或者圆环形；
    所述第二测试环的截面形状包括：正多边形或者圆环形；其中，所述第一测试环的截面形状对称中心与所述第二测试环的截面形状对称中心重合；
    所述穿硅通孔的截面中心覆盖所述第一测试环截面形状的对称中心。
  6. 一种存储器，包括：
    如权利要求1至5任一项所述的半导体结构；其中，所述基底包括衬底和覆盖所述衬底的绝缘层；
    存储元件，设置于所述绝缘层中。
  7. 根据权利要求6所述的存储器，其中，所述存储器还包括：
    导电的互连结构，与所述存储元件电连接；
    其中，所述互连结构与所述保护结构同时形成。
  8. 根据权利要求7所述的存储器，其中，所述存储器还包括：
    晶体管，位于所述衬底表面；
    所述保护结构的一端与所述晶体管的栅极电连接，所述保护结构的另一端用于接收外部电信号。
  9. 根据权利要求8所述的存储器，其中，所述保护结构的另一端接地。
  10. 根据权利要求6所述的存储器，其中，所述衬底包括：
    切割道，位于相邻的两个存储芯片区域之间；
    多个所述半导体结构，等间距设置在所述切割道内。
  11. 一种裂纹测试方法，应用于测试如权利要求1至5任一项所述的半导体结构，所述裂纹测试方法包括：
    提供所述半导体结构；
    向所述第一测试环端部的第一触点和所述第二测试环端部的第二触点提供第一电信号，确定所述保护结构中与所述第一触点及所述第二触点电连接的第一路径的第一电学参数；
    当所述第一电学参数满足第一预设条件时，确定所述穿硅通孔没有出现裂纹；
    当所述第一电学参数不满足所述第一预设条件时，确定所述穿硅通孔出现裂纹。
  12. 根据权利要求11所述的裂纹测试方法，其中，所述保护结构还包括导电的第三测试环和第二连接层，所述第二连接层电连接所述第二测试环和所述第三测试环；
    所述裂纹测试方法还包括：
    向所述第二触点和所述第三测试环端部的第三触点提供第二电信号，确定所述保护结构中与所述第二触点及所述第三触点电连接的第二路径的第二电学参数；
    当所述第一电学参数满足所述第一预设条件，且所述第二电学参数满足第二预设条件时，确定所述穿硅通孔没有出现裂纹；
    当所述第一电学参数不满足所述第一预设条件时，确定所述穿硅通孔在相对靠近所述第一连接层的第一区域出现裂纹；
    当所述第二电学参数不满足所述第二预设条件时，确定所述穿硅通孔在相对靠近所述第二连接层的第二区域出现裂纹。
  13. 根据权利要求11所述的裂纹测试方法，其中，所述保护结构还包括导电的第三测试环和第二连接层，所述第一连接层电连接所述第一测试环、 所述第二测试环以及所述第三测试环；
    所述裂纹测试方法还包括：
    向所述第二触点和所述第三测试环端部的第三触点提供第二电信号，确定所述保护结构中与所述第二触点及所述第三触点电连接的第二路径的第二电学参数；
    当所述第一电学参数满足所述第一预设条件，且所述第二电学参数满足第二预设条件时，确定所述穿硅通孔没有出现裂纹；
    当所述第一电学参数不满足所述第一预设条件，且所述第二电学参数满足所述第二预设条件时，确定所述穿硅通孔靠近所述第一测试环和所述第二测试环之间的第一连接层的区域出现裂纹；
    当所述第一电学参数满足所述第一预设条件，且所述第二电学参数不满足所述第二预设条件时，确定所述穿硅通孔靠近所述第一测试环和所述第二测试环之间的第一连接层的区域出现裂纹。
  14. 根据权利要求12或13所述的裂纹测试方法，其中，
    所述第一电学参数和所述第二电学参数包括以下至少之一：电阻；
    电流；电压差。
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