WO2023037847A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023037847A1
WO2023037847A1 PCT/JP2022/031398 JP2022031398W WO2023037847A1 WO 2023037847 A1 WO2023037847 A1 WO 2023037847A1 JP 2022031398 W JP2022031398 W JP 2022031398W WO 2023037847 A1 WO2023037847 A1 WO 2023037847A1
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Prior art keywords
region
source
drain
back gate
semiconductor device
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Ceased
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PCT/JP2022/031398
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English (en)
French (fr)
Japanese (ja)
Inventor
力 寺田
周作 藤江
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Rohm Co Ltd
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Rohm Co Ltd
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Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to DE112022004276.1T priority Critical patent/DE112022004276T5/de
Priority to JP2023546859A priority patent/JPWO2023037847A1/ja
Priority to CN202280054850.2A priority patent/CN117795687A/zh
Publication of WO2023037847A1 publication Critical patent/WO2023037847A1/ja
Priority to US18/592,203 priority patent/US20240204062A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/115—Resistive field plates, e.g. semi-insulating field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/155—Shapes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/159—Shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • Patent Document 1 discloses a semiconductor device including a semiconductor layer, a first electrode, a second electrode, a lateral element, and a LOCOS oxide film resistive field plate.
  • the first electrode is formed on the surface of the semiconductor layer.
  • a second electrode is formed on the surface of the semiconductor layer spaced apart from the first electrode.
  • the horizontal element is formed in a region between the first electrode and the second electrode in the surface layer portion of the surface of the semiconductor layer, and is electrically connected to the first electrode and the second electrode.
  • the LOCOS oxide film separates the parts forming the lateral element on the surface of the semiconductor layer.
  • a resistive field plate is formed over the LOCOS oxide.
  • One embodiment provides a semiconductor device having a novel configuration.
  • a chip having a main surface, a drain region of a first conductivity type formed in a surface layer portion of the main surface, and a first conductivity type drain region formed in a region different from the drain region in the surface layer portion of the main surface.
  • a source region of one conductivity type and a second conductivity type formed in a region different from the drain region and the source region in a surface layer portion of the main surface so as to be electrically separated from the drain region and the source region; a back gate region, a gate insulating film covering the source region on the main surface, and a gate electrode formed on the gate insulating film.
  • One embodiment has a semiconductor chip, a drain, a source, a gate, and a back gate, and a source potential is individually applied to the sources and a back gate potential is individually applied to the back gates.
  • a transistor structure formed on the semiconductor chip in and a resistor disposed on the semiconductor chip so as to be electrically disconnected from the source and electrically connected to the drain and the backgate. provides a semiconductor device.
  • FIG. 1 is a plan view showing a chip of a semiconductor device according to a first embodiment
  • FIG. 2 is an enlarged plan view of region II shown in FIG.
  • FIG. 3 is a cross-sectional perspective view of region III shown in FIG.
  • FIG. 4 is a cross-sectional view of region III shown in FIG.
  • FIG. 5 is a circuit diagram showing the electrical structure within the transistor region.
  • FIG. 6 is an enlarged plan view showing the essential parts of the semiconductor device according to the second embodiment.
  • FIG. 7 is a cross-sectional perspective view of area VII shown in FIG.
  • FIG. 1 is a plan view showing a chip 2 of a semiconductor device 1A according to the first embodiment.
  • FIG. 2 is an enlarged view of area II shown in FIG.
  • FIG. 3 is a cross-sectional perspective view of region III shown in FIG.
  • FIG. 4 is a cross-sectional view of region III shown in FIG. 1 to 4,
  • a semiconductor device 1A includes a silicon chip 2 (semiconductor chip) formed in a rectangular parallelepiped shape.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. ing.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from the normal direction Z (hereinafter simply referred to as "plan view").
  • the normal direction Z is also the thickness direction of the chip 2 .
  • the first side surface 5A and the second side surface 5B extend in the first direction X and face the second direction Y that intersects (specifically, is perpendicular to) the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. As shown in FIG.
  • the semiconductor device 1A includes an n-type (first conductivity type) first semiconductor region 6 formed in a region on the first main surface 3 side within the chip 2 .
  • the first semiconductor region 6 is formed in a layer extending along the first main surface 3 and exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the thickness of the first semiconductor region 6 may be 5 ⁇ m or more and 20 ⁇ m or less.
  • the first semiconductor region 6 is formed in this embodiment by an n-type epitaxial layer.
  • the semiconductor device 1A includes a p-type (second conductivity type) second semiconductor region 7 formed in a region on the second main surface 4 side within the chip 2 .
  • the second semiconductor region 7 is fixed at the back gate potential.
  • the back gate potential may be a reference potential that serves as a reference for circuit operation, a ground potential, or a potential other than these.
  • the second semiconductor region 7 is formed in a layer extending along the second main surface 4 and exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 is connected to the first semiconductor region 6 inside the chip 2 .
  • the thickness of the second semiconductor region 7 may be 50 ⁇ m or more and 400 ⁇ m or less.
  • the second semiconductor region 7 is formed of a p-type semiconductor substrate in this embodiment. That is, the chip 2 has a laminated structure including a semiconductor substrate and an epitaxial layer, and includes a first semiconductor region 6 formed on the epitaxial layer and a second semiconductor region 7 formed on the semiconductor substrate.
  • a semiconductor device 1A includes a plurality of device regions 8 partitioned on the first main surface 3 .
  • the number and arrangement of the plurality of device regions 8 are arbitrary.
  • the plurality of device regions 8 each include functional devices formed using regions inside and outside the chip 2 .
  • Functional devices may include at least one of semiconductor switching devices, semiconductor rectifying devices and passive devices.
  • a functional device may include a network of combined at least two of a semiconductor switching device, a semiconductor rectifying device and a passive device.
  • the semiconductor switching device may include at least one of MISFET (Metal Insulator Semiconductor Field Effect Transistor), BJT (Bipolar Junction Transistor), IGBT (Insulated Gate Bipolar Junction Transistor) and JFET (Junction Field Effect Transistor) .
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • BJT Bipolar Junction Transistor
  • IGBT Insulated Gate Bipolar Junction Transistor
  • JFET Joint Field Effect Transistor
  • the semiconductor rectifier device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode and a fast recovery diode.
  • Passive devices may include at least one of resistors, capacitors, inductors and fuses.
  • the plurality of device regions 8 includes at least one (one in this embodiment) transistor region 9 (see region II in FIG. 1).
  • Transistor region 9 includes FET structures 10 (transistor structures).
  • the FET structure 10 in this form has a so-called LDMISFET (Lateral Double diffused MISFET) structure.
  • the FET structure 10, in this embodiment consists of a high voltage device capable of applying a drain voltage of 800 V or higher in the off state.
  • the structure of the transistor region 9 side will be specifically described below.
  • semiconductor device 1A includes p-type separation region 11 as an example of a region separation structure that partitions transistor region 9 on first main surface 3. )including.
  • the isolation region 11 is formed in an annular shape surrounding part of the first main surface 3 in plan view, and partitions the transistor region 9 having a predetermined shape.
  • the isolation region 11 electrically isolates the transistor region 9 from other regions (the device region 8).
  • the isolation region 11 is formed in a quadrangular ring shape (specifically, a rectangular ring shape extending in the second direction Y) in plan view, and is formed in a square shape (specifically, a rectangular shape extending in the second direction Y) by the inner edge. partitions the transistor region 9 of .
  • the planar shape of the isolation region 11 (the planar shape of the transistor region 9) is arbitrary.
  • the isolation region 11 extends like a wall from the first main surface 3 toward the second semiconductor region 7 across the first semiconductor region 6 and is electrically connected to the second semiconductor region 7 . That is, the isolation region 11 is fixed at the backgate potential.
  • the isolation region 11 includes a first isolation region 12, a second isolation region 13 and a third isolation region 14 in this form.
  • the first isolation region 12 is formed at the boundary between the first semiconductor region 6 and the second semiconductor region 7 .
  • the first separation region 12 is spaced apart from the first main surface 3 and the second main surface 4 in the normal direction Z, and is electrically connected to the second semiconductor region 7 .
  • the first isolation region 12 has a p-type impurity concentration higher than that of the second semiconductor region 7 .
  • the second isolation region 13 is formed in a region between the first main surface 3 and the first isolation region 12 in the first semiconductor region 6 and electrically connected to the first isolation region 12 .
  • the second isolation region 13 may have a p-type impurity concentration lower than that of the first isolation region 12 .
  • the third isolation region 14 is formed in the surface layer portion of the second isolation region 13 and exposed from the first main surface 3 .
  • the third isolation region 14 may have a p-type impurity concentration higher than that of the second isolation region 13 .
  • the semiconductor device 1A includes an n-type impurity region 15 formed in the surface layer portion of the first main surface 3 in the transistor region 9. As shown in FIG. Impurity region 15 is formed using a portion of first semiconductor region 6 partitioned by isolation region 11 in this embodiment. Therefore, the impurity region 15 has an n-type impurity concentration equal to the n-type impurity concentration of the first semiconductor region 6 .
  • the semiconductor device 1A includes an n-type well region 16 formed in the surface layer portion of the impurity region 15 .
  • Well region 16 is fixed at the drain potential.
  • Well region 16 is formed inside impurity region 15 .
  • Well region 16 has a higher n-type impurity concentration than impurity region 15 .
  • well region 16 is formed in an oval shape extending along impurity region 15 in plan view.
  • Well region 16 may be circular, elliptical, or polygonal (for example, square) in plan view.
  • the semiconductor device 1A includes an n-type drain region 17 formed in the surface layer portion of the well region 16 .
  • the drain region 17 is fixed at the drain potential. Drain region 17 has a higher n-type impurity concentration than well region 16 .
  • the drain region 17 is formed inside the well region 16 apart from the periphery of the well region 16 . Drain region 17 is formed in an oval shape extending along well region 16 in plan view. Drain region 17 may be circular, elliptical, or polygonal (for example, square) in plan view.
  • the semiconductor device 1A includes an n-type buried region 18 formed inside the chip 2 so as to cross the bottom of the impurity region 15 .
  • the embedded region 18 is formed at the boundary between the second semiconductor region 7 and the impurity region 15 below the well region 16 .
  • Buried region 18 has a higher n-type impurity concentration than impurity region 15 .
  • Buried region 18 preferably has a higher n-type impurity concentration than well region 16 .
  • the buried region 18 is spaced apart from the bottom of the well region 16 in the normal direction Z, and faces the well region 16 with a part of the impurity region 15 interposed therebetween. It is preferable that the buried region 18 is formed spaced inwardly from the periphery of the well region 16 in plan view.
  • the embedded region 18 preferably has an area smaller than that of the well region 16 in plan view.
  • the semiconductor device 1A includes a p-type body region 19 formed in the surface layer portion of the first main surface 3 apart from the well region 16 in the transistor region 9 .
  • body region 19 extends like a wall from first main surface 3 toward second semiconductor region 7 across impurity region 15 and is electrically connected to second semiconductor region 7 . That is, body region 19 is fixed at the back gate potential.
  • the body region 19 includes a first body region 20 and a second body region 21 in this form.
  • the first body region 20 is formed at the boundary between the second semiconductor region 7 and the impurity region 15 .
  • the first body region 20 is spaced apart from the first main surface 3 and the second main surface 4 with respect to the normal direction Z, and is electrically connected to the second semiconductor region 7 .
  • the first body region 20 has a p-type impurity concentration higher than that of the second semiconductor region 7 .
  • the second body region 21 is formed in a region between the first main surface 3 and the first body region 20 and electrically connected to the first body region 20 . Second body region 21 is exposed from first main surface 3 . Second body region 21 has a lower p-type impurity concentration than first body region 20 .
  • the body region 19 is formed in an annular shape (elliptic ring in this embodiment) surrounding the drain region 17 (well region 16) in plan view, and has a portion extending in the first direction X and a portion extending in the second direction Y. have.
  • body region 19 includes a first region 19A, a second region 19B, a third region 19C and a fourth region 19D in plan view.
  • First to fourth regions 19A to 19D of body region 19 are formed by first body region 20 and second body region 21 .
  • the first region 19A is a portion extending in a strip shape in the second direction Y away from the drain region 17 (well region 16) to one side in the first direction X in plan view.
  • the second region 19B is a portion extending in the second direction Y in a strip shape away from the drain region 17 (well region 16) to the other side in the first direction X in plan view.
  • the second region 19B extends parallel to the first region 19A in plan view, and faces the first region 19A in the first direction X with the drain region 17 (well region 16) interposed therebetween.
  • the lengths of the first region 19A and the second region 19B are preferably equal to or shorter than the length of the drain region 17 .
  • the third region 19C is a portion extending in the first direction X in a band shape so as to connect one end of the first region 19A and one end of the second region 19B in plan view.
  • the third region 19C extends in an arc band shape between one end of the first region 19A and one end of the second region 19B in plan view.
  • the third region 19C may be formed in the shape of a straight strip extending in the first direction X.
  • the fourth region 19D is a portion extending in the first direction X in a strip shape so as to connect the other end of the first region 19A and the other end of the second region 19B in plan view.
  • the fourth region 19D extends in an arc band shape between the other end of the first region 19A and the other end of the second region 19B in plan view.
  • the fourth region 19D may be formed in the shape of a straight belt extending in the first direction X.
  • the semiconductor device 1A includes at least one (in this embodiment, a plurality) n-type source regions 22 formed on the surface layer of the first main surface 3 apart from the drain region 17 .
  • the plurality of source regions 22 are fixed at source potential.
  • each of the plurality of source regions 22 is formed so as to be fixed at the source potential when the source potential is individually applied from the outside of the chip 2 .
  • the source potential is applied to the multiple source regions 22 independently of the back gate potential.
  • the source potential may be a reference potential, a ground potential, or any other potential.
  • Source region 22 has a higher n-type impurity concentration than well region 16 .
  • the n-type impurity concentration of the source region 22 is preferably equal to the n-type impurity concentration of the drain region 17 .
  • the plurality of source regions 22 are formed in the surface layer portion of the body region 19 while being spaced inwardly from the periphery of the body region 19 .
  • the plurality of source regions 22 are each formed in a strip shape with ends in a partial region of the body region 19 in plan view.
  • the plurality of source regions 22 are formed in the surface layer portion of the first region 19A and the surface layer portion of the second region 19B, respectively, and are not formed in the third region 19C and the fourth region 19D.
  • the plurality of source regions 22 each extend in an edged band shape along the first region 19A and the second region 19B in plan view.
  • the plurality of source regions 22 face the drain region 17 in the first direction X.
  • the length of each source region 22 is preferably less than or equal to the length of the drain region 17 .
  • a single annular (specifically, oval annular) source region 22 may be formed surrounding the impurity region 15 .
  • one or more source regions 22 may be formed in at least one of the first region 19A, the second region 19B, the third region 19C and the fourth region 19D of the body region 19. FIG.
  • the semiconductor device 1A includes an n-type drift region 23 formed in a region on the drain region 17 side between the drain region 17 and the source region 22 in the surface layer portion of the first main surface 3 .
  • drift region 23 is formed in a region between drain region 17 and body region 19 in the surface layer portion of impurity region 15 and forms a current path connecting drain region 17 and source region 22 .
  • the drift region 23 is formed in an annular shape (elliptic annular shape in this embodiment) surrounding the drain region 17 .
  • the drift region 23 includes a first portion (straight portion) linearly partitioned extending in the second direction Y by the first region 19A (second region 19B) of the body region 19, and a It has a second portion (arc portion) partitioned in an arc shape by the third region 19C (fourth region 19D).
  • Drift region 23 forms a current path in a portion of body region 19 along first region 19A (second region 19B), and forms a current path in a portion of body region 19 along third region 19C (fourth region 19D). do not form
  • the width of the drift region 23 may be 50 ⁇ m or more and 200 ⁇ m or less.
  • the width of drift region 23 is the distance between drain region 17 and body region 19 .
  • the width of the drift region 23 may be formed with a substantially constant width along the ring (elliptical ring in this form).
  • the width of the arc portion of the drift region 23 may gradually increase from the straight portion toward the arc central portion. In this case, the linear portion of the drift region 23 may be formed with a substantially constant width.
  • the semiconductor device 1A includes a p-type channel region 24 formed in a region on the source region 22 side between the drain region 17 and the source region 22 in the surface layer portion of the first main surface 3 .
  • channel region 24 is formed in a region between source region 22 and drift region 23 in the surface layer portion of body region 19 .
  • Channel region 24 controls conduction and non-conduction of the current path between drain region 17 and source region 22 .
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) p-type back gate region 25 formed in a region different from the drain region 17 and the source region 22 in the surface layer portion of the first main surface 3 .
  • a plurality of back gate regions 25 are fixed to the back gate potential.
  • each of the plurality of back gate regions 25 is formed so as to be fixed to the back gate potential by individually applying the back gate potential from the outside of the chip 2 . That is, the back gate potential is applied to the plurality of back gate regions 25 independently of the source potential.
  • the plurality of back gate regions 25 are formed in regions different from the source region 22 in the surface layer portion of the body region 19 . More specifically, the plurality of back gate regions 25 are formed in regions of the surface layer of the body region 19 on the opposite side of the source region 22 to the drain region 17 . A plurality of back gate regions 25 are formed spaced inwardly from the periphery of body region 19 .
  • First back gate region 61 has a higher p-type impurity concentration than body region 19 .
  • the plurality of back gate regions 25 are each formed in a strip shape with ends in a partial region of the body region 19 in plan view. Specifically, the plurality of back gate regions 25 are formed in the surface layer portion of the first region 19A and the surface layer portion of the second region 19B, respectively, and are not formed in the third region 19C and the fourth region 19D. The plurality of back gate regions 25 each extend in an edged band shape along the first region 19A and the second region 19B in plan view.
  • the plurality of back gate regions 25 are each connected to the source region 22 in the first direction X in this form. That is, in this embodiment, the source region 22 to which the source potential is individually applied and the back gate region 25 to which the back gate potential is individually applied coexist on the surface layer of the body region 19 .
  • each back gate region 25 is preferably equal to or less than the length of the drain region 17 .
  • a single annular (specifically, oval annular) back gate region 25 may be formed surrounding the impurity region 15 .
  • one or more back gate regions 25 may be formed in at least one of the first region 19A, the second region 19B, the third region 19C and the fourth region 19D of the body region 19. .
  • the semiconductor device 1A includes a field insulating film 30 selectively covering the first main surface 3 in the transistor region 9.
  • FIG. Field insulating film 30 contains silicon oxide.
  • the field insulating film 30 is made of a LOCOS film (local oxidation of silicon film) formed by selective oxidation of the first main surface 3 in this embodiment.
  • Field insulating film 30 may have a thickness of 0.1 ⁇ m or more and 2 ⁇ m or less.
  • Field insulating film 30 selectively covers first main surface 3 so as to expose isolation region 11 , drain region 17 , source region 22 and back gate region 25 .
  • the field insulating film 30 has a portion covering the region between the drain region 17 and the source region 22 on the first main surface 3 .
  • the field insulating film 30 is formed in an annular shape (in this form, an oval annular shape) surrounding the drain region 17 so as to expose the drain region 17 and the body region 19 in plan view. That is, the field insulating film 30 covers the drift region 23 so as to expose the channel region 24 .
  • the field insulating film 30 has a portion covering the region between the isolation region 11 and the source region 22 on the first main surface 3 .
  • field insulating film 30 is formed in a ring shape surrounding body region 19 between isolation region 11 and body region 19 so as to expose isolation region 11 , source region 22 and back gate region 25 . ing. Further, the field insulating film 30 covers the region outside the transistor region 9 so as to expose the isolation region 11 on the first main surface 3 .
  • semiconductor device 1A includes field electrode 31 arranged on field insulating film 30 in transistor region 9 .
  • Field electrode 31 may include conductive polysilicon (n-type or p-type polysilicon).
  • the field electrode 31 consists of a field resistance film electrically connected to the drain region 17 and the back gate region 25 in this form.
  • Field electrode 31 is electrically isolated from source region 22 .
  • the field electrode 31 forms a potential gradient from the drain region 17 toward the back gate region 25 and suppresses uneven distribution of the electric field in the drift region 23 .
  • the field electrode 31 is drawn in a line on the field insulating film 30 .
  • the field electrode 31 extends in a line shape so as to cross the straight line multiple times.
  • the field electrode 31 concentrically surrounds the drain region 17 multiple times in plan view. More specifically, the field electrode 31 is spirally routed around the drain region 17 in plan view.
  • the field electrode 31 has a first end portion 32 (first portion) on the drain region 17 side, a second end portion 33 (second portion) on the back gate region 25 (body region 19) side, and the first end portion 32 and a spiral portion 34 extending between the second end 33 .
  • the first end portion 32 is a connection portion (electrical application end) electrically connected to the drain region 17 (drain potential), and the second end portion 33 is electrically connected to the back gate region 25 (back gate potential). is the connection part (electrical application end) connected to the . That is, the field electrode 31 is electrically separated from the source region 22 (source potential).
  • the arrangement of the first end portion 32 and the second end portion 33 is arbitrary.
  • the first end portion 32 is arranged at a position facing the drain region 17 in the first direction X in this embodiment.
  • the first end portion 32 may face the well region 16 with the field insulating film 30 interposed therebetween.
  • the second end 33 is arranged at a position facing the source region 22 in the first direction X in this embodiment.
  • the second end 33 may face the impurity region 15 with the field insulating film 30 interposed therebetween.
  • the spiral portion 34 is wound in an oval spiral shape from the first end portion 32 toward the second end portion 33 so as to surround the drain region 17 in plan view.
  • the spiral portion 34 faces the drift region 23 with the field insulating film 30 interposed therebetween.
  • the field electrode 31 forms a potential gradient in the spiral direction from the first end 32 to the second end 33 . Further, the field electrode 31 forms a potential gradient that gradually decreases from the drain region 17 toward the back gate region 25 (body region 19) according to the winding pitch of the spiral portion 34 in the direction orthogonal to the spiral direction. The field electrode 31 thins out the electric field in the drift region 23 and suppresses the uneven distribution of the electric field in the drift region 23 .
  • the field electrode 31 may have a line width of 1 ⁇ m or more and 5 ⁇ m or less.
  • the line width is defined by the width in the direction perpendicular to the direction in which the field electrodes 31 extend (that is, the spiral direction).
  • the line width is preferably 3 ⁇ m or less.
  • Field electrode 31 may have a resistance value of 10 M ⁇ or more and 100 M ⁇ or less.
  • the field electrode 31 may be formed with a substantially constant line width in the linear portion and arc portion. Further, for example, when the width of the drift region 23 gradually increases toward the center of the arc, the line width of the field electrode 31 may gradually increase from the straight portion toward the center of the arc.
  • the pitch of the field electrodes 31 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the pitch of the field electrodes 31 is preferably 2 ⁇ m or more.
  • the pitch of the field electrodes 31 is defined by the distance between adjacent line portions (that is, the winding pitch of the spiral portion 34).
  • the number of turns of the field electrode 31 may be 5 or more and 100 or less (preferably 25 or more and 75 or less).
  • the semiconductor device 1A includes an inner field electrode 35 arranged on the field insulating film 30 in a region closer to the drain region 17 than the field electrode 31 is.
  • the inner field electrode 35 is arranged in a region surrounded by the field electrode 31 and fixed at the same potential as the drain region 17 (drain region 17).
  • Inner field electrode 35 has approximately the same thickness as field electrode 31 and comprises the same material as field electrode 31 (ie, conductive polysilicon).
  • the inner field electrode 35 is arranged in a region between the drain region 17 and the field electrode 31 with a gap from the drain region 17 and the field electrode 31 in plan view.
  • the inner field electrode 35 is formed in an annular shape (specifically, an oval annular shape) surrounding the drain region 17 .
  • the inner field electrode 35 may face the well region 16 with the field insulating film 30 interposed therebetween.
  • the inner field electrode 35 includes an inner edge portion 35a and an outer edge portion 35b. It is preferable that the inner edge portion 35a be spaced apart from the drain region 17 by a substantially constant distance. It is preferable that the outer edge portion 35b be spaced from the field electrode 31 at a substantially constant interval. The distance between the inner field electrodes 35 and the field electrodes 31 is preferably equal to the pitch of the field electrodes 31 .
  • the inner field electrode 35 is formed with a non-uniform width along the circumferential direction in this form. Specifically, the inner field electrode 35 has a field projecting portion 35c at the outer edge portion 35b. The field projecting portion 35 c projects toward the field electrode 31 so as to be close to the tip of the first end portion 32 of the field electrode 31 . The field projecting portion 35 c keeps the distance between the inner field electrode 35 and the field electrode 31 substantially constant, and suppresses the bias of the electric field caused by the first end portion 32 of the field electrode 31 .
  • the field projecting portion 35c is connected to the first end portion 32 of the field electrode 31 and fixed to the same potential as the first end portion 32 in this embodiment.
  • the inner field electrode 35 does not necessarily need to be connected to the first end 32 as long as it is fixed to the same potential as the first end 32 . Therefore, the field projecting portion 35 c may face the tip of the first end portion 32 in the spiral direction of the field electrode 31 .
  • the presence or absence of the inner field electrode 35 is optional, and may be removed as necessary.
  • the width of the inner field electrode 35 may be 1 ⁇ m or more and 15 ⁇ m or less.
  • the inner field electrode 35 is preferably formed wider than the field electrode 31 .
  • the width of the inner field electrode 35 is preferably 1.5 to 5 times the width of the field electrode 31 .
  • the inner field electrode 35 having a width equal to or less than the line width of the field electrode 31 may be formed.
  • the semiconductor device 1A includes a gate insulating film 36 that covers the channel region 24 on the first main surface 3 .
  • Gate insulating film 36 has a thickness less than the thickness of field insulating film 30 and is connected to field insulating film 30 .
  • the thickness of the gate insulating film 36 may be 10 nm or more and 200 nm or less.
  • the gate insulating film 36 may contain a silicon oxide film.
  • the gate insulating film 36 is formed in a strip shape extending along the channel region 24 in plan view.
  • the gate insulating film 36 is formed in a ring shape (specifically, an oval ring shape) surrounding the field insulating film 30 in plan view, and covers the drift region 23 , the body region 19 and the source region 22 .
  • the semiconductor device 1A includes a gate electrode 37 arranged on the gate insulating film 36 .
  • Gate electrode 37 has approximately the same thickness as field electrode 31 and may comprise the same material as field electrode 31 (ie, conductive polysilicon).
  • Gate electrode 37 may include either or both n-type and p-type regions in conductive polysilicon.
  • Gate electrode 37 faces drift region 23 and channel region 24 with gate insulating film 36 interposed therebetween.
  • the gate electrode 37 is formed in a strip shape extending along the channel region 24 in plan view.
  • the gate electrode 37 is formed in a ring shape (specifically, an oval ring shape) surrounding the field insulating film 30 in plan view.
  • the gate electrode 37 has a lead portion 38 that extends from above the gate insulating film 36 onto the field insulating film 30 .
  • the lead portion 38 is formed in an annular shape (specifically, an oval annular shape) surrounding the field electrode 31 with a space therebetween.
  • the lead-out portion 38 faces the drift region 23 with the field insulating film 30 interposed therebetween. It is preferable that the lead portion 38 be spaced from the field electrode 31 by a substantially constant distance. The distance between the lead-out portion 38 and the field electrodes 31 is preferably equal to the pitch of the field electrodes 31 .
  • the gate electrode 37 includes an inner edge portion 37a and an outer edge portion 37b.
  • the inner edge portion 37 a is formed by the lead portion 38 .
  • the outer edge portion 37b is formed in a region overlapping the body region 19 in plan view. It is preferable that the outer edge portion 37b be spaced from the outer edge portion 35b of the field insulating film 30 at a substantially constant interval.
  • the gate electrode 37 is formed with a non-uniform width along the circumferential direction in this embodiment. Specifically, the gate electrode 37 has a gate projecting portion 37c projecting toward the drain region 17 at the outer edge portion 37b (leading portion 38). The gate projecting portion 37 c projects toward the field electrode 31 so as to be close to the tip of the second end portion 33 in the spiral direction of the field electrode 31 .
  • the gate projecting portion 37 c faces the tip of the second end portion 33 in the spiral direction of the field electrode 31 .
  • the gate projecting portion 37 c keeps the distance between the gate electrode 37 and the field electrode 31 substantially constant, and suppresses the bias of the electric field caused by the second end portion 33 of the field electrode 31 .
  • semiconductor device 1A includes an insulating layer 40 covering a plurality of device regions 8 on first main surface 3 .
  • the insulating layer 40 has a laminated structure in which a plurality of interlayer insulating films 41 are laminated.
  • the number of laminated interlayer insulating films 41 is arbitrary, and is not limited to a specific numerical value.
  • the insulating layer 40 may include interlayer insulating films 41 of three or more layers. In FIG. 4, the first interlayer insulating film 41A and the second interlayer insulating film 41B among the plurality of interlayer insulating films 41 are shown.
  • the first interlayer insulating film 41A covers the first main surface 3, and the second interlayer insulating film 41B covers the first interlayer insulating film 41A.
  • Each interlayer insulating film 41 includes at least one of a silicon oxide film and a silicon nitride film.
  • Each interlayer insulating film 41 may have a single-layer structure made of a silicon oxide film or a silicon nitride film.
  • Each interlayer insulating film 41 may have a laminated structure in which at least one silicon oxide film and at least one silicon nitride film are laminated in any order.
  • the semiconductor device 1A includes a drain wiring 42 selectively routed within the insulating layer 40 so as to be electrically connected to the drain region 17 and the first end 32 of the field electrode 31 .
  • the drain wiring 42 applies a drain potential to the drain region 17 and the first end 32 of the field electrode 31 .
  • the drain wiring 42 forms a multilayer wiring within the insulating layer 40 .
  • the drain wiring 42 includes a first drain wiring 43, a second drain wiring 44, a first drain via electrode 45 and a second drain via electrode 46 in this form.
  • the first drain wiring 43 integrally includes a first drain wiring 43A on the drain region 17 side and a first drain wiring 43B on the first end 32 side of the field electrode 31 .
  • the first drain wiring 43A and the first drain wiring 43B may be spaced apart from each other as long as they are fixed at the same potential.
  • the first drain wiring 43 is arranged on the first interlayer insulating film 41A so as to face the drain region 17, the first end portion 32 of the field electrode 31 and the inner field electrode 35 in a cross-sectional view.
  • the first drain wiring 43 preferably faces the entire drain region 17 , the first end portion 32 , and the inner field electrode 35 in a cross-sectional view.
  • the second drain wiring 44 is arranged on the second interlayer insulating film 41B so as to face the first drain wiring 43 in a cross-sectional view.
  • the second drain wiring 44 is preferably drawn out to a position facing the inner field electrode 35 in a cross-sectional view.
  • the second drain wiring 44 is preferably drawn out to a position facing the first end 32 of the field electrode 31 in a cross-sectional view. It is particularly preferable that the second drain wiring 44 is drawn out to a position facing the spiral portion 34 of the field electrode 31 in a cross-sectional view.
  • the second drain wiring 44 may have a thickness exceeding the thickness of the first drain wiring 43 .
  • the first drain via electrode 45 is interposed in the region between the drain region 17 and the first drain wiring 43 and electrically connects the drain region 17 to the first drain wiring 43 . Also, the first drain via electrode 45 is interposed in a region between the first end 32 of the field electrode 31 and the first drain wiring 43 to electrically connect the first end 32 to the first drain wiring 43 .
  • first drain via electrode 45 may be interposed in the region of the inner field electrode 35 and the first drain wiring 43 to electrically connect the inner field electrode 35 to the first drain wiring 43 .
  • the second drain via electrode 46 is interposed in a region between the first drain wiring 43 and the second drain wiring 44 and electrically connects the first drain wiring 43 to the second drain wiring 44 .
  • the semiconductor device 1A includes a source wiring 47 selectively routed within the insulating layer 40 apart from the drain wiring 42 so as to be electrically connected to the source region 22 .
  • the source wiring 47 applies a source potential to the source region 22 .
  • Source wiring 47 is electrically isolated from back gate region 25 . Also, the source wiring 47 is electrically separated from the isolation region 11 .
  • the source wiring 47 forms a multilayer wiring within the insulating layer 40 .
  • the source wiring 47 includes a first source wiring 48 , a second source wiring 49 , a first source via electrode 50 and a second source via electrode 51 .
  • the first source wiring 48 is arranged on the first interlayer insulating film 41A so as to face the source region 22 in a cross-sectional view.
  • the first source wiring 48 preferably faces the entire source region 22 in a cross-sectional view. It is preferable that the first source wiring 48 does not face the back gate region 25 in a cross-sectional view.
  • the second source wiring 49 is arranged on the second interlayer insulating film 41B so as to face the first source wiring 48 in a cross-sectional view.
  • the second source wiring 49 preferably covers the entire source region 22 in a cross-sectional view.
  • the second source wiring 49 is preferably drawn across the gate electrode 37 to a position facing the second end 33 of the inner field electrode 35 in a cross-sectional view. It is particularly preferable that the second source wiring 49 is drawn out to a position facing the spiral portion 34 of the inner field electrode 35 in a cross-sectional view.
  • the second source wiring 49 may have a thickness exceeding the thickness of the first source wiring 48 .
  • the first source via electrode 50 is interposed in the region between the source region 22 and the first source wiring 48 and electrically connects the source region 22 to the first source wiring 48 .
  • the second source via electrode 51 is interposed in a region between the first source wiring 48 and the second source wiring 49 and electrically connects the first source wiring 48 to the second source wiring 49 .
  • Semiconductor device 1A is selectively routed in insulating layer 40 away from drain wiring 42 and source wiring 47 so as to be electrically connected to back gate region 25 and second end portion 33 of field electrode 31 . and a back gate wiring 52 .
  • the back gate wiring 52 is also electrically connected to the isolation region 11 in this form.
  • the back gate wiring 52 is electrically separated from the source region 22 .
  • the back gate wiring 52 forms a multilayer wiring within the insulating layer 40 .
  • the back gate wiring 52 includes a first back gate wiring 53 , a second back gate wiring 54 , a first back gate via electrode 55 and a second back gate via electrode 56 .
  • the first back gate wiring 53 includes a first back gate wiring 53A on the back gate region 25 side, a first back gate wiring 53B on the second end portion 33 side of the field electrode 31, and a first back gate wiring 53B on the isolation region 11 side. It integrally includes wiring 53C.
  • the first back gate wiring 53A, the first back gate wiring 53B, and the first back gate wiring 53C may be spaced apart from each other as long as they are fixed at the same potential.
  • the first back gate wiring 53 is formed on the first interlayer insulating film 41A with a space from the source region 22 .
  • the first back gate wiring 53 faces the back gate region 25, the second end portion 33 of the field electrode 31 and the isolation region 11 in a cross-sectional view.
  • the first back gate wiring 53 preferably faces the entire back gate region 25 in a cross-sectional view.
  • the first back gate wiring 53 may face the spiral portion 34 of the field electrode 31 .
  • the first back gate wiring 53 may be drawn out to a region outside the transistor region 9 in plan view.
  • the second back gate wiring 54 is arranged on the second interlayer insulating film 41B so as to face the first back gate wiring 53 in a region outside the transistor region 9 in plan view.
  • the second back gate wiring 54 may be arranged so as to face the first back gate wiring 53 in the transistor region 9 in plan view.
  • the second back gate wiring 54 may have a thickness exceeding the thickness of the first back gate wiring 53 .
  • the first back gate via electrode 55 is interposed in a region between the back gate region 25 and the first back gate wiring 53 and electrically connects the back gate region 25 to the first back gate wiring 53 . Also, the first back gate via electrode 55 is interposed in a region between the second end 33 of the field electrode 31 and the first back gate wiring 53 to connect the second end 33 of the field electrode 31 to the first back gate wiring. 53 is electrically connected.
  • first back gate via electrode 55 is interposed in the region between the isolation region 11 and the first back gate wiring 53 and electrically connects the isolation region 11 to the first back gate wiring 53 .
  • the second back gate via electrode 56 is interposed in a region between the first back gate wiring 53 and the second back gate wiring 54 to electrically connect the first back gate wiring 53 to the second back gate wiring 54.
  • Semiconductor device 1 ⁇ /b>A includes gate wiring 57 selectively routed within insulating layer 40 away from drain wiring 42 , source wiring 47 and back gate wiring 52 so as to be electrically connected to gate electrode 37 . .
  • the gate wiring 57 applies a gate potential to the gate electrode 37 .
  • the gate wiring 57 forms a multilayer wiring within the insulating layer 40 .
  • the gate wiring 57 includes a first gate wiring 58, a second gate wiring (not shown), a first gate via electrode 59 and a second gate via electrode (not shown).
  • the first gate wiring 58 is arranged on the first interlayer insulating film 41A so as to face the gate electrode 37 in a cross-sectional view.
  • the first gate wiring 58 is drawn out to a region outside the transistor region 9 in plan view.
  • the second gate wiring (not shown) is arranged on the second interlayer insulating film 41B so as to face the first gate wiring 58 in a region outside the transistor region 9 in plan view.
  • the second gate wiring may have a thickness exceeding the thickness of the first gate wiring 58 .
  • the first gate via electrode 59 is interposed in a region between the gate electrode 37 and the first gate wiring 58 and electrically connects the gate electrode 37 to the first gate wiring 58 .
  • a second gate via electrode (not shown) is interposed in a region between the first gate line 58 and the second gate line, electrically connecting the first gate line 58 to the second gate line.
  • FIG. 5 is a circuit diagram showing the electrical structure (FET structure 10 and field electrode 31) within transistor region 9.
  • semiconductor device 1A includes FET structure 10 and resistor R in transistor region 9 .
  • FET structure 10 includes drain D (drain region 17), source S (source region 22), back gate BG (back gate region 25) and gate G (gate insulating film 36 and gate electrode 37).
  • the resistor R consists of the field electrode 31 and is electrically connected to the drain D and the back gate BG. Resistor R is not connected to drain D and source S. Resistor R is not connected to drain D and gate G; Resistor R is not connected to source S and gate G of FET structure 10 .
  • transistor region 9 only the FET structure 10 and the resistor R are formed within the transistor region 9 . That is, no other functional device connected between drain D and source S is formed in transistor region 9 . Also, no other functional device connected between drain D and gate G is formed in transistor region 9 . Also, no other functional device connected between source S and gate G is formed within transistor region 9 .
  • the drain potential, the source potential, the backgate potential and the gate potential are applied to the drain D (drain region 17), the source S (source region) from the region outside the transistor region 9 (including the region outside the semiconductor device 1A). 22), back gate BG (back gate region 25) and gate G (gate electrode 37), respectively. That is, the FET structure 10 is configured such that a source potential is individually applied to the source S (source region 22) and a back gate potential is individually applied to the back gate BG (back gate region 25). .
  • the drain potential may be the power supply potential.
  • the source potential is less than or equal to the drain potential.
  • the source potential may be a reference potential, a ground potential, or any other potential.
  • the back gate potential is lower than the drain potential.
  • the back gate potential may be a reference potential, a ground potential, or a potential other than these. It is not prevented that the back gate potential becomes the same potential as the source potential. That is, while the back gate region 25 is electrically isolated from the source region 22 inside the chip 2, the back gate region 25 may be fixed at the same potential as the source region 22 by external potential control.
  • the semiconductor device 1A includes the chip 2 , the n-type drain region 17 , the n-type source region 22 , the p-type back gate region 25 , the gate insulating film 36 and the gate electrode 37 .
  • Chip 2 has a first main surface 3 .
  • the drain region 17 is formed in the surface layer portion of the first main surface 3 .
  • the source region 22 is formed in a region different from the drain region 17 in the surface layer portion of the first main surface 3 .
  • the back gate region 25 is formed in a region different from the drain region 17 and the source region 22 in the surface layer portion of the first main surface 3 .
  • Back gate region 25 is electrically isolated from drain region 17 and source region 22 .
  • a gate insulating film 36 covers the source region 22 .
  • the gate electrode 37 faces the source region 22 with the gate insulating film 36 interposed therebetween.
  • a source potential electrically independent from the back gate region 25 can be applied to the source region 22 , and at the same time, a back gate potential electrically independent from the source region 22 can be applied to the back gate region 25 . Accordingly, it is possible to provide the semiconductor device 1A having a novel configuration in which the gate threshold voltage Vth can be finely adjusted by finely adjusting the source potential.
  • semiconductor device 1A preferably includes field insulating film 30 and field electrode 31 .
  • Field insulating film 30 covers the region between drain region 17 and source region 22 on first main surface 3 .
  • a field electrode 31 is arranged on the field insulating film 30 . According to this structure, the gate threshold voltage Vth can be finely adjusted in the structure including the field insulating film 30 and the field electrode 31 .
  • the field electrode 31 is preferably electrically separated from the source region 22. According to this structure, a source potential electrically independent of the field electrode 31 can be applied to the source region 22 . This can suppress the potential of the field electrode 31 from acting on the source region 22 .
  • field electrode 31 is preferably electrically connected to drain region 17 and back gate region 25 . According to this structure, a potential difference between the potential of the drain region 17 and the potential of the back gate region 25 is generated in the field electrode 31 . Thereby, the field electrode 31 can adjust the electric field distribution between the drain region 17 and the back gate region 25 while maintaining the independence of the source potential applied to the source region 22 .
  • FIG. 6 is an enlarged plan view showing a semiconductor device 1B according to the second embodiment, corresponding to FIG.
  • FIG. 7 is a cross-sectional perspective view of area VII shown in FIG. 6 and 7, semiconductor device 1B has a modified form of semiconductor device 1A.
  • the semiconductor device 1B does not include the back gate region 25 in the surface layer portion of the body region 19 and includes only the plurality of source regions 22 .
  • a plurality of source regions 22 are formed in the same form as in the first embodiment.
  • the semiconductor device 1B includes a p-type back gate region 25 formed in the surface layer portion of the first main surface 3 apart from the drain region 17 and the source region 22 in the transistor region 9 .
  • back gate region 25 is formed in a region between isolation region 11 and body region 19 while being spaced apart from isolation region 11 and body region 19 .
  • back gate region 25 extends like a wall from first main surface 3 toward second semiconductor region 7 across impurity region 15 and is electrically connected to second semiconductor region 7 .
  • the back gate region 25 includes a first back gate region 61, a second back gate region 62 and a third back gate region 63 in this form.
  • a first back gate region 61 is formed at the boundary between the second semiconductor region 7 and the impurity region 15 .
  • the first back gate region 61 is spaced apart from the first main surface 3 and the second main surface 4 in the normal direction Z, and is electrically connected to the second semiconductor region 7 .
  • the first back gate region 61 has a p-type impurity concentration higher than that of the second semiconductor region 7 .
  • the second back gate region 62 is formed in the impurity region 15 between the first main surface 3 and the first back gate region 61 and electrically connected to the first back gate region 61 .
  • the second back gate region 62 may have a p-type impurity concentration lower than that of the first back gate region 61 .
  • the third back gate region 63 is formed in the surface layer portion of the second back gate region 62 and exposed from the first main surface 3 .
  • the third back gate region 63 may have a p-type impurity concentration higher than that of the second back gate region 62 .
  • the back gate region 25 is formed in an annular shape surrounding the body region 19 in plan view, and has a portion extending in the first direction X and a portion extending in the second direction Y. As shown in FIG. In this embodiment, the back gate region 25 is formed in a square annular shape (specifically, a rectangular annular shape extending in the second direction Y) in plan view. That is, in this embodiment, the back gate region 25 has a planar shape that matches the planar shape of the separation region 11 in plan view, but has a planar shape that does not match the planar shape of the body region 19 .
  • the back gate region 25 includes a first region 25A, a second region 25B, a third region 25C and a fourth region 25D in plan view.
  • the first to fourth regions 25A to 25D of the back gate region 25 are formed by a first back gate region 61, a second back gate region 62 and a third back gate region 63. As shown in FIG.
  • the first region 25A is a portion extending in a strip shape in the second direction Y away from the first region 19A of the body region 19 to one side in the first direction X in plan view.
  • the second region 25B is a portion extending in the second direction Y in a strip shape away from the second region 19B of the body region 19 to the other side in the first direction X in plan view.
  • the second region 25B extends parallel to the first region 25A in plan view, and faces the first region 25A in the first direction X with the drain region 17 (well region 16) interposed therebetween. With respect to the second direction Y, the lengths of the first region 25A and the second region 25B may exceed the length of the drain region 17 .
  • the third region 25C is a portion extending in the first direction X in a linear belt shape so as to connect one end of the first region 25A and one end of the second region 25B in plan view.
  • the fourth region 25D is a portion extending linearly in the first direction X so as to connect the other end of the first region 25A and the other end of the second region 25B in plan view.
  • the back gate region 25 may have a planar shape that matches the planar shape of the body region 19 . That is, the third region 25C of the back gate region 25 may extend in an arc band shape along the third region 19C of the body region 19 in plan view. Further, the fourth region 25D of the back gate region 25 may extend in an arc band shape along the fourth region 19D of the body region 19 in plan view.
  • the semiconductor device 1B includes a p-type surface layer region 64 (surficial region) formed in a region between the body region 19 and the back gate region 25 in the surface layer portion of the first main surface 3 .
  • the surface region 64 is formed spaced from the bottom of the impurity region 15 toward the first main surface 3 side. That is, the surface layer region 64 is formed shallower than the body region 19 and the back gate region 25 and is not connected to the second semiconductor region 7 .
  • the surface region 64 may be formed shallower than the second body region 21 and the second back gate region 62 .
  • the surface layer region 64 may be connected to either or both of the body region 19 and the back gate region 25 .
  • Surface layer region 64 is formed in the entire region between body region 19 and back gate region 25 in this embodiment, and is connected to both body region 19 and back gate region 25 .
  • the surface layer region 64 is connected to the source region 22 and the back gate region 25 in this form.
  • Surface layer region 64 suppresses channel inversion in the region between body region 19 and back gate region 25 .
  • the surface region 64 includes a first surface region 65 and a second surface region 66 in this form.
  • the first surface layer region 65 has a p-type impurity concentration higher than that of the second body region 21 and is formed in the surface layer portion of the first main surface 3 .
  • the first surface layer region 65 may have a p-type impurity concentration higher than that of the second back gate region 62 .
  • the first surface layer region 65 is connected to the second body region 21 and the second back gate region 62 .
  • the first surface layer region 65 is connected to the source region 22 within the second body region 21 (body region 19 ) and is connected to the third back gate region 63 within the second back gate region 62 .
  • the second surface layer region 66 has a p-type impurity concentration lower than that of the first surface layer region 65, and is formed in a region between the first surface layer region 65 and the bottom side (second main surface 4 side) of the first semiconductor region 6. It is The second surface layer region 66 is connected to the second body region 21 and the second back gate region 62 .
  • the second surface region 66 may have substantially the same p-type impurity concentration as the second body region 21 and/or the third back gate region 63 .
  • the second surface region 66 may be formed using part of the second body region 21 and/or part of the third back gate region 63 . That is, the second surface layer region 66 may be formed integrally with one or both of the second body region 21 and the third back gate region 63 .
  • the field insulating film 30 described above has a portion covering the region between the source region 22 and the back gate region 25 on the first main surface 3 in this form. Specifically, the field insulating film 30 is formed in a ring shape that covers the entire surface layer region 64 in plan view and surrounds the source region 22 (body region 19) so as to expose the source region 22 and the back gate region 25. ing.
  • the field insulating film 30 has a portion covering the region between the isolation region 11 and the back gate region 25 on the first main surface 3 .
  • field insulating film 30 is formed in a ring shape surrounding back gate region 25 so as to expose isolation region 11 and back gate region 25 .
  • the drain wiring 42 described above has the same form as in the first embodiment, and is electrically connected to the drain region 17 and the first end 32 of the field electrode 31 .
  • the aforementioned source wiring 47 has the same form as in the first embodiment and is electrically connected to the source region 22 .
  • the back gate wiring 52 described above has the same form as in the first embodiment, and is electrically connected to the isolation region 11 , the back gate region 25 and the second end 33 of the field electrode 31 .
  • the gate wiring 57 described above has the same form as in the first embodiment and is electrically connected to the gate electrode 37 .
  • the semiconductor device 1B also has the same effect as described for the semiconductor device 1A.
  • back gate region 25 is formed spaced apart from source region 22 (body region 19). Therefore, according to this structure, the action of the source potential on the back gate region 25 can be suppressed, and the action of the back gate potential on the source region 22 can be suppressed. Therefore, a source potential can be stably applied to the source region 22 and a back gate potential can be stably applied to the back gate region 25 .
  • field electrode 31 made of a field resistive film was shown.
  • a field electrode 31 that is electrically isolated from the drain region 17, the source region 22 and the back gate region 25 and does not function as a field resistance film may be employed.
  • field electrode 31 may be formed in an electrically floating state.
  • the well region 16 extending in the second direction Y in a strip shape was formed in plan view.
  • the well region 16 may be formed in an annular shape (for example, an oval shape extending in the second direction Y) in plan view.
  • the drain region 17 may be formed in an annular shape (oval annular shape) extending along the well region 16 in plan view.
  • the first conductivity type was the n-type and the second conductivity type was the p-type.
  • the first conductivity type may be p-type and the second conductivity type may be n-type.
  • a specific configuration in this case is obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings.
  • a chip (2) having a main surface (3), a first conductivity type (n-type) drain region (17) formed in a surface layer portion of the main surface (3), and the main surface (3) ), a source region (22) of a first conductivity type (n-type) formed in a region different from the drain region (17) in the surface layer portion of the device, and an electric current from the drain region (17) and the source region (22).
  • a semiconductor device (1A, 1B) comprising:
  • the gate insulating film (36) is connected to the field insulating film (30), and the gate electrode (37) extends from above the gate insulating film (36) to above the field insulating film (30).
  • the semiconductor device (1A, 1B) according to any one of A2 to A6, having a lead-out portion (38) led out to the outside.
  • the semiconductor device (1A, 1B) according to any one of A1 to A11, further comprising:
  • the back gate wiring (52) is spaced apart from the drain wiring (42) and the source wiring (47) and is electrically connected to the drain wiring (42) and the source region (22).
  • the semiconductor device (1A, 1B) of A12 which is separated.
  • the drain wiring (42) faces the drain region (17) when viewed in cross section
  • the source wiring (47) faces the source region (22) when viewed in cross section
  • the back gate wiring (47) faces the source region (22) when viewed in cross section.
  • 52) is the semiconductor device (1A, 1B) according to A12 or A13, facing the back gate region (25) and not facing the source region (22) in a cross-sectional view.
  • the drain region (17) is formed in a strip shape or ring shape extending in one direction when viewed in plan
  • the source region (22) is formed in a strip shape extending in the one direction in plan view
  • the back gate region (25) is the semiconductor device (1A, 1B) according to any one of A1 to A14, which is formed in a band shape extending in the one direction in plan view.
  • [A16] further includes a first conductivity type (n-type) well region (16) formed in the surface layer of the main surface (3), wherein the drain region (17) is located within the well region (16)
  • A17 Any one of A1 to A16, further including a buried region (18) of a first conductivity type (n-type) formed apart from the drain region (17) in the thickness direction of the chip (2) 1.
  • the source region (22) further includes a body region (19) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3) at a distance from the drain region (17). ) is formed in the body region (19), and the back gate region (25) is formed in a region different from the source region (22) in the body region (19).
  • the semiconductor device (1A, 1B) according to any one of
  • p-type second conductivity type
  • [B1] has a semiconductor chip (2), a drain (D, 17), a source (S, 22), a gate (G, 36, 37) and a back gate (BG, 25), the source (S, 22) ) is individually applied with a source potential and the back gate (BG, 25) is individually provided with a back gate potential, and a transistor structure (10) formed on the semiconductor chip (2); , on the semiconductor chip (2) so as to be electrically disconnected from the source (S, 22) and electrically connected to the drain (D, 17) and the back gate (BG, 25). and a resistor (R, 31).
  • [B2] further comprising device regions (8, 9) provided in the semiconductor chip (2), wherein the transistor structure (10) is formed in the device regions (8, 9) and the resistor (R, 31)

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
PCT/JP2022/031398 2021-09-08 2022-08-19 半導体装置 Ceased WO2023037847A1 (ja)

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CN202280054850.2A CN117795687A (zh) 2021-09-08 2022-08-19 半导体装置
US18/592,203 US20240204062A1 (en) 2021-09-08 2024-02-29 Semiconductor device

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002094049A (ja) * 2000-09-11 2002-03-29 Hitachi Ltd 半導体集積回路装置およびその製造方法
US20020149067A1 (en) * 2001-04-12 2002-10-17 Mitros Jozef C. Isolated high voltage MOS transistor
JP2009038130A (ja) * 2007-07-31 2009-02-19 Mitsumi Electric Co Ltd 横型ｍｏｓトランジスタ及びこれを用いた半導体装置
JP2014203970A (ja) * 2013-04-04 2014-10-27 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP2017038022A (ja) * 2015-08-13 2017-02-16 ローム株式会社 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5070693B2 (ja) * 2005-11-11 2012-11-14 サンケン電気株式会社 半導体装置
US7851857B2 (en) * 2008-07-30 2010-12-14 Freescale Semiconductor, Inc. Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications
JP5637188B2 (ja) 2011-09-27 2014-12-10 株式会社デンソー 横型素子を有する半導体装置
WO2013075877A1 (en) 2011-11-23 2013-05-30 Crown Packaging Technology, Inc Method for sealing a metal cans with peelable lids and device therefor
JP7377147B2 (ja) 2020-03-24 2023-11-09 テルモ株式会社 台座及び保護キャップ組立体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002094049A (ja) * 2000-09-11 2002-03-29 Hitachi Ltd 半導体集積回路装置およびその製造方法
US20020149067A1 (en) * 2001-04-12 2002-10-17 Mitros Jozef C. Isolated high voltage MOS transistor
JP2009038130A (ja) * 2007-07-31 2009-02-19 Mitsumi Electric Co Ltd 横型ｍｏｓトランジスタ及びこれを用いた半導体装置
JP2014203970A (ja) * 2013-04-04 2014-10-27 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP2017038022A (ja) * 2015-08-13 2017-02-16 ローム株式会社 半導体装置

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