WO2023035615A1 - 一种多核测试处理器及集成电路测试系统与方法 - Google Patents

一种多核测试处理器及集成电路测试系统与方法 Download PDF

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WO2023035615A1
WO2023035615A1 PCT/CN2022/087319 CN2022087319W WO2023035615A1 WO 2023035615 A1 WO2023035615 A1 WO 2023035615A1 CN 2022087319 W CN2022087319 W CN 2022087319W WO 2023035615 A1 WO2023035615 A1 WO 2023035615A1
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test
processor
subsystem
main
test processor
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PCT/CN2022/087319
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French (fr)
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毛国梁
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南京宏泰半导体科技有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master

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  • the invention relates to an ATE (Auto Test Equipment) integrated circuit automatic testing equipment, which belongs to the field of semiconductor manufacturing, instrumentation, digital signal, mixed signal chip testing and memory chip testing.
  • ATE Auto Test Equipment
  • test processors in existing test equipment are all designed based on single-core test processors, and each test processor controls a certain number of test channels. Through the synchronous or asynchronous work of one or more single-core test processors, the parallel or concurrent testing of single or multiple chips is completed.
  • test equipment There are three main traditional test methods derived from test equipment based on this architecture design:
  • test efficiency is the lowest.
  • the total test time is the sum of the test time of each test station. As the number of parallel test stations increases, the overall test efficiency is very low.
  • the second traditional test method is to match the output matching signals of all test stations at the same time.
  • Pass or Fail the matching test is considered to be passed.
  • This test method is more efficient than the first method.
  • the test flexibility of each test station is sacrificed. For example, it is impossible to accurately know the occurrence time of the matching signal of each test station. For some test stations, the matching signal appears first, and it is necessary to wait for the condition of the test station that appears later to be established before continuing. Test, may result in test Fail.
  • the third traditional test method is to assign an independent test processor to each test station. Each station runs in an independent clock domain, and each test station completes its own matching test independently.
  • this method has the advantages of flexible testing, timely matching, accurate testing parameters, and high efficiency.
  • the disadvantage is that the test cost is high, and the test channel usage rate is low.
  • this method is mainly used in high-end mixed-signal automatic test equipment (ATE), and it is widely accepted because the high profit of high-end devices under test can bear the high test cost of high-end platforms. But for a large number of middle and low-end devices under test, the high test cost cannot be accepted. Therefore, low-end test platforms often do not have such functions. If there is a way to solve the problem of high test cost and test channel utilization, it will be a better test method.
  • the invention provides a multi-core test processor and an integrated circuit test system and method. Compared with the current three traditional testing methods, the present invention can inherit the high efficiency, flexibility and testing accuracy of the multiprocessor in the third method. At the same time, the disadvantage of high testing cost of the third method is avoided. The utilization rate of the test channel is high, and the test cost is close to that of method 1 and method 2.
  • each device under test uses an independent test processor, and the number of test processor resources is relatively small for ATE, and the cost is relatively high.
  • each independent test processor is shared by a certain number of test channels. Since the number of pins of a single device under test (DUT) is often smaller than the number of test channels corresponding to a test processor, in order to implement multiple DUTs Independent matching test, each test processor can only correspond to one device under test. As a result, some redundant test channels cannot be used, and the cost of a single test is raised.
  • the multi-core test processor needs to maintain the design of a main test processor.
  • the main test processor hands the test patterns that need to be tested concurrently to the co-test processor for execution, so as to complete the test items similar to the asynchronous signal matching test. After the test of the co-test processor is completed, it returns to the main test processor to continue the follow-up test.
  • test channels can accept switching control between the two test processors. Because the number of channels controlled by each co-test processor is much smaller than that of a main test processor, fewer test channels can be avoided when assigning asynchronous test channels to each device under test, thereby improving test channel utilization Rate.
  • a multi-core test processor including a co-test processor synchronous controller, a main test processor, two or more co-test processors, a test subsystem instruction switcher, and a command between the main test processor and the co-test processor Bus 1 is connected, the main test processor is connected with the test subsystem command switcher through command bus 2, and the co-test processor is connected with the test subsystem command switcher through command bus 3, wherein:
  • the main test processor is a global test processor, and the main test processor works synchronously or asynchronously with other global processors, executes the main test graphic file in parallel or concurrently, and then sends the main test command to each subordinate test subsystem, and simultaneously The partial test pattern of the concurrent test is handed over to the co-test processor for execution.
  • the co-test processor synchronous controller is used to control whether each co-test processor works synchronously or asynchronously.
  • the co-test processor is a local test processor, and the co-test processor is controlled by the main test processor to execute the local test pattern file, and then send the local test instructions to its subordinate test subsystems.
  • the test subsystem instruction switcher is used to switch the main test instruction sent by the main test processor to its subordinate test subsystems. Used to switch the local test instructions sent by the cotest processor to its subordinate test subsystems.
  • the main test processor and the co-test processor are constructed by a Von Neumann structure test processor, and the Von Neumann structure test processor includes a timing generator, a test pattern generator, and a signal processing unit control instruction generator, memory controller, graphics memory, of which:
  • the graphics memory is used to store the compiled test graphics file codes.
  • the timing generator, the test pattern generator, and the signal processing unit control the command generator to access the graphic memory through the memory controller to acquire commands and data.
  • the timing generator is used to generate the precise timing signal needed for each cycle according to the timing requirement specified by the graphic file in the compiled test graphic file code.
  • the test pattern generator is used to generate the control timing required for the pattern test according to the instruction requirements of the pattern file in the compiled test pattern file code and the precise timing signal generated by the timing generator, and at the same time control the address of the memory controller to the pattern memory access.
  • the control instruction generator of the signal processing unit sends the control instruction of the test subsystem to the corresponding subsystem under the control of the control sequence generated by the test pattern generator, so as to realize the synchronous control of the subsystem.
  • each co-test processor and the main test processor work asynchronously in different clock domains, and the co-test processor and other co-test processors work in the same or different clock domains.
  • each co-test processor works independently or in groups in the same or different clock domains under the control of the co-test processor synchronous controller.
  • a digital signal test board device including a bus controller, a multi-core test processor, a test subsystem controller, a test subsystem control bus, and a digital test subsystem, wherein:
  • the bus controller is used for communication control between the digital signal test board device and the PC terminal.
  • the multi-core test processor is used to execute test pattern files and generate control commands to the test subsystem.
  • the test subsystem control bus is used for transmitting control commands between the multi-core test processor and the test subsystem.
  • the test subsystem controller is used to receive a control command for the test subsystem generated by the multi-core test processor, and generate a channel control command for the test subsystem according to the control command.
  • the test subsystem accepts the test subsystem channel control command generated by the test subsystem controller, and outputs any digital test sequence signal according to the requirements of the test pattern file, or performs matching analysis of any measured signal.
  • the test subsystem is composed of a digital level driver, a window comparator, a dynamic load generator, and a precision current source.
  • a kind of automatic test system comprises PC main control computer, one above-mentioned digital signal test board device, wherein:
  • the PC main control computer is used to run the test program to generate the board work signal, and the board work signal is transmitted to the corresponding digital signal test board device, and then controls the digital signal test board device to perform work.
  • the digital signal test board device is used to execute the test pattern file according to the board work signal, generate a test excitation signal to the device under test, analyze the response of the device under test, form a test result, and transmit the test result to the PC main control computer.
  • a PCIE bus controller is included, and the PCIE bus controller is used for data communication between the PC main control computer and the digital signal test board device.
  • a high-speed backplane bus is included, and the high-speed backplane bus is used for data transmission between the PCIE bus controller and the digital signal test board device. And the signal synchronization between each digital signal test board device.
  • An automatic testing method comprising the steps of:
  • Step 1 the PC main control computer downloads the graphics files corresponding to the test processors in each digital signal test board device to the graphics storage of the corresponding test processors through the PCIE bus controller.
  • Step 2 the PC main control computer configures each used digital signal test board device to a required state according to the requirements of the tested device.
  • Step 3 the PC main control computer synchronously starts each main test processor of each digital signal test board device, executes the main test pattern file of the parallel test, and analyzes the response of the device under test at the same time to form a test result 1.
  • Step 4 each main test processor executes to a partial test pattern file that requires asynchronous matching or concurrent testing, and starts the corresponding co-test processor.
  • each co-test processor executes the concurrent test partial test pattern file, performs concurrent matching of multiple tested device signals, analyzes the response of the tested device at the same time, forms a test result 2, and transmits the test result 2 to the PC main control computer.
  • Step 6 whether each co-test processor corresponding to the waiting period of each main test processor finishes executing, and if so, transmits the test result to the PC main control computer.
  • Step 7 the PC main control computer obtains the test result 1 and the test result 2, comprehensively analyzes whether the tested device passes the test, and if it passes, notifies the sorting equipment to process the tested device as a qualified product. If it fails, notify the sorting equipment to treat the device under test as a defective product.
  • the present invention has the following beneficial effects:
  • the concurrent testing of asynchronous concurrent signal matching test items that can only be completed by multi-core testing can be completed at a cost close to that of the single-core testing processor testing method. 2. It can reduce the test time of asynchronous and concurrent matching test items of multiple test stations, thereby reducing the cost of single test. 3. It can generate concurrent multi-clock domain test signals that cannot be generated by a single-core test processor, and complete projects that require concurrent testing.
  • Figure 1 is a schematic diagram of the internal structure of the test processor.
  • Figure 2 is a block diagram of the multi-core test processor.
  • Fig. 3 is a functional block diagram of the digital signal test board device.
  • Figure 4 is a block diagram of the automatic test system.
  • FIG. 5 is a schematic diagram of a concurrent matching test performed on multiple test stations by an MCTP-based test device.
  • FIG. 6 is a schematic diagram of concurrent matching of multiple test stations performed by test devices with multiple single-core test processors.
  • a kind of multi-core test processor as shown in Figure 2, comprises co-test processor synchronization controller 11, a main test processor 12, some co-test processors 13, test subsystem instruction switcher 17, main test processor 12 and co-test processor 13 are connected by command bus one 14, and main test processor 12 is connected with test subsystem command switcher 17 by command bus two 15, and co-test processor 13 is connected with test subsystem command switcher 17 are connected through command bus three 16, wherein:
  • main test processor 12 can work synchronously or asynchronously with other global processors, parallel or concurrent execution main test pattern file, comprises: Sequential execution, jump, loop, etc. of the file (Pattern) vector, and then send the main test command to each subordinate test subsystem, and at the same time, hand over the partial test pattern that needs to be tested concurrently to the co-test processor for execution 13 . Simultaneously control each cotest processor.
  • the co-test processor synchronization control (Co-Test-Porcessor-Sync-Controller, CTPSC) is used to control whether each co-test processor 13 works synchronously or asynchronously.
  • the co-test processor (Co-Test-Processor, CTP) is a local test processor, and the co-test processor 13 is subject to the control of the main test processor 12 to execute the local test pattern file, including: the sequential execution of the Pattern vector , jump, loop, etc., and then send local test instructions to its subordinate test subsystems. Partial test pattern files include items that require concurrent match testing.
  • Each co-test processor CTP works asynchronously in different clock domains from the main test processor, and can work in the same or different clock domains with other co-test processors CTP. Note that each test processor MTP can control several co-test processors CTP.
  • Each CTP can be independent under the control of the CTPSC, or work in groups in the same or different clock domains (that is, work synchronously or asynchronously).
  • Each co-test processor CTP can execute the same test pattern program or different test pattern programs. This enables parallel or concurrent testing processes. Different from the main test processor MTP, the co-test processor CTP supports fewer test instruction sets.
  • the test subsystem instruction switcher 17 is used to switch the main test instruction sent by the main test processor 12 to its subordinate test subsystems. It is used to switch the local test command sent by the co-test processor 13 to its subordinate test subsystems.
  • the main test instruction and partial test instruction are collectively referred to as the control instruction 18 .
  • the command bus 14 is the command bus between the MTP and the CTP, and the main test processor sends through the command bus 14 including: Start: start the CTP, Stop: stop the CTP. Load: Load CTP, wait for instructions to CTP.
  • Command bus 2 15 is a command bus between the MTP and the test subsystem.
  • the MTP controls each test subsystem to perform specified operations through the command bus, including: Drive, Compare, etc.
  • Command bus 3 16 is the command bus between the CTP and the test subsystem.
  • the CTP controls each test subsystem to perform specified operations through the command bus, including: Drive, Compare, etc.
  • Von Neumann structure test processor 4 Described main test processor, cooperative test processor are built and formed by Von Neumann structure test processor 4, as shown in Figure 1, described Von Neumann structure test processor 4 comprises timing generator 1, test pattern generation Device 2, signal processing unit control instruction generator 3, storage controller 5, graphics memory 6, wherein:
  • the graphic storage 5 is used for storing the compiled test graphic file codes.
  • Timing Generator 1 (Timing Generator, be called for short TG), is used for according to the timing requirement specified by the graphic file in the test graphic file code after compiling, produces the precise timing signal (comprising cycle, time edge etc. ).
  • Test pattern generator 2 Puln Generator
  • control timing required for pattern testing including: jump turn, cycle, etc.
  • the signal processing unit control instruction generator 3 sends the test subsystem control instructions to the corresponding subsystems under the control of the control sequence generated by the test pattern generator 2, so as to realize the synchronous control of the subsystems. That is, it is used to generate instruction signals for synchronously controlling the digital channel test subsystem according to the control requirements of the graphic file.
  • Test Processor 4 (Test Processor, referred to as TP) is a typical Von Neumann structure processor, but the instruction set adopts ATE special instruction set, which is dedicated to processing signals instead of data.
  • the graphic storage stores the compiled test graphic file codes.
  • Timing generator 1, test pattern generator 2, and signal processing unit control instruction generator 3 access pattern memory (Pattern Memory) through memory controller (Memory Control) 5 to obtain instructions and data.
  • the timing generator 1 is responsible for generating information such as the corresponding period and edge of the current period, and providing it to other modules.
  • the test pattern generator 2 is responsible for executing the instruction requirements in the test pattern, realizing jumps, loops, etc., and at the same time controlling the address access of the memory controller to the pattern memory.
  • the storage controller under the control of the test pattern generator 2, sends the test subsystem control instructions to the corresponding subsystems, so as to realize the synchronous control of the subsystems.
  • a kind of digital signal test board device as shown in Figure 3: comprise bus controller 21, multi-core test processor 23, test subsystem controller, test subsystem control bus 24, digital test subsystem, wherein:
  • the bus controller 21 is used for communication control between the digital signal test board device and the PC terminal.
  • the multi-core test processor (Multi-Core Test Processor, MCTP) 23 is used to execute the test pattern file and generate control commands to the test subsystem.
  • MCTP Multi-Core Test Processor
  • test subsystem control bus 24 is used for transmitting control commands between the multi-core test processor 23 and the test subsystem. Note that each test subsystem controller corresponds to a cotest processor here. Each subsystem controller controls a set of digital test subsystems.
  • the test subsystem controller is used to receive a control command generated by the multi-core test processor 23 for the test subsystem, and generate a test subsystem channel control command according to the test control command.
  • the test subsystem 25 is composed of a digital level driver, a window comparator, a dynamic load generator, a precision current source and the like. Each digital test subsystem receives the test subsystem channel control command generated by the test subsystem controller, and outputs any digital test timing signal according to the requirements of the test pattern file, or performs matching analysis of any measured signal.
  • the entire test system connects the above-mentioned board devices through a high-speed bus backplane, and can form a large-scale digital test system to complete a complex arbitrary digital signal test system for parallel or concurrent testing of multiple devices under test.
  • a kind of automatic test system as shown in Figure 4: comprise PC main control computer 31, PCIE bus controller 32, high-speed backplane bus 34, more than one digital signal test board device 35, wherein:
  • the PC main control computer 31 is used to run the test program to generate the board work signal, and the board work signal is passed to the corresponding digital signal test board device 35 by the PCIE bus controller 32 and the high-speed backplane bus 34, and then controls the digital signal
  • the test board assembly 35 performs the work. Used to analyze test results and data processing.
  • the PCIE bus controller 32 is used for data communication between the PC main control computer 31 and the digital signal test board device 35 .
  • the high-speed backplane bus 34 is used for data transmission between the PCIE bus controller 32 and the digital signal test board device 35 . And the signal synchronization between each digital signal test board device 35.
  • the digital signal test board device 35 is used to execute the test pattern file according to the board work signal, generate a test excitation signal to the device under test (Device Under Test, DUT), and analyze the response of the device under test to form a test result, and The test results are transmitted to the PC main control computer 31 through the PCIE bus controller 32 and the high-speed backplane bus 34.
  • the PC main control computer 31 judges the Pass/Fail of the device.
  • the device under test 36 (Device Under Test, DUT). Note that each DUT represents a test station. Each DUT may occupy test channel resources of one or more board devices.
  • An automatic testing method comprising the steps of:
  • Step 1 the PC main control computer 31 downloads the graphics files corresponding to the test processors in each digital signal test board device 35 to the graphics memory 5 of the corresponding test processors through the PCIE bus controller 32 .
  • Step 2 the PC main control computer 31 configures each used digital signal test board device 35 to a required state according to the requirements of the device under test.
  • Step 3 the PC main control computer 31 synchronously starts each main test processor of each digital signal test board device 35, executes the main test pattern file of the parallel test, and analyzes the response of the device under test at the same time to form a test result one.
  • Step 4 each main test processor executes to the partial test pattern file that requires asynchronous matching or concurrent testing, and starts the corresponding co-test processor 13 .
  • each co-test processor 13 executes the concurrent test partial test pattern file, performs concurrent matching of multiple tested device signals, analyzes the response of the tested device at the same time, forms the test result 2, and transmits the test result 2 to the PC main control computer 31.
  • Step 6 Whether each co-test processor 13 corresponding to the waiting period of each main test processor finishes executing, and if so, transmits the test result to the PC main control computer 31 .
  • Step 7 the PC main control computer 31 obtains the test result 1 and the test result 2, comprehensively analyzes whether the tested device passes the test, and if it passes, notifies the sorting equipment to process the tested device as a qualified product. If it fails, notify the sorting equipment to treat the device under test as a defective product.
  • the main test processor can concurrently test the concurrent signals of multiple test stations (device under test) only by waiting for each co-test processor to complete the concurrent test.
  • the traditional single-core test processor needs to test each test station serially.
  • test device based on MCTP through the test device based on MCTP, only one board device and one MTP are needed to complete concurrent tests of multiple test stations. It can not only meet the asynchronous matching test requirements of multiple test stations, but also utilize all test channel resources to a greater extent. While reducing the test cost per unit test time of a single test station, it maximizes test efficiency.
  • the invention can realize the asynchronous concurrent test of multiple test stations, improve the test efficiency, and at the same time, when assigning asynchronous test channels to each test station, can avoid less test channels being idle, thereby improving the utilization rate of the test channels.

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Abstract

一种多核测试处理器及集成电路测试系统与方法，包括协测试处理器同步控制器（11）、主测试处理器（12）、两个以上的协测试处理器（13）、测试子系统指令切换器（17），在主测试处理器（12）下引入若干协测试处理器（13）。主测试处理器（12）将需要并发测试的测试图形交给协测试处理器（13）执行，用于完成类似异步信号匹配测试的测试项目。协测试处理器（13）测试完成后，又回到主测试处理器（12）继续后续测试。可以实现多测试站异步并发测试，提高测试效率，同时在给每个测试站分配异步测试通道时可以避免更多的测试通道闲置，从而提高测试通道利用率。

Description

一种多核测试处理器及集成电路测试系统与方法 技术领域
本发明涉及一种ATE(Auto Test Equipment)集成电路自动测试设备，属于半导体制造，仪器仪表，数字信号、混合信号芯片测试、存储器芯片测试领域。
背景技术
由于数字集成电路的测试过程中，会经常需要进行输出信号的匹配测试(Match Test)。例如：等待被测器件(Device Under Test,简称DUT)的IO输出上升沿或下降沿，或等待Memory器件写入数据烧写完成等等。由于实际量产中会需要进行多测试站(Site)的并行测试，而各个DUT的待匹配状态出现的时间不一致，导致各个Site无法通过高效的并行测试方法完成需要匹配测试的项目。
已有的测试设备中的测试处理器都是基于单核测试处理器设计的，每个测试处理器控制一定数量的测试通道。通过一个或多个单核测试处理器的同步或异步工作，完成对单颗或多颗芯片的并行或并发测试。基于这个架构设计的测试设备衍生的传统测试方法主要有三种：
传统解决方法一，整个测试系统共用一个测试处理器，通过串行测试的方法，分别进行每个测试站的输出信号匹配测试。这种方法简单灵活，但是测试效率最低。总测试时间是各个测试站测试时间之和。随着并行测试站数量增加，整体测试效率非常低。
传统测试方法二，同时匹配所有测试站输出匹配信号，当所有测试站匹配信号都成立(Pass或Fail)，则匹配测试认为通过。这种测试方法相较于第一种方法效率更高。但是牺牲了各个测试站的测试灵活性，例如：无法准确获知各个测试站匹配信号的出现时间等，对于部分测试站匹配信号先出现，还需要等待后出现的测试站条件成立后才能一起继续后续测试，可能导致测试Fail。
传统测试方法三，通过每个测试站分配一个独立的测试处理器的方法。每个站跑在独立的时钟域中，各个测试站各自独立完成各自的匹配测试。这种方法相较于前两种方法，具有测试灵活，匹配及时，测试参数准确，效率高等优点。但是缺点是测试成本较高，测试通道使用率较低等问题。目前该方法主要应用在高端混合信号自动测试机(ATE)中，由于高端被测试器件的高利润可以承受高端平台的高测试成本，所以被广泛接受。但是对于大量中低端被测试器件来讲，无法接受过高的测试成本。所以中低端测试平台往往不具备该类功能。如果有方法能解决测试成本高，及测试通道利用率问题，将是更优秀的测试方法。
发明内容
发明目的：考虑到大多数集成电路测试过程中，需要匹配测试的项目在总体测试项目中 所占的比重较低,而且该类项目往往需要的测试向量也较小。本发明提出了一种多核测试处理器及集成电路测试系统与方法。本发明相较于目前三种传统的测试方法，既可以继承方法三中多处理器的高效，灵活，及测试准确性。同时也避免了方法三的测试成本高的缺点。其测试通道利用率较高，测试成本和方法一及方法二接近。
技术方案：
鉴于传统测试方法三中，存在测试成本高，测试通道利用率不高的问题。主要原因是一方面每个被测试器件都采用独立的测试处理器，测试处理器资源对于ATE而言数量较少，成本较高。另一方面每个独立测试处理器又被一定数量的测试通道共用，由于单颗被测试器件(DUT)的管脚数往往小于一个测试处理器对应的测试通道数，为了实现多个被测试器件的独立匹配测试，每个测试处理器只能对应一颗被测试器件。导致部分多余的测试通道无法被使用，从而单颗测试成本被抬高。
为了解决该问题，需要实现一种多核测试处理器的设计架构。首先为了实现测试成本接近或略高于单核测试处理器架构，多核测试处理器需要保持一个主测试处理器的设计。为了实现多个被测试器件异步信号匹配测试问题，同时需要尽最大程度提高测试通道利用率，需要在主测试处理器下引入若干协测试处理器。主测试处理器将需要并发测试的测试图形交给协测试处理器执行，用于完成类似异步信号匹配测试的测试项目。协测试处理器测试完成后，又回到主测试处理器继续后续测试。所有测试通道可以接受在两种测试处理器间切换控制。因为每个协测试处理器所控制的通道数远小于一个主测试处理器的通道数，因此在给每个被测试器件分配异步测试通道时可以避免更少的测试通道闲置，从而提高测试通道利用率。
一种多核测试处理器，包括协测试处理器同步控制器、主测试处理器、两个以上的协测试处理器、测试子系统指令切换器，主测试处理器与协测试处理器之间通过命令总线一连接，主测试处理器与测试子系统指令切换器之间通过命令总线二连接，协测试处理器与测试子系统指令切换器之间通过命令总线三连接，其中：
所述主测试处理器为全局测试处理器，主测试处理器与其他全局处理器同步或异步工作，并行或并发执行主测试图形文件，进而发送主测试指令给下属各个测试子系统，同时将需要并发测试的局部测试图形交给协测试处理器执行。
协测试处理器同步控制器用于控制各个协测试处理器是否同步或异步方式工作。
所述协测试处理器为局部测试处理器，所述协测试处理器受主测试处理器的控制执行局部测试图形文件，进而发送局部测试指令给其下属各个测试子系统。
所述测试子系统指令切换器用于切换主测试处理器发送给其下属测试子系统的主测试指令。用于切换协测试处理器发送给其下属测试子系统的局部测试指令。
优选的：所述主测试处理器、协测试处理器通过冯诺伊曼结构测试处理器搭建构成，所述冯诺伊曼结构测试处理器包括时序发生器、测试图形发生器、信号处理单元控制指令发生器、存储控制器、图形储存器，其中：
所述图形储存器用于存储经过编译后的测试图形文件代码。
时序发生器、测试图形发生器、信号处理单元控制指令发生器通过存储控制器访问图形储存器，获取指令和数据。
所述时序发生器用于按照编译后的测试图形文件代码中的图形文件指定的时序要求，产生每个周期所需的精确时序信号。
测试图形发生器用于按照编译后的测试图形文件代码中的图形文件的指令要求和时序发生器产生的精确时序信号，产生图形测试所需的控制时序，同时控制存储控制器对图形储存器的地址访问。
信号处理单元控制指令发生器在测试图形发生器产生的控制时序的控制下，将测试子系统控制指令发送给相应的子系统，实现对子系统的同步控制。
优选的：每个协测试处理器与主测试处理器异步工作在不同的时钟域中，协测试处理器和其他协测试处理器工作在相同或不同的时钟域中。
优选的：各个协测试处理器在协测试处理器同步控制器的控制下各自独立，或分组工作在相同或不同的时钟域中。
一种数字信号测试板卡装置，包括总线控制器、多核测试处理器、测试子系统控制器、测试子系统控制总线、数字测试子系统，其中：
所述总线控制器用于数字信号测试板卡装置与PC端的通讯控制。
所述多核测试处理器用于执行测试图形文件，产生对测试子系统的控制命令。
所述测试子系统控制总线用于多核测试处理器与测试子系统之间的控制命令传递。
所述测试子系统控制器用于接收多核测试处理器产生对测试子系统的控制命令，并根据测此控制命令产生测试子系统通道控制命令。
所述测试子系统接受测试子系统控制器产生的测试子系统通道控制命令，根据测试图形文件的要求，输出任意的数字测试时序信号，或进行任意被测信号的匹配分析。
优选的：所述测试子系统由数字电平驱动器、窗口比较器、动态负载发生器、精密电流源组成。
一种自动测试系统，包括PC主控电脑、一个以上所述的数字信号测试板卡装置，其中：
所述PC主控电脑用于运行测试程序产生板卡工作信号，板卡工作信号传递给相应的数字信号测试板卡装置，进而控制数字信号测试板卡装置执行工作。
所述数字信号测试板卡装置用于根据板卡工作信号执行测试图形文件，产生测试激励信号给被测试器件，及分析被测试器件的响应，形成测试结果，并将测试结果传递给PC主控电脑。
优选的：包括PCIE总线控制器，所述PCIE总线控制器用于PC主控电脑和数字信号测试板卡装置之间的数据通讯。
优选的：包括高速背板总线，所述所述高速背板总线用于PCIE总线控制器与数字信号测试板卡装置之间的数据传递。及各个数字信号测试板卡装置之间的信号同步。
一种自动测试方法，包括以下步骤：
步骤1，PC主控电脑通过PCIE总线控制器下载各个数字信号测试板卡装置中测试处理器对应的图形文件到对应的测试处理器的图形储存器中。
步骤2，PC主控电脑根据被测试器件要求，将各个用到的数字信号测试板卡装置配置为所需的状态。
步骤3，PC主控电脑同步启动各个数字信号测试板卡装置的各个主测试处理器，执行并行测试的主测试图形文件，同时分析被测试器件的响应，形成测试结果一。
步骤4，各个主测试处理器执行到需要异步匹配或需要并发测试的局部测试图形文件，启动相应的协测试处理器。
步骤5，各个协测试处理器执行并发测试局部测试图形文件，进行多个被测试器件信号并发匹配，同时分析被测试器件的响应，形成测试结果二，将测试结果二传递给PC主控电脑。
步骤6，各个主测试处理器等待期对应的各个协测试处理器是否执行结束，若结束，将测试结果一传递给PC主控电脑。
步骤7，PC主控电脑获取测试结果一和测试结果二，综合分析被测器件是否测试通过，若通过，通知分选设备将被测器件处理为合格品。若不通过，通知分选设备将被测器件处理为不良品。
本发明相比现有技术，具有以下有益效果：
1、可以在接近单核测试处理器测试方法的成本情况下，完成多核测试才能完成的异步并发信号匹配测试项目的并发测试。2、可以降低多测试站异步并发匹配测试项目的测试时间，从而降低单颗测试成本。3、可以产生单核测试处理器无法产生的并发多时钟域测试信号，完成需要并发测试的项目。
附图说明
图1为测试处理器内部结构原理图。
图2为多核测试处理器原理框图。
图3为数字信号测试板卡装置原理框图。
图4为自动测试系统原理框图。
图5为基于MCTP的测试装置进行多测试站的并发匹配测试示意图。
图6为多个单核测试处理器的测试装置进行的多测试站并发匹配示意图。
具体实施方式
下面结合附图和具体实施例，进一步阐明本发明，应理解这些实例仅用于说明本发明而不用于限制本发明的范围，在阅读了本发明之后，本领域技术人员对本发明的各种等价形式的修改均落于本申请所附权利要求所限定的范围。
一种多核测试处理器，如图2所示，包括协测试处理器同步控制器11、一个主测试处理器12、若干的协测试处理器13、测试子系统指令切换器17，主测试处理器12与协测试处理器13之间通过命令总线一14连接，主测试处理器12与测试子系统指令切换器17之间通过命令总线二15连接，协测试处理器13与测试子系统指令切换器17之间通过命令总线三16连接，其中：
所述主测试处理器(Master-Test-Processor,MTP)，为全局测试处理器，主测试处理器12可以与其他全局处理器同步或异步工作，并行或并发执行主测试图形文件，包括：图形文件(Pattern)向量的顺序执行、跳转、循环等，进而发送主测试指令给下属各个测试子系统，同时将需要并发测试的局部测试图形交给协测试处理器执行13。同时控制各个协测试处理器。
协测试处理器同步控制(Co-Test-Porcessor-Sync-Controller,CTPSC)，用于控制各个协测试处理器13是否同步或异步方式工作。
所述协测试处理器(Co-Test-Processor,CTP)，为局部测试处理器，所述协测试处理器13受主测试处理器12的控制执行局部测试图形文件，包括：Pattern向量的顺序执行、跳转、循环等，进而发送局部测试指令给其下属各个测试子系统。局部测试图形文件包括需要并发匹配测试的项目。每个协测试处理器CTP与主测试处理器异步工作在不同的时钟域中，和其他协测试处理器CTP可以工作在相同或不同的时钟域中。注意，每个测试处理器MTP可以控制若干个他协测试处理器CTP。各个CTP可以在CTPSC的控制下各自独立，或分组工作在相同或不同的时钟域中(即同步或异步工作)。各个协测试处理器CTP可以执行相同的测试图形程序，也可以执行不同的测试图形程序。从而实现并行或并发的测试过程。与主测试处理器MTP不同的是，协测试处理器CTP支持更少的测试指令集。
所述测试子系统指令切换器17用于切换主测试处理器12发送给其下属测试子系统的主测试指令。用于切换协测试处理器13发送给其下属测试子系统的局部测试指令。
主测试指令、局部测试指令统称为控制指令18。
命令总线一14为MTP与CTP之间的命令总线，主测试处理器通过命令总线一14发送包括：Start：启动CTP，Stop：停止CTP。Load:载入CTP，等指令给CTP。
命令总线二15为MTP与测试子系统之间的命令总线，MTP通过该命令总线，控制各个测试子系统执行指定的操作，包括：Drive,Compare等。
命令总线三16为CTP与测试子系统之间的命令总线，CTP通过该命令总线，控制各个测试子系统执行指定的操作，包括：Drive,Compare等。
所述主测试处理器、协测试处理器通过冯诺伊曼结构测试处理器4搭建构成，如图1所示，所述冯诺伊曼结构测试处理器4包括时序发生器1、测试图形发生器2、信号处理单元控制指令发生器3、存储控制器5、图形储存器6，其中：
所述图形储存器5用于存储经过编译后的测试图形文件代码。
所述时序发生器1(Timing Generator，简称TG)，用于按照编译后的测试图形文件代码中的图形文件指定的时序要求，产生每个周期所需的精确时序信号(包括周期，时沿等)。
测试图形发生器2(Pattern Generator)，用于按照编译后的测试图形文件代码中的图形文件的指令要求和时序发生器1产生的精确时序信号，产生图形测试所需的控制时序(包括：跳转、循环等)，同时控制存储控制器5对图形储存器的地址访问。
信号处理单元控制指令发生器3在测试图形发生器2产生的控制时序的控制下，将测试子系统控制指令发送给相应的子系统，实现对子系统的同步控制。即用于根据图形文件控制要求，产生用于同步控制数字通道测试子系统的指令信号。
测试处理器4(Test Processor,简称TP)，是一个典型的冯诺伊曼结构的处理器，但指令集采用ATE专用指令集，专用于处理信号，而非数据。图形储存器存储了经过编译后的测试图形文件代码。时序发生器1、测试图形发生器2、信号处理单元控制指令发生器3通过存储控制器(Memory Control)5访问图形储存器(Pattern Memory)，获取指令和数据。时序发生器1负责产生当前周期相应的周期及时沿等信息，提供给其他模块。测试图形发生器2负责执行测试图形中的指令要求，实现跳转、循环等，同时控制存储控制器对图形储存器的地址访问。存储控制器则在测试图形发生器2的控制下，将测试子系统控制指令发送给相应的子系统，实现对子系统的同步控制。
一种数字信号测试板卡装置，如图3所示：包括总线控制器21、多核测试处理器23、测试子系统控制器、测试子系统控制总线24、数字测试子系统，其中：
所述总线控制器21用于数字信号测试板卡装置与PC端的通讯控制。
所述多核测试处理器(Multi-Core Test Processor,MCTP)23用于执行测试图形文件，产生对测试子系统的控制命令。
所述测试子系统控制总线24用于多核测试处理器23与测试子系统之间的控制命令传递。注意这里每个测试子系统控制器对应一个协测试处理器。每个子系统控制器控制一组数字测试子系统。
所述测试子系统控制器用于接收多核测试处理器23产生对测试子系统的控制命令，并根据测此控制命令产生测试子系统通道控制命令。
所述测试子系统25由数字电平驱动器、窗口比较器、动态负载发生器、精密电流源等组成。每个数字测试子系统接受测试子系统控制器产生的测试子系统通道控制命令，根据测试图形文件的要求，输出任意的数字测试时序信号，或进行任意被测信号的匹配分析。
整个测试系统通过高速总线背板将上述板卡装置连接起来，可以组成一个大型的数字测试系统，完成多被测试器件并行或并发测试的复杂的任意数字信号测试系统。
一种自动测试系统，如图4所示：包括PC主控电脑31、PCIE总线控制器32、高速背板总线34、一个以上的数字信号测试板卡装置35，其中：
所述PC主控电脑31用于运行测试程序产生板卡工作信号，板卡工作信号通过PCIE总线控制器32、高速背板总线34传递给相应的数字信号测试板卡装置35，进而控制数字信号测试板卡装置35执行工作。用于分析测试结果及数据处理等。
所述PCIE总线控制器32用于PC主控电脑31和数字信号测试板卡装置35之间的数据通讯。
所述高速背板总线34用于PCIE总线控制器32与数字信号测试板卡装置35之间的数据传递。及各个数字信号测试板卡装置35之间的信号同步。
所述数字信号测试板卡装置35用于根据板卡工作信号执行测试图形文件，产生测试激励信号给被测试器件(Device Under Test,DUT)，及分析被测试器件的响应，形成测试结果，并将测试结果通过PCIE总线控制器32、高速背板总线34传递给PC主控电脑31。PC主控电脑31进行器件Pass/Fail的判断。
被测试器件36(Device Under Test,DUT)。注意，每个DUT代表一个测试站。每个DUT可能占用一个或多个板卡装置的测试通道资源。
一种自动测试方法，包括以下步骤：
步骤1，PC主控电脑31通过PCIE总线控制器32下载各个数字信号测试板卡装置35中测试处理器对应的图形文件到对应的测试处理器的图形储存器5中。
步骤2，PC主控电脑31根据被测试器件要求，将各个用到的数字信号测试板卡装置35配置为所需的状态。
步骤3，PC主控电脑31同步启动各个数字信号测试板卡装置35的各个主测试处理器， 执行并行测试的主测试图形文件，同时分析被测试器件的响应，形成测试结果一。
步骤4，各个主测试处理器执行到需要异步匹配或需要并发测试的局部测试图形文件，启动相应的协测试处理器13。
步骤5，各个协测试处理器13执行并发测试局部测试图形文件，进行多个被测试器件信号并发匹配，同时分析被测试器件的响应，形成测试结果二，将测试结果二传递给PC主控电脑31。
步骤6，各个主测试处理器等待期对应的各个协测试处理器13是否执行结束，若结束，将测试结果一传递给PC主控电脑31。
步骤7，PC主控电脑31获取测试结果一和测试结果二，综合分析被测器件是否测试通过，若通过，通知分选设备将被测器件处理为合格品。若不通过，通知分选设备将被测器件处理为不良品。
通过协测试处理器，主测试处理器只需要等待各个协测试处理器并发测试完成，即可并发测试多个测试站(被测试器件)的并发信号。而传统的单核测试处理器在这一步则需要串行进行各个测试站的测试。
如图5和图6所示，通过基于MCTP的测试装置，只需要一块板卡装置，一个MTP，即可完成多个测试站的并发测试。既可以满足多测试站的异步匹配测试需求，同时可以更大程度的的利用所有测试通道资源。在降低单测试站单位测试时间测试成本的同时，实现了最大化的测试效率。本发明可以实现多测试站异步并发测试，提高测试效率，同时在给每个测试站分配异步测试通道时可以避免更少的测试通道闲置，从而提高测试通道利用率。
以上所述仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种多核测试处理器，其特征在于：包括协测试处理器同步控制器(11)、主测试处理器(12)、两个以上的协测试处理器(13)、测试子系统指令切换器(17)，主测试处理器(12)与协测试处理器(13)之间通过命令总线一(14)连接，主测试处理器(12)与测试子系统指令切换器(17)之间通过命令总线二(15)连接，协测试处理器(13)与测试子系统指令切换器(17)之间通过命令总线三(16)连接，其中：
    所述主测试处理器(12)为全局测试处理器，主测试处理器(12)与其他全局处理器同步或异步工作，并行或并发执行主测试图形文件，进而发送主测试指令给下属各个测试子系统，同时将需要并发测试的局部测试图形交给协测试处理器执行(13)；
    协测试处理器同步控制器(11)用于控制各个协测试处理器(13)是否同步或异步方式工作；
    所述协测试处理器(13)为局部测试处理器，所述协测试处理器(13)受主测试处理器(12)的控制执行局部测试图形文件，进而发送局部测试指令给其下属各个测试子系统；
    所述测试子系统指令切换器(17)用于切换主测试处理器(12)发送给其下属测试子系统的主测试指令；用于切换协测试处理器(13)发送给其下属测试子系统的局部测试指令。
  2. 根据权利要求1所述多核测试处理器，其特征在于：所述主测试处理器、协测试处理器通过冯诺伊曼结构测试处理器(4)搭建构成，所述冯诺伊曼结构测试处理器(4)包括时序发生器(1)、测试图形发生器(2)、信号处理单元控制指令发生器(3)、存储控制器(5)、图形储存器(6)，其中：
    所述图形储存器(5)用于存储经过编译后的测试图形文件代码；
    时序发生器(1)、测试图形发生器(2)、信号处理单元控制指令发生器(3)通过存储控制器(5)访问图形储存器，获取指令和数据；
    所述时序发生器(1)用于按照编译后的测试图形文件代码中的图形文件指定的时序要求，产生每个周期所需的精确时序信号；
    测试图形发生器(2)用于按照编译后的测试图形文件代码中的图形文件的指令要求和时序发生器(1)产生的精确时序信号，产生图形测试所需的控制时序，同时控制存储控制器(5)对图形储存器的地址访问；
    信号处理单元控制指令发生器(3)在测试图形发生器(2)产生的控制时序的控制下，将测试子系统控制指令发送给相应的子系统，实现对子系统的同步控制。
  3. 根据权利要求2所述多核测试处理器，其特征在于：每个协测试处理器(13)与主测试处理器(12)异步工作在不同的时钟域中，协测试处理器(13)和其他协测试处理器工作在相同或不同的时钟域中。
  4. 根据权利要求3所述多核测试处理器，其特征在于：各个协测试处理器(13)在协测试处理器同步控制器(11)的控制下各自独立，或分组工作在相同或不同的时钟域中。
  5. 一种数字信号测试板卡装置，其特征在于：包括总线控制器(21)、权利要求2所述多核测试处理器(23)、测试子系统控制器、测试子系统控制总线(24)、数字测试子系统，其中：
    所述总线控制器(21)用于数字信号测试板卡装置与PC端的通讯控制；
    所述多核测试处理器(23)用于执行测试图形文件，产生对测试子系统的控制命令；
    所述测试子系统控制总线(24)用于多核测试处理器(23)与测试子系统之间的控制命令传递；
    所述测试子系统控制器用于接收多核测试处理器(23)产生对测试子系统的控制命令，并根据测此控制命令产生测试子系统通道控制命令；
    所述测试子系统(25)接受测试子系统控制器产生的测试子系统通道控制命令，根据测试图形文件的要求，输出任意的数字测试时序信号，或进行任意被测信号的匹配分析。
  6. 根据权利要求5所述数字信号测试板卡装置，其特征在于：所述测试子系统由数字电平驱动器、窗口比较器、动态负载发生器、精密电流源组成。
  7. 一种自动测试系统，其特征在于：包括PC主控电脑(31)、一个以上的权利要求5所述的数字信号测试板卡装置(35)，其中：
    所述PC主控电脑(31)用于运行测试程序产生板卡工作信号，板卡工作信号传递给相应的数字信号测试板卡装置(35)，进而控制数字信号测试板卡装置(35)执行工作；
    所述数字信号测试板卡装置(35)用于根据板卡工作信号执行测试图形文件，产生测试激励信号给被测试器件，及分析被测试器件的响应，形成测试结果，并将测试结果传递给PC主控电脑(31)。
  8. 根据权利要求7所述动测试系统，其特征在于：包括PCIE总线控制器(32)，所述PCIE总线控制器(32)用于PC主控电脑(31)和数字信号测试板卡装置(35)之间的数据通讯。
  9. 根据权利要求8所述动测试系统，其特征在于：包括高速背板总线(34)，所述所述高速背板总线(34)用于PCIE总线控制器(32)与数字信号测试板卡装置(35)之间的数据传递；及各个数字信号测试板卡装置(35)之间的信号同步。
  10. 一种基于权利要求7所述的自动测试系统的测试方法，其特征在于，包括以下步骤：
    步骤1，PC主控电脑(31)下载各个数字信号测试板卡装置(35)中测试处理器对应的图形文件到对应的测试处理器的图形储存器(5)中；
    步骤2，PC主控电脑(31)根据被测试器件要求，将各个用到的数字信号测试板卡装置(35)配置为所需的状态；
    步骤3，PC主控电脑(31)同步启动各个数字信号测试板卡装置(35)的各个主测试处理器，执行并行测试的主测试图形文件，同时分析被测试器件的响应，形成测试结果一；
    步骤4，各个主测试处理器执行到需要异步匹配或需要并发测试的局部测试图形文件，启动相应的协测试处理器(13)；
    步骤5，各个协测试处理器(13)执行并发测试局部测试图形文件，进行多个被测试器件信号并发匹配，同时分析被测试器件的响应，形成测试结果二，将测试结果二传递给PC主控电脑(31)；
    步骤6，各个主测试处理器等待期对应的各个协测试处理器(13)是否执行结束，若结束，将测试结果一传递给PC主控电脑(31)；
    步骤7，PC主控电脑(31)获取测试结果一和测试结果二，综合分析被测器件是否测试通过，若通过，通知分选设备将被测器件处理为合格品；若不通过，通知分选设备将被测器件处理为不良品。
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