WO2023035153A1 - 一种集成电路及esd保护器件 - Google Patents

一种集成电路及esd保护器件 Download PDF

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Publication number
WO2023035153A1
WO2023035153A1 PCT/CN2021/117262 CN2021117262W WO2023035153A1 WO 2023035153 A1 WO2023035153 A1 WO 2023035153A1 CN 2021117262 W CN2021117262 W CN 2021117262W WO 2023035153 A1 WO2023035153 A1 WO 2023035153A1
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Prior art keywords
gate
drain
source
integrated circuit
metal
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PCT/CN2021/117262
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English (en)
French (fr)
Inventor
汪玲
王黎晖
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华为技术有限公司
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Priority to CN202180100715.2A priority Critical patent/CN117678071A/zh
Priority to PCT/CN2021/117262 priority patent/WO2023035153A1/zh
Publication of WO2023035153A1 publication Critical patent/WO2023035153A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers

Definitions

  • the present application relates to the field of electronic technology, in particular to an integrated circuit and an ESD protection device.
  • Integrated circuit integrated circuit, IC
  • chip the chip will introduce static electricity during the process of manufacturing, transportation, packaging and testing, and electrostatic discharge (ESD) will cause damage to the internal devices in the chip, so It is necessary to design an ESD protection device for discharging ESD current in the chip, so that the ESD current can be discharged through the ESD protection device when ESD occurs on the chip, thereby protecting the internal devices in the chip.
  • ESD protection devices need to have the characteristics of being able to withstand a large discharge current, low on-resistance, and a suitable turn-on voltage.
  • GGNMOS gate-grounded N-type metal oxide semiconductor
  • FET field-effect transistor
  • GRNMOS gate-resistance NMOS transistor
  • BJT parasitic bipolar transistor
  • the application provides an integrated circuit and an ESD protection device, which are used to improve the service life and performance of the ESD protection device without increasing the area and cost.
  • an integrated circuit in a first aspect, includes an ESD protection device, and the ESD protection device includes: a substrate; a plurality of electrodes located on the substrate, the plurality of electrodes include a dummy gate, a first drain , the second drain, the first gate, the second gate, the first source and the second source; wherein, the first drain and the second drain are located on both sides of the dummy gate, and the first gate and the first source are positioned at the side where the first drain is far away from the dummy gate, and the second grid and the second source are positioned at a side where the second drain is far away from the dummy gate; the first drain, the second drain pole is electrically connected to the dummy gate.
  • the ESD protection device includes a substrate, and a plurality of electrodes located on the substrate, and among the plurality of electrodes, the first drain located on both sides of the dummy gate and adjacent to the dummy gate electrode and the second drain are electrically connected to the dummy gate, so that when the integrated circuit occurs ESD, the dummy gate DG is at the same potential as the first drain and the second drain, for example, the dummy gate DG is connected to the first drain
  • the same potential of the first drain and the second drain is high potential, which can avoid the possibility of burning near the dummy gate due to a certain voltage difference between the dummy gate and the first drain and the second drain.
  • electrically connecting the first drain, the second drain and the dummy gate can further improve the failure current and on-resistance of the ESD protection device, thereby further improving the lifespan and performance of the ESD protection device.
  • the first drain is connected to the first metal through the first via hole
  • the second drain is connected to the second metal through the second via hole
  • the dummy gate is connected to the second metal through the third via hole.
  • third metal the first metal, the second metal and the third metal are on the same metal layer and are electrically connected, for example, the first metal, the second metal and the third metal pass through one of the plurality of metal layers included in the integrated circuit The metal layer or layers are electrically connected. Further, the first metal, the second metal and the third metal are the same piece of metal.
  • the second drain is connected to the second metal through the second via hole
  • the dummy gate is connected to the first metal through the third via hole.
  • Three metals when the first metal, the second metal and the third metal are electrically connected through one metal layer or a plurality of metal layers in the multiple metal layers included in the integrated circuit, without increasing the area and cost, through The short distance realizes the electrical connection of the first drain, the second drain and the dummy gate; in addition, when the first metal, the second metal and the third metal are the same piece of metal in the same metal layer, it can also reduce Small because of the resistance introduced by the electrical connection.
  • the distance between adjacent drains and gates among the plurality of electrodes is greater than the distance between adjacent sources and gates.
  • the distance between the first drain and the first gate is greater than the distance between the first source and the first gate
  • the distance between the second drain and the second gate is greater than the distance between the second source and the first gate. The distance between the two gates.
  • the integrated circuit further includes: a voltage terminal and a ground terminal; both the first drain and the second drain are coupled to the voltage terminal; the first source, the second source, the first gate Both the electrode and the second grid are coupled to the ground terminal.
  • the ESD protection device can be GGNMOS, so that when the GGNMOS is used as the ESD protection device of the integrated circuit, the service life and performance of the GGNMOS can be improved, so as to further improve the service life and performance of the integrated circuit .
  • the integrated circuit further includes: a first resistor, a voltage terminal, and a ground terminal; both the first drain and the second drain are coupled to the voltage terminal; the first source and the second source Both are coupled to the ground terminal, and the first gate and the second gate are coupled to the ground terminal through a first resistor.
  • the ESD protection device can be GRNMOS, so that when the GRNMOS is used as the ESD protection device of the integrated circuit, the service life and performance of the GRNMOS can be improved, so as to further improve the service life and performance of the integrated circuit .
  • the integrated circuit further includes: a voltage terminal and a ground terminal, and the multiple electrodes further include a third source and a third gate, and the third source and the third gate are arranged on The first source is away from the side of the first gate; the first drain is coupled to the voltage terminal; the third source is coupled to the ground terminal; the first gate and the third gate are suspended.
  • the ESD protection device can be 2-stack NMOS, and the 2-stack NMOS has a higher failure current, so that the 2-stack NMOS can be improved when the 2-stack NMOS is used as the ESD protection device of the integrated circuit. The lifetime and performance of 2-stack NMOS to further improve the lifetime and performance of this integrated circuit.
  • the integrated circuit further includes: a voltage terminal and a ground terminal, and the multiple electrodes further include a third source, a third gate, a fourth source and a fourth gate; the third source The pole and the third gate are arranged on the side where the first source is far away from the first gate; the fourth source and the fourth gate are both arranged on a side where the third gate is far away from the first gate; the first The drain is coupled to the voltage terminal; the fourth source is coupled to the ground terminal; the first gate, the third gate and the fourth gate are suspended.
  • the ESD protection device can be a 3-stack NMOS, and the 3-stack NMOS has a higher failure current, so that the 3-stack NMOS can be improved when the 3-stack NMOS is used as the ESD protection device of the integrated circuit.
  • the lifetime and performance of 2-stack NMOS to further improve the lifetime and performance of this integrated circuit.
  • multiple gates, multiple sources, and multiple drains of the multiple electrodes are electrically connected.
  • the plurality of electrodes includes a greater number of sources, drains and gates, all sources, all drains, and all gates of the plurality of electrodes are electrically connected.
  • the integrated circuit further includes a functional circuit
  • the ESD protection device is used to protect the functional circuit
  • the functional circuit is a circuit with a processing function or a circuit with a storage function.
  • the ESD current can be discharged through the ESD protection device, so that the service life of the functional circuit can be guaranteed by improving the service life and performance of the ESD protection device.
  • the integrated circuit adopts a FinFET process.
  • the ESD protection device is produced using a FinFET process.
  • the other transistors can be produced using a FinFET process, or can be produced using other processes such as gate-all-around GAA.
  • the service life and performance of the ESD protection device produced by using the FinFET process can be improved.
  • an electronic device in a second aspect, includes: a printed circuit board, and the integrated circuit provided in the first aspect or any possible implementation manner of the first aspect, and the integrated circuit is fixed on the printed circuit board.
  • the integrated circuit further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB through solder balls, and the integrated circuit is fixed on the packaging substrate through solder balls.
  • the electronic device provided above includes the integrated circuit provided above, therefore, the beneficial effects that it can achieve can refer to the beneficial effects of the integrated circuit provided above, and will not be repeated here.
  • Fig. 1 is the layout of a kind of ESD protection device that the embodiment of the present application provides;
  • FIG. 2 is a schematic structural diagram of an integrated circuit provided in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an electrical connection between a first drain, a second drain, and a dummy gate provided in an embodiment of the present application;
  • Fig. 4 is the schematic circuit diagram of several ESD protection devices that the embodiment of the present application provides;
  • FIG. 5 is a schematic structural diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another integrated circuit provided in the embodiment of the present application.
  • FIG. 7 is a performance comparison diagram of a GGNMOS provided in an embodiment of the present application.
  • At least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.
  • Integrated circuits are easily damaged by static electricity.
  • protection circuits are designed at the input and output terminals of the circuit or power protection devices to prevent internal circuits from being damaged by static electricity.
  • ESD protection devices are often used to reduce electrostatic damage.
  • FIG. 1 is a layout of an ESD protection device designed using a fin field-effect transistor (FinFET) process.
  • the ESD protection device includes a substrate, a plurality of sources (source, S), a plurality of gates (gate, G), a plurality of drains (drain, D) located on the substrate, And a dummy gate (dummy gate, DG) located between any two adjacent drains D.
  • the plurality of sources S includes two sources S
  • the plurality of gates G includes four gates G
  • the plurality of drains D includes two drains D as an example for illustration.
  • vias via, V
  • a dummy gate DG in a floating state is introduced between the two drains D.
  • the potential of the dummy gate DG changes, and the potentials of the two drains D are high potentials, so there will be a certain gap between the dummy gate DG and the two drains D The voltage difference will cause burnout near the dummy gate DG, thereby causing the ESD protection device to fail.
  • an embodiment of the present application provides an integrated circuit and an ESD protection device.
  • the dummy gate DG Equipotential with the two drains D, thereby avoiding the situation of burning near the dummy gate DG, thereby ensuring the service life and performance of the ESD protection device.
  • FIG. 2 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application, the integrated circuit includes: an ESD protection device 1, the ESD protection device 1 includes a substrate 11, a plurality of electrodes 12 located on the substrate 11, the The plurality of electrodes 12 includes a dummy gate DG, a first drain D1, a second drain D2, a first gate G1, a second gate G2, a first source S1, and a second source G2.
  • first drain D1 and the second drain D2 are located on both sides of the dummy gate DG
  • first gate G1 and the first source S1 are located on the side of the first drain D1 away from the dummy gate DG
  • the second gate G2 and the second source S2 are located on a side of the second drain D2 away from the dummy gate DG
  • the first drain D1 , the second drain D2 are electrically connected to the dummy gate DG.
  • Figure 2 is a top view of the integrated circuit.
  • the substrate 11 may include an active area, and the plurality of electrodes 12 may specifically be located on the active area.
  • the substrate 11 may include at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI ), and germanium on insulator (GeOI), etc.
  • the substrate 11 has N-type (N+) doping.
  • the plurality of electrodes 12 may be arranged at intervals in one direction according to a certain rule.
  • the plurality of electrodes 12 may be arranged at intervals in the lateral direction according to the rule of "S-G-D-DG-D-G-S-G-D-DG-D-G-S" (ie, as shown in FIG. 2 above).
  • the distance between the adjacent drains D and the gate G among the plurality of electrodes 12 is greater than the distance between the adjacent source S and the gate G.
  • the distance between D1 and G1 is greater than the distance between S1 and G1
  • the distance between D2 and G2 is greater than the distance between S2 and G2.
  • the plurality of electrodes 12 may partially cover the active area of the substrate 11 .
  • the middle part of the plurality of electrodes 12 may cover the upper part of the active area, and the two ends of the plurality of electrodes 12 may exceed the active area.
  • the integrated circuit may further include a functional circuit, and the functional circuit may be coupled with the ESD protection device 1 , and the ESD protection device 1 may be used to discharge static electricity of the functional circuit to realize protection of the functional circuit.
  • the functional circuit may be a power protection device. This functional circuit is not shown in FIG. 2 .
  • a plurality of electrodes 12 shown in Fig. 2 are only part electrodes of the ESD protection device 1, and in practical applications, the ESD The protection device 1 may also include more electrodes, and the above-mentioned FIG. 2 does not constitute a limitation to the embodiment of the present application.
  • the plurality of electrodes 12 includes a larger number of sources S, drains D and gates G, all sources S in the plurality of electrodes 12 can be electrically connected, all drains D can be electrically connected, all The gate G may be electrically connected.
  • the first drain D1 can be connected to the first metal M1 through the first via hole V1
  • the second drain D2 can be Connected to the second metal M2 through the second via hole V2
  • the dummy gate DG can be connected to the third metal M3 through the third via hole V3
  • the first metal M1, the second metal M2 and the third metal M3 are used to realize the first The electrical connection of the drain D1, the second drain D2 and the dummy gate DG.
  • the ESD protection device may also include other vias (other vias are not shown in FIG. 2 ), for example, the ESD device may also include the vias shown in FIG. 1 above, which is not specifically limited in the embodiment of the present application. .
  • the integrated circuit may further include a plurality of metal layers (metal layer, ML) located on the plurality of electrodes 12 .
  • metal layer metal layer
  • an integrated circuit may include 9 metal layers, which are the first metal layer ML1 to the ninth metal layer ML9 in order from the direction close to the substrate 11 to the direction away from the substrate 11 .
  • the first metal M1 , the second metal M2 and the third metal M3 may be located in the same metal layer or in different metal layers.
  • the three are electrically connected through the metal wiring on the metal layer; when the first metal M1, the second metal M2 and the third metal When M3 is on the same metal layer, the three can also be electrically connected to metal lines on other metal layers through via holes, so as to realize the electrical connection between the three.
  • the first metal M1 , the second metal M2 and the third metal M3 are on different metal layers, the three are electrically connected through via holes and metal lines between the different metal layers.
  • the first metal M1, the second metal M2 and the third metal M3 are on the first metal layer ML1 (that is, the metal layer closest to the substrate 11), and the first The metal M1 and the second metal M2 are electrically connected through the first metal layer ML1 , and the second metal M2 and the third metal M3 are electrically connected through the second metal layer ML2 (ie, the metal layer closest to the first metal layer ML1 ).
  • the first metal M1, the second metal M2 and the third metal M3 are on the first metal layer ML1 (that is, the metal layer closest to the substrate 11)
  • the first The metal M1 and the second metal M2 are electrically connected through the first metal layer ML1
  • the second metal M2 and the third metal M3 are electrically connected through the second metal layer ML2 (ie, the metal layer closest to the first metal layer ML1 ).
  • the second metal M2 is connected to the second metal layer ML2 through the fourth via hole V4, and the third metal M3 is connected to the second metal layer ML2 through the fifth via hole V5, and in the second metal layer In the layer ML2, the electric connection of the same piece of metal is taken as an example for illustration.
  • the first via hole V1, the second via hole V2 and the third via hole V3 may also be respectively located at the same position in the first drain D1, the second drain D2 and the dummy gate DG, so that The first drain D1 , the second drain D2 and the dummy gate DG are electrically connected through a short distance, so as to reduce the resistance introduced by the electrical connection.
  • the ESD protection device can be different types of MOS transistors with ESD protection function.
  • the ESD protection device may be any of the following: GGNMOS, GRNMOS, two-level NMOS (2stack-NMOS), and three-level NMOS (3stack-NMOS).
  • the schematic circuit diagrams of GGNMOS, GRNMOS, 2stack-NMOS and 3stack-NMOS are respectively shown in FIG. 4 .
  • the drawings are schematic only.
  • each MOS structure includes a source, a gate and a drain, and all sources of the multiple MOS structures Electrical connections, all drains are electrically connected, and all gates are electrically connected.
  • FIG. 2 only a pair of MOS structures sharing the same dummy gate DG is used as an example for illustration.
  • the integrated circuit may further include a voltage terminal VDD and a ground terminal GND.
  • both the first drain D1 and the second drain D2 are coupled to the voltage terminal VDD, and the first source S1, the second source S2, the first gate G1 and the second gate G2 are all coupled to the ground terminal GND. coupling.
  • the integrated circuit may further include a voltage terminal VDD, a ground terminal GND and a first resistor R1.
  • both the first drain D1 and the second drain D2 are coupled to the voltage terminal VDD
  • the first source S1 and the second source S2 are both coupled to the ground terminal GND
  • the first gate G1 and the second gate Both G2 are coupled to the ground terminal GND through the first resistor R1.
  • the ESD protection device is 2stack-NMOS, as shown in FIG.
  • the source S3 and the third gate G3 are arranged on the side of the first source S1 away from the first gate G1 .
  • the first drain D1 is coupled to the voltage terminal VDD
  • the third source S3 is coupled to the ground terminal GND
  • the first gate G1 and the third gate G3 are suspended.
  • the plurality of electrodes may further include a third drain D3, and the third drain D3 and the first source S1 may share the same electrode, denoted as S1/D3 in FIG. 5 .
  • the ESD protection device is a 3stack-NMOS, as shown in FIG.
  • the third source S3 and the third gate G3 are arranged on the side of the first source S1 away from the first gate G1, and the fourth source S4 and the fourth gate G4 are arranged on the side of the third gate G3 away from the first gate. side of pole G1.
  • the first drain D1 is coupled to the voltage terminal VDD
  • the fourth source S4 is coupled to the ground terminal GND
  • the first gate G1, the third gate G3 and the four gates G4 are suspended.
  • the plurality of electrodes may also include a third drain D3 and a fourth drain D4, the third drain D3 and the first source S1 may share the same electrode, the fourth drain D4 and the third source S3 can share the same electrode, which are denoted as S1/D3 and S3/D4 respectively in FIG. 6 .
  • the electrode on the left side of the first source S1 is used as an example to illustrate the structure of the integrated circuit when the ESD protection device is 2stack-NMOS or 3stack-NMOS.
  • the right side of the above-mentioned second source S2 can also be sampled in a manner similar to the left side of the first source S1 for the deployment or design of other electrodes, and the corresponding electrodes are denoted as S3' and G3' in the above-mentioned Figures 5 and 6 , S4', G4', S2/D3', and S3'/D4', the embodiments of the present application will not be repeated here.
  • the integrated circuit may adopt fin field-effect transistor (FinFET) process, specifically, it may mean that the ESD protection device 1 in the integrated circuit may be produced by using FinFET process.
  • FinFET fin field-effect transistor
  • the other transistors may also be produced using a FinFET process, or may be produced using other processes such as gate-all-around (GAA), which is not specifically limited in this embodiment of the present application.
  • GAA gate-all-around
  • the GGNMOS provided in FIG. 2 is compared with the GGNMOS provided in FIG. 1, specifically the TLP current, TLP voltage and leakage current (leakage current, LC) measured by a transmission line pulse tester. ) as shown in Figure 7, as an embodiment of the present application, it is not limited to the following specific parameter values. It can be seen from Figure 7 that the TLP current corresponding to the GGNMOS provided in Figure 1 increases from 0A to about 3.4A.
  • the failure current of the GGNMOS provided in Figure 1 is about 3.4A; the TLP current corresponding to the GGNMOS provided in Figure 2 increases from 0A to about 4.2A, and the corresponding leakage current changes suddenly (that is, the curve L2), that is, the GGNMOS provided in FIG. 2 fails when the TLP current is about 4.2A, or the failure current of the GGNMOS provided in FIG. 2 is about 4.2A.
  • the GGNMOS provided in Figure 2 and Figure 1 both correspond to a corresponding TLP current in the process of increasing the TLP voltage from about 4.2V upwards, and the GGNMOS provided in Figure 1 corresponds to a maximum TLP voltage of about 7V, corresponding to The maximum TLP current is about 3.4A (curve L3), the maximum TLP voltage corresponding to the GGNMOS provided in Figure 2 is about 7.2V, and the corresponding maximum TLP current is about 4.2A (curve L4).
  • the maximum TLP current of the GGNMOS provided in FIG. 2 is increased by about 20% compared with the maximum TLP current of the GGNMOS provided in FIG. 1 , and the on-resistance (ron) is reduced by about 12%.
  • the ESD protection device 1 in the integrated circuit includes a substrate 11, and a plurality of electrodes 12 located on the substrate 11, the plurality of electrodes 12 include a dummy gate DG, and a dummy gate DG located on the dummy gate
  • the first drain D1 and the second drain D2 on both sides of the pole DG and adjacent to the dummy gate by electrically connecting the first drain D1, the second drain D2 and the dummy gate DG, can make the dummy gate DG
  • the dummy gate DG is equipotential with the first drain D1 and the second drain D2, so that compared with FIG. 1 , the dummy gate DG is avoided due to the voltage between the first drain D1 and the second drain D2.
  • burnout occurs near the dummy gate DG, thereby ensuring the service life of the ESD protection device without increasing the area and cost.
  • electrically connecting the first drain D1, the second drain D2 and the dummy gate DG can also improve the failure current and on-resistance of the ESD protection device 1, thereby further improving the life and performance of the ESD protection device .
  • the embodiment of the present application also provides an electronic device, the electronic device includes: a printed circuit board (printed circuit board, PCB), and any one of the integrated circuits provided above, the integrated circuit is fixed on the printed circuit board PCB.
  • the integrated circuit may be an integrated circuit corresponding to a processor or memory of the electronic device.
  • the integrated circuit further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB through solder balls, and the integrated circuit is fixed on the packaging substrate through solder balls.

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Abstract

本申请提供一种集成电路及ESD保护器件，涉及电子技术领域，用于在不增加面积和成本的同时，提高ESD保护器件的使用寿命和性能。该ESD保护器件包括：衬底；位于该衬底上的多个电极，该多个电极包括伪栅极、第一漏极、第二漏极、第一栅极、第二栅极、第一源极和第二源极；其中，第一漏极和第二漏极位于该伪栅极的两侧，第一栅极和第一源极位于第一漏极远离该伪栅极的一侧，第二栅极和第二源极位于第二漏极远离该伪栅极的一侧；第一漏极、第二漏极和该伪栅极电连接。这样能够使得该伪栅极与第一漏极和第二漏极等电位，避免该伪栅极附近出现烧毁，提高ESD保护器件的使用寿命和性能。

Description

一种集成电路及ESD保护器件 技术领域
本申请涉及电子技术领域，尤其涉及一种集成电路及ESD保护器件。
背景技术
集成电路(integrated circuit，IC)也称为芯片(chip)，芯片在制造、运输、封装和测试过程中会引入静电，静电泄放(electrostatic discharge，ESD)会导致芯片中的内部器件损坏，所以需要在芯片中设计用于泄放ESD电流的ESD保护器件，使得芯片发生ESD时的ESD电流能够通过ESD保护器件泄放，从而保护芯片中的内部器件。ESD保护器件需要具有能承受大的泄放电流、低的导通电阻、以及合适的开启电压等特点。
目前，一种实现方式是使用栅极接地(gate-grounded，GG)的N型金属氧化半导体(N-type metal oxide semiconductor，NMOS)场效应管(field-effect transistor，FET)(简称GGNMOS)或栅极接电阻(gate-resistance，GR)的NMOS管(简称GRNMOS)作为ESD保护器件，以利用GGNMOS或GRNMOS的寄生双极晶体管(bipolar junction transistor，BJT)导通实现大电流的泄放。但是，如何实现GGNMOS和GRNMOS等ESD保护器件的版图，以保证ESD保护器件的使用寿命和性能仍是一个亟待解决的问题。
发明内容
本申请提供一种集成电路及ESD保护器件，用于在不增加面积和成本的同时，提高ESD保护器件的使用寿命和性能。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种集成电路，该集成电路包括ESD保护器件，该ESD保护器件包括：衬底；位于该衬底上的多个电极，该多个电极包括伪栅极、第一漏极、第二漏极、第一栅极、第二栅极、第一源极和第二源极；其中，第一漏极和第二漏极位于该伪栅极的两侧，第一栅极和第一源极位于第一漏极远离该伪栅极的一侧，第二栅极和第二源极位于第二漏极远离该伪栅极的一侧；第一漏极、第二漏极和该伪栅极电连接。
上述技术方案中，该ESD保护器件包括衬底、以及位于该衬底上的多个电极，该多个电极中通过将位于该伪栅极两侧且与该伪栅极相邻的第一漏极和第二漏极与该伪栅极电连接，可以使得该集成电路发生ESD时，该伪栅极DG与第一漏极和第二漏极等电位，比如，该伪栅极DG与第一漏极和第二漏极等电位均为高电位，这样可以避免由于该伪栅极与第一漏极和第二漏极之间存在一定的电压差而使得该伪栅极附近出现烧毁的情况，从而在不增加面积和成本的同时，能够保证该ESD保护器件的使用寿命和性能。此外，将第一漏极、第二漏极和该伪栅极电连接，还可以进一步改善该ESD保护器件的失效电流和导通电阻，从而进一步提高了该ESD保护器件的寿命和性能。
在一种可能的实现方式中，第一漏极通过第一过孔连接至第一金属，第二漏极通过第二过孔连接至第二金属，该伪栅极通过第三过孔连接至第三金属。可选地，第一金属、第二金属和第三金属在同一金属层上且电连接，比如，第一金属、第二金属和第三金属通过该集成电路包括的多个金属层中的一个金属层或者多个金属层电连接。进一步的，第一金 属、第二金属和第三金属为同一块金属。上述可能的实现方式中，当第一漏极通过第一过孔连接至第一金属，第二漏极通过第二过孔连接至第二金属，该伪栅极通过第三过孔连接至第三金属，第一金属、第二金属和第三金属通过该集成电路包括的多个金属层中的一个金属层或者多个金属层电连接时，可以在不增加面积和成本的情况下，通过较短的距离实现第一漏极、第二漏极和该伪栅极电连接；此外，当第一金属、第二金属和第三金属为同一金属层中的同一块金属时，还能够减小因为电连接引入的电阻。
在一种可能的实现方式中，该多个电极中相邻的漏极与栅极之间的距离大于相邻的源极与栅极之间的距离。比如，第一漏极与第一栅极之间的距离大于第一源极与第一栅极之间的距离，第二漏极与第二栅极之间的距离大于第二源极与第二栅极之间的距离。上述可能的实现方式中，能够保证第一栅极和第二栅极在满足一定的宽度和间距要求，同时又能够保证该多个电极满足一定的工艺要求。
在一种可能的实现方式中，该集成电路还包括：电压端和接地端；第一漏极和第二漏极均与该电压端耦合；第一源极、第二源极、第一栅极和第二栅极均与该接地端耦合。上述可能的实现方式中，该ESD保护器件可以为GGNMOS，从而在将该GGNMOS作为该集成电路的ESD保护器件时可以提高该GGNMOS的使用寿命和性能，以进一步提高该集成电路的使用寿命和性能。
在一种可能的实现方式中，该集成电路还包括：第一电阻、电压端和接地端；第一漏极和第二漏极均与该电压端耦合；第一源极和第二源极均与该接地端耦合，第一栅极和第二栅极通过第一电阻与该接地端耦合。上述可能的实现方式中，该ESD保护器件可以为GRNMOS，从而在将该GRNMOS作为该集成电路的ESD保护器件时可以提高该GRNMOS的使用寿命和性能，以进一步提高该集成电路的使用寿命和性能。
在一种可能的实现方式中，该集成电路还包括：电压端和接地端，该多个电极还包括第三源极和第三栅极，第三源极和所述第三栅极设置在第一源极远离第一栅极的一侧；第一漏极与该电压端耦合；第三源极与该接地端耦合；第一栅极和第三栅极悬空。上述可能的实现方式中，该ESD保护器件可以为2-stack NMOS，该2-stack NMOS具有较高的失效电流，从而在将该2-stack NMOS作为该集成电路的ESD保护器件时可以提高该2-stack NMOS的使用寿命和性能，以进一步提高该集成电路的使用寿命和性能。
在一种可能的实现方式中，该集成电路还包括：电压端和接地端，该多个电极还包括第三源极、第三栅极、第四源极和第四栅极；第三源极和所述第三栅极设置在第一源极远离第一栅极的一侧；第四源极和第四栅极均设置在第三栅极远离第一栅极的一侧；第一漏极与该电压端耦合；第四源极与该接地端耦合；第一栅极、第三栅极和第四栅极悬空。上述可能的实现方式中，该ESD保护器件可以为3-stack NMOS，该3-stack NMOS具有较高的失效电流，从而在将该3-stack NMOS作为该集成电路的ESD保护器件时可以提高该2-stack NMOS的使用寿命和性能，以进一步提高该集成电路的使用寿命和性能。
在一种可能的实现方式中，该多个电极中的多个栅极电连接、多个源极电连接、多个漏极电连接。可选地，该多个电极包括更多数量的源极、漏极和栅极时，该多个电极中的所有源极电连接、所有漏极电连接、所有栅极电连接。
在一种可能的实现方式中，该集成电路还包括功能电路，该ESD保护器件用于保护该功能电路，比如，该功能电路为具有处理功能的电路或者具有存储功能的电路。上述可能 的实现方式中，当该功能电路发生ESD时可以通过该ESD保护器件实现ESD电流的泄放，从而通过提高该ESD保护器件的使用寿命和性能可以保证该功能电路的使用寿命。
在一种可能的实现方式中，该集成电路采用鳍形场效应晶体管FinFET工艺。可选地，该ESD保护器件采用FinFET工艺生成。当该集成电路还包括其他晶体管时，该其他晶体管可以采用FinFET工艺生成，也可以采用环栅GAA等其他工艺生成。上述可能的实现方式中，可以提高采用FinFET工艺生成的ESD保护器件的使用寿命和性能。
第二方面，提供一种电子设备，该电子设备包括：印刷电路板、以及第一方面或者第一方面的任一种可能的实现方式所提供的集成电路，该集成电路固定于印刷电路板。可选的，该集成电路还包括封装基板，该封装基板通过焊球固定于该印刷电路板PCB上，该集成电路通过焊球固定于封装基板上。
可以理解地，上述提供的电子设备包括上文所提供的集成电路，因此，其所能达到的有益效果可参考上文所提供的集成电路中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种ESD保护器件的版图；
图2为本申请实施例提供的一种集成电路的结构示意图；
图3为本申请实施例提供的一种第一漏极、第二漏极和伪栅极电连接的示意图；
图4为本申请实施例提供的几种ESD保护器件的电路原理图；
图5为本申请实施例提供的另一种集成电路的结构示意图；
图6为本申请实施例提供的又一种集成电路的结构示意图；
图7为本申请实施例提供的一种GGNMOS的性能对比图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
集成电路容易受到静电的破坏，一般在电路的输入输出端或者电源保护装置会设计保 护电路，以防止内部电路因受到静电而受损坏。在现有的集成电路设备中，常采用ESD保护器件来减少静电破坏。
图1是一种采用鳍形场效应晶体管(fin field-effect transistor，FinFET)工艺设计的一种ESD保护器件的版图。如图1所示，该ESD保护器件包括衬底，位于该衬底上的多个源极(source，S)、多个栅极(gate，G)、多个漏极(drain，D)、以及位于任意相邻的两个漏极D之间的一个伪栅极(dummy gate，DG)。图1中以该多个源极S包括两个源极S，该多个栅极G包括4个栅极G，该多个漏极D包括2个漏极D为例进行说明。图1中还示出了各个极上的过孔(via，V)。
上述版图中，为了保证栅极的宽度和间距满足一定的工艺要求，同时又保证漏极D与栅极G之间具有较大的间距(该间距用于引入漏极电阻，防止ESD电流集中于局部而造成烧毁)，在两个漏极D之间引入处于浮置状态(floating)的伪栅极DG。但是，在集成电路发生ESD时，该伪栅极DG的电位是变化的，两个漏极D的电位为高电位，这样该伪栅极DG与该两个漏极D之间会存在一定的电压差，该电压差会使得该伪栅极DG附近出现烧毁的情况，从而造成该ESD保护器件失效。
基于此，本申请实施例提供一种集成电路及ESD保护器件，通过将相邻的两个漏极D与这两个漏极D之间的伪栅极DG电连接，使得该伪栅极DG与这两个漏极D等电位，从而避免了该伪栅极DG附近出现烧毁的情况，进而保证了该ESD保护器件的使用寿命和性能。
图2为本申请实施例提供的一种集成电路的结构示意图，该集成电路包括：ESD保护器件1，该ESD保护器件1包括衬底11、位于该衬底11上的多个电极12，该多个电极12包括伪栅极DG、第一漏极D1、第二漏极D2、第一栅极G1、第二栅极G2、第一源极S1和第二源极G2。其中，第一漏极D1和第二漏极D2位于该伪栅极DG的两侧，第一栅极G1和第一源极S1位于第一漏极D1远离该伪栅极DG的一侧，第二栅极G2和第二源极S2位于第二漏极D2远离该伪栅极DG的一侧；第一漏极D1、第二漏极D2和该伪栅极DG电连接。图2为该集成电路的俯视图。
其中，该衬底11可以包括有源区(active)，该多个电极12具体可以位于该有源区上。该衬底11可以包括以下材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)、以及绝缘体上锗(GeOI)等。可选地，该衬底11具有N型(N+)掺杂。
另外，该多个电极12可以按照一定规律在一个方向上间隔排列。比如，该多个电极12可以按照“S-G-D-DG-D-G-S-G-D-DG-D-G-S…”(即上述图2所示)的规律在横向上间隔排列。可选的，该多个电极12中相邻的漏极D与栅极G之间的距离大于相邻的源极S与栅极G之间的距离。比如，D1与G1之间的距离大于S1与G1之间的距离，D2与G2之间的距离大于S2与G2之间的距离。
再者，该多个电极12可以部分覆盖该衬底11的有源区。比如，该多个电极12的中间部分可以覆盖在该有源区的上方，该多个电极12的两端可以超出该有源区。
可选的，该集成电路还可以包括功能电路，该功能电路可以与该ESD保护器件1耦合，该ESD保护器件1可以用于泄放该功能电路的静电，以实现对该功能电路的保护。比如，该功能电路可以是电源保护装置。图2中未示出该功能电路。
需要说明的是，图2中仅示出了该ESD保护器件1的部分结构，比如，图2所示的多个电极12仅是该ESD保护器件1的部分电极，在实际应用中，该ESD保护器件1还可以包括更多的电极，上述图2并不构成对本申请实施例的限制。其中，当该多个电极12包括更多数量的源极S、漏极D和栅极G时，该多个电极12中的所有源极S可以电连接、所有漏极D可以电连接、所有栅极G可以电连接。
进一步的，当第一漏极D1、第二漏极D2和该伪栅极DG电连接时，第一漏极D1可以通过第一过孔V1连接至第一金属M1，第二漏极D2可以通过第二过孔V2连接至第二金属M2，该伪栅极DG可以通过第三过孔V3连接至第三金属M3，通过第一金属M1、第二金属M2和第三金属M3实现第一漏极D1、第二漏极D2和该伪栅极DG的电连接。此外，该ESD保护器件还可以包括其他过孔(图2中未示出其他过孔)，比如，该ESD器件还可以包括上述图1所示的过孔，本申请实施例对此不作具体限制。
其中，该集成电路中还可以包括位于该多个电极12之上的多个金属层(metal layer，ML)。通常一个集成电路中可以包括9个金属层，且从靠近衬底11向着远离衬底11的方向依次为第一金属层ML1至第九金属层ML9。
另外，当该集成电路包括多个金属层时，第一金属M1、第二金属M2和第三金属M3可以位于同一金属层，也可以位于不同的金属层。当第一金属M1、第二金属M2和第三金属M3位于同一金属层上时，三者通过该金属层上的金属布线电性连接；当第一金属M1、第二金属M2和第三金属M3处于同一金属层上时，三者也可以通过过孔电连接至其他金属层上的金属线路，实现三者之间的电连接。当第一金属M1、第二金属M2和第三金属M3处于不同的金属层上时，三者则通过不同的金属层之间的过孔和金属线路，实现电性连接。
比如，如图3中的(a)所示，第一金属M1、第二金属M2和第三金属M3在第一金属层ML1(即最靠近衬底11的一个金属层)上，且第一金属M1和第二金属M2通过第一金属层ML1电连接，第二金属M2和第三金属M3通过第二金属层ML2(即最靠近第一金属层ML1的一个金属层)电连接。图3中的(a)中，以第二金属M2通过第四过孔V4连接至第二金属层ML2，第三金属M3通过第五过孔V5连接至第二金属层ML2且在第二金属层ML2中通过同一块金属电连接为例进行说明。
在另一种可能的实施例中，如图3中的(b)所示，第一金属M1、第二金属M2和第三金属M3在第一金属层ML1(即最靠近衬底11的一个金属层)上，且第一金属M1、第二金属M2和第三金属M3为同一块金属。
需要说明的是，图3中的(a)和(b)仅示出了该集成电路沿着第一过孔V1、第二过孔V2和第三过孔V3所在的直线方向垂直向下的剖视图中的部分结构。另外，上述图3所示出的第一漏极D1、第二漏极D2和该伪栅极DG的电连接方式仅为示例性的，在实际应用中，第一漏极D1、第二漏极D2和该伪栅极DG还可以通过其他的方式电连接，本申请实施例对此不作具体限制。
可选的，上述第一过孔V1、第二过孔V2和第三过孔V3还可以分别位于第一漏极D1、第二漏极D2和该伪栅极DG中的相同位置，以使第一漏极D1、第二漏极D2和该伪栅极DG通过较短的距离实现电连接，以减小因为电连接引入的电阻。
进一步的，该ESD保护器件可以为具有ESD保护功能的不同类型的MOS管。可选的， 该ESD保护器件可以为以下中的任一种：GGNMOS、GRNMOS、二级NMOS(2stack-NMOS)、三级NMOS(3stack-NMOS)。图4中分别示出了GGNMOS、GRNMOS、2stack-NMOS和3stack-NMOS的电路原理图。附图中仅仅是示意图。对附图4中的某一个MOS管来说，在实际实现中可能是包括多个MOS结构，每个MOS结构均包括源极、栅极和漏极，且该多个MOS结构的所有源极电连接、所有漏极电连接、所有栅极电连接，上述图2中仅以共用同一个伪栅极DG的一对MOS结构为例进行说明。
在第一种可能的实施例中，当该ESD保护器件为GGNMOS时，该集成电路还可以包括电压端VDD和接地端GND。其中，第一漏极D1和第二漏极D2均与该电压端VDD耦合，第一源极S1、第二源极S2、第一栅极G1和第二栅极G2均与该接地端GND耦合。
在第二种可能的实施例中，当该ESD保护器件为GRNMOS时，该集成电路还可以包括电压端VDD、接地端GND和第一电阻R1。其中，第一漏极D1和第二漏极D2均与该电压端VDD耦合，第一源极S1和第二源极S2均与该接地端GND耦合，第一栅极G1和第二栅极G2均通过第一电阻R1与该接地端GND耦合。
在第三种可能的实施例中，当该ESD保护器件为2stack-NMOS，如图5所示，该集成电路还可以包括电压端VDD和接地端GND，该多个电极12还可以包括第三源极S3和第三栅极G3，第三源极S3和第三栅极G3设置在第一源极S1远离第一栅极G1的一侧。其中，第一漏极D1与电压端VDD耦合，第三源极S3与接地端GND耦合，第一栅极G1和第三栅极G3悬空。可选地，该多个电极还可以包括第三漏极D3，第三漏极D3与第一源极S1可以共用同一个电极，图5中表示为S1/D3。
在第四种可能的实施例中，当该ESD保护器件为3stack-NMOS，如图6所示，该集成电路还可以包括电压端VDD和接地端GND，该多个电极12还可以包括第三源极S3、第三栅极G3、第四源极S4和第四栅极G4。第三源极S3和第三栅极G3设置在第一源极S1远离第一栅极G1的一侧，第四源极S4和第四栅极G4设置在第三栅极G3远离第一栅极G1的一侧。其中，第一漏极D1与电压端VDD耦合，第四源极S4与接地端GND耦合，第一栅极G1、第三栅极G3和四栅极G4悬空。可选地，该多个电极还可以包括第三漏极D3和第四漏极D4，第三漏极D3与第一源极S1可以共用同一个电极，第四漏极D4与第三源极S3可以共用同一个电极，图6中分别表示为S1/D3和S3/D4。
需要说明的是，上述图5和图6中均以第一源极S1的左侧的电极为例，对该ESD保护器件为2stack-NMOS或者3stack-NMOS时该集成电路的结构进行举例说明，上述第二源极S2的右侧同样可以采样与第一源极S1的左侧类似的方式进行其他电极的部署或设计，上述图5和图6中将对应的电极表示为S3’、G3’、S4’、G4’、S2/D3’和S3’/D4’，本申请实施例在此不再赘述。
进一步的，该集成电路可以采用(fin field-effect transistor，FinFET)鳍形场效应晶体管工艺，具体可以是指该集成电路中的该ESD保护器件1可以采用FinFET工艺生成。当该集成电路还包括其他晶体管时，该其他晶体管也可以采用FinFET工艺生成，也可以采用环栅(gate-all-around，GAA)等其他工艺生成，本申请实施例对此不作具体限制。
本申请实施例将图2所提供的GGNMOS与图1所提供的GGNMOS进行了比较，具体通过传输线脉冲测试仪(transmission line pulse tester)测量得到的TLP电流、TLP电压和泄漏电流(leakage current，LC)如图7所示，作为本申请的一个实施例，其不限定于以 下具体参数值。由图7可知，图1所提供的GGNMOS对应的TLP电流在从0A增长至约3.4A时对应的泄漏电流发生了突变(即曲线L1)，即图1所提供的GGNMOS在TLP电流约为3.4A时失效，或者称为图1所提供的GGNMOS的失效电流约为3.4A；图2所提供的GGNMOS对应的TLP电流在从0A增长至约4.2A时对应的泄漏电流发生了突变(即曲线L2)，即图2所提供的GGNMOS在TLP电流约为4.2A时失效，或者称为图2所提供的GGNMOS的失效电流约为4.2A。此外，图2和图1所提供的GGNMOS均在TLP电压从约4.2V向上增加的过程中对应的TLP电流也相应增大，且图1所提供的GGNMOS对应的最大TLP电压约为7V、对应的最大TLP电流约为3.4A(即曲线L3)，图2所提供的GGNMOS对应的最大TLP电压约为7.2V、对应的最大TLP电流约为4.2A(即曲线L4)。综上可以得到，图2所提供的GGNMOS的最大TLP电流与图1所提供的GGNMOS的最大TLP电流相比增加了约20％，导通电阻(ron)减小了约12％。
在本申请实施例中，该集成电路中的ESD保护器件1包括衬底11、以及位于该衬底11上的多个电极12，该多个电极12包括伪栅极DG、以及位于该伪栅极DG两侧且与该伪栅极相邻的第一漏极D1和第二漏极D2，通过将第一漏极D1、第二漏极D2和该伪栅极DG电连接，可以使得该伪栅极DG与第一漏极D1和第二漏极D2等电位，从而与图1相比，避免了该伪栅极DG由于与第一漏极D1和第二漏极D2之间存在电压差而使得该伪栅极DG附近出现烧毁的情况，进而在不增加面积和成本的同时保证了该ESD保护器件的使用寿命。此外，将第一漏极D1、第二漏极D2和该伪栅极DG电连接还可以改善该ESD保护器件1的失效电流和导通电阻，从而进一步提高了该ESD保护器件的寿命和性能。
基于此，本申请实施例还提供一种电子设备，该电子设备包括：印刷电路板(printed circuit board，PCB)、以及上文所提供的任意一种集成电路，该集成电路固定于印刷电路板PCB。比如，该集成电路可以为该电子设备的处理器或者存储器对应的集成电路。可选的，该集成电路还包括封装基板，该封装基板通过焊球固定于该印刷电路板PCB上，该集成电路通过焊球固定于封装基板上。
需要说明的是，上文中提供的集成电路的相关描述均可引援至该电子设备中，本申请实施例在此不再赘述。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种集成电路，其特征在于，所述集成电路包括：
    衬底；
    位于所述衬底上的多个电极，所述多个电极包括伪栅极、第一漏极、第二漏极、第一栅极、第二栅极、第一源极和第二源极；
    其中，所述第一漏极和所述第二漏极位于所述伪栅极的两侧，所述第一栅极和所述第一源极位于所述第一漏极远离所述伪栅极的一侧，所述第二栅极和所述第二源极位于所述第二漏极远离所述伪栅极的一侧；
    所述第一漏极、所述第二漏极和所述伪栅极电连接。
  2. 根据权利要求1所述的集成电路，其特征在于，所述第一漏极通过第一过孔连接至第一金属，所述第二漏极通过第二过孔连接至第二金属，所述伪栅极通过第三过孔连接至第三金属。
  3. 根据权利要求2所述的集成电路，其特征在于，所述第一金属、所述第二金属和第三金属在同一金属层上且电连接。
  4. 根据权利要求3所述的集成电路，其特征在于，所述第一金属、所述第二金属和第三金属为同一块金属。
  5. 根据权利要求1-4任一项所述的集成电路，其特征在于，所述多个电极中相邻的漏极与栅极之间的距离大于相邻的源极与栅极之间的距离。
  6. 根据权利要求1-5任一项所述的集成电路，其特征在于，所述集成电路还包括：电压端和接地端；
    所述第一漏极和所述第二漏极均与所述电压端耦合；
    所述第一源极、所述第二源极、所述第一栅极和所述第二栅极均与所述接地端耦合。
  7. 根据权利要求6所述的集成电路，其特征在于，所述集成电路还包括：第一电阻；
    所述第一栅极和所述第二栅极通过所述第一电阻与所述接地端耦合。
  8. 根据权利要求1-5任一项所述的集成电路，其特征在于，所述集成电路还包括：电压端和接地端，所述多个电极还包括第三源极和第三栅极，所述第三源极和所述第三栅极设置在所述第一源极远离所述第一栅极的一侧；
    所述第一漏极与所述电压端耦合；
    所述第三源极与所述接地端耦合；
    所述第一栅极和所述第三栅极悬空。
  9. 根据权利要求8所述的集成电路，其特征在于，所述多个电极还包括第四源极和第四栅极，所述第四源极和所述第四栅极均设置在所述第三栅极远离所述第一栅极的一侧；
    所述第四源极与所述接地端耦合；
    所述第四栅极悬空。
  10. 根据权利要求1-9任一项所述的集成电路，其特征在于，所述集成电路采用鳍形场效应晶体管FinFET工艺。
  11. 根据权利要求1所述的集成电路，其特征在于，
    所述第一源极和所述第二源极相互电连接；
    所述第一栅极和第二栅极相互电连接，或者，所述第一栅极和所述第二栅极悬空。
  12. 一种ESD保护器件，其特征在于，所述ESD保护器件包括：
    衬底；
    位于所述衬底上的多个电极，所述多个电极包括伪栅极、第一漏极、第二漏极、第一栅极、第二栅极、第一源极和第二源极；
    其中，所述第一漏极和所述第二漏极位于所述伪栅极的两侧，所述第一栅极和所述第一源极位于所述第一漏极远离所述伪栅极的一侧，所述第二栅极和所述第二源极位于所述第二漏极远离所述伪栅极的一侧；
    所述第一漏极、所述第二漏极和所述伪栅极电连接。
PCT/CN2021/117262 2021-09-08 2021-09-08 一种集成电路及esd保护器件 WO2023035153A1 (zh)

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