WO2023026510A1 - Dispositif de stockage à semi-conducteurs - Google Patents

Dispositif de stockage à semi-conducteurs Download PDF

Info

Publication number
WO2023026510A1
WO2023026510A1 PCT/JP2021/045758 JP2021045758W WO2023026510A1 WO 2023026510 A1 WO2023026510 A1 WO 2023026510A1 JP 2021045758 W JP2021045758 W JP 2021045758W WO 2023026510 A1 WO2023026510 A1 WO 2023026510A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminals
memory device
signal terminals
signal
semiconductor memory
Prior art date
Application number
PCT/JP2021/045758
Other languages
English (en)
Japanese (ja)
Inventor
秋一 石村
Original Assignee
キオクシア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by キオクシア株式会社 filed Critical キオクシア株式会社
Publication of WO2023026510A1 publication Critical patent/WO2023026510A1/fr
Priority to US18/584,427 priority Critical patent/US20240196568A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2039—Modifications to facilitate cooling, ventilating, or heating characterised by the heat transfer by conduction from the heat generating element to a dissipating body
    • H05K7/205—Heat-dissipating body thermally connected to heat generating element via thermal paths through printed circuit board [PCB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector

Definitions

  • This embodiment relates to a semiconductor memory device.
  • a semiconductor memory device includes a substrate, a plurality of memory chips and a controller mounted on one surface of the substrate, and a plurality of terminals provided on the other surface of the substrate.
  • a semiconductor memory device includes a substrate, a plurality of memory chips, a controller, a plurality of terminals, a sealing member, and a sheet.
  • the substrate has a first surface and a second surface opposite the first surface.
  • the plurality of memory chips are mounted on the first surface of the substrate.
  • the controller is mounted on the first surface of the substrate and controls the plurality of memory chips.
  • the plurality of terminals are provided on the second surface of the substrate and include a plurality of test terminals.
  • the sheet is provided on the second surface of the substrate and covers the plurality of test terminals among the plurality of terminals.
  • FIG. 1 is a diagram exemplifying the outer shape of a semiconductor memory device according to a first embodiment
  • FIG. It is a figure which shows the structural example of the same semiconductor memory device.
  • FIG. 2 is a plan view showing an outer shape of a connector to which the same semiconductor memory device is attached and an arrangement example of areas in contact with sheets; 3 is a side view showing a state in which the same semiconductor memory device is set in a connector;
  • FIG. 2 is a side view showing a state in which the same semiconductor memory device is attached (connected) to a connector;
  • FIG. FIG. 11 is a plan view showing a second main surface on which a plurality of terminals and sheets are arranged in a semiconductor memory device according to a second embodiment;
  • FIG. 2 is a plan view showing an outer shape of a connector to which the same semiconductor memory device is attached and an arrangement example of areas in contact with sheets
  • FIG. 11 is a plan view showing a second main surface on which a plurality of terminals and sheets of a semiconductor memory device according to a third embodiment are arranged
  • FIG. 2 is a plan view showing an outer shape of a connector to which the same semiconductor memory device is attached and an arrangement example of areas in contact with sheets
  • FIG. 11 is a plan view showing a second main surface on which a plurality of terminals and sheets are arranged in a semiconductor memory device according to a fourth embodiment
  • FIG. 2 is a plan view showing an outer shape of a connector to which the same semiconductor memory device is attached and an arrangement example of areas in contact with sheets
  • FIG. 14 is a plan view showing a second main surface on which a plurality of terminals and sheets of a semiconductor memory device according to a fifth embodiment are arranged;
  • FIG. 2 is a plan view showing an outer shape of a connector to which the same semiconductor memory device is attached and an arrangement example of areas in contact with sheets;
  • FIG. 20 is a plan view showing a second main surface on which a plurality of terminals and sheets are arranged in a semiconductor memory device according to a sixth embodiment;
  • FIG. 2 is a plan view showing an outer shape of a connector to which the same semiconductor memory device is attached and an arrangement example of areas in contact with sheets;
  • the direction along a predetermined plane is the first direction
  • the direction intersecting the first direction along the predetermined plane is the second direction
  • the direction intersecting the predetermined plane is the third direction. It is sometimes called direction.
  • These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions, which will be described later.
  • expressions such as “upper” and “lower” are based on the substrate on which the semiconductor memory device is mounted.
  • the first direction intersects the surface of the substrate the direction away from the substrate along the first direction is referred to as up, and the direction approaching the substrate along the first direction is referred to as down.
  • the lower surface or the lower end of a certain structure it means the surface or end portion of the structure on the side of the substrate, and when referring to the upper surface or the upper end, the surface or end portion of the structure opposite to the substrate is meant. shall mean.
  • a portion that intersects the first direction or the second direction is called an edge portion
  • a surface that intersects the first direction or the second direction is called an end surface, a side surface, or the like.
  • a “semiconductor memory device” includes a nonvolatile memory and a controller that controls this nonvolatile memory.
  • a semiconductor memory device is a memory device for storage configured so that data can be freely read from and written to a nonvolatile memory.
  • a semiconductor memory device may be implemented as, for example, a memory card or a solid state drive (SSD). In this case, these memory cards and SSDs can be used as storage for various information processing devices that function as various host devices, such as personal computers, mobile devices, video recorders, and in-vehicle devices.
  • FIG. 1 is a diagram exemplifying the external shape of the semiconductor memory device according to the first embodiment.
  • the semiconductor memory device according to the first embodiment has a card shape and can function as an SSD that can be attached to a connector in a host device.
  • the connector to which the semiconductor memory device according to this embodiment is attached may be, for example, a hinge type connector.
  • a push-pull type connector or a push-push type connector may be used.
  • the connector to which the semiconductor memory device is attached is a hinge type connector, but it is not limited to this.
  • semiconductor memory devices may be referred to as memory devices.
  • FIG. 1(a) is a plan view showing one surface of the memory device 10.
  • FIG. 1(b) is a side view showing one side of the memory device 10.
  • FIG. 1(c) is a plan view showing one surface of the memory device 10, and is a plan view showing another surface located on the opposite side of the one surface shown in FIG. 1(a).
  • the X-axis, Y-axis and Z-axis are defined as follows. These X-axis, Y-axis and Z-axis are orthogonal to each other.
  • the X-axis runs along the width direction of the memory device 10 .
  • the Y-axis runs along the length of memory device 10 .
  • the Z-axis runs along the thickness direction of memory device 10 .
  • viewing the memory device 10 and the connector 50 to which the memory device 10 is attached (see FIG. 3, etc.) from the Z-axis direction is referred to as planar view.
  • the memory device 10 is a semiconductor memory device configured to operate with a power supply voltage supplied from the outside.
  • the memory device 10 has, for example, a rectangular card shape having a first width W1 in the X direction, a first length L1 in the Y direction, and a first thickness T1 in the Z direction. has the outline of The first length L1 is greater than the first width W1.
  • the first width W1, the first length L1 and the first thickness T1 may be, for example, 14 ⁇ 0.10 mm, 18 ⁇ 0.10 mm and 1.4 ⁇ 0.10 mm respectively.
  • the memory device 10 has rectangular first and second main surfaces 11 and 12 that are spaced apart in the Z direction and extend in the X and Y directions.
  • the memory device 10 has rectangular first and second end surfaces 21 and 22 spaced apart in the Y direction and extending in the X and Z directions.
  • the first end surface 21 is provided between one edge of the first main surface 11 and the second main surface 12 in the Y direction.
  • the second end surface 22 is provided between the other edge in the Y direction of the first main surface 11 and the second main surface 12 .
  • the memory device 10 has rectangular first and second sides 23 and 24 spaced apart in the X direction and extending in the Y and Z directions.
  • the first side surface 23 is provided between one edge in the X direction of the first main surface 11 and the second main surface 12 .
  • the second side surface 24 is provided between the other edges in the X direction of the first main surface 11 and the second main surface 12 .
  • the memory device 10 has a first corner 25 at the connecting portion of the first end surface 21 and the first side surface 23, a second corner portion 26 at the connecting portion of the first end surface 21 and the second side surface 24, and a second A connecting portion of the second end surface 22 and the first side surface 23 has a third corner portion 27 , and a connecting portion of the second end surface 22 and the second side surface 24 has a fourth corner portion 28 .
  • the first corner 25, the third corner 27 and the fourth corner 28 are chamfered with R0.2, for example.
  • the second corner 26 is chamfered with a chamfer of, for example, C1.1, which is different from the other corners 25, 27, and 28 in order to distinguish between the front and back.
  • FIG. 2 is a diagram showing a configuration example of the memory device 10.
  • the memory device 10 comprises a printed circuit board 15 and a NAND flash memory 16 and a controller 17 mounted on the printed circuit board 15 .
  • the NAND flash memory 16 and controller 17 are mounted on the first surface (upper surface) 13 of the printed circuit board 15 .
  • the second (lower) side 14 of the printed circuit board 15 may be coplanar with the second major side 12 of the memory device 10 .
  • the NAND flash memory 16 may include a plurality of stacked NAND flash memory chips. These multiple NAND flash memory chips may be configured to perform interleaved operations.
  • the controller 17 may be an LSI including an SoC (System on a Chip).
  • SoC System on a Chip
  • the controller 17 controls the NAND flash memory 16 and the entire memory device 10 including the NAND flash memory 16 .
  • the controller 17 can, for example, perform read/write control for the NAND flash memory 16 and communication control with the outside.
  • the memory device 10 has a PCIe interface as a system interface, and the memory device 10 may perform communication control using a protocol such as NVM Express (NVMe) (trademark) conforming to the PCIe standard.
  • NVM Express NVM Express
  • the NAND flash memory 16, the controller 17, and the first surface 13 of the printed circuit board 15 are, for example, entirely covered and completely sealed with a mold resin 19, which is a sealing member.
  • the memory device 10 is implemented as a card-shaped package (memory package).
  • a plurality of terminals 30 are provided on the second main surface 12 of the memory device 10 (the second surface 14 of the printed circuit board 15). These terminals 30 are sometimes called pins or pads.
  • the multiple terminals 30 include multiple signal terminals P and multiple test terminals T.
  • the plurality of signal terminals P includes a plurality of first signal terminals P1, a plurality of second signal terminals P2, a plurality of third signal terminals P3, and a plurality of fourth signal terminals P4.
  • the plurality of first signal terminals P1 are closer to the first end surface 21 than the plurality of second signal terminals P2, and are arranged in the X direction with a first interval from each other.
  • the plurality of second signal terminals P2 are closer to the second end face 22 than the plurality of first signal terminals P1, and are arranged in the X direction at a second interval from each other.
  • the distance in the Y direction between the plurality of first signal terminals P1 and the plurality of second signal terminals P2 is longer than the distance in the Y direction between the plurality of first signal terminals P1 and the first end surface 21, and It is longer than the Y-direction distance between the plurality of second signal terminals P2 and the second end face 22 .
  • the plurality of third signal terminals P3 and the plurality of fourth signal terminals P4 are provided between the plurality of first signal terminals P1 and the plurality of second signal terminals P2.
  • the distance in the Y direction between the plurality of third signal terminals P3 and the plurality of fourth signal terminals P4 and the plurality of first signal terminals P1 is the distance between the plurality of third signal terminals P3 and the plurality of fourth signal terminals P4 and the plurality of first signal terminals P1. 2 larger than the distance in the Y direction from the signal terminal P2.
  • the plurality of third signal terminals P3 are arranged in the X direction with a third interval from each other.
  • the plurality of fourth signal terminals P4 are arranged in the X direction at a fourth interval from each other.
  • the number of the multiple third signal terminals P3 is less than the number of the multiple first signal terminals P1 and less than the number of the multiple second signal terminals P2.
  • the number of the plurality of fourth signal terminals P4 is also less than the number of the plurality of first signal terminals P1 and less than the number of the plurality of second signal terminals P2.
  • a test terminal T is provided between the plurality of third signal terminals P3 and the plurality of fourth signal terminals P4. Note that the first to fourth intervals may all be the same or different.
  • the first signal terminal P1 may include, for example, signal terminals for two lanes for a high-speed serial interface such as PCI Express (registered trademark) (PCIe).
  • the signal terminals P corresponding to one lane may include two receiving differential signal pair terminals and two transmitting differential signal pair terminals. Also, the two differential terminals may be surrounded by ground terminals.
  • PCIe lane can be added between the first signal terminal P1 and the second signal terminal P2.
  • the third signal terminal P3 and the fourth signal terminal P4 may include, for example, signal terminals for arbitrary optional signals that differ for each product.
  • Signal terminals for option signals may include, for example, signal terminals for sideband signals (SMBus signal, WAKE# signal, and PRSNT# signal) conforming to the PCIe standard, ground terminals, and the like.
  • Sideband signals conforming to the PCIe standard may include, for example, a CLKREF signal pair, a CLKREQ# signal, a PERST# signal, and the like.
  • At least part of the third signal terminal P3 and the fourth signal terminal P4 may not be essential signal terminals for the memory device 10.
  • FIG. In other words, it may be an optional signal terminal for memory device 10 . Therefore, the number of the third signal terminal P3 and the fourth signal terminal P4 may be smaller than the number of the first signal terminal P1 and the second signal terminal P2. Note that the sideband signal in this embodiment may be called an optional signal.
  • the second signal terminal P2 may include, for example, a control signal common to each product and a terminal for power supply.
  • This second signal terminal P2 may mainly include a signal terminal for differential clock signals, a signal terminal for common PCIe sideband signals, a power supply terminal and other signal terminals.
  • the plurality of test terminals T are, for example, electrically connected to the controller 17 and used to perform a non-defective product selection test for the memory device 10 product.
  • the plurality of test terminals T are arranged outside the area in which the plurality of signal terminals P are arranged.
  • the plurality of test terminals T are, for example, an area between the first signal terminal P1 and the second signal terminal P2, and an area between the third signal terminal P3 and the fourth signal terminal P4. located in the area.
  • the plurality of test terminals T are, for example, arranged in four rows in the Y direction and six columns in the X direction at regular intervals.
  • a TIM (Thermal Interface Material) 20 is attached as a mask sheet to the portion of the second main surface 12 (the second surface 14 of the printed circuit board 15) of the memory device 10 where the plurality of test terminals T are provided. ing. A plurality of test terminals T are covered by TIM20 and are in contact with TIM20.
  • Attachment area A1 the area of the memory device 10 to which the TIM 20 is attached.
  • a material having excellent thermal conductivity, insulating properties, flexibility and heat resistance can be used.
  • a material having a higher thermal conductivity than polycarbonate is used. The thermal conductivity of polycarbonate is about 0.2 W/(m ⁇ K).
  • TIM 20 for example, one having a thermal conductivity of about 1.0 W/(m ⁇ K) to 8.0 W/(m ⁇ K) may be used. Moreover, as TIM, a material having a thermal conductivity greater than 8.0 W/(m ⁇ K) may be used. As the TIM 20, for example, a material having higher insulating properties than carbon graphite is used.
  • the shape, arrangement, etc. of the terminals 30 described above are merely examples, and the lengths of the plurality of terminals 30 in the Y direction may not all be the same.
  • FIG. 3 is a plan view showing an outer shape of a connector 50 provided in a host device to which the memory device 10 is attached and an arrangement example of a contact area A2 with which the TIM 20 contacts.
  • the memory device 10 is mounted from above the connector 50 shown in FIG. 3 with the terminal surface (second main surface 12) shown in FIG. 1(c) facing downward.
  • 4 is a side view showing a state in which the memory device 10 is set before the memory device 10 is attached (connected) to the connector 50.
  • FIG. FIG. 5 is a side view showing a state in which the memory device 10 is attached (connected) to the connector 50.
  • a connector 50 to which the memory device 10 is attached is provided on the printed circuit board 40 of the host device and has a plurality of lead frames 51, 52, 53 and 54, as shown in FIGS. These lead frames 51 to 54 are arranged so as to correspond to the signal terminals P1, P2, P3 and P4 of the memory device 10, respectively. Each of the lead frames 51 to 54 forms a spring lead whose distal end side is bent in a direction away from the printed circuit board 40 with respect to the base end side.
  • the lead frames 51 to 54 are arranged with their longitudinal directions along the Y direction.
  • the lead frames 51, 53 and 54 are arranged such that the contact portions 55 at the tips thereof, which are connected to the signal terminals P1, P3 and P4, face the lead frame 52 side in the Y direction.
  • the lead frame 52 is arranged such that the contact portion 55 at the tip thereof, which is connected to the signal terminal P2, faces the lead frames 51, 53 and 54 in the Y direction. That is, the tips of the lead frames 53 and 54 face the tip of the lead frame 52 in the Y direction.
  • the lead frames 51 to 54 have the same length in the Y direction. However, the orientation and/or the length in the Y direction of the lead frames 51 to 54 are not limited to this. For example, the lead frames 51 to 54 may have different lengths in the Y direction.
  • the connector 50 has a connector frame 60 and a lid portion 70 connected to the connector frame 60 via a hinge 80 so as to be freely opened and closed.
  • the connector frame 60 fixes the lead frames 51 to 54 and supports the memory device 10 when the memory device 10 is mounted.
  • the connector frame 60 accommodates the memory device 10 and positions it with respect to the lead frames 51 to 54 when the memory device 10 is attached to the connector 50 .
  • the connector frame 60 includes a first wall portion 61, a second wall portion 62, a third wall portion 63, a fourth wall portion 64, a connection portion 65, and a notch portion 66. , and corner guide portions 67 .
  • the first wall portion 61 extends in the X direction.
  • the first wall portion 61 contacts the first end surface 21 of the memory device 10 when the memory device 10 is mounted.
  • the first wall portion 61 supports the mounting portion 56 on the base end side of the lead frame 51 by adhesion or the like.
  • the second wall portion 62 extends in the Y direction.
  • the second wall portion 62 contacts the first side surface 23 of the memory device 10 when the memory device 10 is mounted.
  • the third wall portion 63 extends in the Y direction.
  • the third wall portion 63 contacts the second side surface 24 of the memory device 10 when the memory device 10 is mounted.
  • the fourth wall portion 64 extends in the X direction.
  • the fourth wall portion 64 contacts the second end surface 22 of the memory device 10 when the memory device 10 is mounted.
  • the fourth wall portion 64 supports the mounting portion 56 on the base end side of the lead frame 52 by adhesion or the like.
  • the connecting portion 65 extends in the X direction and connects the second wall portion 62 and the third wall portion 63 at a position between the first wall portion 61 and the fourth wall portion 64 .
  • the connecting portion 65 supports the mounting portion 56 on the base end side of the lead frames 53 and 54 by adhesion or the like.
  • Corner guide portion 67 prevents the memory device 10 from being attached to the connector frame 60 in the wrong orientation. Corner guide portion 67 conforms to second corner portion 26 of memory device 10 when memory device 10 is mounted in connector frame 60 in the correct orientation.
  • the lid part 70 accommodates the memory device 10 while being opened at an angle of 90° to 180° with respect to the printed circuit board 40, as indicated by the two-dot chain line in FIG.
  • the lid portion 70 has a guide portion 72 for positioning the memory device 10 provided near the hinge 80 and a claw portion 71 provided at a position away from the hinge 80 .
  • Notch portions 66 are formed in the second wall portion 62 and the third wall portion 63 of the connector frame 60 . The notch portion 66 is coupled with the claw portion 71 of the lid portion 70 when the lid portion 70 is closed (FIGS. 4 and 5).
  • the contact area A2 is arranged on the printed circuit board 40 on which the connector 50 is mounted, avoiding the plurality of lead frames 52 to 54 and the connecting portion 65. As shown in FIG. More specifically, the contact area A2 is provided between the lead frame 53 and the lead frame 54, for example. Also, the contact area A2 is provided between the plurality of lead frames 52 and the connecting portion 65 .
  • a solid pattern with good thermal conductivity may be formed in the contact area A2 of the printed circuit board 40 .
  • This solid pattern may be connected to a ground pattern.
  • the signal terminals P arranged in the memory device 10 into contact with the lead frames 51 to 54 of the connector 50, it is possible to secure a heat radiation path to the mounting board in the host device. be.
  • the signal terminal P and the lead frames 51 to 54 are in point contact, the heat radiation efficiency is not very good.
  • test terminals T of the memory device 10 are directly connected to, for example, the controller 17 of the memory device 10, and are concentrated in an attachment area A1 of a certain size where the signal terminals P do not exist.
  • the test terminal T is covered with a TIM 20 as a mask sheet.
  • This TIM 20 is attached to an attachment area A1 having a certain size. Therefore, this TIM 20 can be used as a heat dissipation surface.
  • TIM20 which has a higher thermal conductivity than polycarbonate, is used as the mask sheet.
  • Polycarbonate which is the material of the mask sheet, has a high insulating property but a low thermal conductivity of about 0.2 W/(m ⁇ K).
  • TIM20 has a thermal conductivity of, for example, about 1.0 W/(m K) to 8.0 W/(m K), or greater than 8.0 W/(m K). .
  • FIG. 6 is a plan view showing the external shape of a memory device 10A according to the second embodiment, and an attachment area A11 to which a TIM 20A is attached.
  • FIG. 7 is also a plan view showing the outer shape of the connector 50A and the contact area A21 on the printed circuit board (mounting board) with which the TIM 20A contacts.
  • the positions of the third signal terminal P3 and the fourth signal terminal P4 in the center of the Y direction are closer to the first signal terminal P1 than to the second signal terminal P2. and the position of the TIM 20A is closer to the first signal terminal P1 than the second signal terminal P2, and the plurality of test terminals T are arranged in five rows in the Y direction and six columns in the X direction, respectively, etc. It differs from the memory device 10 shown in FIG. 1 in that they are arranged at intervals.
  • the tip side of the contact portion 55 of the lead frame 53 at the center in the Y direction faces the lead frame 51 side with respect to the base end side, and the contact area A21 is connected to the lead frame 51. 65, which is different from the connector 50 shown in FIG.
  • the attachment area A11 to which the TIM 20A of the memory device 10A is attached can be brought closer to the controller 17 (FIG. 2). Also, the heat dissipation area can be increased. Therefore, according to the second embodiment, it is possible to further improve the heat radiation efficiency as compared with the first embodiment.
  • FIG. 8 is a plan view showing the outer shape of the memory device 10B and the attachment area A12 to which the TIM 20B is attached according to the third embodiment.
  • FIG. 9 is also a plan view showing the outer shape of the connector 50B and the contact area A22 on the printed circuit board (mounting board) with which the TIM 20B contacts.
  • the memory device 10B shown in FIG. 8 has only a plurality of fourth signal terminals P4 as the signal terminals in the center in the Y direction, the areas of the test terminals T and the TIM 20B are expanded to the vicinity of the second side surface 24, and the test It is different from the memory device 10 shown in FIG. 1 in that the terminals T are arranged in 5 rows in the Y direction and 9 columns in the X direction at regular intervals.
  • the connector 50B shown in FIG. 9 has only the lead frame 54 on one side in the X direction as the lead frame in the center in the Y direction, and the contact area A22 is expanded to a position near the third wall portion 63. , differs from the connector 50 shown in FIG.
  • the heat dissipation area is reduced to that of the first and second embodiments. can be spread out further. Thereby, it is possible to further improve the heat radiation efficiency.
  • FIG. 10 is a plan view showing the external shape of the memory device 10C according to the fourth embodiment, and the adhesion areas A13-1 and A13-2 to which the TIMs 20C-1 and 20C-2 are adhered.
  • FIG. 11 is a plan view showing the outer shape of the connector 50C and the contact areas A23-1 and A23-2 on the printed circuit board (mounting board) with which the TIMs 20C-1 and 20C-2 are in contact.
  • the memory device 10C shown in FIG. 10 has only the first signal terminal P1 and the second signal terminal P2 as the signal terminals P, and the full width in the X direction is provided between the first signal terminal P1 and the second signal terminal P2.
  • 3 rows and 12 columns of test terminals T and 5 rows and 12 columns of test terminals T are arranged, and an adhesion area A13- where TIM20C-1 is adhered to the area where these test terminals T are arranged. 1 and an attachment area A13-2 to which TIM20C-2 is attached.
  • the connector 50C shown in FIG. 11 has only the lead frames 51 and 52 on both sides in the Y direction as lead frames, and the contact area A23-1 is provided between the lead frame 51 and the connecting portion 65 to cover the full width in the X direction. 3 in that a contact area A23-2 is provided between the connection portion 65 and the lead frame 52 and covers the full width in the X direction.
  • the bonding areas A13-1 and A13-2 where the test terminals T of the memory device 10C and the TIMs 20C-1 and 20C-2 are arranged are extended to both sides in the X direction, thereby dissipating heat.
  • the area can be further expanded as compared with the first to third embodiments. Thereby, it is possible to further improve the heat radiation efficiency.
  • FIG. 12 is a plan view showing the external shape of the memory device 10D and the attachment area A14 to which the TIM 20D is attached according to the fifth embodiment.
  • FIG. 13 is also a plan view showing the outer shape of the connector 50D and the contact area A24 on the printed circuit board (mounting board) with which the TIM 20D contacts.
  • the second signal terminal P2, the third signal terminal P3, the fourth signal terminal P4, the test terminal T, the TIM 20D, and the attachment area A14 are arranged in the first signal terminal P1 more than in the first embodiment. , and further away from the second end face 22, which is different from the memory device 10 shown in FIG.
  • the connector 50D shown in FIG. 13 has the lead frames 53 and 54, the connection portion 65 and the contact area A24 closer to the lead frame 51 than in the first embodiment, and the length of the lead frame 52 and the fourth wall portion 64 in the Y direction is longer than in the first embodiment, which is different from the connector 50 shown in FIG.
  • the heat radiating portion can be brought closer to the controller 17 (FIG. 2). Thereby, heat radiation efficiency can be improved.
  • FIG. 14 is a plan view showing the external shape of the memory device 10E and the attachment area A15 to which the TIM 20E is attached according to the sixth embodiment.
  • FIG. 15 is also a plan view showing the outer shape of the connector 50E and the contact area A25 on the printed circuit board (mounting board) with which the TIM 20E contacts.
  • a memory device 10E shown in FIG. , TIM 20E and the attachment area A15 are formed between the second signal terminal P2 and the second end surface 22 over the entire width in the X direction. .
  • the connector 50E shown in FIG. Another difference from the connector 50 shown in FIG. 3 is that the contact area A25 is formed to the full width in the X direction.
  • a heat dissipation portion can be provided at the Y-direction end of the memory device 10E and the connector 50E.
  • the adhesion area A15 of the TIM 20E is provided between the second signal terminal P2 and the second end face 22, but the adhesion area A15 of the TIM 20E is provided between the first signal terminal P1 and the first end face 21. You can set it in between.
  • the NAND flash memory has been exemplified and explained as the nonvolatile memory.
  • the function of this embodiment is, for example, PRAM (Phase change Random Access Memory), ReRAM (Resistive Random Access Memory), MRAM (Magnetoresistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Thermal Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un dispositif de stockage à semi-conducteurs qui comprend un substrat, une pluralité de puces de mémoire, un dispositif de commande, une pluralité de bornes, un élément d'étanchéité et une feuille. Le substrat comprend une première surface et une seconde surface située sur le côté opposé à la première surface. La pluralité de puces de mémoire sont montées sur la première surface du substrat. Le dispositif de commande est monté sur la première surface du substrat et commande la pluralité de puces de mémoire. La pluralité de bornes sont disposées sur la seconde surface du substrat et comprennent une pluralité de bornes de test. La feuille est disposée sur la seconde surface du substrat et recouvre la pluralité de bornes de test parmi la pluralité de bornes.
PCT/JP2021/045758 2021-08-25 2021-12-13 Dispositif de stockage à semi-conducteurs WO2023026510A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/584,427 US20240196568A1 (en) 2021-08-25 2024-02-22 Semiconductor memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-137113 2021-08-25
JP2021137113A JP2023031558A (ja) 2021-08-25 2021-08-25 半導体記憶装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/584,427 Continuation US20240196568A1 (en) 2021-08-25 2024-02-22 Semiconductor memory device

Publications (1)

Publication Number Publication Date
WO2023026510A1 true WO2023026510A1 (fr) 2023-03-02

Family

ID=85322582

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/045758 WO2023026510A1 (fr) 2021-08-25 2021-12-13 Dispositif de stockage à semi-conducteurs

Country Status (4)

Country Link
US (1) US20240196568A1 (fr)
JP (1) JP2023031558A (fr)
TW (1) TWI824362B (fr)
WO (1) WO2023026510A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016012693A (ja) * 2014-06-30 2016-01-21 株式会社東芝 半導体装置
JP2020161098A (ja) * 2019-03-20 2020-10-01 キオクシア株式会社 半導体記憶装置
US20210103791A1 (en) * 2019-10-02 2021-04-08 Samsung Electronics Co., Ltd. Card type solid state drive

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7872483B2 (en) * 2007-12-12 2011-01-18 Samsung Electronics Co., Ltd. Circuit board having bypass pad
JP5198379B2 (ja) * 2009-07-23 2013-05-15 株式会社東芝 半導体メモリカード
JP7292864B2 (ja) * 2018-04-23 2023-06-19 キオクシア株式会社 半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016012693A (ja) * 2014-06-30 2016-01-21 株式会社東芝 半導体装置
JP2020161098A (ja) * 2019-03-20 2020-10-01 キオクシア株式会社 半導体記憶装置
US20210103791A1 (en) * 2019-10-02 2021-04-08 Samsung Electronics Co., Ltd. Card type solid state drive

Also Published As

Publication number Publication date
TW202310239A (zh) 2023-03-01
US20240196568A1 (en) 2024-06-13
TWI824362B (zh) 2023-12-01
JP2023031558A (ja) 2023-03-09

Similar Documents

Publication Publication Date Title
US10409338B2 (en) Semiconductor device package having an oscillator and an apparatus having the same
TW540004B (en) IC card
US9377825B2 (en) Semiconductor device
US8547703B2 (en) Card-type peripheral apparatus
TWI619227B (zh) 用於高速低剖面記憶體封裝及插腳輸出設計的系統及方法
TW201830654A (zh) 具有不對稱晶片堆疊結構的半導體封裝
US11310905B2 (en) Memory device including a conductive plate with a shielding region
CN101232009A (zh) 用于集成电路模块的安装结构
TWI655737B (zh) 包含複數個堆疊晶片之半導體封裝
US10440826B2 (en) Semiconductor device
JP2001118984A (ja) 電子モジュール及びコネクタ付電子モジュール
TWM343230U (en) Space minimized flash drive
CN110473846B (zh) 与半导体装置一起使用的散热器
US20240178212A1 (en) Semiconductor device and electronic device
WO2023026510A1 (fr) Dispositif de stockage à semi-conducteurs
US20210134693A1 (en) Semiconductor package
US9538661B2 (en) Electronic device module including a printed circuit
US10593648B2 (en) Heart transfer label structure
US20230371209A1 (en) Self-aligning heat fins for thermal management
US20220302661A1 (en) Storage system
US20220229587A1 (en) Memory system
KR102062738B1 (ko) 반도체 패키지
US20230091779A1 (en) Memory card and memory system
KR20220021754A (ko) 메모리 카드
JP2002353409A (ja) 半導体モジュール、半導体モジュール積層体及び電子装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21955118

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21955118

Country of ref document: EP

Kind code of ref document: A1