WO2023020009A1 - 静电保护电路和静电保护结构 - Google Patents

静电保护电路和静电保护结构 Download PDF

Info

Publication number
WO2023020009A1
WO2023020009A1 PCT/CN2022/090055 CN2022090055W WO2023020009A1 WO 2023020009 A1 WO2023020009 A1 WO 2023020009A1 CN 2022090055 W CN2022090055 W CN 2022090055W WO 2023020009 A1 WO2023020009 A1 WO 2023020009A1
Authority
WO
WIPO (PCT)
Prior art keywords
doped region
diode
electrostatic protection
region
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/090055
Other languages
English (en)
French (fr)
Inventor
许杞安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Publication of WO2023020009A1 publication Critical patent/WO2023020009A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/80—Arrangements for protection of devices protecting against overcurrent or overload, e.g. fuses or shunts

Definitions

  • the present disclosure relates to the technical field of integrated circuits, in particular, to an electrostatic protection circuit and an electrostatic protection structure.
  • ESD Electro-Static discharge, electrostatic charge discharge
  • the trigger voltage of the ESD circuit is high, the sustain voltage is low, and latch-up is prone to occur, which is not suitable for electrostatic protection of memory products.
  • the purpose of the present disclosure is to provide an electrostatic protection circuit and an electrostatic protection structure, which can overcome the problems of high trigger voltage, low maintenance voltage, and prone to latch-up caused by the limitations and defects of related technologies to a certain extent.
  • an electrostatic protection circuit which includes a first sub-circuit, and the first sub-circuit includes: a first trigger circuit including a first diode and a second diode; a second trigger circuit circuit, including a third diode and a transistor; a thyristor circuit, including a PNP transistor and an NPN transistor; wherein, the anode of the first diode is connected to the anode of the electrostatic protection circuit, and the first two The cathode of the pole tube is connected to the anode of the second diode, and the cathode of the second diode is connected to the cathode of the electrostatic protection circuit; the anode of the third diode is connected to the anode, and the anode of the first diode is connected to the anode.
  • the cathodes of the three diodes are electrically connected to the drains of the transistors, and the source and gate of the transistors are connected to the cathodes; the emitters of the PNP transistors are connected to the anodes, and the emitters of the NPN transistors are connected to the anodes. the cathode.
  • the base of the PNP transistor is connected to the collector of the NPN transistor, and the base of the NPN transistor is connected to the collector of the PNP transistor.
  • the gate of the transistor is connected with an adjustable resistor.
  • the anode of the first diode is the emitter of the PNP transistor, and the cathode of the first diode is the base of the PNP transistor;
  • the anode of the second diode is the base of the NPN transistor, and the cathode of the second diode is the emitter of the NPN transistor;
  • the anode of the third diode is the PNP
  • the emitter of the transistor, the cathode of the third diode is the base of the PNP transistor, and the source of the transistor is the cathode of the second diode.
  • a second subcircuit is further included, the second subcircuit and the first subcircuit are distributed symmetrically based on the cathodes of the first diodes, and the second subcircuit The cathode of the first diode is shared with the first sub-circuit.
  • the electrostatic protection circuit includes a first resistor and a second resistor, the first resistor is the base equivalent resistance of the PNP transistor, and the second resistor is the NPN transistor base equivalent resistance.
  • an electrostatic protection structure comprising a first substructure, the first substructure comprising: a P-type substrate; an N-well region and a P-well arranged in the P-type substrate region; the first P-doped region and the first N-doped region arranged in the P-well region, and the second N-doped region arranged in the P-well region and the N-well region, arranged in the The second P-doped region and the third N-doped region of the N well region; wherein, the second P-doped region is connected to the anode, the first N-doped region is connected to the cathode, and the first P-doped region It is connected with the third N-doped region, and the surface of the P-well region between the first N-doped region and the second N-doped region is provided with a gate structure.
  • the gate structure is connected to the cathode through an adjustable resistance.
  • it further includes: a deep N well region located in the P-type substrate, under the P well region and the N well region; an isolated N well region located in the One end of the P well region away from the N well region is used as an isolation structure; a shallow trench isolation structure is arranged between the first P doped region and the first N doped region; the second N between the doped region and the second P-doped region, and between the second P-doped region and the third N-doped region.
  • the first N-doped region, the second N-doped region and the gate structure form a gate-grounded N-type transistor.
  • the first P-doped region, the second P-doped region, the first N-doped region, the second N-doped region, the first The doping concentrations of the three N-doped regions are all higher than the doping concentrations of the N-well region and the P-well region.
  • the region length of the second N-doped region is twice that of the other doped regions.
  • it further includes a second substructure, the second substructure and the first substructure are distributed axially symmetrically with respect to the third N-doped region, and the second substructure structure and the first substructure share the third N-doped region.
  • the second P-doped region, the N-well region and the P-well region together form a PNP transistor
  • the first N-doped region and the P-well region region and the N-well region together constitute an NPN type transistor
  • the second P-doped region and the N-well region constitute a first diode
  • the P-doped region and the first N-doped region constitute a second Two diodes.
  • the depths of the shallow trench isolation structures are all smaller than the depths of the doped regions.
  • the electrostatic protection circuit provided by the embodiment of the present disclosure forms two charge discharge paths by using a first trigger circuit composed of a diode and a second trigger circuit composed of a GGNMOS, and uses a thyristor composed of a PNP transistor and an NPN transistor.
  • the circuit forms the third charge discharge path, which has the advantages of low trigger voltage, low leakage, high electrostatic protection ability and small manufacturing area.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit in an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a first sub-circuit in another embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of an electrostatic protection circuit in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an electrostatic protection structure in an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of an electrostatic protection structure in another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of an equivalent circuit of the electrostatic protection structure shown in FIG. 4 or FIG. 5 .
  • FIG. 7A and 7B are schematic diagrams of an electrostatic protection structure in another embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details being omitted, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit in an exemplary embodiment of the present disclosure.
  • the electrostatic protection circuit may include a first sub-circuit 100, and the first sub-circuit 100 includes:
  • the first trigger circuit 1 includes a first diode D1 and a second diode D2;
  • the second trigger circuit 2 includes a third diode D3 and a transistor M;
  • SCR circuit 3 including PNP transistor J1 and NPN transistor J2;
  • the anode of the first diode D1 is connected to the anode of the electrostatic protection circuit
  • the cathode of the first diode D1 is connected to the anode of the second diode D2
  • the cathode of the second diode D2 is connected to the cathode of the electrostatic protection circuit
  • the anode of the third diode D3 is connected to the anode, the cathode of the third diode D3 is electrically connected to the drain of the transistor M, and the source and gate of the transistor M are connected to the cathode;
  • the emitter of the PNP transistor J1 is connected to the anode, and the emitter of the NPN transistor J2 is connected to the cathode.
  • the base of the PNP transistor J1 is connected to the collector of the NPN transistor J2
  • the base of the NPN transistor J2 is connected to the collector of the PNP transistor J1 .
  • the circuit shown in Figure 1 sets three electrostatic discharge paths between the anode and the cathode of the electrostatic protection circuit. Since the gate of the transistor M is grounded, the first trigger circuit 1 and the The second trigger circuit 2 is provided with a dual-trigger SCR (Silicon Controlled Rectifier, SCR) structure, and the trigger voltage of the first trigger circuit 1 composed of diodes and the second trigger circuit 2 composed of diodes and transistors is low, which can be applied In the low-voltage circuit, the electrostatic discharge speed of the circuit can be effectively improved; by setting three electrostatic discharge paths, the electrostatic protection ability of the electrostatic protection circuit can be effectively improved, and the normal operation of the circuit can be protected.
  • SCR Silicon Controlled Rectifier
  • FIG. 2 is a schematic diagram of a first sub-circuit in another embodiment of the present disclosure.
  • the gate of the transistor M of the first sub-circuit 200 is connected to an adjustable resistor Rr.
  • the anode of the first diode D1 is the emitter of the PNP transistor J1
  • the cathode of the first diode D1 is the base of the PNP transistor J1 (the base of the PNP transistor J1 has the same effective resistance Rnw, shown as the first resistor R1 in the figure)
  • the anode of the second diode D1 is the base of the NPN transistor J2 (the base of the NPN transistor J2 has an equivalent resistance Rpw, shown as The second resistor R2)
  • the negative pole of the second diode D2 is the emitter of the NPN transistor J2
  • the positive pole of the third diode D3 is the emitter of the PNP transistor J1
  • the negative pole of the third diode D3 is the PNP Type transistor J1 base.
  • FIG. 3 is a schematic diagram of an electrostatic protection circuit in an embodiment of the present disclosure.
  • the electrostatic protection circuit further includes a second sub-circuit 300, the second sub-circuit 300 is identical to the first sub-circuit 200, and the second sub-circuit 300 and the first sub-circuit 200 are based on the first
  • the cathode of the diode D1 ie the base of the PNP transistor J1
  • the second sub-circuit 300 and the first sub-circuit 200 share the cathode of the first diode D1 (ie the base of the PNP transistor J1 ).
  • two symmetrical and identical sub-circuits are set based on the negative pole of the first diode D1 , which can provide a stronger electrostatic protection function while minimizing the manufacturing area.
  • FIG. 4 is a schematic diagram of an electrostatic protection structure in an embodiment of the present disclosure.
  • the electrostatic protection structure shown in FIG. 4 can be used to realize the first sub-circuit of the electrostatic protection circuit shown in FIGS. 1-2 or the second sub-circuit shown in FIG. 3 .
  • the electrostatic protection structure 400 includes:
  • the doped regions N3 are connected, and a gate structure G is provided on the surface of the P well region 43 between the first N-doped region N1 and the second N-doped region N2.
  • the first P-doped region P1, the second P-doped region P2, the first N-doped region N1, the second N-doped region N2, and the third N-doped region N3 The doping concentration of the N-well region and the P-well region are all greater than the doping concentration of the P-well region.
  • the first sub-circuit shown in Figure 1 can be realized through two well regions and five doped regions, realizing double triggering, low trigger voltage, and relatively strong electrostatic protection capability with three paths Strong attraction protection circuit, small manufacturing area and powerful function.
  • the specific principle of the electrostatic protection structure shown in Figure 4 is detailed below.
  • FIG. 5 is a schematic diagram of an electrostatic protection structure in another embodiment of the present disclosure.
  • the gate structure G of the circuit shown in FIG. 4 is connected to the cathode through an adjustable resistor Rr.
  • the first subcircuit also includes:
  • the deep N well region 44 is located under the P well region 42 and the N well region 43 in the P type substrate 41;
  • An isolated N well region 45 is located at one end of the P well region 42 away from the N well region 43, and is used as an isolation structure;
  • Shallow trench isolation structure (STI, Sallow Trench Isolation) (not shown), arranged between the first P-doped region P1 and the first N-doped region N1, the second N-doped region N2 and the second P-doped region Between the impurity regions P2, between the second P-doped region P2 and the third N-doped region N3.
  • STI Shallow trench isolation structure
  • the depths of the shallow trench isolation structures are all smaller than the depths of the doped regions.
  • FIG. 6 is a schematic diagram of an equivalent circuit of the electrostatic protection structure shown in FIG. 4 or FIG. 5 .
  • the first N-doped region N1, the second N-doped region N2 and the gate structure G form a GGNMOS (Gate-Grounded NMOS, gate-grounded N-type transistor) , that is, the transistor M in FIG. 1 or FIG. 2 .
  • GGNMOS Gate-Grounded NMOS, gate-grounded N-type transistor
  • the second P-doped region P2, the N-well region 43 and the P-well region 42 jointly form a PNP-type transistor J1, the first N-doped region N1, the P-well region 42 and the N-well region 43 jointly form an NPN-type transistor J2, and the second The P doped region P2 and the N well region 43 form a first diode D1, and the P well region 42 and the first N doped region N1 form a second diode D2.
  • first P-doped region P1 and the P-well region 42 constitute the second resistor R2
  • third N-doped region N3 and the N-well region 43 constitute the first resistor R1 .
  • the second N-doped region N2 serves as the drain of the N-type transistor M and the cathode of the third diode D3, and the length of the second N-doped region N2 may be Twice the region length of the other doped regions.
  • the electrostatic current After the electrostatic current enters the second P-doped region P2 from the anode, it is diverted to the cathode through three paths.
  • the first path is the first diode D1 formed from the second P-doped region P2 and the third N-doped region N3, and the second two-phase diode formed from the first P-doped region P1 and the first N-doped region N1.
  • the pole tube D2 leads to the cathode.
  • the second path is that the electrostatic current conducts from the third diode D3 composed of the second P-doped region P2 and the second N-doped region N2 to the drain of the transistor M. Since the electrostatic current is an instantaneous large current, it passes through The strong coupling between the gate and the drain turns on the transistor, and the current flows to the source of the transistor, that is, the first N-doped region N1, and flows into the cathode.
  • the electrostatic current is injected into the N well region 43 from the anode, that is, the emitter of the PNP transistor J1 composed of the second P-doped region P2, the N well region 43, and the P well region 42 injects current into the base electrode, and the collector of the PNP transistor J1 (i.e. the P well region 42) generates a current, the collector of the NPN transistor J2 receives the current of the PNP base, and generates a current to the base of the NPN (i.e.
  • the PNP transistor J1 and the NPN transistor J2 form a conduction In the SCR structure, the electrostatic charge flows from the emitter of the PNP transistor J1 to the emitter of the NPN transistor J2, and then into the cathode, so that the third path is realized to discharge the electrostatic charge.
  • the first sub-circuit shown in Figure 1 or Figure 2 can be realized through two well regions and five doped regions, and when electrostatic charges flow in through the anode, the original ESD design window.
  • FIGS. 7A and 7B are schematic diagrams of an electrostatic protection structure in another embodiment of the present disclosure.
  • 7A is a cross-sectional view of the electrostatic protection structure
  • FIG. 7B is a top view of the structure shown in FIG. 7A.
  • a second substructure 72 of an electrostatic protection structure is further included, and the second substructure 72 and the first substructure 71 are aligned with respect to the third N-doped region N3. Symmetrically distributed, the second substructure 72 and the first substructure 71 share the third N-doped region N3.
  • the electrostatic protection circuit and the electrostatic protection structure of the embodiments of the present disclosure can be applied to the ESD protection of the input and output circuits of semiconductor integrated circuits, especially to the electrostatic protection of low working voltage in advanced manufacturing processes, and can also be applied to various types of semiconductor integrated circuits Such as ESD protection for logic, analog and various memory chips.
  • the electrostatic protection circuit provided by the embodiment of the present disclosure forms two charge discharge paths by using a first trigger circuit composed of a diode and a second trigger circuit composed of a GGNMOS, and uses a thyristor composed of a PNP transistor and an NPN transistor.
  • the circuit forms the third charge discharge path, which has the advantages of low trigger voltage, low leakage, high electrostatic protection ability and small manufacturing area.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种静电保护电路和静电保护结构。静电保护电路包括第一子电路，第一子电路包括：第一触发电路，包括第一二极管和第二二极管；第二触发电路，包括第三二极管和晶体管；可控硅电路，包括PNP型三极管和NPN型三极管；其中，第一二极管的正极连接静电保护电路的阳极，第一二极管的负极连接第二二极管的正极，第二二极管的负极连接静电保护电路的阴极；第三二极管的正极连接阳极，第三二极管的负极电连接晶体管的漏极，晶体管的源极和栅极连接阴极；PNP型三极管的发射极连接阳极，NPN型三极管的发射极连接阴极。本公开实施例的静电保护电路和静电保护结构具有更高的静电保护能力和更小的制造尺寸。 (图1)

Description

静电保护电路和静电保护结构
交叉引用
本公开要求于2021年08月19日提交的申请号为202110955199.3、名称为“静电保护电路和静电保护结构”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种静电保护电路和静电保护结构。
背景技术
为了保护集成电路免于受到静电的危害，通常要对集成电路进行静电保护。现代半导体的制程越来越先进，沟道长度越来越短，结深越来越浅，氧化层越来越薄，ESD(Electro-Static discharge，静电电荷泄放)设计的窗口越来越小，ESD保护设计面临的挑战越来越大。
相关技术中，ESD电路的触发电压高、维持电压低、易发生闩锁，不适于应用于存储器产品的静电保护。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种静电保护电路、静电保护结构，可以一定程度上克服由于相关技术的限制和缺陷而导致的静电保护电路触发电压高、维持电压低、易发生闩锁等问题。
根据本公开的第一方面，提供一种静电保护电路，包括第一子电路，所述第一子电路包括：第一触发电路，包括第一二极管和第二二极管；第二触发电路，包括第三二极管和晶体管；可控硅电路，包括PNP型三极管和NPN型三极管；其中，所述第一二极管的正极连接所述静电保护电路的阳极，所述第一二极管的负极连接所述第二二极管的正极，所述第二二极管的负极连接所述静电保护电路的阴极；所述第三二极管的正极连接所述阳极，所述第三二极管的负极电连接晶体管的漏极，所述晶体管的源极和栅极连接所述阴极；所述PNP型三极管的发射极连接所述阳极，所述NPN型三极管的发射极连接所述阴极。
在本公开的一个示例性实施例中，所述PNP型三极管的基极连接所述NPN型三极管的集电极，所述NPN型三极管的基极连接所述PNP型三极管的集电极。
在本公开的一个示例性实施例中，所述晶体管的栅极连接可调电阻。
在本公开的一个示例性实施例中，所述第一二极管的正极是所述PNP型三极管的发 射极，所述第一二极管的负极是所述PNP型三极管的基极；所述第二二极管的正极是所述NPN型三极管的基极，所述第二二极管的负极是所述NPN型三极管的发射极；所述第三二极管的正极是所述PNP型三极管的发射极，所述第三二级管的负极是所述PNP型三极管的基极，所述晶体管的源极是所述第二二极管的负极。
在本公开的一个示例性实施例中，还包括第二子电路，所述第二子电路和所述第一子电路基于所述第一二极管的负极对称分布，所述第二子电路和第一子电路共用所述第一二极管的负极。
在本公开的一个示例性实施例中，所述静电保护电路包括第一电阻和第二电阻，第一电阻是所述PNP型三极管的基极等效电阻，第二电阻是所述NPN型三极管的基极等效电阻。
根据本公开的第二方面，提供一种静电保护结构，包括第一子结构，所述第一子结构包括：P型衬底；设置在所述P型衬底中的N阱区和P阱区；设置在所述P阱区的第一P掺杂区和第一N掺杂区，同时设置在所述P阱区和所述N阱区的第二N掺杂区，设置在所述N阱区的第二P掺杂区和第三N掺杂区；其中，所述第二P掺杂区连接阳极，所述第一N掺杂区连接阴极，所述第一P掺杂区与所述第三N掺杂区相连，所述第一N掺杂区和所述第二N掺杂区之间的P阱区表面设置有栅极结构。
在本公开的一个示例性实施例中，所述栅极结构通过可调电阻连接所述阴极。
在本公开的一个示例性实施例中，还包括：深N阱区，位于所述P型衬底中、所述P阱区和所述N阱区之下；隔离N阱区，位于所述P阱区远离所述N阱区的一端，用于作为隔离结构；浅沟槽隔离结构，设置在所述第一P掺杂区和所述第一N掺杂区之间所述第二N掺杂区和所述第二P掺杂区之间，所述第二P掺杂区和所述第三N掺杂区之间。
在本公开的一个示例性实施例中，所述第一N掺杂区、所述第二N掺杂区和所述栅极结构组成栅极接地N型晶体管。
在本公开的一个示例性实施例中，所述第一P掺杂区、所述第二P掺杂区、所述第一N掺杂区、所述第二N掺杂区、所述第三N掺杂区的掺杂浓度均大于所述N阱区和所述P阱区的掺杂浓度。
在本公开的一个示例性实施例中，所述第二N掺杂区的区域长度是其他掺杂区的区域长度的两倍。
在本公开的一个示例性实施例中，还包括第二子结构，所述第二子结构和所述第一子结构关于所述第三N掺杂区呈轴对称分布，所述第二子结构和所述第一子结构共用所述第三N掺杂区。
在本公开的一个示例性实施例中，所述第二P掺杂区与所述N阱区和所述P阱区共同构成PNP型三极管，所述第一N掺杂区与所述P阱区和所述N阱区共同构成NPN型三极管，所述第二P掺杂区与所述N阱区构成第一二极管，所述P阱区与所述第一N掺杂区构成第二二极管。
在本公开的一个示例性实施例中，所述浅沟槽隔离结构的深度均小于所述掺杂区的深度。
本公开实施例提供的静电保护电路通过使用由二极管构成的第一触发电路和由GGNMOS构成的第二触发电路形成两条电荷泄放通路，使用由PNP型三极管和NPN型三极管构成的可控硅电路形成第三条电荷泄放通路，具有触发电压低，漏电低，静电保护能力高，制造面积小的优点。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中静电保护电路的结构示意图。
图2是本公开另一个实施例中第一子电路的示意图。
图3是本公开一个实施例中静电保护电路的示意图。
图4是本公开一个实施例中静电保护结构的示意图。
图5是本公开另一个实施例中静电保护结构的示意图。
图6是图4或图5所示静电保护结构的等效电路示意图。
图7A和图7B是本公开另一个实施例中静电保护结构的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装 置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1是本公开示例性实施例中静电保护电路的结构示意图。
参考图1，静电保护电路可以包括第一子电路100，第一子电路100包括：
第一触发电路1，包括第一二极管D1和第二二极管D2；
第二触发电路2，包括第三二极管D3和晶体管M；
可控硅电路3，包括PNP型三极管J1和NPN型三极管J2；
其中，第一二极管D1的正极连接静电保护电路的阳极，第一二极管D1的负极连接第二二极管D2的正极，第二二极管D2的负极连接静电保护电路的阴极；
第三二极管D3的正极连接阳极，第三二极管D3的负极电连接晶体管M的漏极，晶体管M的源极和栅极连接阴极；
PNP型三极管J1的发射极连接阳极，NPN型三极管J2的发射极连接阴极。
在本公开的一个示例性实施例中，PNP型三极管J1的基极连接NPN型三极管J2的集电极，NPN型三极管J2的基极连接PNP型三极管J1的集电极。
图1所示电路通过在静电保护电路的阳极和阴极之间设置三条静电释放通路，由于晶体管M的栅极接地，可以在不影响输入电路的正常功能的情况下，通过第一触发电路1和第二触发电路2设置双触发的可控硅(Silicon Controlled Rectifier，SCR)结构，且由二极管构成的第一触发电路1和由二极管和晶体管构成的第二触发电路2的触发电压低，可以应用在低电压电路中，有效提高电路的静电泄放速度；通过设置三条静电释放通路，可以有效提高静电保护电路的静电保护能力，能够保护电路正常工作。
图2是本公开另一个实施例中第一子电路的示意图。
参考图2，在本公开的一个示例性实施例中，第一子电路200的晶体管M的栅极连接可调电阻Rr。
结合图2和图1，第一二极管D1的正极是PNP型三极管J1的发射极，第一二极管D1的负极是PNP型三极管J1的基极(PNP型三极管J1的基极具有等效电阻Rnw，在图中显示为第一电阻R1)；第二二极管D1的正极是NPN型三极管J2的基极(NPN型三极管J2的基极具有等效电阻Rpw，在图中显示为第二电阻R2)，第二二极管D2的负极是NPN型三极管J2的发射极；第三二极管D3的正极是PNP型三极管J1的发射极，第三二级管D3的负极是PNP型三极管J1的基极。
即，由于二极管和三极管均涉及到N型掺杂和P型掺杂，通过图2所示电路200的连接设计，可以在制造过程中实现几个元件共用一个掺杂区，从而极大减小静电保护电路的制造(layout)面积。
图3是本公开一个实施例中静电保护电路的示意图。
在本公开的一个示例性实施例中，静电保护电路还包括第二子电路300，第二子电路300与第一子电路200完全相同，第二子电路300和第一子电路200基于第一二极管D1 的负极(即PNP型三极管J1的基极)对称分布，第二子电路300和第一子电路200共用第一二极管D1的负极(即PNP型三极管J1的基极)。
图3所示实施例中基于第一二极管D1的负极设置两个对称相同的子电路，可以在尽量减小制造面积的情况下，设置更强的静电保护功能。
下面，通过静电保护结构介绍图1～图3所示静电保护电路的制造形态。
图4是本公开一个实施例中静电保护结构的示意图。图4所示静电保护结构可以用于实现如图1～图2所示的静电保护电路的第一子电路或图3所示的第二子电路。
参考图4，静电保护结构400包括：
P型衬底41；
设置在P型衬底41中的N阱区42和P阱区43；
设置在P阱区43的第一P掺杂区P1和第一N掺杂区N1，同时设置在P阱区43和N阱区42的第二N掺杂区N2，设置在N阱区42的第二P掺杂区P2和第三N掺杂区N3；其中，第二P掺杂区P2连接阳极，第一N掺杂区N1连接阴极，第一P掺杂区P1与第三N掺杂区N3相连，第一N掺杂区N1和第二N掺杂区N2之间的P阱区43表面设置有栅极结构G。
在本公开的一个示例性实施例中，第一P掺杂区P1、第二P掺杂区P2、第一N掺杂区N1、第二N掺杂区N2、第三N掺杂区N3的掺杂浓度均大于N阱区和P阱区的掺杂浓度。
图4所示静电保护结构中，通过两个阱区和五个掺杂区即可以实现图1所示的第一子电路，实现双触发、触发电压低、具有三个通路的静电保护能力较强的景点保护电路，制造面积小且功能强大。图4所示静电保护结构的具体原理详见下文。
图5是本公开另一个实施例中静电保护结构的示意图。
参考图5，在本公开的一个示例性实施例中，图4所示电路的栅极结构G通过可调电阻Rr连接阴极。
第一子电路还包括：
深N阱区44，位于P型衬底41中P阱区42和N阱区43之下；
隔离N阱区45，位于P阱区42远离N阱区43的一端，用于作为隔离结构；
浅沟槽隔离结构(STI，Sallow Trench Isolation)(未示出)，设置在第一P掺杂区P1和第一N掺杂区N1之间、第二N掺杂区N2和第二P掺杂区P2之间、第二P掺杂区P2和第三N掺杂区N3之间。
在本公开的一个示例性实施例中，所述浅沟槽隔离结构的深度均小于所述掺杂区的深度。
图6是图4或图5所示静电保护结构的等效电路示意图。
参考图6，在本公开的一个示例性实施例中，第一N掺杂区N1、第二N掺杂区N2和栅极结构G组成GGNMOS(Gate-Grounded NMOS，栅极接地N型晶体管)，即图1 或图2中的晶体管M。第二P掺杂区P2与N阱区43和P阱区42共同构成PNP型三极管J1，第一N掺杂区N1与P阱区42和N阱区43共同构成NPN型三极管J2，第二P掺杂区P2与N阱区43构成第一二极管D1，P阱区42与第一N掺杂区N1构成第二二极管D2。
另外，第一P掺杂区P1与P阱区42构成第二电阻R2，第三N掺杂区N3与N阱区43构成第一电阻R1。
在本公开的一个示例性实施例中，有第二N掺杂区N2同时作为N型晶体管M的漏极和第三二极管D3的负极，第二N掺杂区N2的区域长度可以是其他掺杂区的区域长度的两倍。
静电电流从阳极进入第二P掺杂区P2后，分三条路径导流到阴极。第一条路径是从第二P掺杂区P2与第三N掺杂区N3构成的第一二极管D1、第一P掺杂区P1与第一N掺杂区N1构成的第二二极管D2导流到阴极。
第二条路径是静电电流从由第二P掺杂区P2和第二N掺杂区N2构成的第三二极管D3导流到晶体管M的漏极，由于静电电流为瞬间大电流，通过栅极和漏极的强耦合使晶体管导通，电流流至晶体管的源极即第一N掺杂区N1，流入阴极。
当静电电流从阳极注入N阱区43，即由第二P掺杂区P2、N阱区43、P阱区42构成的PNP三极管J1的发射极向基极注入电流，PNP三极管J1的集电极(即P阱区42)产生电流，NPN三极管J2的集电极接收到PNP基极的电流，向NPN的基极(即P阱区42)产生电流，PNP三极管J1和NPN三极管J2构成导通的SCR结构，静电电荷从PNP三极管J1的发射极流入NPN三极管J2的发射极，导入阴极，从而实现第三条路径泄放静电电荷。
如此，通过图4或图5所示结构，即可通过两个阱区和五个掺杂区实现图1或图2所示的第一子电路，在静电电荷通过阳极流入时，恢复原来的ESD设计窗口。结构简单，制造面积小，具有较低的触发电压和强大的静电保护功能。
图7A和图7B是本公开另一个实施例中静电保护结构的示意图。其中图7A是静电保护结构的剖视图，图7B是图7A所示结构的俯视图。
参考图7A和图7B，在本公开的一个示例性实施例中，还包括静电保护结构第二子结构72，第二子结构72和第一子结构71关于第三N掺杂区N3呈轴对称分布，第二子结构72和第一子结构71共用第三N掺杂区N3。
通过共用第三N掺杂区N3，共用N阱区，可以在较小制造面积内设置两个完整的静电保护子结构，从而可以进一步提高固定制造面积内的静电保护能力。
综上所述，本公开实施例通过将一个由PNP三极管和NPN三极管构成的SCR结构，以及一个GGNMOS结构连接在阳极和阴极之间，可以实现触发电压较低的三条电荷泄放通路，具有强大的静电保护能力；同时，通过在制造时共用N阱区、P阱区、N掺杂区、P掺杂区构建上述结构，可以极大缩小静电保护电路的制造面积，继而提高单位制造面积 内的静电电荷泄放能力。本公开实施例的静电保护电路和静电保护结构可以应用于半导体集成电路的输入和输出电路的ESD保护，尤其可应用于先进制程的低工作电压的静电保护，也可应用于各类半导体集成电路如逻辑、模拟以及各类存储器芯片的的ESD保护。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例提供的静电保护电路通过使用由二极管构成的第一触发电路和由GGNMOS构成的第二触发电路形成两条电荷泄放通路，使用由PNP型三极管和NPN型三极管构成的可控硅电路形成第三条电荷泄放通路，具有触发电压低，漏电低，静电保护能力高，制造面积小的优点。

Claims (15)

  1. 一种静电保护电路，包括第一子电路，所述第一子电路包括：
    第一触发电路，包括第一二极管和第二二极管；
    第二触发电路，包括第三二极管和晶体管；
    可控硅电路，包括PNP型三极管和NPN型三极管；
    其中，所述第一二极管的正极连接所述静电保护电路的阳极，所述第一二极管的负极连接所述第二二极管的正极，所述第二二极管的负极连接所述静电保护电路的阴极；
    所述第三二极管的正极连接所述阳极，所述第三二极管的负极电连接晶体管的漏极，所述晶体管的源极和栅极连接所述阴极；
    所述PNP型三极管的发射极连接所述阳极，所述NPN型三极管的发射极连接所述阴极。
  2. 如权利要求1所述的静电保护电路，其中，所述PNP型三极管的基极连接所述NPN型三极管的集电极，所述NPN型三极管的基极连接所述PNP型三极管的集电极。
  3. 如权利要求1所述的静电保护电路，其中，所述晶体管的栅极连接可调电阻。
  4. 如权利要求1所述的静电保护电路，其中，所述第一二极管的正极是所述PNP型三极管的发射极，所述第一二极管的负极是所述PNP型三极管的基极；所述第二二极管的正极是所述NPN型三极管的基极，所述第二二极管的负极是所述NPN型三极管的发射极；所述第三二极管的正极是所述PNP型三极管的发射极，所述第三二级管的负极是所述PNP型三极管的基极，所述晶体管的源极是所述第二二极管的负极。
  5. 如权利要求1所述的静电保护电路，其中，还包括第二子电路，所述第二子电路和所述第一子电路基于所述第一二极管的负极对称分布，所述第二子电路和第一子电路共用所述第一二极管的负极。
  6. 如权利要求1所述的静电保护电路，其中，所述静电保护电路包括第一电阻和第二电阻，第一电阻是所述PNP型三极管的基极等效电阻，第二电阻是所述NPN型三极管的基极等效电阻。
  7. 一种静电保护结构，包括第一子结构，所述第一子结构包括：
    P型衬底；
    设置在所述P型衬底中的N阱区和P阱区；
    设置在所述P阱区的第一P掺杂区和第一N掺杂区，同时设置在所述P阱区和所述N阱区的第二N掺杂区，设置在所述N阱区的第二P掺杂区和第三N掺杂区；
    其中，所述第二P掺杂区连接阳极，所述第一N掺杂区连接阴极，所述第一P掺杂区与所述第三N掺杂区相连，所述第一N掺杂区和所述第二N掺杂区之间的P阱区表面设置有栅极结构。
  8. 如权利要求7所述的静电保护结构，其中，所述栅极结构通过可调电阻连接所述阴 极。
  9. 如权利要求7所述的静电保护结构，其中，还包括：
    深N阱区，位于所述P型衬底中、所述P阱区和所述N阱区之下；
    隔离N阱区，位于所述P阱区远离所述N阱区的一端，用于作为隔离结构；
    浅沟槽隔离结构，设置在所述第一P掺杂区和所述第一N掺杂区之间，所述第二N掺杂区和所述第二P掺杂区之间，所述第二P掺杂区和所述第三N掺杂区之间。
  10. 如权利要求7所述的静电保护结构，其中，所述第一N掺杂区、所述第二N掺杂区和所述栅极结构组成栅极接地N型晶体管。
  11. 如权利要求7所述的静电保护结构，其中，所述第一P掺杂区、所述第二P掺杂区、所述第一N掺杂区、所述第二N掺杂区、所述第三N掺杂区的掺杂浓度均大于所述N阱区和所述P阱区的掺杂浓度。
  12. 如权利要求7所述的静电保护结构，其中，所述第二N掺杂区的区域长度是其他掺杂区的区域长度的两倍。
  13. 如权利要求7所述的静电保护结构，其中，还包括第二子结构，所述第二子结构和所述第一子结构关于所述第三N掺杂区呈轴对称分布，所述第二子结构和所述第一子结构共用所述第三N掺杂区。
  14. 如权利要求7所述的静电保护结构，其中，所述第二P掺杂区与所述N阱区和所述P阱区共同构成PNP型三极管，所述第一N掺杂区与所述P阱区和所述N阱区共同构成NPN型三极管，所述第二P掺杂区与所述N阱区构成第一二极管，所述P阱区与所述第一N掺杂区构成第二二极管。
  15. 如权利要求9所述的静电保护结构，其中，所述浅沟槽隔离结构的深度均小于所述掺杂区的深度。
PCT/CN2022/090055 2021-08-19 2022-04-28 静电保护电路和静电保护结构 Ceased WO2023020009A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110955199.3 2021-08-19
CN202110955199.3A CN115708208B (zh) 2021-08-19 2021-08-19 静电保护电路和静电保护结构

Publications (1)

Publication Number Publication Date
WO2023020009A1 true WO2023020009A1 (zh) 2023-02-23

Family

ID=85212652

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/090055 Ceased WO2023020009A1 (zh) 2021-08-19 2022-04-28 静电保护电路和静电保护结构

Country Status (2)

Country Link
CN (1) CN115708208B (zh)
WO (1) WO2023020009A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002033454A (ja) * 2000-07-17 2002-01-31 Nec Miyagi Ltd 半導体集積回路
CN101640200A (zh) * 2009-08-25 2010-02-03 上海宏力半导体制造有限公司 Scr静电保护器件
CN102456747A (zh) * 2010-10-19 2012-05-16 上海华虹Nec电子有限公司 静电保护二极管
CN110323207A (zh) * 2019-06-26 2019-10-11 电子科技大学 一种用于低压防护的新型scr器件
CN111403380A (zh) * 2019-08-21 2020-07-10 中国科学院上海微系统与信息技术研究所 一种静电保护结构及静电保护电路
CN111933639A (zh) * 2020-07-03 2020-11-13 中国科学院上海微系统与信息技术研究所 一种用于高压容限电路的静电保护结构
CN112466947A (zh) * 2020-11-26 2021-03-09 中国科学院微电子研究所 一种基于静电放电保护结构的场效应管

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208408B (zh) * 2010-03-31 2014-12-17 上海华虹宏力半导体制造有限公司 栅驱动晶闸管以及静电保护电路
US9472511B2 (en) * 2014-01-16 2016-10-18 Cypress Semiconductor Corporation ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage
CN110491875B (zh) * 2019-08-23 2020-05-01 湘潭大学 一种双向可控硅静电保护器件
CN111900159A (zh) * 2020-08-26 2020-11-06 璨隆科技发展有限公司 功率器件静电放电保护电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002033454A (ja) * 2000-07-17 2002-01-31 Nec Miyagi Ltd 半導体集積回路
CN101640200A (zh) * 2009-08-25 2010-02-03 上海宏力半导体制造有限公司 Scr静电保护器件
CN102456747A (zh) * 2010-10-19 2012-05-16 上海华虹Nec电子有限公司 静电保护二极管
CN110323207A (zh) * 2019-06-26 2019-10-11 电子科技大学 一种用于低压防护的新型scr器件
CN111403380A (zh) * 2019-08-21 2020-07-10 中国科学院上海微系统与信息技术研究所 一种静电保护结构及静电保护电路
CN111933639A (zh) * 2020-07-03 2020-11-13 中国科学院上海微系统与信息技术研究所 一种用于高压容限电路的静电保护结构
CN112466947A (zh) * 2020-11-26 2021-03-09 中国科学院微电子研究所 一种基于静电放电保护结构的场效应管

Also Published As

Publication number Publication date
CN115708208A (zh) 2023-02-21
CN115708208B (zh) 2024-07-26

Similar Documents

Publication Publication Date Title
US20220165725A1 (en) High Voltage ESD Protection Apparatus
US9105477B2 (en) ESD protection structure and ESD protection circuit
US7372109B2 (en) Diode and applications thereof
CN100342535C (zh) 用于芯片上静电放电保护的具有深n型阱的有效开启双极结构
US6759691B2 (en) ESD protection circuit having a high triggering threshold
CN108520875B (zh) 一种高维持电压npnpn型双向可控硅静电防护器件
CN111668209B (zh) 一种低漏电的用于低压esd防护的可控硅整流器
CN110491875B (zh) 一种双向可控硅静电保护器件
US10192863B2 (en) Series connected ESD protection circuit
CN110828453B (zh) 一种内嵌p+注入区分段型非对称可控硅静电释放器件
WO2009092188A1 (zh) 用于静电放电的器件及其制造方法
CN111739887B (zh) 基于晶闸管的静电保护单元及其并联结构
CN107680965A (zh) 一种基于scr结构的双mos辅助触发的esd保护器件
CN115050734A (zh) 可控硅整流器
TWI594393B (zh) 靜電放電保護元件
CN115528019B (zh) Esd保护器件、保护电路及制备方法
US11222886B2 (en) ESD protection device with low trigger voltage
CN108766964B (zh) Ldmos静电保护器件
JP2009038130A (ja) 横型ｍｏｓトランジスタ及びこれを用いた半導体装置
CN110120391A (zh) 一种用于esd防护的高鲁棒性esd器件
KR20040090480A (ko) 내부 회로를 보호하는 보호 회로를 구비한 반도체 장치
WO2023020009A1 (zh) 静电保护电路和静电保护结构
US6084272A (en) Electrostatic discharge protective circuit for semiconductor device
CN115312512B (zh) 二极管触发的可控硅器件和集成电路
CN115621277A (zh) 用于esd防护的pwell隔离的栅控二极管触发scr器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22857327

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22857327

Country of ref document: EP

Kind code of ref document: A1