WO2023019902A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2023019902A1
WO2023019902A1 PCT/CN2022/077727 CN2022077727W WO2023019902A1 WO 2023019902 A1 WO2023019902 A1 WO 2023019902A1 CN 2022077727 W CN2022077727 W CN 2022077727W WO 2023019902 A1 WO2023019902 A1 WO 2023019902A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
trench
initial
layer
word line
Prior art date
Application number
PCT/CN2022/077727
Other languages
English (en)
French (fr)
Inventor
邵光速
肖德元
邱云松
吴敏敏
Original Assignee
长鑫存储技术有限公司
北京超弦存储器研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司, 北京超弦存储器研究院 filed Critical 长鑫存储技术有限公司
Priority to US17/810,634 priority Critical patent/US20230057480A1/en
Publication of WO2023019902A1 publication Critical patent/WO2023019902A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Definitions

  • the present disclosure relates to the technical field of semiconductors, and relates to but not limited to a semiconductor structure and a method for forming the same.
  • Semiconductor devices typically include multiple transistors, for example, in memory devices such as Dynamic Random Access Memory (DRAM), memory cells include Metal-Oxide-Semiconductor Field-Effect Transistors (Metal-Oxide-Semiconductor Field-Effect Transistor , MOSFET).
  • DRAM Dynamic Random Access Memory
  • memory cells include Metal-Oxide-Semiconductor Field-Effect Transistors (Metal-Oxide-Semiconductor Field-Effect Transistor , MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • VCT Vertical Channel Transistor
  • bit lines are all buried at the bottom of the channel.
  • bit line resistance, the bit line voltage and the bit line current are relatively large; on the other hand, since the bit lines are in contact with the semiconductor pillars, A large parasitic capacitance is generated between the bit lines.
  • embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including:
  • a semiconductor substrate includes a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction; the bit line isolation trenches extend along a second direction, and the first direction perpendicular to the second direction;
  • a bit line isolation layer is formed in the bit line isolation trench; wherein, there is a gap between the bit line isolation layer and the bit line isolation trench, and the gap is located at the bottom of the bit line isolation trench at a corner and extending along the second direction, and the gap exposes part of the bottom of the bit line isolation trench;
  • Bit lines are formed in the bit line trenches.
  • bit line isolation layer in the bit line isolation trench includes:
  • bit line isolation layer removing part of the initial bit line isolation layer to form the bit line isolation layer and the gap.
  • forming an initial bit line isolation layer in the bit line isolation trench includes:
  • the third direction sequentially etching and removing part of the second initial isolation layer and part of the first initial isolation layer to form a first etching groove; wherein, the first etching groove exposes the position the first sidewall of the line isolation trench and part of the bottom of the bit line isolation trench; the third direction is the depth direction of the bit line isolation trench;
  • the remaining first initial isolation layer, the remaining second initial isolation layer and the third initial isolation layer constitute the initial bit line isolation layer.
  • the removing part of the initial bit line isolation layer to form the bit line isolation layer and the gap includes:
  • bit line isolation trench sequentially etching the remaining second initial isolation layer and the remaining first initial isolation layer along the third direction to form at least one opening
  • the remaining first initial isolation layer in the initial bit line isolation layer is removed to form the bit line isolation layer and the void.
  • etching the first semiconductor pillar along the first direction through the gap to form a bit line trench includes:
  • the first semiconductor column is partially etched along the first direction to form a second etching groove; wherein, the size of the second etching groove in the third direction is equal to the The dimension of the void in the third direction, and the dimension of the second etched groove in the first direction is smaller than the dimension of the first semiconductor pillar in the first direction;
  • the second etching groove and the gap together form the bit line trench.
  • etching the first semiconductor pillar along the first direction through the gap to form a bit line trench includes:
  • the first semiconductor column is completely etched along the first direction to form a third etching groove; wherein, the size of the third etching groove in the third direction is equal to the The size of the void in the third direction, and the size of the third etched groove in the first direction is equal to the size of the first semiconductor pillar in the first direction;
  • the third etch groove and the gap together form the bit line trench.
  • the method before forming the bit line, the method further includes:
  • etching removes the remaining second initial isolation layer to form a fourth etching groove; wherein, the fourth etching groove exposes the gap and the bit line isolation trench the second side wall of the slot;
  • the bit line is formed in the bit line trench through the fourth etching groove.
  • forming the bit line in the bit line trench through the fourth etching groove includes:
  • the initial bit line layer is etched back to remove the initial bit line layer located in the fourth etching groove to form the bit line.
  • the method further includes:
  • the top surface of the insulating layer is flush with the top surface of the third initial isolation layer.
  • the method further includes:
  • Word lines are formed in the word line trenches.
  • a plurality of word line trenches are formed in the first semiconductor pillar, including:
  • the bottom of the word line trench exceeds the top of the bit line.
  • forming a word line in the word line trench includes:
  • a bottom initial barrier layer, an initial word line layer and a top initial barrier layer are sequentially formed;
  • the method further includes:
  • An insulating material is filled in the word line isolation trench to form a word line isolation layer.
  • an embodiment of the present disclosure provides a semiconductor structure, at least including:
  • a semiconductor substrate includes a plurality of semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction; the bit line isolation trenches extend along a second direction, and the first direction is perpendicular to the the second direction;
  • bit line isolation layer located in the bit line isolation trench
  • a bit line is partially buried at the bottom of the semiconductor pillar, and another part of the bit line is buried at a bottom corner between the bit line isolation layer and the bit line isolation trench.
  • the semiconductor substrate further includes a plurality of word line trenches and second semiconductor pillars arranged at intervals along the second direction; the semiconductor structure further includes:
  • a gate insulating layer located on the sidewall of the word line trench
  • a word line isolation layer located at the center of the word line trench, and the top surface of the word line isolation layer is flush with the top surface of the second semiconductor pillar; the size of the word line isolation layer in the third direction smaller than the size of the word line trench in the third direction; the third direction is the depth direction of the word line trench;
  • a top barrier layer located between the gate insulating layer on the top of the word line trench and the corresponding word line isolation layer;
  • the word line is located between the gate insulating layer in the middle of the word line trench and the corresponding word line isolation layer;
  • the bottom barrier layer is located at the bottom of the word line groove formed with the gate insulating layer, and the bottom barrier layer is in contact with the word line and part of the word line isolation layer.
  • the semiconductor structure further includes: a channel
  • the channel is located between two adjacent gate insulating layers, and the channel is a second semiconductor column region corresponding to the word line and between two adjacent gate insulating layers.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure includes: providing a semiconductor substrate, the semiconductor substrate including a plurality of first semiconductor columns and bit line isolation trenches arranged at intervals along a first direction Groove; the bit line isolation trench extends along the second direction; a bit line isolation layer is formed in the bit line isolation trench, and there is a gap between the bit line isolation layer and the bit line isolation trench, and the gap is located in the bit line isolation trench and extending along the second direction at the corner of the bottom; etching the first semiconductor column along the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.
  • the bit line is partially buried in the bit line isolation trench, and the other part of the bit line is buried in the bottom of the first semiconductor pillar. In this way, the formation cost can be reduced.
  • the bit line resistance, voltage and current of the semiconductor structure are improved, and the parasitic capacitance between adjacent bit lines is reduced to improve the performance of the semiconductor structure.
  • FIG. 1 is an optional schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 4a is an optional top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • 4b-4d are cross-sectional views along different directions of the semiconductor structure provided by the embodiments of the present disclosure.
  • 20-semiconductor substrate 201-bit line isolation trench; 201-1-first side wall of bit line isolation trench; 201-2-second side wall of bit line isolation trench; 202-first semiconductor column ; 203a-first initial isolation layer; 203-remaining first initial isolation layer; 204a-second initial isolation layer; 204-remaining second initial isolation layer; 205-third initial isolation layer; 206a-initial bit line Isolation layer; 206/404-bit line isolation layer; 207a-initial bit line layer; 207/402-bit line; 208-insulation layer; 301/405-second semiconductor pillar; 302-word line trench; 303/406 - gate insulating layer; 304a - bottom initial barrier layer; 304/409 - bottom barrier layer; 305a - initial word line layer; 305/403 - word line; 306a - top initial barrier layer; 306/408 - top barrier layer; 307a-word line isolation trench; 307/407-word line isolation layer;
  • an embodiment of the present disclosure provides a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure includes providing a semiconductor substrate, and the semiconductor substrate includes a plurality of first A semiconductor pillar and a bit line isolation trench; the bit line isolation trench extends along the second direction; a bit line isolation layer is formed in the bit line isolation trench, and there is a gap between the bit line isolation layer and the bit line isolation trench, The void is located at the bottom corner of the bit line isolation trench and extends along the second direction; through the void, the first semiconductor column is etched along the first direction to form a bit line trench; and a bit line is formed in the bit line trench.
  • the bit line is partially buried in the bit line isolation trench, and the other part of the bit line is buried in the bottom of the first semiconductor pillar. In this way, the formation cost can be reduced.
  • the bit line resistance, voltage and current of the semiconductor structure are improved, and the parasitic capacitance between adjacent bit lines is reduced to improve the performance of the semiconductor structure.
  • An embodiment of the present disclosure provides a method for forming a semiconductor structure. As shown in FIG. 1 , the method for forming a semiconductor structure includes the following steps:
  • Step S101 providing a semiconductor substrate, the semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction.
  • bit line isolation trench extends along a second direction, and the first direction is perpendicular to the second direction.
  • the semiconductor substrate may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), Gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or including other semiconductor alloys such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), Aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.
  • germanium germanium
  • SiC silicon carbide
  • GaAs gallium arsenide
  • GaP Gallium
  • the semiconductor substrate may include a top surface at the front side and a bottom surface at the back side opposite to the front side; under the condition of ignoring the flatness of the top surface and the bottom surface, the direction vertical to the top surface and the bottom surface of the semiconductor substrate is defined as third direction.
  • the direction of the top surface and the bottom surface of the semiconductor substrate that is, the plane where the semiconductor substrate is located
  • two first and second directions that intersect each other for example, are perpendicular to each other
  • a plurality of bit line isolation trenches can be defined
  • the arrangement direction of the bit line isolation trench is defined as the first direction
  • the extension direction of the bit line isolation trench is defined as the second direction
  • the plane direction of the semiconductor substrate can be determined based on the first direction and the second direction.
  • first direction is defined as the X-axis direction
  • second direction is defined as the Y-axis direction
  • third direction is defined as the Z-axis direction
  • the bit line isolation trench is used to fill the isolation material to isolate the finally formed bit line.
  • the first semiconductor column is a semiconductor substrate located between two adjacent bit line isolation trenches after etching the semiconductor substrate to form a plurality of bit line isolation trenches.
  • the bit line isolation trench and the first semiconductor column are arranged at intervals along the first direction.
  • Step S102 forming a bit line isolation layer in the bit line isolation trench; wherein, there is a gap between the bit line isolation layer and the bit line isolation trench, and the gap is located in the bit line isolation trench
  • the bottom corner of the trench extends along the second direction, and the gap exposes part of the bottom of the bit line isolation trench.
  • Step S103 etching the first semiconductor pillar along the first direction through the gap to form a bit line trench.
  • etching the first semiconductor pillar along the first direction may be etching a part of the first semiconductor pillar in the first direction, or may be etching all the first semiconductor pillar in the first direction.
  • Step S104 forming a bit line in the bit line trench.
  • FIGS. 2a-2t, 3a-3h are structural schematic diagrams of the formation process of the semiconductor structure provided by the embodiment of the present disclosure. Next, please refer to FIGS. 2a-2t, 3a-3h to further describe the method of forming the semiconductor structure provided by the embodiment of the present disclosure. .
  • step S101 is performed to provide a semiconductor substrate, the semiconductor substrate including a plurality of first semiconductor columns and bit line isolation trenches arranged at intervals along a first direction.
  • the step S101 may include the following steps:
  • Step S1011 providing a semiconductor substrate.
  • Step S1012 forming a patterned photoresist layer on the surface of the semiconductor substrate.
  • Step S1013 etching the semiconductor substrate through the patterned photoresist layer to form a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals along the first direction.
  • the semiconductor substrate 20 is etched along the Z-axis direction to form bit line isolation trenches 201 and first semiconductor pillars 202 arranged at intervals along the X-axis direction.
  • the bit line isolation trenches 201 are arranged along the X-axis direction. Extends in the Y-axis direction.
  • Figure 2c is a top view of the etched semiconductor pillar, and Figures 2d and 2e are cross-sectional views along the aa', bb', and cc' directions in Figure 2c, respectively. It can be seen that the bit line isolation trench The bottom of 201 still has a partial thickness of the semiconductor substrate.
  • step S102 is performed to form a bit line isolation layer in the bit line isolation trench; wherein, there is a gap between the bit line isolation layer and the bit line isolation trench The gap is located at a bottom corner of the bit line isolation trench and extends along the second direction, and the gap exposes part of the bottom of the bit line isolation trench.
  • step S102 may be formed by the following steps:
  • Step S1021 forming an initial bit line isolation layer in the bit line isolation trench.
  • the initial bit line isolation layer may be formed through the following steps:
  • Step S10 sequentially forming a first initial isolation layer and a second initial isolation layer in the bit line isolation trench.
  • the material of the first initial isolation layer and the second initial isolation layer can be any suitable insulating material, but the first initial isolation layer is different from the second initial isolation layer.
  • the first initial isolation layer may be a silicon oxide layer
  • the second initial isolation layer may be a silicon nitride layer.
  • the first initial isolation layer and the second initial isolation layer can be formed by any suitable deposition process, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process, spin coating process or coating process.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • spin coating process or coating process spin coating process.
  • the second initial isolation layer when forming the second initial isolation layer, due to the influence of the process, the second initial isolation layer will often cover the top surface of the first semiconductor pillar. At this time, the second initial isolation layer needs to be dry-etched. etch treatment or chemical mechanical polishing (Chemical Mechanical Polishing, CMP) to expose the top surface of the first semiconductor pillar, therefore, in the embodiment of the present disclosure, the top surface of the second initial isolation layer and the first semiconductor The top surface of the column is flush.
  • CMP chemical mechanical polishing
  • a first initial isolation layer 203a and a second initial isolation layer 204a are sequentially formed in the bit line isolation trench, wherein the top surface of the second initial isolation layer 204a is connected to the top surface of the first semiconductor pillar 202 flush.
  • Step S11 along the third direction, sequentially etching and removing part of the second initial isolation layer and part of the first initial isolation layer to form a first etching groove; wherein, the first etching groove exposes The first sidewall of the bit line isolation trench and part of the bottom of the bit line isolation trench; the third direction is the depth direction of the bit line isolation trench.
  • part of the second initial isolation layer and part of the first initial isolation layer may be removed by a dry etching process, for example, a plasma etching process, a reactive ion etching process or an ion milling process.
  • the second initial isolation layer 204a and the first initial isolation layer 203a are sequentially etched to remove part of the second initial isolation layer 204a and part of the first initial isolation layer 203a , exposing the first sidewall 201-1 of the bit line isolation trench and part of the bottom of the bit line isolation trench, forming a first etching groove A.
  • the remaining first initial isolation layer 203 and the remaining second initial isolation layer 204 remain in the bit line isolation trench.
  • removing part of the second initial isolation layer 204a and part of the first initial isolation layer 203a may be removing half of the second initial isolation layer 204a in each bit line isolation trench and removing each bit line isolation trench. half of the groove in the first initial isolation layer 203a.
  • other proportions of the second initial isolation layer and the first initial isolation layer may also be removed, for example, 3/5 of the second initial isolation layer and the first initial isolation layer may be removed.
  • Step S12 filling the isolation material in the first etching groove to form a third initial isolation layer.
  • the isolation material may be any insulating material, such as silicon oxide, silicon nitride or silicon oxynitride. In the embodiment of the present disclosure, the isolation material is the same as the composition material of the second initial isolation layer.
  • the third initial isolation layer when forming the third initial isolation layer, due to the influence of the process, the third initial isolation layer will often cover the top surfaces of the first semiconductor pillars and the second initial isolation layer. At this time, the third initial isolation layer needs to be The isolation layer is subjected to dry etching treatment or CMP treatment to expose the top surface of the first semiconductor pillar and the second initial isolation layer. Therefore, in the embodiment of the present disclosure, the top surface of the third initial isolation layer is the same as the Top surfaces of the first semiconductor pillars and the remaining second initial isolation layer are flush.
  • an isolation material is filled in the first etching groove A to form a third initial isolation layer 205, and the top surface of the third initial isolation layer is connected with the first semiconductor pillar 202 and the remaining second initial isolation layer.
  • the top surface of the isolation layer 204 is even.
  • the remaining first initial isolation layer 203 , the remaining second initial isolation layer 204 and the third initial isolation layer 205 constitute the initial bit line isolation layer 206 a.
  • Step S1022 removing part of the initial bit line isolation layer to form the bit line isolation layer and the gap.
  • bit line isolation layer and the gap can be formed by the following steps:
  • Step S13 sequentially etching the remaining second initial isolation layer and the remaining first initial isolation layer along the third direction at the end of the bit line isolation trench to form at least one opening.
  • the process of forming the opening may be formed through a dry etching process.
  • the remaining second initial isolation layer 204 and the remaining first initial isolation layer 203 are sequentially etched to form one or two The opening B, the bottom of the opening B is located inside the remaining first initial isolation layer 203 .
  • Step S14 removing the remaining first initial isolation layer in the initial bit line isolation layer through the opening to form the bit line isolation layer and the void.
  • a wet etching process is used to remove the initial bit line isolation layer 206a by injecting an etching solution, such as phosphoric acid solution (H 3 PO 4 ), sulfuric acid solution or hydrofluoric acid solution, into the opening B.
  • an etching solution such as phosphoric acid solution (H 3 PO 4 ), sulfuric acid solution or hydrofluoric acid solution.
  • the remaining first initial isolation layer 203 forms a bit line isolation layer 206 and a gap C extending along the Y-axis direction.
  • step S103 is performed to etch the first semiconductor pillar along the first direction through the gap to form a bit line trench.
  • the process of etching the first semiconductor column through the gap is a wet etching process, and the process of etching the first semiconductor column may include the following two etching processes:
  • the first etching process is: partially etching the first semiconductor pillar along the first direction through the gap to form a second etching groove.
  • the size of the second etched groove in the third direction is equal to the size of the gap in the third direction, and the size of the second etched groove in the first direction is smaller than The size of the first semiconductor pillar in the first direction.
  • the second etching groove and the gap together form the bit line trench.
  • the first semiconductor column 202 is partially etched along the X-axis direction through the gap C to form a second etching groove D, and the size of the second etching groove D in the Z-axis direction is h1 is equal to the dimension h2 of the gap C in the Z-axis direction, and the dimension w1 of the second etching groove D in the Y-axis direction is smaller than the dimension w2 of the gap C in the Y-axis direction.
  • the second etched groove D and the gap C form the bit line trench E together.
  • the second etching process is: through the gap, etch the entire first semiconductor column along the first direction to form a third etching groove.
  • the size of the third etching groove in the third direction is equal to the size of the gap in the third direction
  • the size of the third etching groove in the first direction is equal to The size of the first semiconductor pillar in the first direction.
  • the third etch groove and the gap together form the bit line trench.
  • the first semiconductor column 202 is completely etched along the X-axis direction through the gap C to form a third etching groove D', and the third etching groove D' is along the Z-axis direction.
  • the dimension h3 of the gap C is equal to the dimension h2 of the gap C in the Z-axis direction
  • the dimension w3 of the third etched groove D' in the Y-axis direction is equal to the dimension w2 of the gap C in the Y-axis direction.
  • the third etching groove D' and the gap C together form the bit line trench E'.
  • step S104 is performed to form a bit line in the bit line trench.
  • the method before forming the bit line, the method further includes:
  • Step S15 etching and removing the remaining second initial isolation layer along the third direction to form a fourth etching groove; wherein, the fourth etching groove exposes the gap and the position The second sidewall of the line isolation trench.
  • the remaining second initial isolation layer may be etched and removed by using a dry etching process to form the fourth etching groove.
  • the remaining second initial isolation layer 204 is etched away to form a fourth etching groove F.
  • the fourth etch groove F exposes the gap C and the second sidewall 201-2 of the bit line isolation trench.
  • Step S16 forming the bit line in the bit line trench through the fourth etching groove.
  • step S16 may be implemented through the following steps:
  • Step S161 forming an initial bit line layer in the fourth etching groove and the bit line trench.
  • an initial bit line layer 207a is formed in the fourth etching groove F and bit line trench E or bit line trench E' by any suitable deposition process.
  • Step S162 etching back the initial bit line layer, removing the initial bit line layer located in the fourth etching groove, and forming the bit line.
  • the initial bit line layer 207a is etched back to remove the initial bit line layer located in the fourth etching groove F to form a bit line 207 .
  • the material of the initial bit line layer or bit line includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.
  • the method for forming the semiconductor structure further includes:
  • Step S17 filling the fourth etching groove with an insulating material to form an insulating layer.
  • the insulating material forming the insulating layer may be the same as or different from the composition material of the third initial isolation layer.
  • an insulating material is filled in the fourth etching groove F to form an insulating layer 208, wherein the top surface of the insulating layer 208 is flat with the top surface of the third initial isolation layer 205. together.
  • the method for forming the semiconductor structure further includes the following steps, below, taking the partial etching of the first semiconductor column (ie, the bit line trench E) in the first direction as an example , the subsequent forming process will be described with reference to FIGS. 3a to 3h.
  • Step S18 forming a plurality of word line trenches in the first semiconductor pillar; the word line trenches extend along the first direction.
  • the word line trench is used to form a word line and a word line isolation structure.
  • step S18 may be formed by the following steps:
  • Step S181 etching the first semiconductor pillar along the third direction to form a plurality of word line trenches and second semiconductor pillars arranged at intervals along the second direction.
  • the first semiconductor column is etched along the Z-axis direction to form a plurality of second semiconductor columns 301 and word line trenches 302 arranged at intervals along the Y-axis direction, and the word line trenches 302 are arranged along the X-axis direction.
  • Figure 3b is a top view of the etched semiconductor pillar
  • Figures 3c and 3d are cross-sectional views along the aa', bb', cc' and dd' directions in Figure 3b, respectively. It can be seen that, The bottom of the wordline trench 302 protrudes beyond the top of the bitline 206 .
  • Step S19 forming a word line in the word line trench.
  • the process of forming word lines may include the following steps:
  • Step S191 forming a gate insulating layer on the sidewall of the word line trench.
  • Step S192 forming a bottom initial barrier layer, an initial word line layer, and a top initial barrier layer in sequence in the word line trench where the gate insulating layer is formed.
  • the material of the gate insulating layer may be any insulating material, such as silicon oxide.
  • Materials of the bottom initial barrier layer and the top initial barrier layer may be the same or different, for example, both the bottom initial barrier layer and the top initial barrier layer may be silicon nitride.
  • the material of the initial word line layer includes tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, titanium nitride or any combination thereof.
  • the gate insulating layer, the bottom initial barrier layer, the initial word line layer and the top initial barrier layer may be formed by any suitable deposition process.
  • a gate insulating layer 303 is formed on the sidewall of the word line trench 302, and in the word line trench formed with the gate insulating layer 303, a bottom initial barrier layer 304a, an initial word line layer are sequentially formed 305a and top initial barrier layer 306a.
  • Step S193 along the third direction, sequentially etch part of the top initial barrier layer, part of the initial word line layer and part of the bottom initial barrier layer to form a word line isolation located in the center of the word line trench trench, and the rest of the initial word line layer constitutes the word line; wherein, a part of the bottom initial barrier layer remains at the bottom of the word line isolation trench.
  • part of the top initial barrier layer 306a, part of the initial word line layer 305a and part of the bottom initial barrier layer 304a are sequentially etched to form a word line isolation trench 307a located in the center of the word line trench,
  • the remaining initial word line layer constitutes the word line 305
  • the remaining top initial barrier layer constitutes the top barrier layer 306 of the semiconductor structure
  • the remaining bottom initial barrier layer constitutes the bottom barrier layer 304 of the semiconductor structure.
  • part of the bottom initial barrier layer 304a remains at the bottom of the formed word line isolation trench 307a.
  • the method for forming the semiconductor structure further includes:
  • Step S20 filling the word line isolation trench with an insulating material to form a word line isolation layer.
  • an insulating material is deposited in the word line isolation trench 307 a by any suitable deposition process to form the word line isolation layer 307 .
  • the word line isolation layer is used to isolate adjacent word lines 305 .
  • VGAA vertical gate-all-around
  • DRAM Dynamic Random Access Memory
  • the semiconductor structure formed by the method for forming a semiconductor structure provided by an embodiment of the present disclosure includes a buried word line and a buried bit line, wherein the bit line is partially buried in the bit line isolation trench, and the other part of the bit line is buried in the first semiconductor
  • the bottom of the pillar in this way, can reduce the bit line resistance, voltage and current of the formed semiconductor structure, and reduce the parasitic capacitance between adjacent bit lines, and improve the performance of the semiconductor structure.
  • the embodiments of the present disclosure further provide a semiconductor structure, which is formed by the method for forming the semiconductor structure provided in the above embodiments.
  • Figure 4a is an optional top view of the semiconductor structure provided by the embodiment of the present disclosure
  • Figures 4b-4d are respectively cross-sectional views of the semiconductor structure along different directions, as shown in Figures 4a-4d, the semiconductor structure 40 includes: a semiconductor substrate bottom, bit line 402 and word line 403.
  • the semiconductor substrate includes a plurality of semiconductor pillars 401 (corresponding to the first semiconductor pillars etched to form the second semiconductor pillars in the above implementation) arranged at intervals along the first direction and bit line isolation trenches;
  • the bit line isolation trench is filled with a bit line isolation layer 404 .
  • the bit line isolation trench extends along the second direction, that is, the bit line isolation layer 404 extends along the second direction, and the first direction is perpendicular to the second direction.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction
  • the third direction is defined as the Z-axis direction.
  • the bit line 402 is partially buried at the bottom of the semiconductor pillar 401, and another part of the bit line 402 is buried at the bottom corner between the bit line isolation layer 404 and the bit line isolation trench, so The bit line 402 extends along the Y-axis direction.
  • the semiconductor substrate further includes a plurality of word line trenches arranged at intervals along the Y-axis direction and a second semiconductor column 405, the first semiconductor column 401 includes the second semiconductor column 405,
  • the semiconductor structure 40 further includes: a gate insulating layer 406 located on the sidewall of the word line trench; a word line isolation layer 407 located at the center of the word line trench, and the word line isolation layer 407
  • the top surface is flush with the top surface of the second semiconductor pillar 405; the size h4 of the word line isolation layer in the third direction is smaller than the size h5 of the word line trench in the third direction; the third The direction is the depth direction of the word line trench.
  • the word line 403 is located between the gate insulating layer 406 in the middle of the word line trench and the corresponding word line isolation layer 407; the semiconductor structure 40 further includes: a top barrier layer 408 located in the word line trench Between the gate insulating layer 406 on the top of the word line trench and the corresponding word line isolation layer 407; the bottom barrier layer 409 is located at the bottom of the word line trench formed with the gate insulating layer 406, and the bottom The barrier layer 409 is in contact with the word line 403 and part of the word line isolation layer 407 .
  • the semiconductor structure further includes: a channel 410; the channel 410 is located between two adjacent gate insulating layers 406, and the channel 410 is corresponding to the word line 403 , the second semiconductor pillar region between two adjacent gate insulating layers 406 .
  • the semiconductor structure may further include functional devices such as storage capacitors or adjustable resistors, which will not be described in detail here.
  • the method for forming the semiconductor structure in the embodiment of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments.
  • the technical features not disclosed in detail in the embodiments of the present disclosure please refer to the above-mentioned embodiments for understanding, and details will not be repeated here.
  • the bit line is partially buried in the bit line isolation trench, and the other part is buried in the bottom of the semiconductor pillar, the bit line resistance, voltage and current of the formed semiconductor structure can be reduced, and the Parasitic capacitance between adjacent bit lines is reduced, improving the performance of the semiconductor structure.
  • the disclosed devices and methods may be implemented in non-target ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the various components shown or discussed are coupled with each other, or directly coupled.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure includes: providing a semiconductor substrate, the semiconductor substrate including a plurality of first semiconductor columns and bit line isolation trenches arranged at intervals along a first direction Groove; the bit line isolation trench extends along the second direction; a bit line isolation layer is formed in the bit line isolation trench, and there is a gap between the bit line isolation layer and the bit line isolation trench, and the gap is located in the bit line isolation trench and extending along the second direction at the corner of the bottom; etching the first semiconductor column along the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.
  • the bit line is partially buried in the bit line isolation trench, and the other part of the bit line is buried in the bottom of the first semiconductor pillar. In this way, the formation cost can be reduced.
  • the bit line resistance, voltage and current of the semiconductor structure are improved, and the parasitic capacitance between adjacent bit lines is reduced to improve the performance of the semiconductor structure.

Abstract

一种半导体结构及其形成方法，该方法包括：提供半导体衬底（20），该半导体衬底（20）包括多个沿第一方向间隔排布的第一半导体柱（202）和位线隔离沟槽（201）；该位线隔离沟槽（201）沿第二方向延伸，该第一方向垂直于该第二方向；在该位线隔离沟槽（201）中形成位线隔离层（206、404）；其中，该位线隔离层（206、404）与该位线隔离沟槽（201）之间具有一空隙（C），该空隙（C）位于该位线隔离沟槽（201）的底部拐角处且沿该第二方向延伸，且该空隙（C）暴露出部分该位线隔离沟槽（201）的底部；通过该空隙（C），沿该第一方向刻蚀该第一半导体柱（202），形成位线沟槽（E、E'）；在该位线沟槽（E、E'）中形成位线（207、402）。

Description

半导体结构及其形成方法
相关的交叉引用
本公开基于申请号为202110941165.9、申请日为2021年08月17日、发明名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构及其形成方法。
背景技术
半导体器件通常包括多个晶体管，例如，在诸如动态随机存储器(Dynamic Random Access Memory，DRAM)的存储器件中，存储器单元包括金属-氧化物-半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。通常，在MOSFET中，源极/漏极区域形成在半导体衬底的表面，并且在这样的布置下，源极区域与漏极区域之间形成平面沟道。
随着存储器件的集成度的不断增加，MOSFET制造将达到物理极限，且随着MOSFET尺寸的不断缩小，存储器件对数据维持性能确越来越差。在这种情况下，垂直沟道晶体管(Vertical Channel Transistor，VCT)应运而生。在VCT中，源极区域和漏极区域形成在柱体的相应端部，源极区域和漏极区域中的任何一个可以与位线连接，位线是通过被掩埋在半导体柱之间所限定的沟槽内而形成的，因此被称作为掩埋位线(Buried Bit Line，BBL)。
相关技术中，位线全部掩埋在沟道底部，一方面，使得位线电阻、位线电压和位线电流均比较大；另一方面，由于位线与半导体柱相接触，因此，在相邻位线之间产生了较大的寄生电容。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其形成方法。
第一方面，本公开实施例提供一种半导体结构的形成方法，所述方法包括：
提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的第一半导体柱和位线隔离沟槽；所述位线隔离沟槽沿第二方向延伸，所述第一方向垂直于所述第二方向；
在所述位线隔离沟槽中形成位线隔离层；其中，所述位线隔离层与所述位线隔离沟槽之间具有一空隙，所述空隙位于所述位线隔离沟槽的底部拐角处且沿所述第二方向延伸，且所述空隙暴露出部分所述位线隔离沟槽的底部；
通过所述空隙，沿所述第一方向刻蚀所述第一半导体柱，形成位线沟槽；
在所述位线沟槽中形成位线。
在一些实施例中，在所述位线隔离沟槽中形成位线隔离层，包括：
在所述位线隔离沟槽中形成初始位线隔离层；
去除部分所述初始位线隔离层，形成所述位线隔离层和所述空隙。
在一些实施例中，在所述位线隔离沟槽中形成初始位线隔离层，包括：
在所述位线隔离沟槽中依次形成第一初始隔离层和第二初始隔离层；
沿第三方向，依次刻蚀去除部分所述第二初始隔离层和部分所述第一初始隔离层，形成第一刻蚀凹槽；其中，所述第一刻蚀凹槽暴露出所述位线隔离沟槽的第一侧壁和所 述位线隔离沟槽的部分底部；所述第三方向为所述位线隔离沟槽的深度方向；
在所述第一刻蚀凹槽中填充隔离材料，形成第三初始隔离层；
剩余的所述第一初始隔离层、剩余的所述第二初始隔离层和所述第三初始隔离层，构成所述初始位线隔离层。
在一些实施例中，所述去除部分初始位线隔离层，形成所述位线隔离层和所述空隙，包括：
在所述位线隔离沟槽的端部，沿所述第三方向，依次刻蚀所述剩余的第二初始隔离层和所述剩余的第一初始隔离层，形成至少一个开口；
通过所述开口，去除所述初始位线隔离层中的所述剩余的第一初始隔离层，形成所述位线隔离层和所述空隙。
在一些实施例中，通过所述空隙，沿所述第一方向刻蚀所述第一半导体柱，形成位线沟槽，包括：
通过所述空隙，沿所述第一方向，部分刻蚀所述第一半导体柱，形成第二刻蚀凹槽；其中，所述第二刻蚀凹槽在所述第三方向上的尺寸等于所述空隙在所述第三方向上的尺寸，且所述第二刻蚀凹槽在所述第一方向上的尺寸小于所述第一半导体柱在所述第一方向上的尺寸；
所述第二刻蚀凹槽和所述空隙共同构成所述位线沟槽。
在一些实施例中，通过所述空隙，沿所述第一方向刻蚀所述第一半导体柱，形成位线沟槽，包括：
通过所述空隙，沿所述第一方向，全部刻蚀所述第一半导体柱，形成第三刻蚀凹槽；其中，所述第三刻蚀凹槽在所述第三方向上的尺寸等于所述空隙在所述第三方向上的尺寸，且所述第三刻蚀凹槽在所述第一方向上的尺寸等于所述第一半导体柱在所述第一方向上的尺寸；
所述第三刻蚀凹槽和所述空隙共同构成所述位线沟槽。
在一些实施例中，在形成所述位线之前，所述方法还包括：
沿所述第三方向，刻蚀去除所述剩余的第二初始隔离层，形成第四刻蚀凹槽；其中，所述第四刻蚀凹槽暴露出所述空隙和所述位线隔离沟槽的第二侧壁；
通过所述第四刻蚀凹槽，在所述位线沟槽中，形成所述位线。
在一些实施例中，通过所述第四刻蚀凹槽，在所述位线沟槽中形成所述位线，包括：
在所述第四刻蚀凹槽和所述位线沟槽中形成初始位线层；
对所述初始位线层进行回刻，去除位于所述第四刻蚀凹槽中的初始位线层，形成所述位线。
在一些实施例中，在形成所述位线之后，所述方法还包括：
在所述第四刻蚀凹槽中填充绝缘材料，形成绝缘层；
其中，所述绝缘层的顶表面与所述第三初始隔离层的顶表面平齐。
在一些实施例中，在形成所述绝缘层之后，所述方法还包括：
在所述第一半导体柱中形成多个字线沟槽，所述字线沟槽沿所述第一方向延伸；
在所述字线沟槽中形成字线。
在一些实施例中，在所述第一半导体柱中形成多个字线沟槽，包括：
沿所述第三方向，刻蚀所述第一半导体柱，形成多个沿所述第二方向间隔排布的所述字线沟槽和第二半导体柱；
其中，所述字线沟槽的底部超出于所述位线的顶部。
在一些实施例中，在所述字线沟槽中形成字线，包括：
在所述字线沟槽的侧壁形成栅极绝缘层；
在形成有所述栅极绝缘层的字线沟槽中，依次形成底部初始阻挡层、初始字线层和顶部初始阻挡层；
沿所述第三方向，依次刻蚀部分所述顶部初始阻挡层、部分所述初始字线层和部分所述底部初始阻挡层，形成位于所述字线沟槽中心的字线隔离沟槽，剩余的所述初始字线层构成所述字线；
其中，所述字线隔离沟槽的底部保留有部分底部初始阻挡层。
在一些实施例中，在形成所述字线之后，所述方法还包括：
在所述字线隔离沟槽中填充绝缘材料，形成字线隔离层。
第二方面，本公开实施例提供一种半导体结构，至少包括：
半导体衬底；所述半导体衬底包括多个沿第一方向间隔排布的半导体柱和位线隔离沟槽；所述位线隔离沟槽沿第二方向延伸，所述第一方向垂直于所述第二方向；
位线隔离层，位于所述位线隔离沟槽中；
位线，所述位线部分掩埋于所述半导体柱的底部，且所述位线的另一部分掩埋于所述位线隔离层与所述位线隔离沟槽之间的底部拐角处。
在一些实施例中，所述半导体衬底还包括多个沿第二方向间隔排布的字线沟槽和第二半导体柱；所述半导体结构还包括：
栅极绝缘层，位于所述字线沟槽的侧壁；
字线隔离层，位于所述字线沟槽的中心，且所述字线隔离层的顶表面与所述第二半导体柱的顶表面平齐；所述字线隔离层在第三方向上的尺寸小于所述字线沟槽在所述第三方向上的尺寸；所述第三方向为所述字线沟槽的深度方向；
顶部阻挡层，位于所述字线沟槽顶部的栅极绝缘层与对应的字线隔离层之间；
字线，位于所述字线沟槽中间的栅极绝缘层与对应的字线隔离层之间；
底部阻挡层，位于形成有所述栅极绝缘层的字线沟槽的底部，且所述底部阻挡层与所述字线和部分所述字线隔离层相接触。
在一些实施例中，所述半导体结构还包括：沟道；
所述沟道位于相邻两个栅极绝缘层之间，且所述沟道为与所述字线对应的、相邻两个栅极绝缘层之间的第二半导体柱区域。
本公开实施例提供的半导体结构及其形成方法，其中，半导体结构的形成方法包括：提供半导体衬底，半导体衬底包括多个沿第一方向间隔排布的第一半导体柱和位线隔离沟槽；位线隔离沟槽沿第二方向延伸；在位线隔离沟槽中形成位线隔离层，位线隔离层与位线隔离沟槽之间具有一空隙，空隙位于位线隔离沟槽的底部拐角处且沿第二方向延伸；通过空隙，沿第一方向刻蚀第一半导体柱，形成位线沟槽；在位线沟槽中形成位线。通过本公开实施例提供的半导体结构的形成方法所形成的半导体结构，位线部分掩埋于位线隔离沟槽中，位线的另一部分掩埋于第一半导体柱的底部，如此，可以降低形成的半导体结构的位线电阻、电压和电流，并降低了相邻位线之间的寄生电容，提高半导体结构的性能。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本公开实施例提供的半导体结构的形成方法的一种可选的流程示意图；
图2a～2t、3a～3h为本公开实施例提供的半导体结构形成过程的结构示意图；
图4a为本公开实施例提供的半导体结构的一种可选的俯视图；
图4b～4d为本公开实施例提供的半导体结构沿不同方向的剖视图；
附图标记说明：
20-半导体衬底；201-位线隔离沟槽；201-1-位线隔离沟槽的第一侧壁；201-2-位线隔离沟槽的第二侧壁；202-第一半导体柱；203a-第一初始隔离层；203-剩余的第一初始隔离层；204a-第二初始隔离层；204-剩余的第二初始隔离层；205-第三初始隔离层；206a-初始位线隔离层；206/404-位线隔离层；207a-初始位线层；207/402-位线；208-绝缘层；301/405-第二半导体柱；302-字线沟槽；303/406-栅极绝缘层；304a-底部初始阻挡层；304/409-底部阻挡层；305a-初始字线层；305/403-字线；306a-顶部初始阻挡层；306/408-顶部阻挡层；307a-字线隔离沟槽；307/407-字线隔离层；40-半导体结构；401-半导体柱；410-沟道；A-第一刻蚀凹槽；B-开口；C-空隙；D-第二刻蚀凹槽；D’-第三刻蚀凹槽； E/E’-位线沟槽；F-第四刻蚀凹槽。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
基于相关技术中存在的问题，本公开实施例提供一种半导体结构及其形成方法，其中，半导体结构的形成方法包括提供半导体衬底，半导体衬底包括多个沿第一方向间隔排布的第一半导体柱和位线隔离沟槽；位线隔离沟槽沿第二方向延伸；在位线隔离沟槽中形成位线隔离层，位线隔离层与位线隔离沟槽之间具有一空隙，空隙位于位线隔离沟槽的底部拐角处且沿第二方向延伸；通过空隙，沿第一方向刻蚀第一半导体柱，形成位线沟槽；在位线沟槽中形成位线。通过本公开实施例提供的半导体结构的形成方法所形成的半导体结构，位线部分掩埋于位线隔离沟槽中，位线的另一部分掩埋于第一半导体柱的底部，如此，可以降低形成的半导体结构的位线电阻、电压和电流，并降低了相邻位线之间的寄生电容，提高半导体结构的性能。
本公开实施例提供一种半导体结构的形成方法，如图1所示，所述半导体结构的形成方法包括以下步骤：
步骤S101、提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的第一半导体柱和位线隔离沟槽。
其中，所述位线隔离沟槽沿第二方向延伸，所述第一方向垂直于所述第二方向。
所述半导体衬底可以是硅衬底，所述半导体衬底也可以包括其他半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其他半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、及/或磷砷化铟镓(GaInAsP)或其组合。
所述半导体衬底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面； 在忽略顶表面和底表面的平整度的情况下，定义垂直半导体衬底顶表面和底表面的方向为第三方向。在半导体衬底顶表面和底表面(即半导体衬底所在的平面)方向上，定义两彼此相交(例如彼此垂直)的第一方向和第二方向，例如，可以定义多个位线隔离沟槽的排列方向为第一方向，定义所述位线隔离沟槽的延伸方向为第二方向，基于所述第一方向和所述第二方向可以确定所述半导体衬底的平面方向。这里，所述第一方向、所述第二方向和所述第三方向两两垂直。本公开实施例中，定义所述第一方向为X轴方向，定义所述第二方向为Y轴方向，定义所述第三方向为Z轴方向。
本公开实施例中，所述位线隔离沟槽用于填充隔离材料，以隔离最终形成的位线。所述第一半导体柱为刻蚀所述半导体衬底形成多个位线隔离沟槽之后，位于相邻两个位线隔离沟槽之间的半导体衬底。位线隔离沟槽与第一半导体柱沿第一方向间隔排布。
步骤S102、在所述位线隔离沟槽中形成位线隔离层；其中，所述位线隔离层与所述位线隔离沟槽之间具有一空隙，所述空隙位于所述位线隔离沟槽的底部拐角处且沿所述第二方向延伸，且所述空隙暴露出部分所述位线隔离沟槽的底部。
步骤S103、通过所述空隙，沿所述第一方向刻蚀所述第一半导体柱，形成位线沟槽。
这里，通过所述空隙，沿第一方向刻蚀所述第一半导体柱可以是刻蚀第一方向上的部分第一半导体柱，也可以是刻蚀第一方向上的全部第一半导体柱。
步骤S104、在所述位线沟槽中形成位线。
图2a～2t、3a～3h为本公开实施例提供的半导体结构形成过程的结构示意图，接下来请参考图2a～2t、3a～3h对本公开实施例提供的半导体结构的形成方法进一步地详细说明。
首先，可以参考图2a至2e，执行步骤S101、提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的第一半导体柱和位线隔离沟槽。
在一些实施例中，所述步骤S101可以包括以下步骤：
步骤S1011、提供半导体衬底。
步骤S1012、在所述半导体衬底的表面形成一图形化的光阻层。
步骤S1013、通过所述图形化的光阻层，刻蚀所述半导体衬底，形成多个沿第一方向间隔排布的第一半导体柱和位线隔离沟槽。
如图2a和2b所示，沿Z轴方向刻蚀所述半导体衬底20，形成沿X轴方向间隔排布的位线隔离沟槽201和第一半导体柱202，位线隔离沟槽201沿Y轴方向延伸。图2c为刻蚀后的半导体柱的俯视图，图2d和2e分别为沿图2c中的a-a’、b-b’和c-c’方向的剖视图，可以看出，位线隔离沟槽201的底部仍然保留有部分厚度的半导体衬底。
接下来，可以参考图2f至2j，执行步骤S102、在所述位线隔离沟槽中形成位线隔离层；其中，所述位线隔离层与所述位线隔离沟槽之间具有一空隙，所述空隙位于所述位线隔离沟槽的底部拐角处且沿所述第二方向延伸，且所述空隙暴露出部分所述位线隔离沟槽的底部。
在一些实施例中，步骤S102可以通过以下步骤形成：
步骤S1021、在所述位线隔离沟槽中形成初始位线隔离层。
在一些实施例中，所述初始位线隔离层可以通过以下步骤形成：
步骤S10、在所述位线隔离沟槽中依次形成第一初始隔离层和第二初始隔离层。
所述第一初始隔离层和所述第二初始隔离层的材料均可以为任意一种合适的绝缘材料，但是第一初始隔离层与第二初始隔离层不同。示例性地，所述第一初始隔离层可以是氧化硅层，所述第二初始隔离层可以是氮化硅层。
本公开实施例中，可以通过任意一种合适的沉积工艺形成第一初始隔离层和第二初始隔离层，例如，化学气相沉积(Chemical Vapor Deposition，CVD)工艺、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工艺或者涂敷工艺。
需要说明的是，在形成第二初始隔离层时，由于工艺的影响，第二初始隔离层往往会覆盖在第一半导体柱的顶表面，此时，需要对第二初始隔离层进行干法刻蚀处理或者 化学机械抛光处理(Chemical Mechanical Polishing，CMP)，以暴露出第一半导体柱的顶表面，因此，本公开实施例中，所述第二初始隔离层的顶表面与所述第一半导体柱的顶表面平齐。
如图2f所示，在位线隔离沟槽中依次形成了第一初始隔离层203a和第二初始隔离层204a，其中，第二初始隔离层204a的顶表面与第一半导体柱202的顶表面平齐。
步骤S11、沿第三方向，依次刻蚀去除部分所述第二初始隔离层和部分所述第一初始隔离层，形成第一刻蚀凹槽；其中，所述第一刻蚀凹槽暴露出所述位线隔离沟槽的第一侧壁和所述位线隔离沟槽的部分底部；所述第三方向为所述位线隔离沟槽的深度方向。
本公开实施例中，可以采用干法刻蚀工艺去除部分所述第二初始隔离层和部分所述第一初始隔离层，例如，等离子刻蚀工艺，反应离子刻蚀工艺或者离子铣工艺。
如图2g所示，沿Z轴方向，依次刻蚀所述第二初始隔离层204a和所述第一初始隔离层203a，去除部分所述第二初始隔离层204a和部分第一初始隔离层203a，暴露出位线隔离沟槽的第一侧壁201-1和部分位线隔离沟槽的底部，形成了第一刻蚀凹槽A。在形成了第一刻蚀凹槽A后，位线隔离沟槽中保留有剩余的第一初始隔离层203和剩余的第二初始隔离层204。
本公开实施例中，去除部分第二初始隔离层204a和部分第一初始隔离层203a可以是去除每一位线隔离沟槽中的一半的第二初始隔离层204a和去除每一位线隔离沟槽中的一半的第一初始隔离层203a。在其它实施例中，也可以是去除其它比例的第二初始隔离层和第一初始隔离层，例如，去除3/5的第二初始隔离层和第一初始隔离层。
步骤S12、在所述第一刻蚀凹槽中填充隔离材料，形成第三初始隔离层。
在一些实施例中，所述隔离材料可以是任意一种绝缘材料，例如氧化硅、氮化硅或者氮氧化硅。本公开实施例中，所述隔离材料与所述第二初始隔离层的组成材料相同。
需要说明的是，在形成第三初始隔离层时，由于工艺的影响，第三初始隔离层往往会覆盖在第一半导体柱和第二初始隔离层的顶表面，此时，需要对第三初始隔离层进行干法刻蚀处理或者CMP处理，以暴露出第一半导体柱和第二初始隔离层的顶表面，因此，本公开实施例中，所述第三初始隔离层的顶表面与所述第一半导体柱和所述剩余的第二初始隔离层的顶表面平齐。
如图2h所示，在所述第一刻蚀凹槽A中填充隔离材料，形成了第三初始隔离层205，第三初始隔离层的顶表面与第一半导体柱202和剩余的第二初始隔离层204的顶表面平齐。剩余的第一初始隔离层203、剩余的第二初始隔离层204和所述第三初始隔离层205，构成所述初始位线隔离层206a。
步骤S1022、去除部分所述初始位线隔离层，形成所述位线隔离层和所述空隙。
在一些实施例中，所述位线隔离层和所述空隙可以通过以下步骤形成：
步骤S13、在所述位线隔离沟槽的端部，沿所述第三方向，依次刻蚀所述剩余的第二初始隔离层和所述剩余的第一初始隔离层，形成至少一个开口。
这里，形成开口的过程可以通过干法刻蚀工艺形成。
如图2i所示，在位线隔离沟槽的任意一端或两端，沿Z轴方向，依次刻蚀剩余的第二初始隔离层204和剩余的第一初始隔离层203，形成一个或者两个开口B，所述开口B的底部位于剩余的第一初始隔离层203的内部。
步骤S14、通过所述开口，去除所述初始位线隔离层中的所述剩余的第一初始隔离层，形成所述位线隔离层和所述空隙。
如图2j所示，采用湿法刻蚀工艺，通过在开口B中注入腐蚀液，例如磷酸溶液(H 3PO 4)、硫酸溶液或者氢氟酸溶液，以去除初始位线隔离层206a中的剩余的第一初始隔离层203，形成位线隔离层206和空隙C，所述空隙C沿Y轴方向延伸。
接下来，可以参考图2k和2l，执行步骤S103，通过所述空隙，沿所述第一方向刻蚀所述第一半导体柱，形成位线沟槽。
本公开实施例中，通过空隙，刻蚀第一半导体柱的过程为湿法刻蚀过程，刻蚀第一半导体柱的过程可以包括以下两种刻蚀过程：
第一种刻蚀过程是：通过所述空隙，沿所述第一方向，部分刻蚀所述第一半导体柱，形成第二刻蚀凹槽。其中，所述第二刻蚀凹槽在所述第三方向上的尺寸等于所述空隙在所述第三方向上的尺寸，且所述第二刻蚀凹槽在所述第一方向上的尺寸小于所述第一半导体柱在所述第一方向上的尺寸。所述第二刻蚀凹槽和所述空隙共同构成所述位线沟槽。
如图2k所示，通过空隙C，沿X轴方向，部分刻蚀第一半导体柱202，形成了第二刻蚀凹槽D，所述第二刻蚀凹槽D在Z轴方向上的尺寸h1等于空隙C在Z轴方向上的尺寸h2，且第二刻蚀凹槽D在Y轴方向上的尺寸w1小于空隙C在Y轴方向上的尺寸w2。本公开实施例中，第二刻蚀凹槽D和空隙C共同构成位线沟槽E。
第二种刻蚀过程是：通过所述空隙，沿所述第一方向，全部刻蚀所述第一半导体柱，形成第三刻蚀凹槽。其中，所述第三刻蚀凹槽在所述第三方向上的尺寸等于所述空隙在所述第三方向上的尺寸，且所述第三刻蚀凹槽在所述第一方向上的尺寸等于所述第一半导体柱在所述第一方向上的尺寸。所述第三刻蚀凹槽和所述空隙共同构成所述位线沟槽。
如图2l所示，通过空隙C，沿X轴方向，全部刻蚀第一半导体柱202，形成了第三刻蚀凹槽D’，所述第三刻蚀凹槽D’在Z轴方向上的尺寸h3等于空隙C在Z轴方向上的尺寸h2，且第三刻蚀凹槽D’在Y轴方向上的尺寸w3等于空隙C在Y轴方向上的尺寸w2。本公开实施例中，第三刻蚀凹槽D’和空隙C共同构成位线沟槽E’。
接下来，可以参考图2m至2t，执行步骤S104、在所述位线沟槽中形成位线。
在一些实施例中，在形成所述位线之前，所述方法还包括：
步骤S15、沿所述第三方向，刻蚀去除所述剩余的第二初始隔离层，形成第四刻蚀凹槽；其中，所述第四刻蚀凹槽暴露出所述空隙和所述位线隔离沟槽的第二侧壁。
本公开实施例中，可以采用干法刻蚀工艺刻蚀去除剩余的第二初始隔离层，形成所述第四刻蚀凹槽。
如图2m和2n所示，沿Z轴方向，刻蚀去除剩余的第二初始隔离层204，形成第四刻蚀凹槽F。第四刻蚀凹槽F暴露出空隙C和位线隔离沟槽的第二侧壁201-2。
步骤S16、通过所述第四刻蚀凹槽，在所述位线沟槽中，形成所述位线。
在一些实施例中，步骤S16可以通过以下步骤实现：
步骤S161、在所述第四刻蚀凹槽和所述位线沟槽中形成初始位线层。
如图2o和2p所示，采用任意一种合适的沉积工艺，在所述第四刻蚀凹槽F和位线沟槽E或位线沟槽E’中形成初始位线层207a。
步骤S162、对所述初始位线层进行回刻，去除位于所述第四刻蚀凹槽中的初始位线层，形成所述位线。
如图2q和2r所示，对初始位线层207a进行回刻，去除了位于第四刻蚀凹槽F中的初始位线层，形成了位线207。
本公开实施例中，初始位线层或位线的材料包括钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。
在一些实施例中，在形成所述位线之后，所述半导体结构的形成方法还包括：
步骤S17、在所述第四刻蚀凹槽中填充绝缘材料，形成绝缘层。
这里，形成所述绝缘层的绝缘材料与所述第三初始隔离层的组成材料可以相同也可以不同。
如图2s和2t所示，在第四刻蚀凹槽F中填充绝缘材料，形成了绝缘层208，其中，所述绝缘层208的顶表面与所述第三初始隔离层205的顶表面平齐。
在一些实施例中，在形成所述绝缘层之后，所述半导体结构的形成方法还包括以下步骤，下面，以部分刻蚀第一方向上的第一半导体柱(即位线沟槽E)为例，结合图3a至3h说明后续的形成过程。
步骤S18、在所述第一半导体柱中形成多个字线沟槽；所述字线沟槽沿所述第一方向延伸。
本公开实施例中，所述字线沟槽用于形成字线以及字线隔离结构。
在一些实施例中，步骤S18可以通过以下步骤形成：
步骤S181、沿所述第三方向，刻蚀所述第一半导体柱，形成多个沿所述第二方向间隔排布的所述字线沟槽和第二半导体柱。
如图3a所示，沿Z轴方向，刻蚀第一半导体柱，形成多个沿Y轴方向间隔排布的第二半导体柱301和字线沟槽302，字线沟槽302沿X轴方向延伸。图3b为刻蚀后的半导体柱的俯视图，图3c和3d分别为沿图3b中的a-a’、b-b’、c-c’和d-d’方向的剖视图，可以看出，字线沟槽302的底部超出于位线206的顶部。
步骤S19、在所述字线沟槽中形成字线。
在一些实施例中，形成字线的过程可以包括以下步骤：
步骤S191、在所述字线沟槽的侧壁形成栅极绝缘层。
步骤S192、在形成有所述栅极绝缘层的字线沟槽中，依次形成底部初始阻挡层、初始字线层和顶部初始阻挡层。
所述栅极绝缘层的材料可以是任意一种绝缘材料，例如氧化硅。所述底部初始阻挡层和所述顶部初始阻挡层的材料可以相同也可以不同，例如所述底部初始阻挡层和所述顶部初始阻挡层均可以为氮化硅。所述初始字线层的材料包括钨、钴、铜、铝、多晶硅、掺杂硅、硅化物、氮化钛或其任何组合。
本公开实施例中，可以通过任意一种合适的沉积工艺形成所述栅极绝缘层、底部初始阻挡层、初始字线层和顶部初始阻挡层。
如图3e所示，在字线沟槽302的侧壁形成栅极绝缘层303，且在形成有栅极绝缘层303的字线沟槽中，依次形成底部初始阻挡层304a、初始字线层305a和顶部初始阻挡层306a。
步骤S193、沿所述第三方向，依次刻蚀部分所述顶部初始阻挡层、部分所述初始字线层和部分所述底部初始阻挡层，形成位于所述字线沟槽中心的字线隔离沟槽，剩余的所述初始字线层构成所述字线；其中，所述字线隔离沟槽的底部保留有部分底部初始阻挡层。
如图3f所示，沿Z轴方向，依次刻蚀部分顶部初始阻挡层306a、部分初始字线层305a和部分底部初始阻挡层304a，形成位于字线沟槽中心的字线隔离沟槽307a，剩余的初始字线层构成所述字线305，且剩余的顶部初始阻挡层构成所述半导体结构的顶部阻挡层306、剩余的底部初始阻挡层构成所述半导体结构的底部阻挡层304。本公开实施例中，所形成的字线隔离沟槽307a的底部还保留有部分底部初始阻挡层304a。
在一些实施例中，在形成所述字线之后，所述半导体结构的形成方法还包括：
步骤S20、在所述字线隔离沟槽中填充绝缘材料，形成字线隔离层。
如图3g和3h所示，采用任意一种合适的沉积工艺，在字线隔离沟槽307a中沉积绝缘材料，形成字线隔离层307。所述字线隔离层用于隔离相邻的字线305。
需要说明的是，本公开实施例提供的半导体结构的形成方法可以适用于任意一种垂直全环栅(Vertical Gate-All-Around，VGAA)半导体器件，例如动态随机存取存储器(Dynamic Random Access Memory，DRAM)。
本公开实施例提供的半导体结构的形成方法所形成的半导体结构，包括掩埋字线和掩埋位线，其中，位线部分掩埋于位线隔离沟槽中，位线的另一部分掩埋于第一半导体柱的底部，如此，可以降低形成的半导体结构的位线电阻、电压和电流，并降低了相邻位线之间的寄生电容，提高半导体结构的性能。
除此之外，本公开实施例还提供一种半导体结构，所述半导体结构通过上述实施例提供的半导体结构的形成方法形成。图4a为本公开实施例提供的半导体结构的一种可选的俯视图，图4b～4d分别为半导体结构沿不同方向的剖视图，如图4a～4d所示，所述半导体结构40包括：半导体衬底、位线402和字线403。
其中，所述半导体衬底包括多个沿第一方向间隔排布的半导体柱401(对应上述实施中被刻蚀形成第二半导体柱后的第一半导体柱)和位线隔离沟槽；所述位线隔离沟槽中填充有位线隔离层404。本公开实施例中，所述位线隔离沟槽沿第二方向延伸，即所述位线隔离层404沿第二方向延伸，所述第一方向垂直于所述第二方向。
本公开实施例中，定义第一方向为X轴方向，定义第二方向为Y轴方向，定义第三方向为Z轴方向。
所述位线402部分掩埋于所述半导体柱401的底部，且所述位线402的另一部分掩埋于所述位线隔离层404与所述位线隔离沟槽之间的底部拐角处，所述位线402沿Y轴方向延伸。
在一些实施例中，所述半导体衬底还包括多个沿Y轴方向间隔排布的字线沟槽和第二半导体柱405，所述第一半导体柱401包括所述第二半导体柱405，所述半导体结构40还包括：栅极绝缘层406，位于所述字线沟槽的侧壁；字线隔离层407，位于所述字线沟槽的中心，且所述字线隔离层407的顶表面与所述第二半导体柱405的顶表面平齐；所述字线隔离层在第三方向上的尺寸h4小于所述字线沟槽在所述第三方向上的尺寸h5；所述第三方向为所述字线沟槽的深度方向。
在一些实施例中，字线403，位于所述字线沟槽中间的栅极绝缘层406与对应的字线隔离层407之间；所述半导体结构40还包括：顶部阻挡层408，位于所述字线沟槽顶部的栅极绝缘层406与对应的字线隔离层407之间；底部阻挡层409，位于形成有所述栅极绝缘层406的字线沟槽的底部，且所述底部阻挡层409与所述字线403和部分所述字线隔离层407相接触。
在一些实施例中，所述半导体结构还包括：沟道410；所述沟道410位于相邻两个栅极绝缘层406之间，且所述沟道410为与所述字线403对应的、相邻两个栅极绝缘层406之间的第二半导体柱区域。
在其它实施例中，所述半导体结构还可以包括：存储电容或者可调电阻等功能器件，这里不再详细说明。
本公开实施例中的半导体结构与上述实施例中的半导体结构的形成方法类似，对于本公开实施例未详尽披露的技术特征，请参考上述实施例进行理解，这里，不再赘述。
本公开实施例提供的半导体结构，由于位线部分掩埋于位线隔离沟槽中，另一部分掩埋于半导体柱的底部，如此，可以降低形成的半导体结构的位线电阻、电压和电流，并降低了相邻位线之间的寄生电容，提高了半导体结构的性能。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开实施例的一些实施方式，但本公开实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开实施例的保护范围之内。因此，本公开实施例的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供的半导体结构及其形成方法，其中，半导体结构的形成方法包括：提供半导体衬底，半导体衬底包括多个沿第一方向间隔排布的第一半导体柱和位线隔离沟槽；位线隔离沟槽沿第二方向延伸；在位线隔离沟槽中形成位线隔离层，位线隔离层与位线隔离沟槽之间具有一空隙，空隙位于位线隔离沟槽的底部拐角处且沿第二方向延伸；通过空隙，沿第一方向刻蚀第一半导体柱，形成位线沟槽；在位线沟槽中形成位线。通过本公开实施例提供的半导体结构的形成方法所形成的半导体结构，位线部分掩埋于位线隔离沟槽中，位线的另一部分掩埋于第一半导体柱的底部，如此，可以降低形成的 半导体结构的位线电阻、电压和电流，并降低了相邻位线之间的寄生电容，提高半导体结构的性能。

Claims (16)

  1. 一种半导体结构的形成方法，所述方法包括：
    提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的第一半导体柱和位线隔离沟槽；所述位线隔离沟槽沿第二方向延伸，所述第一方向垂直于所述第二方向；
    在所述位线隔离沟槽中形成位线隔离层；其中，所述位线隔离层与所述位线隔离沟槽之间具有一空隙，所述空隙位于所述位线隔离沟槽的底部拐角处且沿所述第二方向延伸，且所述空隙暴露出部分所述位线隔离沟槽的底部；
    通过所述空隙，沿所述第一方向刻蚀所述第一半导体柱，形成位线沟槽；
    在所述位线沟槽中形成位线。
  2. 根据权利要求1所述的方法，其中，在所述位线隔离沟槽中形成位线隔离层，包括：
    在所述位线隔离沟槽中形成初始位线隔离层；
    去除部分所述初始位线隔离层，形成所述位线隔离层和所述空隙。
  3. 根据权利要求2所述的方法，其中，在所述位线隔离沟槽中形成初始位线隔离层，包括：
    在所述位线隔离沟槽中依次形成第一初始隔离层和第二初始隔离层；
    沿第三方向，依次刻蚀去除部分所述第二初始隔离层和部分所述第一初始隔离层，形成第一刻蚀凹槽；其中，所述第一刻蚀凹槽暴露出所述位线隔离沟槽的第一侧壁和所述位线隔离沟槽的部分底部；所述第三方向为所述位线隔离沟槽的深度方向；
    在所述第一刻蚀凹槽中填充隔离材料，形成第三初始隔离层；
    剩余的所述第一初始隔离层、剩余的所述第二初始隔离层和所述第三初始隔离层，构成所述初始位线隔离层。
  4. 根据权利要求3所述的方法，其中，去除部分所述初始位线隔离层，形成所述位线隔离层和所述空隙，包括：
    在所述位线隔离沟槽的端部，沿所述第三方向，依次刻蚀所述剩余的第二初始隔离层和所述剩余的第一初始隔离层，形成至少一个开口；
    通过所述开口，去除所述初始位线隔离层中的所述剩余的第一初始隔离层，形成所述位线隔离层和所述空隙。
  5. 根据权利要求4所述的方法，其中，通过所述空隙，沿所述第一方向刻蚀所述第一半导体柱，形成位线沟槽，包括：
    通过所述空隙，沿所述第一方向，部分刻蚀所述第一半导体柱，形成第二刻蚀凹槽；其中，所述第二刻蚀凹槽在所述第三方向上的尺寸等于所述空隙在所述第三方向上的尺寸，且所述第二刻蚀凹槽在所述第一方向上的尺寸小于所述第一半导体柱在所述第一方向上的尺寸；
    所述第二刻蚀凹槽和所述空隙共同构成所述位线沟槽。
  6. 根据权利要求4所述的方法，其中，通过所述空隙，沿所述第一方向刻蚀所述第一半导体柱，形成位线沟槽，包括：
    通过所述空隙，沿所述第一方向，全部刻蚀所述第一半导体柱，形成第三刻蚀凹槽；其中，所述第三刻蚀凹槽在所述第三方向上的尺寸等于所述空隙在所述第三方向上的尺寸，且所述第三刻蚀凹槽在所述第一方向上的尺寸等于所述第一半导体柱在所述第一方向上的尺寸；
    所述第三刻蚀凹槽和所述空隙共同构成所述位线沟槽。
  7. 根据权利要求5或6所述的方法，其中，在形成所述位线之前，所述方法还包括：
    沿所述第三方向，刻蚀去除所述剩余的第二初始隔离层，形成第四刻蚀凹槽；其中，所述第四刻蚀凹槽暴露出所述空隙和所述位线隔离沟槽的第二侧壁；
    通过所述第四刻蚀凹槽，在所述位线沟槽中，形成所述位线。
  8. 根据权利要求7所述的方法，其中，通过所述第四刻蚀凹槽，在所述位线沟 槽中形成所述位线，包括：
    在所述第四刻蚀凹槽和所述位线沟槽中形成初始位线层；
    对所述初始位线层进行回刻，去除位于所述第四刻蚀凹槽中的初始位线层，形成所述位线。
  9. 根据权利要求8所述的方法，其中，在形成所述位线之后，所述方法还包括：
    在所述第四刻蚀凹槽中填充绝缘材料，形成绝缘层；
    其中，所述绝缘层的顶表面与所述第三初始隔离层的顶表面平齐。
  10. 根据权利要求9所述的方法，其中，在形成所述绝缘层之后，所述方法还包括：
    在所述第一半导体柱中形成多个字线沟槽，所述字线沟槽沿所述第一方向延伸；
    在所述字线沟槽中形成字线。
  11. 根据权利要求10所述的方法，其中，在所述第一半导体柱中形成多个字线沟槽，包括：
    沿所述第三方向，刻蚀所述第一半导体柱，形成多个沿所述第二方向间隔排布的所述字线沟槽和第二半导体柱；
    其中，所述字线沟槽的底部超出于所述位线的顶部。
  12. 根据权利要求11所述的方法，其中，所述在所述字线沟槽中形成字线，包括：
    在所述字线沟槽的侧壁形成栅极绝缘层；
    在形成有所述栅极绝缘层的字线沟槽中，依次形成底部初始阻挡层、初始字线层和顶部初始阻挡层；
    沿所述第三方向，依次刻蚀部分所述顶部初始阻挡层、部分所述初始字线层和部分所述底部初始阻挡层，形成位于所述字线沟槽中心的字线隔离沟槽，剩余的所述初始字线层构成所述字线；
    其中，所述字线隔离沟槽的底部保留有部分底部初始阻挡层。
  13. 根据权利要求12所述的方法，其中，在形成所述字线之后，所述方法还包括：
    在所述字线隔离沟槽中填充绝缘材料，形成字线隔离层。
  14. 一种半导体结构，至少包括：
    半导体衬底；所述半导体衬底包括多个沿第一方向间隔排布的半导体柱和位线隔离沟槽；所述位线隔离沟槽沿第二方向延伸，所述第一方向垂直于所述第二方向；
    位线隔离层，位于所述位线隔离沟槽中；
    位线，所述位线部分掩埋于所述半导体柱的底部，且所述位线的另一部分掩埋于所述位线隔离层与所述位线隔离沟槽之间的底部拐角处。
  15. 根据权利要求14所述的半导体结构，其中，所述半导体衬底还包括多个沿第二方向间隔排布的字线沟槽和第二半导体柱；所述半导体结构还包括：
    栅极绝缘层，位于所述字线沟槽的侧壁；
    字线隔离层，位于所述字线沟槽的中心，且所述字线隔离层的顶表面与所述第二半导体柱的顶表面平齐；所述字线隔离层在第三方向上的尺寸小于所述字线沟槽在所述第三方向上的尺寸；所述第三方向为所述字线沟槽的深度方向；
    顶部阻挡层，位于所述字线沟槽顶部的栅极绝缘层与对应的字线隔离层之间；
    字线，位于所述字线沟槽中间的栅极绝缘层与对应的字线隔离层之间；
    底部阻挡层，位于形成有所述栅极绝缘层的字线沟槽的底部，且所述底部阻挡层与所述字线和部分所述字线隔离层相接触。
  16. 根据权利要求15所述的半导体结构，其中，所述半导体结构还包括：沟道；
    所述沟道位于相邻两个栅极绝缘层之间，且所述沟道为与所述字线对应的、相邻两个栅极绝缘层之间的第二半导体柱区域。
PCT/CN2022/077727 2021-08-17 2022-02-24 半导体结构及其形成方法 WO2023019902A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/810,634 US20230057480A1 (en) 2021-08-17 2022-07-04 Semiconductor structure and method for forming same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110941165.9 2021-08-17
CN202110941165.9A CN116133371A (zh) 2021-08-17 2021-08-17 半导体结构及其形成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/810,634 Continuation US20230057480A1 (en) 2021-08-17 2022-07-04 Semiconductor structure and method for forming same

Publications (1)

Publication Number Publication Date
WO2023019902A1 true WO2023019902A1 (zh) 2023-02-23

Family

ID=85239449

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/077727 WO2023019902A1 (zh) 2021-08-17 2022-02-24 半导体结构及其形成方法

Country Status (3)

Country Link
CN (1) CN116133371A (zh)
TW (1) TWI820868B (zh)
WO (1) WO2023019902A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116347889B (zh) * 2023-03-14 2024-01-12 北京超弦存储器研究院 存储单元、存储器、存储器的制备方法及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054819A (zh) * 2009-10-30 2011-05-11 海力士半导体有限公司 具有掩埋栅和掩埋位线的半导体器件及其制造方法
CN110880507A (zh) * 2018-09-05 2020-03-13 长鑫存储技术有限公司 半导体存储器及其形成方法
CN113241346A (zh) * 2021-05-08 2021-08-10 福建省晋华集成电路有限公司 半导体器件及其形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8691680B2 (en) * 2011-07-14 2014-04-08 Nanya Technology Corp. Method for fabricating memory device with buried digit lines and buried word lines
KR20150019069A (ko) * 2013-08-12 2015-02-25 에스케이하이닉스 주식회사 매립 비트라인을 갖는 반도체 장치 및 이를 이용한 전자 장치
US10636796B2 (en) * 2017-08-02 2020-04-28 Winbond Electronics Corp. Dynamic random access memory and method of fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054819A (zh) * 2009-10-30 2011-05-11 海力士半导体有限公司 具有掩埋栅和掩埋位线的半导体器件及其制造方法
CN110880507A (zh) * 2018-09-05 2020-03-13 长鑫存储技术有限公司 半导体存储器及其形成方法
CN113241346A (zh) * 2021-05-08 2021-08-10 福建省晋华集成电路有限公司 半导体器件及其形成方法

Also Published As

Publication number Publication date
TWI820868B (zh) 2023-11-01
TW202310342A (zh) 2023-03-01
CN116133371A (zh) 2023-05-16

Similar Documents

Publication Publication Date Title
KR100673012B1 (ko) 이중 게이트형 수직 채널 트랜지스터들을 구비하는다이내믹 랜덤 억세스 메모리 장치 및 그 제조 방법
US11532556B2 (en) Structure and method for transistors having backside power rails
US8283715B2 (en) Method and apparatus for buried word line formation
JP3860582B2 (ja) 半導体装置の製造方法
CN110729291B (zh) 半导体器件
US20200083356A1 (en) Photomask layout, methods of forming fine patterns and method of manufacturing semiconductor devices
TW202127664A (zh) 積體電路裝置
US20180158871A1 (en) Semiconductor memory device and method of manufacturing the same
US9337105B1 (en) Methods for fabricating semiconductor devices with wet etching
US20190206867A1 (en) Semiconductor device
WO2023019902A1 (zh) 半导体结构及其形成方法
US10014220B2 (en) Self heating reduction for analog radio frequency (RF) device
US11024631B2 (en) Integrated circuit device including field isolation layer and method of manufacturing the same
US20230197450A1 (en) Methods of manufacturing semiconductor devices using enhanced patterning techniques
WO2022057369A1 (zh) 半导体器件及其制备方法
US11621332B2 (en) Wraparound contact to a buried power rail
JP2010520645A (ja) 半導体材料内へのトレンチの形成
CN115701213A (zh) 半导体结构及其形成方法
US20230057480A1 (en) Semiconductor structure and method for forming same
WO2023040157A1 (zh) 半导体结构及其形成方法
US11037937B2 (en) SRAM bit cells formed with dummy structures
WO2023245811A1 (zh) 半导体结构及其形成方法、版图结构
US20230411473A1 (en) Self-aligned gate jumper connecting adjacent gates
WO2023065492A1 (zh) 半导体结构及其形成方法
US20240155833A1 (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22857223

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE