WO2023040157A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2023040157A1
WO2023040157A1 PCT/CN2022/072418 CN2022072418W WO2023040157A1 WO 2023040157 A1 WO2023040157 A1 WO 2023040157A1 CN 2022072418 W CN2022072418 W CN 2022072418W WO 2023040157 A1 WO2023040157 A1 WO 2023040157A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
active
etching
forming
semiconductor substrate
Prior art date
Application number
PCT/CN2022/072418
Other languages
English (en)
French (fr)
Inventor
张魁
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/867,432 priority Critical patent/US20230089265A1/en
Publication of WO2023040157A1 publication Critical patent/WO2023040157A1/zh

Links

Images

Definitions

  • the present disclosure relates to the technical field of semiconductors, and relates to but not limited to a semiconductor structure and a method for forming the same.
  • Dynamic Random Access Memory is a semiconductor storage device commonly used in computers. DRAM is composed of many repeated storage units. Each memory cell includes a transistor and a capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.
  • the source or drain of the transistor in the DRAM storage unit is usually formed on the surface of the semiconductor substrate, therefore, the bit line of the DRAM is also formed on the surface of the semiconductor substrate, so it will not meet the requirements of current semiconductor devices. High integration is required, and the bit line is located on the surface of the semiconductor substrate, so that the control ability of the bit line is weak. In addition, the structure of the bit line and the manufacturing process of the bit line in the related art are complicated, which further increases the production cost of the semiconductor device.
  • embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including:
  • a base includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active columns arranged at intervals along a first direction, and each active column The column includes a plurality of active pillars arranged at intervals along the second direction; wherein, the first direction is perpendicular to the second direction;
  • bit lines are formed.
  • bit line trench includes a first bit line trench or a second bit line trench; the method further includes:
  • the bottoms of two adjacent active pillars in the active pillar group along the first direction communicate with each other;
  • the bottoms of two adjacent active pillars in the active pillar group along the first direction are independent from each other.
  • forming a buried bit line in the bit line trench includes:
  • a bit line metal material is deposited in the first bit line trench or the second bit line trench to form the buried bit line.
  • a first insulating material is filled between any two adjacent active pillars; the first bit line trench is formed through the following steps:
  • the method also includes:
  • a second insulating material is filled in the first etching groove.
  • a first insulating material is filled between any two adjacent active pillars; the second bit line trench is formed through the following steps:
  • the third direction at least the first insulating material between two adjacent active column columns in each active column group is etched to form a plurality of second etching grooves; wherein, the third direction, the first direction and the second direction are perpendicular to each other;
  • the method also includes:
  • a second insulating material is filled in the second etching groove.
  • the method also includes:
  • bit line metal material Before depositing the bit line metal material in the first bit line trench or the second bit line trench, forming a barrier on the inner wall of the first bit line trench or the second bit line trench layer.
  • the active pillars are formed by:
  • a partial thickness of the well region is etched through the patterned mask layer to form a plurality of active pillars arranged at intervals along the first direction and the second direction.
  • the method before forming the bit line trench, the method further includes:
  • the second insulating material is filled in the third etching groove.
  • the method also includes:
  • etching part of the second insulating material between any two adjacent active pillars exposing active pillars with a first preset height; wherein, the first preset height is smaller than the initial height of the active column;
  • Buried word lines are formed on exposed sidewalls of the active pillars having a first predetermined height.
  • forming a buried word line on the exposed sidewall of the active pillar having a first preset height includes:
  • Etching back the gate oxide layer and the word line metal layer exposing active pillars with a second predetermined height; the second predetermined height is smaller than the first predetermined height;
  • the word line metal layer is patterned to form the buried word line.
  • the patterning the word line metal layer to form the buried word line includes:
  • the method also includes:
  • a third insulating material is filled between the fourth etched groove and the exposed active pillar having a second predetermined height to form a top insulating layer; wherein, the top surface of the top insulating layer is in contact with the pattern flush with the top surface of the mask layer.
  • the method also includes:
  • Capacitive structures are formed on top surfaces of the active pillars.
  • an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure is formed by the above method for forming a semiconductor structure; the semiconductor structure includes:
  • the base includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active column columns arranged at intervals along the first direction, and each active column column comprising a plurality of active pillars arranged at intervals along a second direction; wherein the first direction is perpendicular to the second direction;
  • Buried bit lines are located in bit line trenches, and the bit line trenches are located at least in the well region at the bottom of each active pillar and in a partial thickness of the semiconductor substrate.
  • bit line trenches include a first bit line trench or a second bit line trench; every two adjacent active column columns are an active column group;
  • the bottoms of two adjacent active pillars in the active pillar group along the first direction communicate with each other;
  • the bottoms of two adjacent active pillars in the active pillar group along the first direction are independent from each other.
  • the forming method of the semiconductor structure includes providing a base; the base includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; A plurality of active columns, and each active column includes a plurality of active columns arranged at intervals along the second direction; wherein, the first direction is perpendicular to the second direction; since each active column can be etched by at least The well region at the bottom of the column and the semiconductor substrate with a partial thickness form a plurality of bit line trenches; in this way, buried bit lines can be formed in the bit line trenches, which improves the integration of the formed semiconductor device; in addition,
  • the preparation process of the buried bit line in the embodiment of the present disclosure is simple, and the formed buried bit line can be effectively conducted and has strong control ability.
  • FIG. 1 is a schematic flow diagram of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIGS. 2a to 2p are schematic structural diagrams of the process of forming a semiconductor structure provided by an embodiment of the present disclosure
  • 3a-3k are another schematic structural diagrams of the semiconductor structure formation process provided by the embodiments of the present disclosure.
  • FIGS. 4a and 4b are cross-sectional views of semiconductor structures provided by embodiments of the present disclosure.
  • 200-semiconductor substrate 201-well region; 202-patterned mask layer; 201a-active column; 203-first insulating material; 204-second insulating material; 205-barrier layer; 206-embedded Bit line; 207-gate oxide layer; 208-word line metal layer; 209-buried word line; 210-top insulating layer; A-third etching groove; B-first etching groove; C1 - first bitline trench; C2 - second bitline trench; D - second etched groove; E - fourth etched groove.
  • an embodiment of the present disclosure provides a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure includes: providing a base; the base includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; The region includes a plurality of active pillar rows arranged at intervals along the first direction, and each active pillar row includes a plurality of active pillars arranged at intervals along the second direction; wherein, the first direction is perpendicular to the second direction; Since a plurality of bit line trenches can be formed by at least etching the well region at the bottom of each active pillar and the semiconductor substrate with partial thickness; in this way, buried bit lines can be formed in the bit line trenches, improving the The integration degree of the formed semiconductor device; in addition, the preparation process of the buried bit line in the embodiment of the present disclosure is simple, and the formed buried bit line can be effectively conducted, and has strong control ability.
  • An embodiment of the present disclosure provides a method for forming a semiconductor structure. As shown in FIG. 1 , the method for forming a semiconductor structure includes the following steps:
  • Step S101 providing a substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active columns arranged at intervals along a first direction, and each of the The active column array includes a plurality of active columns arranged at intervals along a second direction; wherein, the first direction is perpendicular to the second direction.
  • the base may be a structure formed by partially doping the semiconductor substrate.
  • the semiconductor substrate may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), Gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or including other semiconductor alloys such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), Aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.
  • the well region may be an N well
  • the semiconductor substrate may include a top surface at the front side and a bottom surface at the back side opposite to the front side; under the condition of ignoring the flatness of the top surface and the bottom surface, the direction vertical to the top surface and the bottom surface of the semiconductor substrate is defined as third direction.
  • the direction of the top surface and the bottom surface of the semiconductor substrate that is, the plane where the semiconductor substrate is located
  • two first and second directions that intersect each other for example, are perpendicular to each other
  • a plurality of active column columns can be defined
  • the arrangement direction is a first direction
  • the plane direction of the semiconductor substrate can be determined based on the first direction and the second direction.
  • the first direction, the second direction and the third direction are perpendicular to each other.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction
  • the third direction is defined as the Z-axis direction.
  • Step S102 etching at least the well region at the bottom of each active pillar and a partial thickness of the semiconductor substrate to form a plurality of bit line trenches.
  • a part of the well region remains at the bottom of each active pillar, and the bit line trench is located at the bottom of each active pillar.
  • Step S103 forming a buried bit line in the bit line trench.
  • FIGS. 2a-2p are a schematic structural view of the formation process of the semiconductor structure provided by the embodiment of the present disclosure. Next, please refer to FIGS. 2a-2p to further describe the formation method of the semiconductor structure provided by the embodiment of the present disclosure in detail.
  • step S101 is performed to provide a substrate;
  • the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate;
  • the well region includes a plurality of Active pillar rows, and each active pillar row includes a plurality of active pillars arranged at intervals along a second direction; wherein, the first direction is perpendicular to the second direction.
  • the base includes a semiconductor substrate 200 and a well region 201 located on the surface of the semiconductor substrate 200 .
  • the semiconductor substrate may be a P-type substrate, and the well region may be an N well.
  • the semiconductor substrate may also be an N-type substrate, and the well region may also be a P well.
  • the active pillars located in the well region can be formed by the following steps:
  • a patterned mask layer is formed on the surface of the well region.
  • a partial thickness of the well region is etched through the patterned mask layer to form a plurality of active pillars arranged at intervals along the first direction and the second direction.
  • a patterned mask layer 202 is formed on the surface of the well region 201, and the well region 201 is etched through the patterned mask layer 202 along the Z-axis direction to form a pattern along the X-axis direction and the Y-axis direction.
  • Active pillars 201a arranged at intervals.
  • a plurality of active columns arranged at intervals along the Y-axis direction constitute an active column column, and a plurality of active column columns are arranged at intervals along the X-axis direction.
  • the method for forming the semiconductor structure further includes:
  • Step S20 filling a first insulating material between any two adjacent active pillars.
  • the first insulating material may be any insulating material, for example, silicon oxide, silicon nitride or silicon oxynitride.
  • a first insulating material 203 is filled between any adjacent active pillars 201 a , wherein the top surface of the first insulating material 203 is flush with the top surface of the patterned mask layer 202 .
  • Step S21 sequentially determining every two adjacent columns of active pillars as an active pillar group.
  • Step S22 etching at least the first insulating material between two adjacent active column groups to form a plurality of third etching grooves; wherein, the bottom of the third etching grooves is located on the semiconductor substrate internal.
  • the first insulating material 203 between two adjacent active column groups and the bottom of the first insulating material 203 between two adjacent active column groups are etched.
  • the well region and part of the thickness of the semiconductor substrate form a third etching groove A, and the bottom of the third etching groove A is located inside the semiconductor substrate 200 .
  • the first insulating material, the well region and part of the semiconductor substrate may be etched by a dry etching process to form the third etching groove, for example, a plasma etching process, a reactive ion etching process Or ion milling process.
  • Step S23 filling the third etching groove with a second insulating material.
  • the second insulating material may also be any insulating material, for example, silicon oxide, silicon nitride or silicon oxynitride.
  • the second insulating material may be the same as or different from the first insulating material. In the embodiment of the present disclosure, the second insulating material is the same as the first insulating material.
  • the second insulating material 204 is filled in the third etching groove A. As shown in FIG. 2e, the second insulating material 204 is filled in the third etching groove A. As shown in FIG. 2e, the second insulating material 204 is filled in the third etching groove A. As shown in FIG. 2e, the second insulating material 204 is filled in the third etching groove A. As shown in FIG. 2e, the second insulating material 204 is filled in the third etching groove A.
  • step S102 is performed to etch at least the well region at the bottom of each active pillar and a part of the thickness of the semiconductor substrate to form a plurality of bit line trenches.
  • the bit line trench includes a first bit line trench; the first bit line trench may be formed by the following steps:
  • the first insulating material 203 between two adjacent active column columns in each active column group is etched to form a plurality of first etching grooves B, the The first etched groove B exposes the well region 201 .
  • etching the well region at the bottom of the active pillar and the semiconductor substrate with the partial thickness may be etching all the wells at the bottom of each active pillar for each active pillar row. region and the corresponding partial thickness of the semiconductor substrate, or the partial well region along the X-axis direction at the bottom of the active pillar and the corresponding partial thickness of the semiconductor substrate may be etched.
  • the etching along the X-axis direction may be wet etching or bias dry lateral etching.
  • the method for forming the semiconductor structure may further include: in each active column group, two adjacent active columns along the first direction The sidewalls form a protective layer.
  • the protective layer is used to protect the active column from damage when the first bit line trench is formed by etching; and the protective layer needs to be removed after the first bit line trench is formed.
  • step S103 is performed to form a buried bit line in the bit line trench.
  • the bit line trench includes a first bit line trench, and forming a buried bit line in the bit line trench includes:
  • a bit line metal material is deposited in the first bit line trench to form the buried bit line.
  • the bit line metal material includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.
  • the method before depositing the bit line metal material in the first bit line trench, the method further includes: forming a barrier layer on an inner wall of the first bit line trench.
  • the barrier layer is located between the metal material of the bit line and the semiconductor substrate, the metal material of the bit line and the well region, and the barrier layer is used to prevent the metal material of the bit line from diffusing into the semiconductor substrate or the well region.
  • the barrier layer can be formed by any suitable deposition process, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition) Layer Deposition, ALD) process, spin coating process or coating process.
  • the barrier layer may be a silicon nitride layer.
  • a barrier layer 205 is formed in the first bit line trench C1, and a bit line metal material is deposited in the first bit line trench with the barrier layer 205 to form a buried bit line 206. .
  • the bottoms of two adjacent active pillars in the active pillar group along the first direction communicate with each other.
  • bit line metal material in the first bit line trench when depositing the bit line metal material in the first bit line trench, the bit line metal material will also be deposited in the first etched groove B, and subsequently need to be deposited in the first The metal material of the bit line in the groove B is etched for etching back, and only the metal material of the bit line in the first bit line trench C1 remains as a buried bit line.
  • steps S21 to S23 there is no strict sequence relationship between steps S21 to S23 and the formation process of the buried bit lines, and steps S21 to S23 can also be performed after forming the buried bit lines.
  • the method for forming the semiconductor structure further includes: filling a second insulating layer in the first etched groove Material.
  • the second insulating material 204 is filled in the first etching groove B. As shown in FIG. 2 j , the second insulating material 204 is filled in the first etching groove B. As shown in FIG. 2 j , the second insulating material 204 is filled in the first etching groove B. As shown in FIG. 2 j , the second insulating material 204 is filled in the first etching groove B. As shown in FIG. 2 j , the second insulating material 204 is filled in the first etching groove B.
  • the method for forming the semiconductor structure further includes the following steps:
  • etching part of the second insulating material between any two adjacent active pillars exposing active pillars with a first preset height; wherein, the first preset height is smaller than the The initial height of the active column.
  • a portion of the second insulating material 204 between any two adjacent active columns is etched to expose an active column 201a with a first preset height h1, wherein the first preset height h1
  • the height h1 is set to be smaller than the initial height h0 of the active pillar 201a.
  • the height difference between the initial height h0 and the first preset height h1 may be 10nm-50nm.
  • Buried word lines are formed on exposed sidewalls of the active pillars having a first preset height.
  • forming a buried word line on the exposed sidewall of the active pillar with a first preset height includes the following steps:
  • a gate oxide layer is formed on the exposed sidewalls of the active pillars having a first preset height.
  • a word line metal material is filled between any two adjacent active pillars having the gate oxide layer to form a word line metal layer.
  • the word line metal material may be titanium nitride, tungsten or a combination thereof.
  • Etching back the gate oxide layer and the word line metal layer exposes the active column with a second preset height; the second preset height is smaller than the first preset height.
  • a gate oxide layer 207 and a word line metal layer 208 are formed on the exposed sidewalls of the active pillars 201a having a first predetermined height, and exposed with a second predetermined height h2. active column.
  • the second preset height h2 is smaller than the first preset height h1.
  • the second preset height includes 10nm-50nm.
  • the process of etching back the gate oxide layer and the word line metal layer may be performed in two steps, or may be performed simultaneously.
  • the word line metal layer is patterned to form the buried word line.
  • the patterning the word line metal layer to form the buried word line includes: etching the word line metal layer along the third direction, and retaining the first The word line metal layer between two adjacent active pillars in the direction forms the buried word line and the fourth etching groove extending along the first direction.
  • the word line metal layer 208 is etched along the Z-axis direction, and the word line metal layer between two adjacent active pillars 201a in the X-axis direction is reserved to form a buried word line 209 and A fourth etching groove E extending in the X-axis direction.
  • the method for forming the semiconductor structure further includes: filling a third insulating material between the fourth etched groove and the exposed active column having a second predetermined height, forming a top insulating layer; wherein the top surface of the top insulating layer is flush with the top surface of the patterned mask layer.
  • the third insulating material may also be any insulating material, for example, silicon oxide, silicon nitride or silicon oxynitride.
  • the third insulating material may be the same as or different from the second insulating material.
  • the third insulating material, the second insulating material and the first insulating material are all the same.
  • a third insulating material is filled between the fourth etched groove E and the exposed active column with a second predetermined height to form a top insulating layer 210, the top insulating layer 210 The top surface is flush with the top surface of the patterned mask layer 202 .
  • the method for forming the semiconductor structure further includes: removing the patterned mask layer on the surface of each active pillar to expose the top surface of the active pillar.
  • the patterned mask layer 202 on the surface of the active column is removed to expose the top surface of the active column 201a, and the top insulating layer 210 is subjected to chemical mechanical polishing (CMP) treatment, The top surface of the top insulating layer 210 is made flush with the top surface of the active pillar 201a.
  • CMP chemical mechanical polishing
  • the method for forming a semiconductor structure further includes: forming a capacitor structure on a top surface of the active pillar.
  • the capacitive structure may be a columnar capacitor or a cup-shaped capacitor.
  • the bit line is buried inside the semiconductor substrate, and the source and drain of the transistor are respectively located at the vertical ends of the active column, and the source and the semiconductor structure
  • the buried bit line is connected, the drain is connected to the formed capacitor structure, and the buried word line in the embodiment of the present disclosure is a ring-gate structure, and the voltage signal on the word line can control the opening or closing of the transistor, and then through
  • the bit line reads the data information stored in the capacitor structure, or writes the data information into the capacitor structure through the bit line for storage.
  • adjacent transistors share a buried bit line, the structure and preparation process of the bit line are simple, and they can be effectively conducted.
  • the integration and electrical performance of the formed semiconductor structure also reduces the production cost of the semiconductor structure.
  • FIGS. 3a-3k are another schematic structural diagrams of the formation process of the semiconductor structure provided by the embodiment of the present disclosure. Next, please refer to FIGS. 3a-3k to further describe the method of forming the semiconductor structure provided by the embodiment of the present disclosure in detail.
  • step S101 is performed to provide a substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active columns arranged at intervals along a first direction, and each One of the active pillar columns includes a plurality of active pillars arranged at intervals along a second direction; wherein, the first direction is perpendicular to the second direction.
  • step S101 is the same as the implementation process of step S101 in the above embodiment, and will not be repeated here.
  • the method for forming the semiconductor structure further includes:
  • the first insulating material is filled between any two adjacent active pillars.
  • Each two adjacent active column rows are determined as an active column group in turn.
  • the second insulating material is filled in the third etching groove.
  • step S102 is performed to etch at least the well region at the bottom of each active pillar and a partial thickness of the semiconductor substrate to form a plurality of bit line trenches.
  • the bit line trench includes a second bit line trench; the second bit line trench may be formed by the following steps:
  • the third direction at least the first insulating material between two adjacent active column columns in each active column group is etched to form a plurality of second etching grooves; wherein, the third direction, the first direction and the second direction are perpendicular to each other.
  • the first insulating material 203 between two adjacent active column columns in each active column group, and the first insulating material 203 between two adjacent active column columns are etched.
  • the well region at the bottom of the first insulating material 203 and the partial thickness of the semiconductor substrate form a plurality of second etching grooves D, and the second etching grooves D expose the semiconductor substrate 200 .
  • the first insulating material, the well region and part of the semiconductor substrate can be etched by a dry etching process to form the second etching groove, for example, a plasma etching process, a reactive ion etching process Or ion milling process.
  • the well region at the bottom of the active pillar and the semiconductor substrate of the partial thickness are etched along the X-axis direction to form a second bit line trench C2, and the bottom of the second bit line trench C2 is connected to the second bit line trench C2.
  • the bottom of the second etching groove D is even.
  • the etching along the X-axis direction may be wet etching or bias dry lateral etching.
  • etching the well region at the bottom of the active pillar and the semiconductor substrate with the partial thickness may be etching all the wells at the bottom of each active pillar for each active pillar row. region and the corresponding partial thickness of the semiconductor substrate, or the partial well region along the X-axis direction at the bottom of the active pillar and the corresponding partial thickness of the semiconductor substrate may be etched.
  • step S103 is performed to form a buried bit line in the bit line trench.
  • the bit line trench includes a second bit line trench, and forming a buried bit line in the bit line trench includes:
  • a bit line metal material is deposited in the second bit line trench to form the buried bit line.
  • the method before depositing the bit line metal material in the second bit line trench, the method further includes: forming a barrier layer on an inner wall of the second bit line trench.
  • the barrier layer is located between the metal material of the bit line and the semiconductor substrate, the metal material of the bit line and the well region, and the barrier layer is used to prevent the metal material of the bit line from diffusing into the semiconductor substrate or the well region.
  • a barrier layer 205 is formed in the second bit line trench C2, and a bit line metal material is deposited in the second bit line trench with the barrier layer 205 to form a buried bit line 206.
  • the bottoms of two adjacent active pillars in the active pillar group along the first direction are independent from each other.
  • bit line metal material in the second bit line trench when depositing the bit line metal material in the second bit line trench, the bit line metal material will also be partially deposited in the second etching groove D, and the deposition in the second 2.
  • the bit line metal material in the groove D is etched back and only the bit line metal material in the second bit line trench C2 remains as a buried bit line.
  • the method for forming the semiconductor structure further includes: filling a second insulating layer in the second etched groove Material.
  • the second insulating material 204 is filled in the second etching groove D. As shown in FIG. 3 e , the second insulating material 204 is filled in the second etching groove D. As shown in FIG. 3 e , the second insulating material 204 is filled in the second etching groove D. As shown in FIG. 3 e , the second insulating material 204 is filled in the second etching groove D. As shown in FIG. 3 e , the second insulating material 204 is filled in the second etching groove D.
  • the method for forming the semiconductor structure further includes the following steps:
  • etching part of the second insulating material between any two adjacent active pillars exposing active pillars with a first preset height; wherein, the first preset height is smaller than the The initial height of the active column.
  • a portion of the second insulating material 204 between any two adjacent active pillars is etched to expose the active pillar 201a with a first preset height h1, wherein the first preset The height h1 is set to be smaller than the initial height h0 of the active pillar 201a.
  • the height difference between the initial height h0 and the first preset height h1 may be 10nm-50nm.
  • Buried word lines are formed on exposed sidewalls of the active pillars having a first preset height.
  • the process of forming the buried word line on the exposed sidewall of the active pillar with the first predetermined height is the same as the above embodiment, and will not be described in detail here.
  • a gate oxide layer 207 and a word line metal layer 208 are formed on the exposed sidewalls of the active pillars 201a having a first predetermined height, and exposed with a second predetermined height h2. active column.
  • the second preset height h2 is smaller than the first preset height h1.
  • the second preset height includes 10nm-50nm.
  • the word line metal layer is patterned to form the buried word line.
  • the patterning the word line metal layer to form the buried word line includes: etching the word line metal layer along the third direction, and retaining the first The word line metal layer between two adjacent active pillars in the direction forms the buried word line and the fourth etching groove extending along the first direction.
  • the word line metal layer 208 is etched along the Z-axis direction, and the word line metal layer between two adjacent active pillars 201a in the X-axis direction is reserved to form a buried word line 209 and A fourth etching groove E extending in the X-axis direction.
  • the method for forming the semiconductor structure further includes: filling a third insulating material between the fourth etched groove and the exposed active column having a second predetermined height, forming a top insulating layer; wherein the top surface of the top insulating layer is flush with the top surface of the patterned mask layer.
  • a third insulating material is filled between the fourth etched groove E and the exposed active column with a second predetermined height, forming a top insulating layer 210, and the top insulating layer 210 The top surface is flush with the top surface of the patterned mask layer 202 .
  • the method for forming the semiconductor structure further includes: removing the patterned mask layer on the surface of each active pillar to expose the top surface of the active pillar.
  • the patterned mask layer 202 on the surface of the active pillar is removed to expose the top surface of the active pillar 201a, and the top insulating layer 210 is chemically mechanically polished, so that the top surface of the top insulating layer 210 flush with the top surface of the active pillar 201a.
  • the method for forming a semiconductor structure further includes: forming a capacitor structure on a top surface of the active pillar.
  • the capacitive structure may be a columnar capacitor or a cup-shaped capacitor.
  • the method for forming the semiconductor structure provided by the embodiments of the present disclosure is similar to the method for forming the semiconductor structure in the above-mentioned embodiments.
  • the technical features not disclosed in detail in the embodiments of the present disclosure please refer to the above-mentioned embodiments for understanding, and no further details are given here. .
  • the semiconductor structure formed by the method for forming the semiconductor structure provided by the embodiments of the present disclosure corresponds to each transistor having an independent embedded bit line, the structure and preparation process of the bit line are simple, and it can be effectively turned on. In this way, not only The integration degree and electrical performance of the formed semiconductor structure are improved, and the production cost of the semiconductor structure is also reduced.
  • FIGS. 4 a and 4 b are cross-sectional views of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure 40 includes: a substrate and a buried bit line 206 .
  • the base includes a semiconductor substrate 200 and a well region 201 located on the surface of the semiconductor substrate 200;
  • the well region 201 includes a plurality of active columns arranged at intervals along the X-axis direction, and each of the The active pillar column includes a plurality of active pillars 201 a arranged at intervals along the Y-axis direction (not shown in the figure).
  • the buried bit line 206 is located in a bit line trench, and the bit line trench is located at least in the well region at the bottom of each active pillar and in a partial thickness of the semiconductor substrate.
  • the bit line trenches include a first bit line trench or a second bit line trench; every two adjacent active column rows form an active column group;
  • the bottoms of two adjacent active pillars in the active pillar group along the X-axis direction communicate with each other (as shown in FIG. 4 a );
  • the bottoms of the two adjacent active pillars along the X-axis direction in the active pillar group are independent of each other (as shown in FIG. 4b ).
  • the semiconductor structure 40 further includes a device located between the semiconductor substrate and the buried bit line, and located between the well region and the buried bit line.
  • the barrier layer 205 is used to prevent the bit line metal material of the buried bit line from diffusing into the semiconductor substrate or the well region.
  • the semiconductor structure 40 further includes a gate oxide layer 207 on the sidewall of the active pillar and a buried word line 209 , the buried word line 209 forms a fully surrounding gate structure of the semiconductor structure 40 .
  • the semiconductor structure further includes a capacitor structure (not shown) on the surface of the active pillar.
  • the method for forming the semiconductor structure in the embodiment of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments.
  • the technical features not disclosed in detail in the embodiments of the present disclosure please refer to the above-mentioned embodiments for understanding, and details will not be repeated here.
  • the bit line since the bit line is buried inside the semiconductor substrate, the bit line can be effectively turned on and has a strong control capability, thereby improving the electrical performance of the formed semiconductor device; in addition, the embedded bit lines formed in the embodiments of the present disclosure can also improve the integration level of semiconductor devices and increase the application range of semiconductor devices.
  • the disclosed devices and methods may be implemented in non-target ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the various components shown or discussed are coupled with each other, or directly coupled.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • the forming method of the semiconductor structure includes providing a base; the base includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; A plurality of active columns, and each active column includes a plurality of active columns arranged at intervals along the second direction; wherein, the first direction is perpendicular to the second direction; since each active column can be etched by at least The well region at the bottom of the column and the semiconductor substrate with a partial thickness form a plurality of bit line trenches; in this way, buried bit lines can be formed in the bit line trenches, which improves the integration of the formed semiconductor device; in addition,
  • the preparation process of the buried bit line in the embodiment of the present disclosure is simple, and the formed buried bit line can be effectively conducted and has strong control ability.

Abstract

本公开实施例提供一种半导体结构及其形成方法，其中，所述半导体结构的形成方法包括：提供基底；所述基底包括半导体衬底和位于所述半导体衬底表面的阱区；所述阱区包括沿第一方向间隔排布的多个有源柱列，且每一所述有源柱列包括沿第二方向间隔排布的多个有源柱；其中，所述第一方向垂直于所述第二方向；至少刻蚀每一所述有源柱底部的阱区和部分厚度的半导体衬底，形成多个位线沟槽；在所述位线沟槽中，形成埋入式位线。

Description

半导体结构及其形成方法
相关申请的交叉引用
本公开基于申请号为202111074102.4、申请日为2021年09月14日、发明名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构及其形成方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机常用的半导体存储器件，DRAM由许多重复的存储单元组成。每个存储单元包含晶体管和电容器，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连。字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
相关技术中，DRAM存储单元中晶体管的源极或者漏极通常形成在半导体衬底的表面，因此，动态随机存储器的位线也形成于半导体衬底的表面，如此，将不能满足当前对半导体器件高集成度的需求，且位线位于半导体衬底的表面，使得位线的控制能力弱。另外，相关技术中位线的结构和位线的制作工艺复杂，进而增加了半导体器件的生产成本。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其形成方法。
第一方面，本公开实施例提供一种半导体结构的形成方法，所述方法包括：
提供基底；所述基底包括半导体衬底和位于所述半导体衬底表面的阱区；所述阱区包括沿第一方向间隔排布的多个有源柱列，且每一所述有源柱列包括沿第二方向间隔排布的多个有源柱；其中，所述第一方向垂直于所述第二方向；
至少刻蚀每一所述有源柱底部的阱区和部分厚度的半导体衬底，形成 多个位线沟槽；
在所述位线沟槽中，形成埋入式位线。
在一些实施例中，所述位线沟槽包括第一位线沟槽或第二位线沟槽；所述方法还包括：
依次将每相邻的两个有源柱列，确定为一个有源柱组；
其中，位于所述第一位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互连通；
位于所述第二位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互独立。
在一些实施例中，所述在所述位线沟槽中，形成埋入式位线，包括：
在所述第一位线沟槽或所述第二位线沟槽中沉积位线金属材料，形成所述埋入式位线。
在一些实施例中，任意相邻两个有源柱之间填充有第一绝缘材料；所述第一位线沟槽通过以下步骤形成：
沿第三方向，刻蚀每一所述有源柱组中的相邻两个有源柱列之间的第一绝缘材料，形成多个第一刻蚀凹槽；其中，所述第三方向、所述第一方向和所述第二方向两两相互垂直；
以所述第一刻蚀凹槽的底部为刻蚀起点，沿所述第三方向，刻蚀所述第一刻蚀凹槽底部的阱区和所述部分厚度的半导体衬底，并沿所述第一方向，刻蚀所述有源柱底部的阱区和所述部分厚度的半导体衬底，形成所述第一位线沟槽。
在一些实施例中，所述方法还包括：
在所述第一位线沟槽中形成所述埋入式位线之后，在所述第一刻蚀凹槽中填充第二绝缘材料。
在一些实施例中，任意相邻两个有源柱之间填充有第一绝缘材料；所述第二位线沟槽通过以下步骤形成：
沿第三方向，至少刻蚀每一所述有源柱组中的相邻两个有源柱列之间的第一绝缘材料，形成多个第二刻蚀凹槽；其中，所述第三方向、所述第一方向和所述第二方向两两相互垂直；
沿所述第一方向，刻蚀所述有源柱底部的阱区和所述部分厚度的半导体衬底，形成所述第二位线沟槽；其中，所述第二位线沟槽的底部与所述第二刻蚀凹槽的底部平齐。
在一些实施例中，所述方法还包括：
在所述第二位线沟槽中形成所述埋入式位线之后，在所述第二刻蚀凹槽中填充第二绝缘材料。
在一些实施例中，所述方法还包括：
在所述第一位线沟槽或所述第二位线沟槽中沉积所述位线金属材料之前，在所述第一位线沟槽或所述第二位线沟槽的内壁形成阻挡层。
在一些实施例中，所述有源柱通过以下方式形成：
在所述阱区的表面形成图形化的掩膜层；
通过所述图形化的掩膜层，刻蚀部分厚度的所述阱区，形成多个沿所述第一方向和所述第二方向间隔排布的所述有源柱。
在一些实施例中，在形成所述位线沟槽之前，所述方法还包括：
至少刻蚀相邻两个有源柱组之间的第一绝缘材料，形成多个第三刻蚀凹槽；其中，所述第三刻蚀凹槽的底部位于所述半导体衬底的内部；
在所述第三刻蚀凹槽中填充所述第二绝缘材料。
在一些实施例中，所述方法还包括：
沿所述第三方向，刻蚀任意相邻两个有源柱之间部分第二绝缘材料，暴露出具有第一预设高度的有源柱；其中，所述第一预设高度小于所述有源柱的初始高度；
在暴露出的具有第一预设高度的有源柱的侧壁，形成埋入式字线。
在一些实施例中，所述在暴露出的具有第一预设高度的有源柱的侧壁，形成埋入式字线，包括：
在暴露出的具有第一预设高度的有源柱的侧壁形成栅极氧化层；
在具有所述栅极氧化层的任意相邻的两个有源柱之间填充字线金属材料，形成字线金属层；
回刻所述栅极氧化层和所述字线金属层，暴露出具有第二预设高度的有源柱；所述第二预设高度小于所述第一预设高度；
图形化所述字线金属层，形成所述埋入式字线。
在一些实施例中，所述图形化所述字线金属层，形成所述埋入式字线，包括：
沿所述第三方向，刻蚀所述字线金属层，并保留所述第一方向上相邻两个有源柱之间的字线金属层，形成所述埋入式字线和沿所述第一方向延伸的第四刻蚀凹槽。
在一些实施例中，所述方法还包括：
在所述第四刻蚀凹槽和暴露出的具有第二预设高度的有源柱之间填充第三绝缘材料，形成顶部绝缘层；其中，所述顶部绝缘层的顶表面与所述图形化的掩膜层的顶表面平齐。
在一些实施例中，所述方法还包括：
去除每一所述有源柱表面的图形化的掩膜层，暴露出所述有源柱的顶表面；
在所述有源柱的顶表面形成电容结构。
第二方面，本公开实施例提供一种半导体结构，所述半导体结构通过上述半导体结构的形成方法形成；所述半导体结构包括：
基底；所述基底包括半导体衬底和位于所述半导体衬底表面的阱区；所述阱区包括沿第一方向间隔排布的多个有源柱列，且每一所述有源柱列 包括沿第二方向间隔排布的多个有源柱；其中，所述第一方向垂直于所述第二方向；
埋入式位线；所述埋入式位线位于位线沟槽中，且所述位线沟槽至少位于每一所述有源柱的底部的阱区和部分厚度的半导体衬底中。
在一些实施例中，所述位线沟槽包括第一位线沟槽或第二位线沟槽；每相邻的两个有源柱列为一个有源柱组；
其中，位于所述第一位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互连通；
位于所述第二位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互独立。
本公开实施例提供的半导体结构及其形成方法，其中，半导体结构的形成方法包括提供基底；基底包括半导体衬底和位于半导体衬底表面的阱区；阱区包括沿第一方向间隔排布的多个有源柱列，且每一有源柱列包括沿第二方向间隔排布的多个有源柱；其中，第一方向垂直于第二方向；由于可以通过至少刻蚀每一有源柱底部的阱区和部分厚度的半导体衬底，形成多个位线沟槽；如此，可以在位线沟槽中，形成埋入式位线，提高了形成的半导体器件的集成度；另外，本公开实施例中埋入式位线的制备工艺简单，且所形成的埋入式位线能够有效导通，具有较强的控制能力。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本公开实施例提供的半导体结构的形成方法的流程示意图；
图2a～2p为本公开实施例提供的半导体结构形成过程的一种结构示意图；
图3a～3k为本公开实施例提供的半导体结构形成过程的另一种结构示意图；
图4a和4b为本公开实施例提供的半导体结构的剖视图；
附图标记说明：
200-半导体衬底；201-阱区；202-图形化的掩膜层；201a-有源柱；203-第一绝缘材料；204-第二绝缘材料；205-阻挡层；206-埋入式位线；207-栅极氧化层；208-字线金属层；209-埋入式字线；210-顶部绝缘层；A-第三刻蚀凹槽；B-第一刻蚀凹槽；C1-第一位线沟槽；C2-第二位线沟槽；D-第二刻蚀凹槽；E-第四刻蚀凹槽。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
基于相关技术中存在的问题，本公开实施例提供一种半导体结构及其形成方法，其中，半导体结构的形成方法包括：提供基底；基底包括半导体衬底和位于半导体衬底表面的阱区；阱区包括沿第一方向间隔排布的多个有源柱列，且每一有源柱列包括沿第二方向间隔排布的多个有源柱；其中，第一方向垂直于第二方向；由于可以通过至少刻蚀每一有源柱底部 的阱区和部分厚度的半导体衬底，形成多个位线沟槽；如此，可以在位线沟槽中，形成埋入式位线，提高了形成的半导体器件的集成度；另外，本公开实施例中埋入式位线的制备工艺简单，且所形成的埋入式位线能够有效导通，具有较强的控制能力。
本公开实施例提供一种半导体结构的形成方法，如图1所示，所述半导体结构的形成方法包括以下步骤：
步骤S101、提供基底；所述基底包括半导体衬底和位于所述半导体衬底表面的阱区；所述阱区包括沿第一方向间隔排布的多个有源柱列，且每一所述有源柱列包括沿第二方向间隔排布的多个有源柱；其中，所述第一方向垂直于所述第二方向。
本公开实施例中，所述基底可以是对所述半导体衬底进行部分掺杂后形成的结构。所述半导体衬底可以是硅衬底，所述半导体衬底也可以包括其他半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其他半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、及/或磷砷化铟镓(GaInAsP)或其组合。所述阱区可以是N阱(Nwelll)，也可以是P阱(Pwelll)。
所述半导体衬底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面；在忽略顶表面和底表面的平整度的情况下，定义垂直半导体衬底顶表面和底表面的方向为第三方向。在半导体衬底顶表面和底表面(即半导体衬底所在的平面)方向上，定义两彼此相交(例如彼此垂直)的第一方向和第二方向，例如，可以定义多个有源柱列的排列方向为第一方向，基于所述第一方向和所述第二方向可以确定所述半导体衬底的平面方向。这里，所述第一方向、所述第二方向和所述第三方向两两垂直。本公开实施例中，定义所述第一方向为X轴方向，定义所述第二方向为Y轴方向，定义所述第三方向为Z轴方向。
步骤S102、至少刻蚀每一所述有源柱底部的阱区和部分厚度的半导体衬底，形成多个位线沟槽。
本公开实施例中，每一所述有源柱的底部保留有部分阱区，所述位线沟槽位于每一所述有源柱的底部。
步骤S103、在所述位线沟槽中，形成埋入式位线。
图2a～2p为本公开实施例提供的半导体结构形成过程的一种结构示意图，接下来请参考图2a～2p对本公开实施例提供的半导体结构的形成方法进一步地详细说明。
首先，可以参考图2a和2b，执行步骤S101、提供基底；所述基底包括半导体衬底和位于所述半导体衬底表面的阱区；所述阱区包括沿第一方向间隔排布的多个有源柱列，且每一所述有源柱列包括沿第二方向间隔排 布的多个有源柱；其中，所述第一方向垂直于所述第二方向。
如图2a所示，基底包括半导体衬底200和位于半导体衬底200表面的阱区201。本公开实施例中，所述半导体衬底可以是P型衬底，所述阱区可以是N阱。在其它实施例中，所述半导体衬底也可以是N型衬底，所述阱区也可以是P阱。
在一些实施例中，位于所述阱区中的有源柱可以通过以下步骤形成：
在所述阱区的表面形成图形化的掩膜层。
通过所述图形化的掩膜层，刻蚀部分厚度的所述阱区，形成多个沿所述第一方向和所述第二方向间隔排布的所述有源柱。
如图2b所示，在阱区201的表面形成图形化的掩膜层202，沿Z轴方向，通过图形化的掩膜层202刻蚀阱区201，形成了沿X轴方向和Y轴方向间隔排布的有源柱201a。其中，沿Y轴方向间隔排布的多个有源柱构成一个有源柱列，多个有源柱列沿X轴方向间隔排布。
在一些实施例中，在形成所述有源柱之后，所述半导体结构的形成方法还包括：
步骤S20、在任意相邻两个有源柱之间填充第一绝缘材料。
所述第一绝缘材料可以是任意一种绝缘材料，例如，氧化硅、氮化硅或者氮氧化硅。
如图2c所示，在任意相邻的有源柱201a之间填充第一绝缘材料203，其中，第一绝缘材料203的顶表面与所述图形化的掩膜层202的顶表面平齐。
步骤S21、依次将每相邻的两个有源柱列，确定为一个有源柱组。
步骤S22、至少刻蚀相邻两个有源柱组之间的第一绝缘材料，形成多个第三刻蚀凹槽；其中，所述第三刻蚀凹槽的底部位于所述半导体衬底的内部。
如图2d所示，沿Z轴方向，刻蚀相邻两个有源柱组之间的第一绝缘材料203、以及位于相邻两个有源柱组之间的第一绝缘材料203底部的阱区和部分厚度的半导体衬底，形成第三刻蚀凹槽A，第三刻蚀凹槽A的底部位于半导体衬底200的内部。
本公开实施例中，可以采用干法刻蚀工艺刻蚀第一绝缘材料、阱区和部分半导体衬底，形成所述第三刻蚀凹槽，例如，等离子刻蚀工艺，反应离子刻蚀工艺或者离子铣工艺。
步骤S23、在所述第三刻蚀凹槽中填充第二绝缘材料。
所述第二绝缘材料也可以是任意一种绝缘材料，例如，氧化硅、氮化硅或者氮氧化硅。所述第二绝缘材料与所述第一绝缘材料可以相同，也可以不同。本公开实施例中，所述第二绝缘材料与所述第一绝缘材料相同。
如图2e所示，在第三刻蚀凹槽A中填充第二绝缘材料204。
接下来，可以参考图2f和2g，执行步骤S102、至少刻蚀每一所述有源 柱底部的阱区和部分厚度的半导体衬底，形成多个位线沟槽。
本公开实施例中，所述位线沟槽包括第一位线沟槽；所述第一位线沟槽可以通过以下步骤形成：
沿第三方向，刻蚀每一所述有源柱组中的相邻两个有源柱列之间的第一绝缘材料，形成多个第一刻蚀凹槽；其中，所述第三方向、所述第一方向和所述第二方向两两相互垂直。
如图2f所示，沿Z轴方向，刻蚀每一有源柱组中相邻两个有源柱列之间的第一绝缘材料203，形成多个第一刻蚀凹槽B，所述第一刻蚀凹槽B暴露出阱区201。
以所述第一刻蚀凹槽的底部为刻蚀起点，沿所述第三方向，刻蚀所述第一刻蚀凹槽底部的阱区和所述部分厚度的半导体衬底，并沿所述第一方向，刻蚀所述有源柱底部的阱区和所述部分厚度的半导体衬底，形成所述第一位线沟槽。
本公开实施例中，刻蚀所述有源柱底部的阱区和所述部分厚度的半导体衬底，对于每一有源柱列而言，可以是刻蚀每一有源柱底部的全部阱区和对应的部分厚度的半导体衬底，也可以是刻蚀有源柱底部的沿X轴方向的部分阱区和对应的部分厚度的半导体衬底。
如图2g所示，以第一刻蚀凹槽B的底部为刻蚀起点，沿Z轴方向刻蚀第一刻蚀凹槽B底部的阱区和所述部分厚度的半导体衬底，并沿X轴方向刻蚀所述有源柱201a底部的阱区和所述部分厚度的半导体衬底，形成了第一位线沟槽C1。
本公开实施例中，在形成第一位线沟槽C1时，沿X轴方向的刻蚀可以是湿法刻蚀或者偏压干法侧向刻蚀。
在一些实施例中，在刻蚀形成第一位线沟槽之前，所述半导体结构的形成方法还可以包括：在每一有源柱组中，沿第一方向相邻的两个有源柱的侧壁形成保护层。所述保护层用于在刻蚀形成第一位线沟槽时，保护有源柱不产生损伤；且在形成第一位线沟槽之后，需要去除所述保护层。
接下来，可以参考图2h和2i，执行步骤S103、在所述位线沟槽中，形成埋入式位线。
本公开实施例中，所述位线沟槽包括第一位线沟槽，所述在所述位线沟槽中，形成埋入式位线，包括：
在所述第一位线沟槽沉积位线金属材料，形成所述埋入式位线。
所述位线金属材料包括钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。
在一些实施例中，在所述第一位线沟槽中沉积所述位线金属材料之前，所述方法还包括：在所述第一位线沟槽的内壁形成阻挡层。
所述阻挡层位于位线金属材料与半导体衬底、位线金属材料与阱区之间，阻挡层用于防止位线金属材料向半导体衬底或阱区中扩散。
本公开实施例中，可以通过任意一种合适的沉积工艺形成阻挡层，例如，化学气相沉积(Chemical Vapor Deposition，CVD)工艺、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工艺或者涂敷工艺。所述阻挡层可以是氮化硅层。
如图2h和2i所示，在第一位线沟槽C1中形成了阻挡层205，并且在具有阻挡层205的第一位线沟槽中沉积位线金属材料，形成埋入式位线206。
本公开实施例中，位于所述第一位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互连通。
需要说明的是，本公开实施例中，在第一位线沟槽中沉积位线金属材料时，位线金属材料也会沉积在第一刻蚀凹槽B中，后续需要对沉积在第一刻蚀凹槽B中的位线金属材料进行回刻处理，仅保留位于第一位线沟槽C1中的位线金属材料，作为埋入式位线。
值得注意的是，步骤S21至步骤S23与埋入式位线的形成过程没有严格的顺序关系，步骤S21至步骤S23也可以在形成所述埋入式位线之后执行。
在一些实施例中，在所述第一位线沟槽中形成所述埋入式位线之后，所述半导体结构的形成方法还包括：在所述第一刻蚀凹槽中填充第二绝缘材料。
如图2j所示，在第一刻蚀凹槽B中填充第二绝缘材料204。
在一些实施例中，在所述第一刻蚀凹槽中填充第二绝缘材料之后，所述半导体结构的形成方法还包括以下步骤：
沿所述第三方向，刻蚀任意相邻两个有源柱之间部分第二绝缘材料，暴露出具有第一预设高度的有源柱；其中，所述第一预设高度小于所述有源柱的初始高度。
如图2k所示，沿Z轴方向，刻蚀任意相邻两个有源柱之间部分第二绝缘材料204，暴露出具有第一预设高度h1的有源柱201a，其中，第一预设高度h1小于有源柱201a的初始高度h0。本公开实施例中，所述初始高度h0与所述第一预设高度h1之间的高度差可以是10nm-50nm。
在暴露出的具有第一预设高度的有源柱的侧壁，形成埋入式字线。
在一些实施例中，所述在暴露出的具有第一预设高度的有源柱的侧壁，形成埋入式字线，包括以下步骤：
在暴露出的具有第一预设高度的有源柱的侧壁形成栅极氧化层。
在具有所述栅极氧化层的任意相邻的两个有源柱之间填充字线金属材料，形成字线金属层。
本公开实施例中，所述字线金属材料可以为氮化钛、钨或其组合。
回刻所述栅极氧化层和所述字线金属层，暴露出具有第二预设高度的有源柱；所述第二预设高度小于所述第一预设高度。
如图2l和2m所示，在暴露出的具有第一预设高度的有源柱201a的侧壁形成栅极氧化层207和字线金属层208，并暴露出具有第二预设高度h2的有源柱。第二预设高度h2小于所述第一预设高度h1。本公开实施例中，所述第二预设高度包括10nm-50nm。
需要说明的是，本公开实施例中，对栅极氧化层和字线金属层进行回刻的过程可以分两步进行，也可以同时进行。
图形化所述字线金属层，形成所述埋入式字线。
在一些实施例中，所述图形化所述字线金属层，形成所述埋入式字线，包括：沿所述第三方向，刻蚀所述字线金属层，并保留所述第一方向上相邻两个有源柱之间的字线金属层，形成所述埋入式字线和沿所述第一方向延伸的第四刻蚀凹槽。
如图2n所示，沿Z轴方向，刻蚀字线金属层208，并保留X轴方向上相邻两个有源柱201a之间的字线金属层，形成埋入式字线209和沿X轴方向延伸的第四刻蚀凹槽E。
在一些实施例中，所述半导体结构的形成方法还包括：在所述第四刻蚀凹槽和暴露出的具有第二预设高度的有源柱之间填充第三绝缘材料，形成顶部绝缘层；其中，所述顶部绝缘层的顶表面与所述图形化的掩膜层的顶表面平齐。
所述第三绝缘材料也可以是任意一种绝缘材料，例如，氧化硅、氮化硅或者氮氧化硅。所述第三绝缘材料与所述第二绝缘材料可以相同，也可以不同。本公开实施例中，所述第三绝缘材料、所述第二绝缘材料与所述第一绝缘材料均相同。
如图2o所示，在所述第四刻蚀凹槽E和暴露出的具有第二预设高度的有源柱之间填充第三绝缘材料，形成了顶部绝缘层210，顶部绝缘层210的顶表面与图形化的掩膜层202的顶表面平齐。
在一些实施例中，所述半导体结构的形成方法还包括：去除每一所述有源柱表面的图形化的掩膜层，暴露出所述有源柱的顶表面。
如图2p所示，去除了有源柱表面的图形化的掩膜层202，暴露出有源柱201a的顶表面，并对顶部绝缘层210进行化学机械抛光(Chemical Mechanical Polishing，CMP)处理，使得顶部绝缘层210的顶表面与有源柱201a的顶表面平齐。
在一些实施例中，所述半导体结构的形成方法还包括：在所述有源柱的顶表面形成电容结构。所述电容结构可以是柱状电容器或者杯状的电容器。
本公开实施例提供的半导体结构的形成方法所形成的半导体结构，位线埋入半导体衬底内部，且晶体管的源极和漏极分别位于有源柱的竖直两端，源极与半导体结构的埋入式位线连接，漏极与形成的电容结构连接，且本公开实施例中的埋入式字线为环栅结构，字线上的电压信号能够控制 晶体管的打开或关闭，进而通过位线读取存储在电容结构中的数据信息，或者通过位线将数据信息写入到电容结构中进行存储。
本公开实施例提供的半导体结构的形成方法所形成的半导体结构，相邻的晶体管共用一条埋入式位线，位线的结构和制备工艺简单，且能够有效导通，如此，不仅提高了所形成的半导体结构的集成度和电性能，还降低了半导体结构的生产成本。
图3a～3k为本公开实施例提供的半导体结构形成过程的另一种结构示意图，接下来请参考图3a～3k对本公开实施例提供的半导体结构的形成方法进一步地详细说明。
首先，执行步骤S101、提供基底；所述基底包括半导体衬底和位于所述半导体衬底表面的阱区；所述阱区包括沿第一方向间隔排布的多个有源柱列，且每一所述有源柱列包括沿第二方向间隔排布的多个有源柱；其中，所述第一方向垂直于所述第二方向。
步骤S101的实现过程与上述实施例中步骤S101的实现过程相同，这里不再赘述。
在一些实施例中，在形成所述有源柱之后，所述半导体结构的形成方法还包括：
在任意相邻两个有源柱之间填充第一绝缘材料。
依次将每相邻的两个有源柱列，确定为一个有源柱组。
至少刻蚀相邻两个有源柱组之间的第一绝缘材料，形成多个第三刻蚀凹槽；其中，所述第三刻蚀凹槽的底部位于所述半导体衬底的内部。
在所述第三刻蚀凹槽中填充第二绝缘材料。
接下来，可以参考图3a和3b，执行步骤S102、至少刻蚀每一所述有源柱底部的阱区和部分厚度的半导体衬底，形成多个位线沟槽。
本公开实施例中，所述位线沟槽包括第二位线沟槽；所述第二位线沟槽可以通过以下步骤形成：
沿第三方向，至少刻蚀每一所述有源柱组中的相邻两个有源柱列之间的第一绝缘材料，形成多个第二刻蚀凹槽；其中，所述第三方向、所述第一方向和所述第二方向两两相互垂直。
如图3a所示，沿Z轴方向，刻蚀每一有源柱组中相邻两个有源柱列之间的第一绝缘材料203、以及位于相邻两个有源柱列之间的第一绝缘材料203底部的阱区和部分厚度的半导体衬底，形成多个第二刻蚀凹槽D，所述第二刻蚀凹槽D暴露出半导体衬底200。
本公开实施例中，可以采用干法刻蚀工艺刻蚀第一绝缘材料、阱区和部分半导体衬底，形成所述第二刻蚀凹槽，例如，等离子刻蚀工艺，反应离子刻蚀工艺或者离子铣工艺。
沿所述第一方向，刻蚀所述有源柱底部的阱区和所述部分厚度的半导体衬底，形成所述第二位线沟槽；其中，所述第二位线沟槽的底部与所述 第二刻蚀凹槽的底部平齐。
如图3b所示，沿X轴方向刻蚀有源柱底部的阱区和所述部分厚度的半导体衬底，形成了第二位线沟槽C2，第二位线沟槽C2的底部与第二刻蚀凹槽D的底部平齐。本公开实施例中，在形成第二位线沟槽C2时，沿X轴方向的刻蚀可以是湿法刻蚀或者偏压干法侧向刻蚀。
本公开实施例中，刻蚀所述有源柱底部的阱区和所述部分厚度的半导体衬底，对于每一有源柱列而言，可以是刻蚀每一有源柱底部的全部阱区和对应的部分厚度的半导体衬底，也可以是刻蚀有源柱底部的沿X轴方向的部分阱区和对应的部分厚度的半导体衬底。
接下来，可以参考图3c和3d，执行步骤S103、在所述位线沟槽中，形成埋入式位线。
本公开实施例中，所述位线沟槽包括第二位线沟槽，所述在所述位线沟槽中，形成埋入式位线，包括：
在所述第二位线沟槽沉积位线金属材料，形成所述埋入式位线。
在一些实施例中，在所述第二位线沟槽中沉积所述位线金属材料之前，所述方法还包括：在所述第二位线沟槽的内壁形成阻挡层。
所述阻挡层位于位线金属材料与半导体衬底、位线金属材料与阱区之间，阻挡层用于防止位线金属材料向半导体衬底或阱区中扩散。
如图3c和3d所示，在第二位线沟槽C2中形成了阻挡层205，并且在具有阻挡层205的第二位线沟槽中沉积位线金属材料，形成埋入式位线206。
本公开实施例中，位于所述第二位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互独立。
需要说明的是，本公开实施例中，在第二位线沟槽中沉积位线金属材料时，位线金属材料也会部分沉积在第二刻蚀凹槽D中，后续需要对沉积在第二刻蚀凹槽D中的位线金属材料进行回刻处理，仅保留位于第二位线沟槽C2中的位线金属材料，作为埋入式位线。
在一些实施例中，在所述第二位线沟槽中形成所述埋入式位线之后，所述半导体结构的形成方法还包括：在所述第二刻蚀凹槽中填充第二绝缘材料。
如图3e所示，在第二刻蚀凹槽D中填充第二绝缘材料204。
在一些实施例中，在所述第二刻蚀凹槽中填充第二绝缘材料之后，所述半导体结构的形成方法还包括以下步骤：
沿所述第三方向，刻蚀任意相邻两个有源柱之间部分第二绝缘材料，暴露出具有第一预设高度的有源柱；其中，所述第一预设高度小于所述有源柱的初始高度。
如图3f所示，沿Z轴方向，刻蚀任意相邻两个有源柱之间部分第二绝缘材料204，暴露出具有第一预设高度h1的有源柱201a，其中，第一预设高度h1小于有源柱201a的初始高度h0。本公开实施例中，所述初始高度 h0与所述第一预设高度h1之间的高度差可以是10nm-50nm。
在暴露出的具有第一预设高度的有源柱的侧壁，形成埋入式字线。
本公开实施例中，在暴露出的具有第一预设高度的有源柱的侧壁，形成埋入式字线的过程与上述实施例相同，这里不再详细描述。
如图3g和3h所示，在暴露出的具有第一预设高度的有源柱201a的侧壁形成栅极氧化层207和字线金属层208，并暴露出具有第二预设高度h2的有源柱。第二预设高度h2小于所述第一预设高度h1。本公开实施例中，所述第二预设高度包括10nm-50nm。
图形化所述字线金属层，形成所述埋入式字线。
在一些实施例中，所述图形化所述字线金属层，形成所述埋入式字线，包括：沿所述第三方向，刻蚀所述字线金属层，并保留所述第一方向上相邻两个有源柱之间的字线金属层，形成所述埋入式字线和沿所述第一方向延伸的第四刻蚀凹槽。
如图3i所示，沿Z轴方向，刻蚀字线金属层208，并保留X轴方向上相邻两个有源柱201a之间的字线金属层，形成埋入式字线209和沿X轴方向延伸的第四刻蚀凹槽E。
在一些实施例中，所述半导体结构的形成方法还包括：在所述第四刻蚀凹槽和暴露出的具有第二预设高度的有源柱之间填充第三绝缘材料，形成顶部绝缘层；其中，所述顶部绝缘层的顶表面与所述图形化的掩膜层的顶表面平齐。
如图3j所示，在所述第四刻蚀凹槽E和暴露出的具有第二预设高度的有源柱之间填充第三绝缘材料，形成了顶部绝缘层210，顶部绝缘层210的顶表面与图形化的掩膜层202的顶表面平齐。
在一些实施例中，所述半导体结构的形成方法还包括：去除每一所述有源柱表面的图形化的掩膜层，暴露出所述有源柱的顶表面。
如图3k所示，去除有源柱表面的图形化的掩膜层202，暴露出有源柱201a的顶表面，并对顶部绝缘层210进行化学机械抛光处理，使得顶部绝缘层210的顶表面与有源柱201a的顶表面平齐。
在一些实施例中，所述半导体结构的形成方法还包括：在所述有源柱的顶表面形成电容结构。所述电容结构可以是柱状电容器或者杯状的电容器。
本公开实施例提供的半导体结构的形成方法，与上述实施例中的半导体结构的形成方法类似，对于本公开实施例未详尽披露的技术特征，请参考上述实施例进行理解，这里，不再赘述。
本公开实施例提供的半导体结构的形成方法所形成的半导体结构，对应于每一晶体管均具有独立的埋入式位线，位线的结构和制备工艺简单，且能够有效导通，如此，不仅提高了所形成的半导体结构的集成度和电性能，还降低了半导体结构的生产成本。
除此之外，本公开实施例还提供一种半导体结构，所述半导体结构通过上述实施例提供的半导体结构的形成方法形成。图4a和4b为本公开实施例提供的半导体结构的剖视图，如图4a和4b所示，所述半导体结构40包括：基底和埋入式位线206。
其中，所述基底包括半导体衬底200和位于所述半导体衬底200表面的阱区201；所述阱区201包括沿X轴方向间隔排布的多个有源柱列，且每一所述有源柱列包括沿Y轴方向(图中未示出)间隔排布的多个有源柱201a。
所述埋入式位线206位于位线沟槽中，且所述位线沟槽至少位于每一所述有源柱的底部的阱区和部分厚度的半导体衬底中。
本公开实施例中，所述位线沟槽包括第一位线沟槽或第二位线沟槽；每相邻的两个有源柱列为一个有源柱组；其中，位于所述第一位线沟槽中的埋入式位线，在所述有源柱组中沿X轴方向相邻的两个有源柱的底部相互连通(如图4a所示)；位于所述第二位线沟槽中的埋入式位线，在所述有源柱组中沿X轴方向相邻的两个有源柱的底部相互独立(如图4b所示)。
在一些实施例中，请继续参见图4a和4b，所述半导体结构40还包括位于所述半导体衬底与所述埋入式位线、且位于所述阱区与所述埋入式位线之间的阻挡层205，阻挡层205用于防止埋入式位线的位线金属材料向半导体衬底或阱区中扩散。
在一些实施例中，请继续参见图4a和4b，所述半导体结构40还包括位于所述有源柱侧壁的栅极氧化层207和埋入式字线209，所述埋入式字线209形成所述半导体结构40的全环绕栅极结构。
在一些实施例中，所述半导体结构还包括位于所述有源柱表面的电容结构(图中未示出)。
本公开实施例中的半导体结构与上述实施例中的半导体结构的形成方法类似，对于本公开实施例未详尽披露的技术特征，请参考上述实施例进行理解，这里，不再赘述。
本公开实施例提供的半导体结构，由于位线埋入半导体衬底的内部，如此，位线能够有效导通，具有较强的控制能力，进而提高了所述形成半导体器件的电性能；另外，本公开实施例中形成的埋入式位线还可以提高半导体器件的集成度，增加了半导体器件的应用范围。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的， 作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本公开所提供的几个方法或结构实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或结构实施例。
以上所述，仅为本公开实施例的一些实施方式，但本公开实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开实施例的保护范围之内。因此，本公开实施例的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供的半导体结构及其形成方法，其中，半导体结构的形成方法包括提供基底；基底包括半导体衬底和位于半导体衬底表面的阱区；阱区包括沿第一方向间隔排布的多个有源柱列，且每一有源柱列包括沿第二方向间隔排布的多个有源柱；其中，第一方向垂直于第二方向；由于可以通过至少刻蚀每一有源柱底部的阱区和部分厚度的半导体衬底，形成多个位线沟槽；如此，可以在位线沟槽中，形成埋入式位线，提高了形成的半导体器件的集成度；另外，本公开实施例中埋入式位线的制备工艺简单，且所形成的埋入式位线能够有效导通，具有较强的控制能力。

Claims (17)

  1. 一种半导体结构的形成方法，所述方法包括：
    提供基底；所述基底包括半导体衬底和位于所述半导体衬底表面的阱区；所述阱区包括沿第一方向间隔排布的多个有源柱列，且每一所述有源柱列包括沿第二方向间隔排布的多个有源柱；其中，所述第一方向垂直于所述第二方向；
    至少刻蚀每一所述有源柱底部的阱区和部分厚度的半导体衬底，形成多个位线沟槽；
    在所述位线沟槽中，形成埋入式位线。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，所述位线沟槽包括第一位线沟槽或第二位线沟槽；所述方法还包括：
    依次将每相邻的两个有源柱列，确定为一个有源柱组；
    其中，位于所述第一位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互连通；
    位于所述第二位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互独立。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述在所述位线沟槽中，形成埋入式位线，包括：
    在所述第一位线沟槽或所述第二位线沟槽中沉积位线金属材料，形成所述埋入式位线。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，任意相邻两个有源柱之间填充有第一绝缘材料；所述第一位线沟槽通过以下步骤形成：
    沿第三方向，刻蚀每一所述有源柱组中的相邻两个有源柱列之间的第一绝缘材料，形成多个第一刻蚀凹槽；其中，所述第三方向、所述第一方向和所述第二方向两两相互垂直；
    以所述第一刻蚀凹槽的底部为刻蚀起点，沿所述第三方向，刻蚀所述第一刻蚀凹槽底部的阱区和所述部分厚度的半导体衬底，并沿所述第一方向，刻蚀所述有源柱底部的阱区和所述部分厚度的半导体衬底，形成所述第一位线沟槽。
  5. 根据权利要求4所述的半导体结构的形成方法，其中，所述方法还包括：
    在所述第一位线沟槽中形成所述埋入式位线之后，在所述第一刻蚀凹槽中填充第二绝缘材料。
  6. 根据权利要求3所述的半导体结构的形成方法，其中，任意相邻两个有源柱之间填充有第一绝缘材料；所述第二位线沟槽通过以下步骤形成：
    沿第三方向，至少刻蚀每一所述有源柱组中的相邻两个有源柱列之间 的第一绝缘材料，形成多个第二刻蚀凹槽；其中，所述第三方向、所述第一方向和所述第二方向两两相互垂直；
    沿所述第一方向，刻蚀所述有源柱底部的阱区和所述部分厚度的半导体衬底，形成所述第二位线沟槽；其中，所述第二位线沟槽的底部与所述第二刻蚀凹槽的底部平齐。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，所述方法还包括：
    在所述第二位线沟槽中形成所述埋入式位线之后，在所述第二刻蚀凹槽中填充第二绝缘材料。
  8. 根据权利要求5或7所述的半导体结构的形成方法，其中，所述方法还包括：
    在所述第一位线沟槽或所述第二位线沟槽中沉积所述位线金属材料之前，在所述第一位线沟槽或所述第二位线沟槽的内壁形成阻挡层。
  9. 根据权利要求8所述的方法，其中，所述有源柱通过以下方式形成：
    在所述阱区的表面形成图形化的掩膜层；
    通过所述图形化的掩膜层，刻蚀部分厚度的所述阱区，形成多个沿所述第一方向和所述第二方向间隔排布的所述有源柱。
  10. 根据权利要求9所述的方法，其中，在形成所述位线沟槽之前，所述方法还包括：
    至少刻蚀相邻两个有源柱组之间的第一绝缘材料，形成多个第三刻蚀凹槽；其中，所述第三刻蚀凹槽的底部位于所述半导体衬底的内部；
    在所述第三刻蚀凹槽中填充所述第二绝缘材料。
  11. 根据权利要求10所述的方法，其中，所述方法还包括：
    沿所述第三方向，刻蚀任意相邻两个有源柱之间部分第二绝缘材料，暴露出具有第一预设高度的有源柱；其中，所述第一预设高度小于所述有源柱的初始高度；
    在暴露出的具有第一预设高度的有源柱的侧壁，形成埋入式字线。
  12. 根据权利要求11所述的方法，其中，所述在暴露出的具有第一预设高度的有源柱的侧壁，形成埋入式字线，包括：
    在暴露出的具有第一预设高度的有源柱的侧壁形成栅极氧化层；
    在具有所述栅极氧化层的任意相邻的两个有源柱之间填充字线金属材料，形成字线金属层；
    回刻所述栅极氧化层和所述字线金属层，暴露出具有第二预设高度的有源柱；所述第二预设高度小于所述第一预设高度；
    图形化所述字线金属层，形成所述埋入式字线。
  13. 根据权利要求12所述的方法，其中，所述图形化所述字线金属层，形成所述埋入式字线，包括：
    沿所述第三方向，刻蚀所述字线金属层，并保留所述第一方向上相邻 两个有源柱之间的字线金属层，形成所述埋入式字线和沿所述第一方向延伸的第四刻蚀凹槽。
  14. 根据权利要求13所述的方法，其中，所述方法还包括：
    在所述第四刻蚀凹槽和暴露出的具有第二预设高度的有源柱之间填充第三绝缘材料，形成顶部绝缘层；其中，所述顶部绝缘层的顶表面与所述图形化的掩膜层的顶表面平齐。
  15. 根据权利要求14所述的方法，其中，所述方法还包括：
    去除每一所述有源柱表面的图形化的掩膜层，暴露出所述有源柱的顶表面；
    在所述有源柱的顶表面形成电容结构。
  16. 一种半导体结构，所述半导体结构通过上述权利要求1至15任一项所述的半导体结构的形成方法形成；所述半导体结构包括：
    基底；所述基底包括半导体衬底和位于所述半导体衬底表面的阱区；所述阱区包括沿第一方向间隔排布的多个有源柱列，且每一所述有源柱列包括沿第二方向间隔排布的多个有源柱；其中，所述第一方向垂直于所述第二方向；
    埋入式位线；所述埋入式位线位于位线沟槽中，且所述位线沟槽至少位于每一所述有源柱的底部的阱区和部分厚度的半导体衬底中。
  17. 根据权利要求16所述的半导体结构，其中，所述位线沟槽包括第一位线沟槽或第二位线沟槽；每相邻的两个有源柱列为一个有源柱组；
    其中，位于所述第一位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互连通；
    位于所述第二位线沟槽中的埋入式位线，在所述有源柱组中沿所述第一方向相邻的两个有源柱的底部相互独立。
PCT/CN2022/072418 2021-09-14 2022-01-17 半导体结构及其形成方法 WO2023040157A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/867,432 US20230089265A1 (en) 2021-09-14 2022-07-18 Semiconductor structure and forming method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111074102.4 2021-09-14
CN202111074102.4A CN116133394A (zh) 2021-09-14 2021-09-14 半导体结构及其形成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/867,432 Continuation US20230089265A1 (en) 2021-09-14 2022-07-18 Semiconductor structure and forming method thereof

Publications (1)

Publication Number Publication Date
WO2023040157A1 true WO2023040157A1 (zh) 2023-03-23

Family

ID=85602376

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/072418 WO2023040157A1 (zh) 2021-09-14 2022-01-17 半导体结构及其形成方法

Country Status (2)

Country Link
CN (1) CN116133394A (zh)
WO (1) WO2023040157A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1344029A (zh) * 2000-09-08 2002-04-10 株式会社东芝 半导体存储器及其制造方法
CN101673744A (zh) * 2008-09-12 2010-03-17 南亚科技股份有限公司 晶体管结构、动态随机存取存储器结构及其制造方法
CN101944508A (zh) * 2009-07-03 2011-01-12 海力士半导体有限公司 具有垂直晶体管的半导体器件的制造方法
US20120299088A1 (en) * 2011-05-27 2012-11-29 Micron Technology, Inc. Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions
CN103681510A (zh) * 2012-08-28 2014-03-26 爱思开海力士有限公司 具有掩埋位线的半导体器件及其制造方法
CN110957319A (zh) * 2018-09-27 2020-04-03 长鑫存储技术有限公司 集成电路存储器及其形成方法、半导体集成电路器件
CN111211170A (zh) * 2018-11-21 2020-05-29 长鑫存储技术有限公司 半导体器件及其制备方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1344029A (zh) * 2000-09-08 2002-04-10 株式会社东芝 半导体存储器及其制造方法
CN101673744A (zh) * 2008-09-12 2010-03-17 南亚科技股份有限公司 晶体管结构、动态随机存取存储器结构及其制造方法
CN101944508A (zh) * 2009-07-03 2011-01-12 海力士半导体有限公司 具有垂直晶体管的半导体器件的制造方法
US20120299088A1 (en) * 2011-05-27 2012-11-29 Micron Technology, Inc. Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions
CN103681510A (zh) * 2012-08-28 2014-03-26 爱思开海力士有限公司 具有掩埋位线的半导体器件及其制造方法
CN110957319A (zh) * 2018-09-27 2020-04-03 长鑫存储技术有限公司 集成电路存储器及其形成方法、半导体集成电路器件
CN111211170A (zh) * 2018-11-21 2020-05-29 长鑫存储技术有限公司 半导体器件及其制备方法

Also Published As

Publication number Publication date
CN116133394A (zh) 2023-05-16

Similar Documents

Publication Publication Date Title
CN110071108B (zh) 半导体存储器元件及其制作方法
TWI471981B (zh) 製作具有埋入式位元線與埋入式字元線的記憶體裝置之方法
CN101297392B (zh) 经硅化物化的内嵌硅
US9947666B2 (en) Semiconductor device structures including buried digit lines and related methods
JP2013058676A (ja) 半導体装置及びその製造方法、並びにデータ処理システム
US10424586B2 (en) Memory device including a trench isolation structure between buried word lines and manufacturing method thereof
CN111223863B (zh) 动态随机存取存储器结构
JP2022027622A (ja) 三次元メモリデバイス及びその方法
EP2237315A2 (en) Memory arrays, semiconductor constructions and electronic systems; and method of forming memory arrays, semiconductor constructions and electronic systems
US20110263089A1 (en) Method for fabricating semiconductor device
US9171848B2 (en) Deep trench MIM capacitor and moat isolation with epitaxial semiconductor wafer scheme
US8772866B2 (en) Semiconductor device and method for fabricating the same
WO2023040157A1 (zh) 半导体结构及其形成方法
KR20140091845A (ko) 증착 확장된 활성영역을 갖는 반도체 및 반도체 제조 방법
US11862723B2 (en) Integrated circuit memory and manufacturing method thereof, and semiconductor integrated circuit device
TW202310342A (zh) 半導體結構及其形成方法
US6849495B2 (en) Selective silicidation scheme for memory devices
US10014301B2 (en) Semiconductor constructions
US20230089265A1 (en) Semiconductor structure and forming method thereof
US20160225820A1 (en) Semiconductor device and method for producing a semiconductor device
JP2013219179A (ja) 半導体装置及びその製造方法
US20050142740A1 (en) Method and resulting structure for fabricating dram cell structure using oxide line spacer
WO2024026933A1 (zh) 半导体结构及其形成方法
CN113517286B (zh) 一种半导体器件及其形成方法、电子设备
WO2023060790A1 (zh) 半导体结构及其形成方法