WO2023019891A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2023019891A1
WO2023019891A1 PCT/CN2022/076171 CN2022076171W WO2023019891A1 WO 2023019891 A1 WO2023019891 A1 WO 2023019891A1 CN 2022076171 W CN2022076171 W CN 2022076171W WO 2023019891 A1 WO2023019891 A1 WO 2023019891A1
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Prior art keywords
contact
bit line
capacitive
semiconductor
initial
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PCT/CN2022/076171
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English (en)
French (fr)
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郭帅
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长鑫存储技术有限公司
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Publication of WO2023019891A1 publication Critical patent/WO2023019891A1/zh
Priority to US18/327,143 priority Critical patent/US20230328952A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present disclosure relates to but not limited to a method for fabricating a semiconductor structure and the semiconductor structure.
  • metal-semiconductor contact structure Indium Tin-semiconductor
  • the work function of the metal affects the affinity of the semiconductor material, and the energy band of the semiconductor material at the interface bends, and a metal-induced gap is easily generated at the contact interface between the metal and the semiconductor material.
  • State Metal Induced Gap States, MIGS
  • MIGS Metal Induced Gap States
  • the metal-induced gap state causes the contact interface of metal and semiconductor materials to form a Schottky barrier, the Schottky barrier inhibits the flow of charge carriers, and the presence of the Schottky barrier increases
  • the contact resistance of the metal-semiconductor contact structure is reduced, which is not conducive to the improvement of device performance.
  • the disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure.
  • a first aspect of the present disclosure provides a method for fabricating a semiconductor structure, the fabricating method comprising:
  • An initial structure includes a base and a plurality of bit line structures arranged on the base, initial trenches are formed between adjacent bit line structures, the base includes an active region structure, the The initial trench exposes part of the active region structure;
  • the capacitive contact structure covering the exposed part of the active region structure, the capacitive contact structure comprising a first groove;
  • the gold half-contact structure covering at least the top surface of the capacitive contact structure and filling the first groove;
  • a conductive structure is formed, the conductive structure covers the barrier structure and fills the unfilled initial trench, and the conductive structure is connected to the capacitive contact structure through the gold half-contact structure.
  • a second aspect of the present disclosure provides a semiconductor structure comprising:
  • the capacitive contact structure formed between the bit line structures, the capacitive contact structure comprising a first groove
  • the gold half-contact structure covering at least the top surface of the capacitive contact structure and filling the first groove;
  • the blocking structure covers part of the sidewalls of the gold half-contact structure and the bit line structure;
  • a conductive structure covers the barrier structure, and the conductive structure is connected to the capacitive contact structure through the gold half-contact structure.
  • Fig. 1 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 3 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 4 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram of an initial structure provided in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 6 is a schematic diagram of forming an initial capacitive contact structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 7 is a schematic diagram of forming a capacitive contact structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 8 is a schematic diagram of forming a first groove on a capacitive contact structure in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 9 is a schematic diagram of depositing a first contact material in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 10 is a schematic diagram of forming a first contact layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 11 is a schematic diagram of depositing a second contact material in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 12 is a schematic diagram of forming a second contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 13 is a schematic structural diagram of a gold half-contact structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 14 is a schematic diagram of forming a barrier structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 15 shows a schematic diagram of forming a conductive structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 16 shows a schematic diagram of forming a first contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 17 is a schematic diagram of depositing a second contact material in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 18 shows a schematic diagram of forming a second contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 19 is a schematic structural diagram of a gold half-contact structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 20 is a schematic diagram of forming a photoresist mask on a substrate in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 21 is a schematic diagram showing the projection of a photoresist mask on a substrate in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 22 is a schematic diagram of etching a substrate to form an active region structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 23 is a schematic diagram of forming a shallow trench isolation structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 24 is a schematic structural diagram of a bit line contact hole formed in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 25 is a schematic projection view of a bit line contact hole formed in a method of manufacturing a semiconductor structure on a substrate according to an exemplary embodiment.
  • Fig. 26 is a schematic diagram of forming a bit line contact part in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 27 is a schematic diagram of forming a bit line structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 28 is a schematic diagram of forming a spacer structure in an initial trench in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 29 is a schematic diagram showing a projection of a spacer structure formed in a method for manufacturing a semiconductor structure on a substrate according to an exemplary embodiment.
  • capacitive contact structure 210, capacitive contact structure; 211, initial capacitive contact structure; 215, first groove; 220, gold half-contact structure; 221, first contact layer; 222, second contact layer; 230, barrier structure; 240, conductive structure .
  • FIG. 1 shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 2 - FIG. 10 is a schematic diagram of various stages of the manufacturing method of the semiconductor structure, and the manufacturing method of the semiconductor structure will be introduced below in conjunction with FIGS. 2-10 .
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM). However, this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S110 providing an initial structure, the initial structure includes a base and a plurality of bit line structures disposed on the base, an initial trench is formed between adjacent bit line structures, the base includes an active region structure, and the active part of the initial trench is exposed district structure.
  • the substrate 110 includes a plurality of active region structures 111, and the plurality of active region structures 111 are independently arranged.
  • the active region structures 111 include semiconductor materials, and the semiconductor materials can be silicon, germanium, silicon germanium compounds, and silicon carbon. Any one or more of the compounds.
  • a plurality of bit line structures 120 are disposed on the substrate 110 at intervals, and initial trenches 130 are formed between adjacent bit line structures 120 , and the initial trenches 130 expose part of the top surface of the active region structure 111 .
  • Step S120 forming a capacitive contact structure, the capacitive contact structure covers the exposed part of the active region structure, and the capacitive contact structure includes a first groove.
  • the material of the capacitive contact structure 210 is a doped semiconductor, and the material of the capacitive contact structure 210 is n-type or p-type doped polysilicon.
  • the step of forming the capacitive contact structure 210 includes: as shown in FIG. 6 , referring to FIG. 5 , forming an initial capacitive contact structure 211 , and the initial capacitive contact structure 211 fills the initial trench 130 .
  • an initial capacitive contact structure 211 may be formed by depositing doped polysilicon by using an atomic layer deposition (Atomic layer deposition, ALD) process. Then, as shown in FIG. 7, referring to FIG. 6, the initial capacitive contact structure 211 is etched, and the retained initial capacitive contact structure 211 forms a capacitive contact structure 210. In this embodiment, a dry or wet etching process can be used.
  • the initial capacitive contact structure 211 is etched, and the initial capacitive contact structure 211 is etched back below the top surface of the substrate 110 . Finally, as shown in FIG. 8 , referring to FIG. 7 , the capacitive contact structure 210 is etched to form a first groove 215 on the top surface of the capacitive contact structure 210 .
  • Step S130 forming a gold half-contact structure, the gold half-contact structure at least covers the top surface of the capacitive contact structure and fills the first groove.
  • a gold half-contact structure 220 is formed, and the gold half-contact structure 220 is used as an intermediate transition structure between the capacitive contact structure 210 and the subsequently formed conductive structure 240 .
  • the gold half-contact structure 220 formed in this embodiment is formed of a two-dimensional semiconductor material (two-dimensional semimetal) and a material having half metal properties.
  • the energy band structure of materials with semi-metallic properties includes two different sub-band structures, one of which has a metallic spin orientation, and the other sub-band structure has semiconductor properties.
  • the two-dimensional semiconductor material (two-dimensional semimetal) in the gold half-contact structure 220 and the Schottky barrier ratio capacitive contact structure 210 formed by the material with semi-metal (half metal) characteristics are formed by direct contact with the subsequently formed conductive structure.
  • the Schottky barrier is small.
  • Step S140 forming a barrier structure covering the exposed sidewalls of the gold half-contact structure and the initial trench.
  • an atomic layer deposition (Atomic layer deposition, ALD) process can be used to deposit and form a barrier structure 230.
  • the barrier structure 230 covers the exposed portion of the gold half-contact structure 220 and the exposed portion of the initial trench 130. side wall.
  • the material of the barrier structure 230 includes inorganic metal nitride.
  • the material of the barrier structure 230 includes any one or more of titanium nitride, aluminum nitride, boron nitride, hafnium nitride, tantalum nitride, titanium nitride or zirconium nitride.
  • the material of the blocking structure 230 is titanium nitride.
  • Step S150 forming a conductive structure, the conductive structure covers the barrier structure and fills the unfilled initial trench, and the conductive structure is connected to the capacitive contact structure through the gold half-contact structure.
  • a conductive structure 240 can be formed by depositing a metal conductive material by chemical vapor deposition (Chemical Vapor Deposition, CVD), and the conductive structure 240 fills the remaining unfilled regions in the initial trench 130.
  • CVD chemical Vapor Deposition
  • the material of the conductive structure 240 includes metal tungsten.
  • the step of forming the conductive structure 240 includes: depositing metal tungsten to fill the initial trench 130 to the position covering the top surface of the bit line structure 120, and etching and removing the covering bit line structure by a dry or wet etching process The metal tungsten on the top surface of 120 forms the conductive structure 240 .
  • a gold half-contact structure is formed between the capacitive contact structure and the conductive structure, and the Schottky barrier of the gold half-contact structure is higher than the Schottky barrier formed by the direct contact between the capacitive contact structure and the conductive structure.
  • the potential barrier is small, and the gold half-contact structure is used as a transition structure for the connection between the capacitive contact structure and the conductive structure, which reduces the Schottky barrier generated by the connection between the capacitive contact structure and the conductive structure, and reduces the electrical connection between the capacitive contact structure and the conductive structure.
  • the contact resistance can further reduce the size of semiconductor devices.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 2 , which shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S210 providing an initial structure.
  • the initial structure 100 includes a base 110 and a plurality of bit line structures 120 disposed on the base 110, initial trenches 130 are formed between adjacent bit line structures 120, the base 110 includes an active region structure 111, The initial trench 130 exposes a portion of the active region structure 111 .
  • Step S220 forming a capacitive contact structure, the capacitive contact structure covers the exposed part of the active region structure, and the capacitive contact structure includes a first groove.
  • Step S230 forming a first contact layer, the first contact layer filling the first groove and part of the initial trench.
  • the first contact layer 221 may be formed by depositing a first contact material, and the first contact material 221 includes monolayer semiconductors.
  • the first contact layer 221 can be formed by a top-down lift-off process (Lift-Off) or a bottom-up low-pressure metal-organic chemical vapor deposition process (Metal-organic Chemical Vapor Deposition, MOCVD).
  • a low-pressure metal-organic chemical vapor deposition process (Metal-organic Chemical Vapor Deposition, MOCVD) is used to grow a single-layer semiconductor material on the top surface of the capacitor contact structure, and the single-layer semiconductor material The unfilled regions in the first groove 215 and the initial trench 130 are filled, and the top surface of the bit line structure 120 is covered.
  • FIG. 10 referring to FIG.
  • the single-layer semiconductor material covering the top surface of the bit line structure 120 is etched away and the single-layer semiconductor material filled in the initial trench 130 is etched back, and the retained single-layer semiconductor material forms the first A contact layer 221 , the top surface of the first contact layer 221 is lower than the top surface of the bit line structure 120 , and the first contact layer 221 fills the first groove 215 and part of the initial trench 130 .
  • the single-layer semiconductor material included in the first contact material is two-dimensional transition metal dichalcogenides (TMDs).
  • the first contact material may include molybdenum disulfide (MoS 2 ), tungsten disulfide (WS 2 ), rhenium disulfide (ReS 2 ), titanium diselenide (TiSe 2 ), niobium diselenide (NbSe 2 ), diselenide at least one of rhenium (ReSe 2 ).
  • Step S240 forming a second contact layer, the second contact layer covers the top surface of the first contact layer and part of the exposed sidewall of the initial trench, and the first contact layer and the second contact layer form a gold half-contact structure.
  • the second contact layer 222 may be formed by depositing a second contact material including a group VA semi-metal element.
  • the material including the Group VA semimetal element may be heated and evaporated by an electron beam evaporation process, or the material including the Group VA semimetal element may be sputtered by a magnetron sputtering process, so that the material including the Group VA semimetal element is deposited on the On the top surface of the first contact layer 221 and the exposed sidewall of the initial trench 130 .
  • the second contact material may include at least one of the fourth-sixth period of the chemical element periodic table, the semi-metal element of Group VA, arsenic (Arsenic, As), antimony (stibium, Sb), and bismuth (Bismuth, Bi) .
  • the first contact layer 221 and the second contact layer 222 form the gold half-contact structure 220, the contact interface between the first contact layer 221 and the second contact layer 222, the VA of the second contact layer 222
  • the Fermi energy level of the group semimetal element is close to the minimum value of the semiconductor conduction band of the two-dimensional transition metal chalcogenide of the first contact layer 221, and the valence band of the two-dimensional transition metal chalcogenide is saturated (gap state saturation), group VA
  • group VA The metal-induced interstitial state induced by the half-metal element to induce the generation of the two-dimensional transition metal chalcogenide is suppressed, and the Schottky barrier generated at the contact interface of the first contact layer 221 and the second contact layer 222 tends to be close to zero Reduced, the Schottky barrier produced by the contact interface between the first contact layer 221 and the second contact layer 222 is negligible, and there is no potential barrier for carriers to enter the second contact layer 222 from the first contact
  • Step S250 forming a barrier structure covering the top surface of the second contact layer and the exposed sidewalls of the initial trench.
  • Step S260 forming a conductive structure, the conductive structure covers the barrier structure and fills the unfilled initial trench, and the conductive structure is connected with the capacitive contact structure through the gold half-contact structure.
  • Steps S210-S220 in this embodiment are implemented in the same manner as steps S110-S120 in the above-mentioned embodiment, and steps S250-S260 are implemented in the same manner as steps S140-S150 in the above-mentioned embodiment, so details are not repeated here.
  • the gold half-contact structure includes a first contact layer and a second contact layer, the first contact layer includes a single-layer semiconductor material, the second contact layer includes a group VA semi-metal element, and the single-layer semiconductor material and the group VA
  • the half-metal element material contact reduces the Schottky barrier generated by the contact interface between the first contact layer and the second contact layer, and the contact interface between the first contact layer and the second contact layer forms a good ohmic contact, thereby reducing The resistance between the first contact layer and the second contact layer is improved.
  • the gold half-contact structure is used as an intermediate transition structure for the electrical connection between the capacitive contact structure and the conductive structure, which reduces the contact resistance between the capacitive contact structure and the conductive structure, and the on-state current density between the capacitive contact structure and the conductive structure is higher.
  • the potential of the semiconductor structure to high performance and high miniaturization is improved, and the size of the semiconductor device can be further reduced.
  • the first contact layer fills the first groove to increase the contact area between the first contact layer and the first groove, and the second contact layer covers the top surface of the first contact layer and the exposed part of the sidewall of the initial groove, increasing the second contact layer.
  • the contact area between the contact layer and the conductive structure further increases the mobility of carriers from the capacitive contact structure to the conductive structure, and increases the on-state current density between the capacitive contact structure and the conductive structure.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 3 , which shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S310 providing an initial structure.
  • the initial structure provided in this embodiment includes the following steps:
  • the substrate 101 may be made of a semiconductor material, and the semiconductor material may be any one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
  • S312 Etching the substrate to form a plurality of active region structures arranged in an array.
  • a photoresist mask layer 102 is formed on the top surface of the substrate 101.
  • the portion of the substrate 101 exposed by the photoresist mask layer 102 is removed by dry or wet etching to form shallow trenches 103 .
  • the photoresist mask layer 102 is removed, and the substrate covered by the photoresist mask layer 102 forms a plurality of independently arranged active region structures 111 , and the plurality of active region structures 111 are separated by shallow trenches 103 .
  • S313 forming a shallow trench isolation structure, where the shallow trench isolation structure is used to isolate each active region structure.
  • a low-k dielectric material is deposited to fill the shallow trench 103 to form a shallow trench by using a chemical vapor deposition process (Chemical Vapor Deposition, CVD) or an atomic layer deposition process (Atomic layer deposition, ALD).
  • CVD chemical Vapor Deposition
  • ALD atomic layer deposition
  • the trench isolation structure 112 , the shallow trench isolation structure 112 separates a plurality of active region structures 111 .
  • the shallow trench isolation structure 112 and the active region structure 111 form a substrate 110 .
  • silicon oxide is deposited into the shallow trench 103 to form the shallow trench isolation structure 112 .
  • bit line contact hole exposes part of the active region structure and part of the shallow trench isolation structure.
  • a first mask layer 104 is formed on the top surfaces of the active region structure 111 and the shallow trench isolation structure 112 , and the projection of the first mask layer 104 on the substrate 101 exposes part of the active region structure 111 and part of the shallow trench isolation structure 112 .
  • a part of the active region structure 111 and a part of the shallow trench isolation structure 112 exposed by the first mask layer 104 are etched and removed by a dry or wet etching process to form a bit line contact hole 105, as shown in FIG.
  • the bit line contact hole 105 exposes part of the active region structure 111 and part of the shallow trench isolation structure 112 .
  • bit line contact 121 As shown in FIG. 26 , referring to FIG. 24 , by chemical vapor deposition (Chemical Vapor Deposition, CVD) or atomic layer deposition (Atomic layer deposition, ALD), a doped semiconductor material is deposited to form a bit line contact 121.
  • CVD Chemical Vapor Deposition
  • ALD atomic layer deposition
  • a doped semiconductor material is deposited to form a bit line contact 121.
  • the material of the bit line contact portion 121 includes conductivity-type doped polysilicon.
  • the bit line structure 120 is arranged on the top surface of the active region structure 111 and the shallow trench isolation structure 112, the bit line structure is connected to the bit line contact portion 121, and a plurality of bit line structures 120 are connected to each other.
  • an initial trench 130 is formed between adjacent bit line structures 120 , and the initial trench 130 exposes part of the top surface of the active region structure 111 .
  • providing an initial structure also includes the following steps:
  • S317 forming a spacer structure in the initial trench, the extending direction of the spacer structure is perpendicular to the extending direction of the bit line structure.
  • a spacer structure 150 is formed, and the spacer structure 150 is located in the initial trench 130 and covers part of the initial trench 130 .
  • the arrangement direction of the spacer structure 150 is perpendicular to the extension direction of the bit line structure 120 , and the spacer structure 150 exposes part of the top surface of the active region structure 111 and part of the shallow trench isolation structure 112 .
  • S318 Using the spacer structure and the bit line structure as a mask, removing part of the active region structure and the shallow trench isolation structure exposed by the initial trench to form a capacitor contact hole.
  • a part of the active region structure 111 and a part of the shallow trench isolation structure exposed by the spacer structure 150 and the bit line structure 120 are etched and removed by a dry or wet etching process.
  • 112 forming a capacitor contact hole 140 , and the capacitor contact hole 140 exposes part of the active region structure 111 and part of the shallow trench isolation structure 112 .
  • Step S320 forming a capacitive contact structure, the capacitive contact structure covers the exposed part of the active region structure, and the capacitive contact structure includes a first groove.
  • forming the capacitive contact structure 210 includes the following steps: as shown in FIG. 6, referring to FIG. , the initial capacitive contact structure 211 fills the capacitive contact hole 140 and the initial trench 130 . Then, as shown in FIG. 7 , referring to FIG. 6 , the initial capacitive contact structure 211 is etched by a dry or wet etching process, and the initial capacitive contact structure 211 is etched back below the top surface of the substrate 110 to preserve the initial capacitive contact structure 211. The contact structure 211 forms a capacitive contact structure 210 , and the capacitive contact structure 210 fills the capacitive contact hole 140 and part of the initial trench 130 . Finally, as shown in FIG. 8 , referring to FIG. 7 , the top surface of the capacitive contact structure 210 is etched to form a first groove 215 recessed toward the substrate 110 on the top surface of the capacitive contact structure 210 .
  • Step S330 forming a first contact layer, the first contact layer covers the top surface of the capacitive contact structure.
  • a top-down lift-off process (Lift-Off) or a bottom-up low-pressure metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD) process can be used to deposit
  • the first contact material forms the first contact layer 221 , and the first contact material includes monolayer semiconductors.
  • the single-layer semiconductor material included in the first contact material is two-dimensional transition metal dichalcogenides (TMDs).
  • the first contact material may include molybdenum disulfide (MoS 2 ), tungsten disulfide (WS 2 ), rhenium disulfide (ReS 2 ), titanium diselenide (TiSe2), niobium diselenide (NbSe 2 ), diselenide At least one of rhenium (ReSe 2 ).
  • the single-layer two-dimensional transition metal dichalcogenides include three atomic layers, and the three atomic layers are arranged in the form of sulfur atoms-transition metal atoms-sulfur atoms.
  • the single-layer two-dimensional transition metal chalcogenides have Good semiconductor properties, high carrier mobility in the plane.
  • a three-dimensional semiconductor material can be formed by using a lift-off process, and a single atomic layer or multiple atomic layers in the three-dimensional semiconductor material can be removed by the lift-off process to form a single-layer two-dimensional semiconductor material.
  • a layer of two-dimensional semiconductor material is transferred onto the capacitive contact structure 210 , and a single layer of two-dimensional semiconductor material covers the top surface of the capacitive contact structure to form a first contact layer 221 .
  • Step S340 forming a second contact layer, the second contact layer fills the first groove and covers the exposed part of the sidewall of the initial trench, and the first contact layer and the second contact layer form a gold half-contact structure.
  • the second contact material can be formed by sputtering and depositing a second contact material by electron beam evaporation process heating evaporation or magnetron sputtering process to form a second contact layer 222, and the second contact material includes the VA group semi-metal element.
  • Material, the material of group VA semi-metal covers the top surface of the first contact layer 221 and fills the exposed sidewalls of the first groove 215 and the initial trench 130 .
  • part of the material covering the sidewall of the initial trench 130 is removed by etching to form the second contact layer 222 .
  • the second contact material may include at least one of Group VA semimetal elements arsenic (Arsenic, As), antimony (stibium, Sb) and bismuth (Bismuth, Bi) in periods 4-6 of the periodic table of chemical elements.
  • Step S350 forming a barrier structure covering the top surface of the second contact layer and the exposed sidewalls of the initial trench.
  • Step S360 forming a conductive structure, the conductive structure covers the barrier structure and fills the unfilled initial trench, and the conductive structure is connected to the capacitive contact structure through the gold half-contact structure.
  • Steps S350-S360 in this embodiment are implemented in the same way as steps S140-S150 in the above-mentioned embodiment, and will not be repeated here.
  • the gold half-contact structure in this embodiment includes a first contact layer and a second contact layer.
  • the first contact layer covers the top surface of the capacitive contact structure, that is, the first contact layer is a bottom-down concave structure, which increases the first
  • the contact area between the contact layer and the second contact layer reduces the contact resistance of the gold half-contact structure; at the same time, the second contact layer covers part of the sidewall of the initial trench, increasing the contact area between the second contact layer and the conductive structure, The contact resistance between the gold half-contact structure and the conductive structure is reduced, and the size of the semiconductor device can be further reduced.
  • the Schottky barrier produced by the two-dimensional semiconductor material of the first contact layer and the contact interface of the second contact layer including the VA group semi-metal element is small, and the contact resistance of the gold half-contact structure is small, so that the contact structure from the capacitive contact structure to the conductive
  • the carrier mobility of the structural flow is higher.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 4 , which shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S410 providing an initial structure.
  • the initial structure 100 includes a base 110 and a plurality of bit line structures 120 disposed on the base 110, initial trenches 130 are formed between adjacent bit line structures 120, the base 110 includes an active region structure 111, The initial trench 130 exposes a portion of the active region structure 111 .
  • Step S420 forming a capacitive contact structure, the capacitive contact structure covers the exposed part of the active region structure, and the capacitive contact structure includes a first groove.
  • Step S430 forming a first contact layer, the first contact layer covers the top surface of the capacitive contact structure, and the material of the first contact layer includes molybdenum disulfide.
  • the first contact layer 221 can be formed by a low-pressure metal-organic chemical vapor deposition process (Metal-organic Chemical Vapor Deposition, MOCVD).
  • MOCVD Metal-organic Chemical Vapor Deposition
  • molybdenum hexacarbonyl (Mo(CO) 6 ) can be used and diethyl sulfide (C 4 H 10 S) as precursors of molybdenum (Mo) and sulfur (S) respectively
  • MoCl 5 molybdenum pentachloride
  • MoCl 5 hexamethyldisilathane
  • HMDST hexamethyldisilathane
  • HMDST is used as the precursor of molybdenum (Mo) and sulfur (S) respectively
  • argon (Ar) as the carrier gas
  • the precursors of molybdenum (Mo) and sulfur (S) are separated by steam
  • the form is supplied to the semiconductor structure, the precursor of molybdenum (Mo)
  • Molybdenum disulfide (MoS 2 ) has an in-plane carrier mobility between 200 and 500 cm 2 V -1 s -1 and a band gap of 1.3 eV. It is an indirect gap semiconductor material.
  • Molybdenum disulfide deposited on the capacitive contact structure 210 is a single-layer molybdenum disulfide, and the single-layer molybdenum disulfide has a band gap of 1.8 eV, which is a semiconductor material that changes from an indirect gap to a direct gap.
  • Step S440 forming a second contact layer, the second contact layer fills the first groove and covers the exposed part of the sidewall of the initial trench, the material of the second contact layer includes bismuth, and the first contact layer and the second contact layer are formed of gold semi-contact structure.
  • the second contact layer 222 can be formed by heating and evaporating bismuth (Bismuth, Bi) or a bismuth compound through an electron beam evaporation process.
  • the deposition rate was The second contact layer 222 covers the top surface of the first contact layer 221 , fills the first groove 215 and part of the exposed sidewall of the initial trench 130 .
  • Bismuth (Bismuth, Bi) is the metal with the highest diamagnetism, and has high Hall coefficient and resistivity. When the thickness of bismuth is reduced to the nanometer level, the energy band structure of bismuth changes, and the energy band structure of bismuth is converted into one of the sub-band structures with metallic spin orientation, and the other sub-band structure with semiconductor properties. Nanoscale bismuth has semi-metallic properties. Bismuth compounds also have the above characteristics, for example, bismuth selenide (Bismuth selenide, Bi 2 Se 3 ), bismuth (III) telluride (Bismuth(III) telluride, Bi 2 Te 3 ).
  • the second contact layer 222 and the first contact layer 221 form the gold half-contact structure 220, the contact interface of the second contact layer 222 and the first contact layer 221, the second contact layer 222 and the first contact layer 221
  • the contact interface of bismuth, the Fermi level of bismuth is higher than the conduction band minimum of molybdenum disulfide
  • the pz orbital of bismuth resonates with the pz and dz2 orbitals of molybdenum disulfide
  • the inductive electric dipole of the contact interface between bismuth and molybdenum disulfide The distribution falls into the van der Waals gap, the metal-induced interstitial state electron saturation of MoS2 leads to the saturation of the gap state of MoS2, the contact interface of Bi and MoS2 realizes zero Schottky barrier, and the bismuth and MoS2
  • the molybdenum contact interface forms an ohmic contact, which reduces the contact resistance between the second contact layer 222 and the first contact layer 221
  • Step S450 forming a barrier structure covering the exposed sidewalls of the gold half-contact structure and the initial trench.
  • Step S460 forming a conductive structure, the conductive structure covers the barrier structure and fills the unfilled initial trench, and the conductive structure is connected with the capacitive contact structure through the gold half-contact structure.
  • Steps S410-S420 in this embodiment are implemented in the same manner as steps S310-S320 in the above-mentioned embodiment, and steps S450-S460 are implemented in the same manner as steps S350-S360 in the above-mentioned embodiment, so details are not repeated here.
  • the gold half-contact structure formed by semi-metal bismuth and semiconductor molybdenum disulfide is used as an intermediate transition structure between the capacitive contact structure and the conductive structure to avoid direct contact between the semiconductor material of the capacitive contact structure and the metal material of the conductive structure.
  • Bismuth The contact interface with molybdenum disulfide achieves zero Schottky barrier, and the transfer of carriers between the first contact layer and the second contact layer does not need to jump over the barrier, so that the contact interface between bismuth and molybdenum disulfide forms a good ohmic contact , the contact resistance of the gold half-contact structure reaches the minimum.
  • a semiconductor structure provided by an exemplary embodiment of the present disclosure includes a substrate 110 and a plurality of bit line structures 120 disposed on the substrate 110 .
  • the semiconductor structure further includes a capacitive contact structure 210 including a first groove 215 , and the capacitive contact structure 210 is formed between adjacent bit line structures 120 .
  • the semiconductor structure further includes a gold half-contact structure 220 , the gold half-contact structure 220 at least covers the top surface of the capacitive contact structure 210 and fills the gold half-contact structure 220 of the first groove 215 .
  • the semiconductor structure further includes a barrier structure 230 and a conductive structure 240.
  • the barrier structure 230 covers part of the sidewalls of the gold half-contact structure 220 and the bit line structure 120.
  • the conductive structure 240 covers the barrier structure 230.
  • the conductive structure 240 passes through the gold half-contact structure 220 and the capacitor.
  • the contact structure 210 is connected.
  • the material of the conductive structure 240 includes metal tungsten.
  • the material of the capacitive contact structure 210 is doped semiconductor, and the material of the capacitive contact structure is n-type or p-type doped polysilicon.
  • the material of the barrier structure 230 includes any one or more of titanium nitride, aluminum nitride, boron nitride, hafnium nitride, tantalum nitride, titanium nitride or zirconium nitride.
  • the barrier structure The material is titanium nitride.
  • the function of the barrier structure 230 is to prevent the material of the conductive structure 240 from permeating into the substrate 110 to cause contamination of the substrate 110 , so as to ensure the yield and service life of the semiconductor structure.
  • the gold half-contact structure 220 formed in this embodiment includes a two-dimensional semiconductor material (two-dimensional semimetal) and a material having half metal properties.
  • the energy band structure of materials with semi-metallic properties includes two different sub-band structures, one of which has a metallic spin orientation, and the other sub-band structure has semiconductor properties.
  • the two-dimensional semiconductor material (two-dimensional semimetal) of 220 in the gold half-contact structure and the material contact with half metal (half metal) characteristics produce Schottky barrier ratio capacitive contact structure 210 and the subsequently formed conductive structure 240 in direct contact The resulting Schottky barrier is small.
  • a gold half-contact structure 220 is provided between the capacitive contact structure 210 and the conductive structure 240, and the gold half-contact structure 220 serves as an intermediate transition structure connecting the capacitive contact structure 210 and the conductive structure 240. , the Schottky barrier generated by the contact between the capacitive contact structure 210 and the conductive structure 240 is reduced, the size of the semiconductor structure can be further reduced, and the potential for further miniaturization of the semiconductor structure is improved.
  • the gold half-contact structure 220 includes : filling the first groove 215 , the first contact layer 221 covering part of the sidewall of the bit line structure 120 , and the second contact layer 222 covering the first contact layer 221 and part of the sidewall of the bit line structure 120 .
  • the first contact layer 221 fills the first groove 215 to increase the contact area between the first contact layer 221 and the first groove 215, and the second contact layer 222 covers the top surface and the position of the first contact layer 221.
  • Part of the sidewall of the line structure 120 increases the contact area between the second contact layer 222 and the conductive structure 240, further improves the mobility of carriers from the capacitive contact structure 210 to the conductive structure 240, and improves the contact area between the capacitive contact structure 210 and the conductive structure 240.
  • the gold half-contact structure 220 includes : the first contact layer 221 covering the top surface of the capacitive contact structure 210 and the second contact layer 222 filling the first groove 215 and covering part of the sidewall of the bit line structure 120 .
  • the first contact layer 221 covers the top surface of the capacitive contact structure 210, that is, the first contact layer 221 has a bottom-down concave structure, which increases the contact area between the first contact layer 221 and the second contact layer 222 , reducing the contact resistance of the gold half-contact structure 220; at the same time, the second contact layer 222 covers part of the sidewall of the bit line structure 120, increasing the contact area between the second contact layer 222 and the conductive structure 240, and reducing the contact resistance of the gold half-contact structure 220.
  • the contact resistance of the contact structure 220 and the conductive structure 240 can further reduce the size of the semiconductor structure.
  • most of the content of the semiconductor structure of this embodiment is the same as that of the above embodiment, the difference between this embodiment and the above embodiment is that the material of the first contact layer 221 includes a single layer of semiconductor material , the material of the second contact layer 222 includes group VA elements.
  • the monolayer semiconductors included in the first contact material are two-dimensional transition metal dichalcogenides (TMDs).
  • TMDs transition metal dichalcogenides
  • the first contact material may include molybdenum disulfide (MoS 2 ), tungsten disulfide (WS 2 ), rhenium disulfide (ReS 2 ), titanium diselenide (TiSe 2 ), niobium diselenide (NbSe 2 ), at least one of rhenium diselenide (ReSe 2 ).
  • the second contact material may include at least one of Group VA semimetal elements arsenic (Arsenic, As), antimony (stibium, Sb), and bismuth (Bismuth, Bi) in periods 4-6 of the periodic table of chemical elements.
  • the first contact layer 221 and the second contact layer 222 of the gold half-contact structure 220 form a half-metal-semiconductor contact interface, and the Fermi energy level of the VA group semi-metal element in the second contact layer 222 is close to the first
  • the minimum value of the semiconductor conduction band of the two-dimensional transition metal chalcogenide of the contact layer 221, the valence band of the two-dimensional transition metal chalcogenide is saturated (interstitial state saturation), and the VA semi-metal element induces the The resulting metal-induced gap state is suppressed, and the Schottky barrier generated at the contact interface of the first contact layer 221 and the second contact layer 222 is close to zero, and the contact resistance of the Schottky barrier to the gold half-contact structure 220
  • the resulting influence is negligible, and the first contact layer 221 and the second contact layer 222 form a good ohmic contact.
  • the gold half-contact structure 220 in this embodiment reduces the contact resistance between the capacitive contact structure 210 and the conductive structure 240, the carrier mobility between the capacitive contact structure 210 and the conductive structure 240 is greater, and the on-state current density is higher , can further reduce the size of the semiconductor structure, and improve the potential of the semiconductor structure to develop high performance and high miniaturization.
  • most of the content of the semiconductor structure of this embodiment is the same as that of the above embodiment, and the difference between this embodiment and the above embodiment is that, as shown in FIG. 15 , referring to FIG. 5 , the substrate 110 including an active region structure 111 and a shallow trench isolation structure 112, the top surface of the active region structure 111 is flush with the top surface of the shallow trench isolation structure 112, and a part of the active region is exposed between adjacent bit line structures 120 structure 111 and shallow trench isolation structure 112 .
  • the semiconductor structure also includes: a capacitance contact hole 140, the capacitance contact hole 140 is disposed on the substrate 110, the capacitance contact hole 140 is located between the adjacent bit line structures 120, the capacitance contact hole 140 exposes part of the active region structure 111 and part of the shallow trench The isolation structure 112 ; the capacitive contact structure 210 fills the capacitive contact hole 140 .
  • the capacitive contact 111 is provided on the substrate 110 to increase the contact area between the capacitive contact structure 210 and the active region structure 111 , further reducing the contact resistance of the semiconductor structure.
  • the gold half-contact structure is used as an intermediate transition structure for electrical connection between the capacitive contact structure and the conductive structure, thereby reducing the contact resistance of the capacitive contact structure and the conductive structure.

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Abstract

本公开公布了一种半导体结构的制作方法及半导体结构，制作方法包括，提供初始结构，初始结构包括基底及初始沟槽，初始沟槽暴露部分有源区结构；形成电容接触结构，电容接触结构覆盖暴露出的部分有源区结构，电容接触结构包括第一凹槽；形成金半接触结构，金半接触结构至少覆盖电容接触结构的顶面并填充第一凹槽；形成阻挡结构，阻挡结构覆盖金半接触结构和初始沟槽的暴露的侧壁；形成导电结构，导电结构通过金半接触结构和电容接触结构连接。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202110955818.9，申请日为2021年08月19日，申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及半导体结构。
背景技术
在集成电路领域，根据摩尔定律，封装在集成电路中的半导体器件每增加一倍，集成电路的性能也会随之翻一番，为此，集成电路的集成度不断提高，半导体器件的线宽不断减小。
但是，半导体器件常通过形成金属-半导体接触结构形成电连接，金属的功函数影响半导体材料的亲和势，界面处半导体材料的能带弯曲，在金属和半导体材料的接触界面容易产生金属诱导间隙状态(Metal Induced Gap States，MIGS)，金属诱导间隙状态导致金属和半导体材料的接触界面形成肖特基势垒，肖特基势垒抑制电荷载流子流动，肖特基势垒的存在增大了金属-半导体接触结构的接触电阻，不利于器件性能的提高。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供了一种半导体结构的制作方法，所述制作方法包括：
提供初始结构，所述初始结构包括基底以及设置在所述基底上的多条位线结构，相邻的所述位线结构之间形成初始沟槽，所述基底包括有源区结构，所述初始沟槽暴露部分所述有源区结构；
形成电容接触结构，所述电容接触结构覆盖暴露出的部分所述有源区结构，所述电容接触结构包括第一凹槽；
形成金半接触结构，所述金半接触结构至少覆盖所述电容接触结构的顶面并填充所述第一凹槽；
形成阻挡结构，所述阻挡结构覆盖所述金半接触结构和所述初始沟槽的暴露的侧壁；
形成导电结构，所述导电结构覆盖所述阻挡结构并填充未被填充的所述初始沟槽，所述导电结构通过所述金半接触结构和所述电容接触结构连接。
本公开的第二方面提供了一种半导体结构，包括：
基底以及设置在所述基底上的多条位线结构；
电容接触结构，形成于所述位线结构之间，所述电容接触结构包括第一凹槽；
金半接触结构，所述金半接触结构至少覆盖所述电容接触结构的顶面并填充所述第一凹槽；
阻挡结构，所述阻挡结构覆盖所述金半接触结构和所述位线结构的部 分侧壁；
导电结构，所述导电结构覆盖所述阻挡结构，所述导电结构通过所述金半接触结构和所述电容接触结构连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全结构实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图2是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图3是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图4是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图5是根据一示例性实施例示出的一种半导体结构的制作方法中提供的初始结构的示意图。
图6是根据一示例性实施例示出的一种半导体结构的制作方法中形成初始电容接触结构的示意图。
图7是根据一示例性实施例示出的一种半导体结构的制作方法中形成电容接触结构的示意图。
图8是根据一示例性实施例示出的一种半导体结构的制作方法中在电容接触结构上形成第一凹槽的示意图。
图9是根据一示例性实施例示出的一种半导体结构的制作方法中沉积第一接触材料的示意图。
图10是根据一示例性实施例示出的一种半导体结构的制作方法中形成第一接触层的示意图。
图11是根据一示例性实施例示出的一种半导体结构的制作方法中沉积第二接触材料的示意图。
图12是根据一示例性实施例示出的一种半导体结构的制作方法中形成第二接触层的示意图。
图13是根据一示例性实施例示出的一种半导体结构的制作方法中形成的金半接触结构的结构示意图。
图14是根据一示例性实施例示出的一种半导体结构的制作方法中形成阻挡结构的示意图。
图15根据一示例性实施例示出的一种半导体结构的制作方法中形成导电结构的示意图。
图16根据一示例性实施例示出的一种半导体结构的制作方法中形成第一接触层的示意图。
图17是根据一示例性实施例示出的一种半导体结构的制作方法中沉积第二接触材料的示意图。
图18根据一示例性实施例示出的一种半导体结构的制作方法中形成 第二接触层的示意图。
图19是根据一示例性实施例示出的一种半导体结构的制作方法中形成的金半接触结构的结构示意图。
图20是根据一示例性实施例示出的一种半导体结构的制作方法中在衬底上形成光刻胶掩膜的示意图。
图21是根据一示例性实施例示出的一种半导体结构的制作方法中光刻胶掩膜在衬底上的投影示意图。
图22是根据一示例性实施例示出的一种半导体结构的制作方法中刻蚀衬底形成有源区结构的示意图。
图23是根据一示例性实施例示出的一种半导体结构的制作方法中形成浅沟槽隔离结构的示意图。
图24是根据一示例性实施例示出的一种半导体结构的制作方法中形成的位线接触孔的结构示意图。
图25是根据一示例性实施例示出的一种半导体结构的制作方法中形成的位线接触孔在基底上的投影示意图。
图26是根据一示例性实施例示出的一种半导体结构的制作方法中形成位线接触部的示意图。
图27是根据一示例性实施例示出的一种半导体结构的制作方法中形成位线结构的示意图。
图28是根据一示例性实施例示出的一种半导体结构的制作方法中在初始沟槽中形成间隔结构的示意图。
图29是根据一示例性实施例示出的一种半导体结构的制作方法中形成的间隔结构在基底上的投影示意图。
附图标记：
100、初始结构；101、衬底；102、光刻胶掩膜；103、浅沟槽；104、第一掩膜层；105、位线接触孔；110、基底110；111、有源区结构；112、浅沟槽隔离结构；120、位线结构；121、位线接触部；130、初始沟槽；140、电容接触孔；150、间隔结构；
210、电容接触结构；211、初始电容接触结构；215、第一凹槽；220、金半接触结构；221、第一接触层；222、第二接触层；230、阻挡结构；240、导电结构。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全结构的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图2-图10为半导体结构的制作方法的各个阶段的示意图，下面结合图2-图10对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的 半导体结构还可以为其他的结构。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S110：提供初始结构，初始结构包括基底以及设置在基底上的多条位线结构，相邻的位线结构之间形成初始沟槽，基底包括有源区结构，初始沟槽暴露部分有源区结构。
如图5所示，基底110包括多个有源区结构111，多个有源区结构111独立设置，有源区结构111包括半导体材料，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的任意一种或者多种。多条位线结构120间隔设置在基底110上，相邻的位线结构120之间形成初始沟槽130，初始沟槽130暴露出部分有源区结构111的顶面。
步骤S120：形成电容接触结构，电容接触结构覆盖暴露出的部分有源区结构，电容接触结构包括第一凹槽。
如图8所示，电容接触结构210的材料为掺杂半导体，电容接触结构210的材料为n型或p型导电型掺杂多晶硅。
在本实施例中，形成电容接触结构210的步骤包括：如图6所示，参照图5，形成初始电容接触结构211，初始电容接触结构211填充初始沟槽130。在本实施例中，可以采用原子层沉积(Atomic layer deposition，ALD)工艺沉积掺杂多晶硅形成初始电容接触结构211。然后，如图7所示，参照图6，刻蚀初始电容接触结构211，被保留的初始电容接触结构211形成电容接触结构210，在本实施例中，可以通过干法或湿法刻蚀工艺刻蚀初始电容接触结构211，将初始电容接触结构211回刻至低于基底110顶面。最后，如图8所示，参照图7，刻蚀电容接触结构210，在电容接触结构210的顶面形成第一凹槽215。
步骤S130：形成金半接触结构，金半接触结构至少覆盖电容接触结构的顶面并填充第一凹槽。
如图12所示，形成金半接触结构220，以金半接触结构220作为电容接触结构210和后续形成的导电结构240的中间过渡结构。
本实施例中形成的金半接触结构220由二维半导体材料(two-dimensional semimetal)和具有半金属(half metal)特性的材料形成。具有半金属特性的材料的能带结构包括两种不同的子能带结构，其中的一种子能带结构的自旋取向具有金属性，另一种子能带结构具有半导体性。金半接触结构220中的二维半导体材料(two-dimensional semimetal)和具有半金属(half metal)特性的材料形成的肖特基势垒比电容接触结构210和后续形成的导电结构直接接触形成的肖特基势垒小。
步骤S140：形成阻挡结构，阻挡结构覆盖金半接触结构和初始沟槽的暴露的侧壁。
如图14所示，参照图12，可以采用原子层沉积(Atomic layer deposition，ALD)工艺沉积形成阻挡结构230，阻挡结构230覆盖金半接触结构220暴露出的部分以及初始沟槽130的暴露的侧壁。
阻挡结构230的材料包括无机金属氮化物。示例性的，阻挡结构230的材料包括氮化钛、氮化铝、氮化硼、氮化铪、氮化钽、氮化钛或氮化锆中的任意一种或多种，在本实施例中，阻挡结构230的材料为氮化钛。
步骤S150：形成导电结构，导电结构覆盖阻挡结构并填充未被填充的初始沟槽，导电结构通过金半接触结构和电容接触结构连接。
如图15所示，参照图14，可以通过化学气相沉积(Chemical Vapor Deposition，CVD)沉积金属导电材料形成导电结构240，导电结构240填充 初始沟槽130中未被填充的其余区域。本实施例中，导电结构240的材料包括金属钨。
在本实施例中，形成导电结构240的步骤包括：沉积金属钨填充初始沟槽130至覆盖位线结构120的顶面的位置，通过干法或湿法刻蚀工艺刻蚀去除覆盖位线结构120的顶面的金属钨，形成导电结构240。
本实施例的半导体结构的制作方法中，在电容接触结构和导电结构之间形成金半接触结构，金半接触结构的肖特基势垒比电容接触结构和导电结构直接接触形成的肖特基势垒小，金半接触结构作为电容接触结构和导电结构连接的过渡结构，减小了电容接触结构和导电结构连接产生的肖特基势垒，减小了电容接触结构和导电结构电连接产生的接触电阻，可进一步减小半导体器件的尺寸。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图2所示，图2示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图。
如图2所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S210：提供初始结构。
如图5所示，初始结构100包括基底110以及设置在基底110上的多条位线结构120，相邻的位线结构120之间形成初始沟槽130，基底110包括有源区结构111，初始沟槽130暴露部分有源区结构111。
步骤S220：形成电容接触结构，电容接触结构覆盖暴露出的部分有源区结构，电容接触结构包括第一凹槽。
步骤S230：形成第一接触层，第一接触层填充第一凹槽以及部分初始沟槽。
如图9、图10所示，可以通过沉积第一接触材料形成第一接触层221，第一接触材料221包括单层半导体材料(monolayer semiconductors)。
可以采用自上而下的剥离工艺(Lift-Off)或自下而上的低压金属有机化学气相沉积工艺(Metal-organic Chemical Vapor Deposition，MOCVD)形成第一接触层221。在本实施例中，如图9所示，参照图8，使用低压金属有机化学气相沉积工艺(Metal-organic Chemical Vapor Deposition，MOCVD)在电容接触结构顶面生长单层半导体材料，单层半导体材料填充第一凹槽215和初始沟槽130中未被填充的区域，以及覆盖位线结构120的顶面。如图10所示，参照图9，刻蚀去除覆盖位线结构120的顶面的单层半导体材料并回刻填充于初始沟槽130的单层半导体材料，被保留的单层半导体材料形成第一接触层221，第一接触层221的顶面低于位线结构120的顶面，第一接触层221填充第一凹槽215以及部分初始沟槽130。
在本实施例中，第一接触材料包括的单层半导体材料为二维过渡金属硫属化合物(transition metal dichalcogenides，TMDs)。第一接触材料可以包括二硫化钼(MoS 2)、二硫化钨(WS 2)、二硫化铼(ReS 2)、二硒化钛(TiSe 2)、二硒化铌(NbSe 2)、二硒化铼(ReSe 2)中的至少一种。
步骤S240：形成第二接触层，第二接触层覆盖第一接触层的顶面以及初始沟槽暴露的部分侧壁，第一接触层和第二接触层形成金半接触结构。
如图11所示，参照图10，可以通过沉积第二接触材料形成第二接触层222，第二接触材料包括第VA族半金属元素。可以通过电子束蒸发工艺加热蒸发包括第VA族半金属元素的材料，或者通过磁控溅射工艺溅射包括第VA族半金属元素的材料，以使包括第VA族半金属元素的材料沉积在第一接触层221的顶面以及初始沟槽130暴露的侧壁上。
如图12所示，参照图11，刻蚀去除覆盖初始沟槽130侧壁的部分材料，形成第二接触层222，第二接触层222覆盖第一接触层221的顶面以及初始沟槽130暴露的部分侧壁。第二接触材料可以包括化学元素周期表第四-第六周期、第VA族的半金属元素，砷(Arsenic，As)、锑(stibium，Sb)、铋(Bismuth，Bi)中的至少一种。
如图12、图13所示，第一接触层221和第二接触层222形成金半接触结构220，第一接触层221和第二接触层222的接触界面，第二接触层222的第VA族半金属元素的费米能级接近第一接触层221的二维过渡金属硫属化合物的半导体导带的最小值，二维过渡金属硫属化合物价带饱和(间隙状态饱和)，第VA族半金属元素诱导二维过渡金属硫属化合物的产生的金属诱导间隙状态受到抑制，则在第一接触层221和第二接触层222的接触界面产生的肖特基势垒向着接近于零的趋势减小，第一接触层221和第二接触层222的接触界面产生的肖特基势垒可忽略不计，载流子从第一接触层221进入第二接触层222没有势垒，而从第二接触层222进入第一接触层221只有很小甚至可忽略不计的势垒，第一接触层221的二维过渡金属硫属化合物和第二接触层222的第VA族半金属元素形成良好的欧姆接触，第一接触层221和第二接触层222的接触界面的电阻小，第一接触层221向第二接触层222流动的载流子密度高。
步骤S250：形成阻挡结构，阻挡结构覆盖第二接触层的顶面和初始沟槽的暴露的侧壁。
步骤S260：形成导电结构，导电结构覆盖阻挡结构并填充未被填充的初始沟槽，导电结构通过金半接触结构和电容接触结构连接。
本实施例的步骤S210-S220和上述实施例步骤S110-S120的实现方式相同，步骤S250-S260和上述实施例步骤S140-S150的实现方式相同，在此，不再赘述。
本实施例中，金半接触结构包括第一接触层和第二接触层，第一接触层包括单层半导体材料，第二接触层包括第VA族半金属元素，单层半导体材料与第VA族半金属元素材料接触，减小了第一接触层和第二接触层的接触界面产生的肖特基势垒，第一接触层和第二接触层的接触界面形成良好的欧姆接触，从而减小了第一接触层与第二接触层之间的电阻。金半接触结构作为电容接触结构和导电结构实现电连接的中间过渡结构，减小了电容接触结构和导电结构之间的接触电阻，电容接触结构和导电结构之间的通态电流密度更高，提高了半导体结构向高性能化、高微缩化发展的潜力，可进一步缩小半导体器件的尺寸。第一接触层填充第一凹槽增加了第一接触层和第一凹槽的接触面积，第二接触层覆盖第一接触层的顶面以及初始沟槽暴露的部分侧壁，增加了第二接触层与导电结构的接触面积，进一步提高载流子从电容接触结构向导电结构的迁移率，提高电容接触结构和导电结构之间的通态电流密度。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图3所示，图3示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图。
如图3所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S310：提供初始结构。
示例性的，本实施例中提供初始结构，包括以下步骤：
S311：提供衬底。
如图20所示，衬底101可以由半导体材料制成，半导体材料可以为硅、 锗、硅锗化合物以及硅碳化合物中的任意一种或者多种。
S312：刻蚀衬底以形成阵列排布的多个有源区结构。
如图20所示，在衬底101的顶面形成光刻胶掩膜层102，如图21所示，光刻胶掩膜层102在衬底101上的投影暴露出衬底101的部分顶面，如图22所示，通过干法或湿法刻蚀去除光刻胶掩膜层102暴露出的部分衬底101，形成浅沟槽103。去除光刻胶掩膜层102，被光刻胶掩膜层102覆盖的衬底形成多个独立设置的有源区结构111，多个有源区结构111被浅沟槽103隔开。
S313：形成浅沟槽隔离结构，浅沟槽隔离结构用于隔离各有源区结构。
如图23所示，参照图22，采用化学气相沉积工艺(Chemical Vapor Deposition，CVD)、或原子层沉积工艺(Atomic layer deposition，ALD)，沉积低k介电材料填充浅沟槽103形成浅沟槽隔离结构112，浅沟槽隔离结构112将多个有源区结构111隔开。浅沟槽隔离结构112和有源区结构111形成基底110。在本实施例中，向浅沟槽103中沉积氧化硅形成浅沟槽隔离结构112。
S314：形成位线接触孔，位线接触孔暴露部分有源区结构以及部分浅沟槽隔离结构。
如图23所示，在有源区结构111和浅沟槽隔离结构112顶面形成第一掩膜层104，第一掩膜层104在衬底101上的投影暴露出部分有源区结构111以及部分浅沟槽隔离结构112。如图24所示，通过干法或湿法刻蚀工艺刻蚀去除第一掩膜层104暴露出的部分有源区结构111以及部分浅沟槽隔离结构112，形成位线接触孔105，如图25所示，位线接触孔105暴露部分有源区结构111以及部分浅沟槽隔离结构112。
S315：形成位线接触部，位线接触部填充位线接触孔。
如图26所示，参照图24，通过化学气相沉积工艺(Chemical Vapor Deposition，CVD)、或原子层沉积工艺(Atomic layer deposition，ALD)，沉积掺杂半导体材料形成位线接触部121，在本实施例中，位线接触部121的材料包括导电型掺杂多晶硅。
S316：形成位线结构。
如图27所示，参照图26，位线结构120设置在有源区结构111和浅沟槽隔离结构112的顶面，位线结构和位线接触部121连接，多条位线结构120相互平行，相邻的位线结构120间形成初始沟槽130，初始沟槽130暴露部分有源区结构111的顶面。
在本实施例中，提供初始结构，还包括如下的步骤：
S317：在初始沟槽中形成间隔结构，间隔结构的延伸方向垂直于位线结构的延伸方向。
如图28所示，参照图27，形成间隔结构150，间隔结构150位于初始沟槽130中覆盖部分初始沟槽130。如图28、图29所示，间隔结构150的设置方向与位线结构120的延伸方向垂直，间隔结构150暴露部分有源区结构111以及部分浅沟槽隔离结构112的顶面。
S318：以间隔结构和位线结构为掩膜，去除初始沟槽暴露出的部分有源区结构和浅沟槽隔离结构，形成电容接触孔。
如图5所示，参照图28、图29，通过干法或湿法刻蚀工艺刻蚀去除被间隔结构150和位线结构120暴露出的部分有源区结构111以及部分浅沟槽隔离结构112，形成电容接触孔140，电容接触孔140暴露部分有源区结构111以及部分浅沟槽隔离结构112。
步骤S320：形成电容接触结构，电容接触结构覆盖暴露出的部分有源区结构，电容接触结构包括第一凹槽。
示例性的，本实施例中形成电容接触结构210，包括以下步骤：如图6所示，参照图5，采用原子层沉积工艺(Atomic layer deposition，ALD)沉积掺杂多晶硅形成初始电容接触结构211，初始电容接触结构211填充电容接触孔140以及初始沟槽130。然后，如图7所示，参照图6，通过干法或湿法刻蚀工艺刻蚀初始电容接触结构211，将初始电容接触结构211回刻至低于基底110顶面，被保留的初始电容接触结构211形成电容接触结构210，电容接触结构210填充电容接触孔140以及部分初始沟槽130。最后，如图8所示，参照图7，刻蚀电容接触结构210的顶面，在电容接触结构210的顶面形成向基底110方向凹陷的第一凹槽215。
步骤S330：形成第一接触层，第一接触层覆盖电容接触结构的顶面。
如图16所示，参照图8，可以采用自上而下的剥离工艺(Lift-Off)或自下而上的低压金属有机化学气相沉积(Metal-organic Chemical Vapor Deposition，MOCVD)工艺，通过沉积第一接触材料形成第一接触层221，第一接触材料包括单层半导体材料(monolayer semiconductors)。
在本实施例中，第一接触材料包括的单层半导体材料为二维过渡金属硫属化合物(transition metal dichalcogenides，TMDs)。第一接触材料可以包括二硫化钼(MoS 2)、二硫化钨(WS 2)、二硫化铼(ReS 2)、二硒化钛(TiSe2)、二硒化铌(NbSe 2)、二硒化铼(ReSe 2)中的至少一种。
单层二维过渡金属硫属化合物(transition metal dichalcogenides，TMDs)包括三层原子层，三层原子层呈硫原子-过渡金属原子-硫原子的方式排列，单层二维过渡金属硫属化合物具有良好的半导体性质，平面载流子迁移率高。
在本实施例中，如图16所示，可以使用剥离工艺，形成三维半导体材料，通过剥离工艺去除三维半导体材中的单层原子层或多层原子层形成单层二维半导体材料，将单层二维半导体材料转移到电容接触结构210上，单层二维半导体材料覆盖电容接触结构的顶面形成第一接触层221。
步骤S340：形成第二接触层，第二接触层填充第一凹槽以及覆盖初始沟槽暴露的部分侧壁，第一接触层和第二接触层形成金半接触结构。
如图17所示，参照图16，可以通过电子束蒸发工艺加热蒸发或磁控溅射工艺溅射沉积第二接触材料形成第二接触层222，第二接触材料包括第VA族半金属元素的材料，第VA族半金属元素的材料覆盖在第一接触层221的顶面、并填充第一凹槽215以及初始沟槽130暴露的侧壁上。如图18所示，参照图17，刻蚀去除覆盖初始沟槽130的侧壁的部分材料，形成第二接触层222。第二接触材料可以包括化学元素周期表第四-第六周期，第VA族半金属元素砷(Arsenic，As)、锑(stibium，Sb)、铋(Bismuth，Bi)中的至少一种。
步骤S350：形成阻挡结构，阻挡结构覆盖第二接触层的顶面和初始沟槽的暴露的侧壁。
步骤S360：形成导电结构，导电结构覆盖阻挡结构并填充未被填充的初始沟槽，导电结构通过金半接触结构和电容接触结构连接。
本实施例的步骤S350-S360和上述实施例步骤S140-S150的实现方式相同，在此，不再赘述。
本实施例中的金半接触结构包括第一接触层和第二接触层，第一接触层覆盖电容接触结构的顶面，也即第一接触层呈底部向下的凹型结构，增加了第一接触层和第二接触层的接触面积，减小了金半接触结构的接触电阻；同时，第二接触层覆盖初始沟槽的部分侧壁，增加了第二接触层和导电结构的接触面积，减小了金半接触结构与导电结构的接触电阻，可进一步缩小半导体器件的尺寸。第一接触层的二维半导体材料和第二接触层包括第VA族半金属元素的接触界面产生的肖特基势垒较小，金半接触结构的接触电阻小， 使得从电容接触结构向导电结构流动的载流子迁移率更高。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图4所示，图4示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图。
如图4所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S410：提供初始结构。
如图5所示，初始结构100包括基底110以及设置在基底110上的多条位线结构120，相邻的位线结构120之间形成初始沟槽130，基底110包括有源区结构111，初始沟槽130暴露部分有源区结构111。
步骤S420：形成电容接触结构，电容接触结构覆盖暴露出的部分有源区结构，电容接触结构包括第一凹槽。
步骤S430：形成第一接触层，第一接触层覆盖电容接触结构的顶面，第一接触层的材料包括二硫化钼。
如图16所示，可以采用低压金属有机化学气相沉积工艺(Metal-organic Chemical Vapor Deposition，MOCVD)形成第一接触层221，在本实施例中，可以选用六羰基钼(Mo(CO) 6)和二乙基硫醚(C 4H 10S)分别作为钼(Mo)的前驱体和硫(S)的前驱体，也可以选用五氯化钼(MoCl 5)和六甲基二硅硫烷(HMDST)分别作为钼(Mo)的前驱体和硫(S)的前驱体，以氩气(Ar)作为载气，将钼(Mo)的前驱体和硫(S)的前驱体分别以蒸汽形式向半导体结构供应，钼(Mo)的前驱体和硫(S)的前驱体反应形成二硫化钼(Molybdenum disulfide，MoS 2)，二硫化钼沉积在电容接触结构210的顶面形成第一接触层221。
二硫化钼(Molybdenum disulfide，MoS 2)的平面载流子迁移率在200～500cm 2V -1s -1之间，禁带宽度为1.3eV，是一种间接禁隙的半导体材料，本实施例沉积在电容接触结构210上的二硫化钼为单层二硫化钼，单层二硫化钼的禁带宽度为1.8eV，是一种由间接禁隙转变为直接禁隙的半导体材料。
步骤S440：形成第二接触层，第二接触层填充第一凹槽以及覆盖初始沟槽暴露的部分侧壁，第二接触层的材料包括铋元素，第一触层和第二接触层形成金半接触结构。
如图17、图18所示，可以通过电子束蒸发工艺加热蒸发铋(Bismuth，Bi)或铋化合物形成第二接触层222。在本实施例中，沉积速率为
Figure PCTCN2022076171-appb-000001
第二接触层222覆盖第一接触层221的顶面、填充第一凹槽215以及初始沟槽130暴露的部分侧壁。
铋(Bismuth，Bi)是具有最高抗磁性的金属，具有高霍尔系数和电阻率。当铋的厚度降低到纳米量级时，铋的能带结构发生变化，铋的能带结构转化为其中一种子能带结构的自旋取向具有金属性，另一种子能带结构具有半导体性，纳米量级的铋具有半金属性。铋化合物也具有以上特性，例如，硒化铋(bismuth selenide，Bi 2Se 3)、碲化铋(Bismuth(III)telluride，Bi 2Te 3)。
如图19所示，第二接触层222和第一接触层221形成金半接触结构220，第二接触层222和第一接触层221的接触界面，第二接触层222和第一接触层221的接触界面，铋的费米能级高于二硫化钼的导带最小值，铋的pz轨道与二硫化钼pz和dz2轨道共振，铋和二硫化钼的接触界面的感性电偶极子的分布落入范德瓦尔斯间隙，二硫化钼的金属诱导间隙状态电子饱和，导致二硫化钼的间隙态饱和，铋和二硫化钼的接触界面实现零肖特基势垒，并且铋和二硫化钼的接触界面形成欧姆接触，降低了第二接触层222和第一接触层221的接触电阻。
步骤S450：形成阻挡结构，阻挡结构覆盖金半接触结构和初始沟槽的暴露的侧壁。
步骤S460：形成导电结构，导电结构覆盖阻挡结构并填充未被填充的初始沟槽，导电结构通过金半接触结构和电容接触结构连接。
本实施例的步骤S410-S420和上述实施例步骤S310-S320的实现方式相同，步骤S450-S460和上述实施例步骤S350-S360的实现方式相同，在此，不再赘述。
本实施例中，以半金属铋和半导体二硫化钼形成的金半接触结构作为电容接触结构和导电结构接触的中间过渡结构，避免电容接触结构的半导体材料和导电结构的金属材料直接接触，铋和二硫化钼的接触界面实现零肖特基势垒，载流子第一接触层和第二接触层之间迁移无需跃过势垒，从而铋和二硫化钼的接触界面形成良好的欧姆接触，金半接触结构的接触电阻达到最小。
本公开一示例性的实施例提供的一种半导体结构，如图15所示，参照图5，包括基底110和设置在基底110上的多条位线结构120。半导体结构还包括电容接触结构210，电容接触结构210包括第一凹槽215，电容接触结构210形成于相邻的位线结构120之间。半导体结构还包括金半接触结构220，金半接触结构220至少覆盖电容接触结构210的顶面并填充第一凹槽215的金半接触结构220。半导体结构还包括阻挡结构230以及导电结构240，阻挡结构230覆盖金半接触结构220和位线结构120的部分侧壁，导电结构240覆盖阻挡结构230，导电结构240通过金半接触结构220和电容接触结构210连接。在本实施例中，导电结构240的材料包括金属钨。
电容接触结构210的材料为掺杂半导体，电容接触结构的材料为n型或p型导电型掺杂多晶硅。
阻挡结构230的材料包括氮化钛、氮化铝、氮化硼、氮化铪、氮化钽、氮化钛或氮化锆中的任意一种或多种，在本实施例中，阻挡结构的材料为氮化钛。阻挡结构230的作用是防止导电结构240的材料向基底110中渗透导致基底110污染，以保证半导体结构的良率和使用寿命。
本实施例中形成的金半接触结构220包括二维半导体材料(two-dimensional semimetal)和具有半金属(half metal)特性的材料。具有半金属特性的材料的能带结构包括两种不同的子能带结构，其中的一种子能带结构的自旋取向具有金属性，另一种子能带结构具有半导体性。金半接触结构中220的二维半导体材料(two-dimensional semimetal)和具有半金属(half metal)特性的材料接触产生的肖特基势垒比电容接触结构210和后续形成的导电结构240直接接触产生的肖特基势垒小。
本实施例的半导体结构，如图15所示，在电容接触结构210和导电结构240之间设置金半接触结构220，金半接触结构220作为电容接触结构210和导电结构240连接的中间过渡结构，减小了电容接触结构210和导电结构240接触产生的肖特基势垒，可进一步减小半导体结构的尺寸，提高了半导体结构进一步微缩化发展的潜力。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图13所示，金半接触结构220包括：填充第一凹槽215以及覆盖位线结构120的部分侧壁的第一接触层221以及覆盖第一接触层221和位线结构120的部分侧壁的第二接触层222。
本实施例中，第一接触层221填充第一凹槽215增加而来第一接触层221和第一凹槽215的接触面积，第二接触层222覆盖第一接触层221的顶面以 及位线结构120的部分侧壁，增加了第二接触层222与导电结构240的接触面积，进一步提高载流子从电容接触结构210向导电结构240的迁移率，提高电容接触结构210和导电结构240之间的通态电流密度。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图19所示，金半接触结构220包括：覆盖电容接触结构210的顶面的第一接触层221以及填充第一凹槽215以及覆盖位线结构120的部分侧壁的第二接触层222。
本实施例中，第一接触层221覆盖电容接触结构210的顶面，也即第一接触层221呈底部向下的凹型结构，增加了第一接触层221和第二接触层222的接触面积，减小了金半接触结构220的接触电阻；同时，第二接触层222覆盖位线结构120的部分侧壁，增加了第二接触层222和导电结构240的接触面积，减小了金半接触结构220与导电结构240的接触电阻，可进一步缩小半导体结构的尺寸。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，第一接触层221的材料包括单层半导体材料，第二接触层222的材料包括第VA族元素。
在本实施例中，第一接触材料包括的单层半导体材料(monolayer semiconductors)为二维过渡金属硫属化合物(transition metal dichalcogenides，TMDs)。示例性的，第一接触材料可以包括二硫化钼(MoS 2)、二硫化钨(WS 2)、二硫化铼(ReS 2)、二硒化钛(TiSe 2)、二硒化铌(NbSe 2)、二硒化铼(ReSe 2)中的至少一种。
第二接触材料可以包括化学元素周期表第四-第六周期，第VA族半金属元素砷(Arsenic，As)、锑(stibium，Sb)、铋(Bismuth，Bi)中的至少一种。
本实施例中，金半接触结构220的第一接触层221和第二接触层222形成半金属-半导体接触界面，第二接触层222的第VA族半金属元素的费米能级接近第一接触层221的二维过渡金属硫属化合物的半导体导带的最小值，二维过渡金属硫属化合物价带饱和(间隙状态饱和)，第VA族半金属元素诱导二维过渡金属硫属化合物的产生的金属诱导间隙状态受到抑制，则在第一接触层221和第二接触层222的接触界面产生的肖特基势垒接近于零，肖特基势垒对金半接触结构220的接触电阻产生的影响可忽略不计，第一接触层221和第二接触层222形成良好的欧姆接触。本实施例中的金半接触结构220减小了电容接触结构210和导电结构240的接触电阻，电容接触结构210和导电结构240之间的载流子迁移率更大，通态电流密度更高，可进一步缩小半导体结构的尺寸，提高了半导体结构向高性能化、高微缩化发展的潜力。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图15所示，参照图5，基底110包括有源区结构111和浅沟槽隔离结构112，有源区结构111的顶面和浅沟槽隔离结构112的顶面平齐，相邻的位线结构120之间暴露出部分有源区结构111和浅沟槽隔离结构112。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图15所示，参照图5，半导体结构还包括：电容接触孔140，电容接触孔140设置在基底110上，电容接触孔140位于相邻的位线结构120之间，电容接触孔140暴露出部分有源区结构111和部分浅沟槽隔离结构112；电容接触结构210填充电容接触孔140。
本实施例中，在基底110上设置电容接触111以增大电容接触结构210和有源区结构111的接触面积，进一步减小了半导体结构的接触电阻。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全结构技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开的半导体结构的制作方法及半导体结构，金半接触结构作为电容接触结构和导电结构电连接的中间过渡结构，减小电容接触结构和导电结构的接触电阻。

Claims (15)

  1. 一种半导体结构的制作方法，所述半导体结构的制作方法包括：
    提供初始结构，所述初始结构包括基底以及设置在所述基底上的多条位线结构，相邻的所述位线结构之间形成初始沟槽，所述基底包括有源区结构，所述初始沟槽暴露部分所述有源区结构；
    形成电容接触结构，所述电容接触结构覆盖暴露出的部分所述有源区结构，所述电容接触结构包括第一凹槽；
    形成金半接触结构，所述金半接触结构至少覆盖所述电容接触结构的顶面并填充所述第一凹槽；
    形成阻挡结构，所述阻挡结构覆盖所述金半接触结构和所述初始沟槽的暴露的侧壁；
    形成导电结构，所述导电结构覆盖所述阻挡结构并填充未被填充的所述初始沟槽，所述导电结构通过所述金半接触结构和所述电容接触结构连接。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述形成金半接触结构，包括：
    形成第一接触层，所述第一接触层填充所述第一凹槽以及部分所述初始沟槽；
    形成第二接触层，所述第二接触层覆盖所述第一接触层的顶面以及所述初始沟槽暴露的部分侧壁。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，所述形成金半接触结构，包括：
    形成第一接触层，所述第一接触层覆盖所述电容接触结构的顶面；
    形成第二接触层，所述第二接触层填充所述第一凹槽以及覆盖所述初始沟槽暴露的部分侧壁。
  4. 根据权利要求2或3所述的半导体结构的制作方法，其中，所述形成第一接触层，包括：
    沉积第一接触材料形成所述第一接触层，所述第一接触材料包括单层半导体材料。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，所述形成第二接触层，包括：
    沉积第二接触材料形成所述第二接触层，所述第二接触材料包括第VA族半金属元素。
  6. 根据权利要求1所述的半导体结构的制作方法，其中，所述形成电容接触结构，包括：
    形成初始电容接触结构，所述初始电容接触结构填充所述初始沟槽；
    回刻所述初始电容接触结构，被保留的所述初始电容接触结构形成所述电容接触结构；
    刻蚀所述电容接触结构，在所述电容接触结构的顶面形成所述第一凹槽。
  7. 根据权利要求1所述的半导体结构的制作方法，其中，所述提供初始结构包括：
    提供衬底；
    刻蚀所述衬底以形成阵列排布的多个有源区结构；
    形成浅沟槽隔离结构，所述浅沟槽隔离结构用于隔离各所述有源区结构；
    形成位线接触孔，所述位线接触孔暴露部分所述有源区结构以及部分所述浅沟槽隔离结构；
    形成位线接触部，所述位线接触部填充所述位线接触孔；
    形成位线结构，所述位线结构设置在所述有源区结构和所述浅沟槽隔离结构的顶面，所述位线结构和所述位线接触部连接，多条所述位线结构相互平行，相邻的所述位线结构之间形成所述初始沟槽，所述初始沟槽暴露部分所述有源区结构的顶面。
  8. 根据权利要求7所述的半导体结构的制作方法，所述形成位线结构之后，还包括：
    在所述初始沟槽中形成间隔结构，所述间隔结构的延伸方向垂直于所述位线结构的延伸方向；
    以所述间隔结构和所述位线结构为掩膜，去除所述初始沟槽暴露出的部分所述有源区结构和所述浅沟槽隔离结构，形成电容接触孔。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，所述形成电容接触结构，包括：
    形成电容接触结构，所述电容接触结构填充所述电容接触孔以及部分所述初始沟槽。
  10. 一种半导体结构，包括：
    基底以及设置在所述基底上的多条位线结构；
    电容接触结构，形成于所述位线结构之间，所述电容接触结构包括第一凹槽；
    金半接触结构，所述金半接触结构至少覆盖所述电容接触结构的顶面并填充所述第一凹槽；
    阻挡结构，所述阻挡结构覆盖所述金半接触结构和所述位线结构的部分侧壁；
    导电结构，所述导电结构覆盖所述阻挡结构，所述导电结构通过所述金半接触结构和所述电容接触结构连接。
  11. 根据权利要求10所述的半导体结构，其中，所述金半接触结构包括：
    第一接触层，所述第一接触层填充所述第一凹槽以及覆盖所述位线结构的部分侧壁；
    第二接触层，所述第二接触层覆盖所述第一接触层和所述位线结构的部分侧壁。
  12. 根据权利要求10所述的半导体结构，其中，所述金半接触结构包括：
    第一接触层，所述第一接触层覆盖所述电容接触结构的顶面；
    第二接触层，所述第二接触层填充所述第一凹槽以及覆盖所述位线结构的部分侧壁。
  13. 根据权利要求11或12所述的半导体结构，其中，所述第一接触层的材料包括单层半导体材料，所述第二接触层的材料包括第VA族元素。
  14. 根据权利要求10所述的半导体结构，其中，所述基底包括有源区结构和浅沟槽隔离结构，所述有源区结构的顶面和所述浅沟槽隔离结构的顶面平齐，相邻的所述位线结构之间暴露出部分所述有源区结构和所述浅沟槽隔离结构。
  15. 根据权利要求14所述的半导体结构，所述半导体结构还包括：
    电容接触孔，所述电容接触孔设置在所述基底上，所述电容接触孔位于相邻的所述位线结构之间，所述电容接触孔暴露出部分所述有源区结构和所述浅沟槽隔离结构；所述电容接触结构填充所述电容接触孔。
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