WO2020124929A1 - 一种相变存储器及其制备方法 - Google Patents

一种相变存储器及其制备方法 Download PDF

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WO2020124929A1
WO2020124929A1 PCT/CN2019/085520 CN2019085520W WO2020124929A1 WO 2020124929 A1 WO2020124929 A1 WO 2020124929A1 CN 2019085520 W CN2019085520 W CN 2019085520W WO 2020124929 A1 WO2020124929 A1 WO 2020124929A1
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crystal film
dimensional crystal
phase change
change memory
lower electrode
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PCT/CN2019/085520
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French (fr)
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钟旻
陈寿面
李铭
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上海集成电路研发中心有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

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  • the invention relates to the field of integrated circuits, in particular to a phase change memory and a preparation method thereof.
  • the structure adopted in the current phase change memory is generally a 1T1R structure, that is, one triode plus one phase change material resistance, and the triode acts as a gate of the phase change material resistance.
  • the cell density of the phase change memory cannot be further increased.
  • the structure of 1D1R has emerged, that is, a structure with a diode and a phase-change material resistance.
  • Using a vertical diode instead of a triode as a strobe can greatly reduce the size of the phase-change memory device unit and improve memory storage. density.
  • the driving current of the conventional diode is generally not large enough to meet the operating current requirements of the phase change unit, and the manufacturing process is complicated. Therefore, a new type of phase change memory cell structure is needed to meet the high-density storage requirements of phase change memory devices.
  • the two-dimensional crystalline material generally refers to a material having a single-layer two-dimensional honeycomb grid structure, having an electronic band gap and high electron mobility.
  • Two-dimensional crystal materials generally include: silene, phosphorene, black phosphorus, germane, tinene, triazine-based graphite phase carbon nitride, transition metal disulfide (TMD), etc.
  • TMD transition metal disulfide
  • the transition metal disulfide (Transition Metal Dichalcogenide, TMD) has a chemical formula of MX 2 type, M is a metal, and X represents a chalcogen element (such as S, Se, Te).
  • TMD material Because the band gap of TMD material is very close to that of silicon, it has often been used to prepare two-dimensional transistors in recent years.
  • the transistor using a two-dimensional crystal film as a channel has far better performance than the existing silicon transistors, so it will become the most promising new transistor below 7nm.
  • the diode prepared by the two-dimensional crystal has small series resistance and high saturation electron drift speed, which can effectively improve the driving ability of the diode.
  • the contact resistance of the two-dimensional crystal material with any metal is very high, which affects the electrical performance of the two-dimensional crystal as a diode. Therefore, how to combine a diode prepared by a two-dimensional crystal and a phase change resistance into a phase change memory device unit is an urgent problem to be solved.
  • a phase-change memory device unit of a 1D1R structure composed of a diode prepared by a two-dimensional crystal and a phase-change resistor has a small cell size and can improve the phase Changing the storage density of the memory, while using graphene as the lower electrode, can reduce device power consumption.
  • a phase change memory includes a substrate, a doped layer, a diode, and a phase change resistor from bottom to top, wherein the substrate is doped layer above, so The doped layer and the substrate include at least two shallow trench isolations, the depth of the shallow trench isolation is greater than the depth of the doped layer; the diode is located between the two shallow trench isolations, the diode It includes a first two-dimensional crystal film and a second two-dimensional crystal film, and the first two-dimensional crystal film is in contact with the doped layer, and the second two-dimensional crystal film is located on the first two-dimensional crystal film Above, the phase change resistance includes a lower electrode, a sulfide with a phase change capability, and an upper electrode, wherein the lower electrode, the sulfide, and the upper electrode are sequentially positioned above the second two-dimensional crystal film.
  • the first two-dimensional crystal film includes one of silene, phosphorene, black phosphorous, germane, tinene, triazine-based graphite phase carbon nitride or transition metal disulfide;
  • the second The two-dimensional crystal film includes one of silene, phosphorene, black phosphorous, germane, tinene, triazine-based graphite phase carbon nitride, or transition metal disulfide.
  • transition metal disulfide is MoTe 2, MoS 2, MoSe 2 , WSe 2, ReSe 2, TaS 2, TaSe 2, TaTe 2, NbS 2, NbSe 2, NbTe 2, MoS 2, WTe 2 in At least one.
  • the first two-dimensional crystal film has N-type semiconductor properties
  • the second two-dimensional crystal film has metal properties
  • the first two-dimensional crystal film has N-type semiconductor properties
  • the second two-dimensional crystal film has P-type semiconductor properties
  • the sulfide with phase transformation capability includes at least one of the following systems: GeTe-Sb 2 Te 3 system, doped Sc, Ag, In, Al, In, C, S, Se, N, Cu , GeTe-Sb 2 Te 3 system, GeTe-SnTe system, at least one of W element, doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W element GeTe-SnTe system, Sb 2 Te system, Sb 2 Te system, In 3 SbTe 2 system doped with at least one of Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, In 3 SbTe 2 system, Sb doping system, doped Sc, Ag, In, Al, doped with at least one element of Sc, Ag, In, Al, In, C, S, Se, N, Cu, W Sb doping system of at least one of In, C, Se, N, Cu, and W elements.
  • the lower electrode is a graphene electrode.
  • the method for preparing a phase change memory includes the following steps:
  • S04 depositing a first two-dimensional crystal film, a second two-dimensional crystal film and a lower electrode on the surface separated by the doped layer and the shallow trench in sequence;
  • S05 Deposit sulfide with phase change ability and upper electrode in sequence on the surface of the lower electrode;
  • a first two-dimensional crystal film having an N-type semiconductor property, a second two-dimensional crystal film having a metallic property, and a graphene lower electrode are sequentially deposited on the doped layer and the shallow trench isolation surface;
  • the first two-dimensional crystal film, the second two-dimensional crystal film and the lower electrode are deposited and grown under the same conditions.
  • a first two-dimensional crystal film having an N-type semiconductor property, a second two-dimensional crystal film having a P-type semiconductor property and a graphene lower electrode are sequentially deposited on the doped layer and the shallow trench isolation surface .
  • a diode prepared by using a two-dimensional crystal has a small series resistance, a high saturation electron drift speed, and can effectively improve the driving capability of the diode.
  • Graphene is used as the lower electrode to contact the two-dimensional crystal film. Due to the similar structure of the lower electrode and the two-dimensional crystal film, the contact resistance between the two is very small, which can effectively improve the electrical performance of the two-dimensional crystal diode.
  • graphene as the lower electrode can avoid the phenomenon that the two-dimensional crystal film of the diode diffuses into the phase change resistance.
  • graphene has very good thermal conductivity and high carrier mobility.
  • the lower electrode of the phase change resistance As the lower electrode of the phase change resistance, it can improve the heating efficiency of the phase change layer and reduce the power consumption of the device. Therefore, the 1D1R structure of a phase change memory device unit composed of a diode and a phase change resistor made of a two-dimensional crystal film has a small cell size, which can increase the storage density of the phase change memory, and the use of graphene as the lower electrode can reduce Device power consumption.
  • Figure 1 is a structural diagram of a doped layer formed on a substrate
  • FIG. 2 is a structural diagram of forming grooves on the doped layer
  • Figure 3 is a structural diagram of forming a shallow trench isolation
  • FIG. 4 is a structural diagram after sequentially depositing a first two-dimensional crystal film, a second two-dimensional crystal film and a lower electrode;
  • FIG. 5 is a structural diagram after sequentially depositing a sulfide with phase transformation ability and an upper electrode.
  • FIG. 6 is a structural diagram of a phase change memory finally formed.
  • phase change memory cell 101 substrate, 102 doped layer, 103 groove, 104 shallow trench isolation, 105 first two-dimensional crystal film, 106 second two-dimensional crystal film, 107 lower electrode, 108 sulfide with phase change ability , 109 upper electrode, 110 phase change memory cell.
  • a doped layer 102 is formed on the surface of the substrate 101 by ion implantation.
  • a conventional P-type Si substrate 101 may be used, and an N-type heavily doped layer 102 may be formed on the surface of the P-type Si substrate 101 by ion implantation.
  • the implanted element may be As.
  • a groove 103 is formed in the doped layer and the substrate by photolithography, and the depth of the groove is greater than the depth of the doped layer.
  • the groove 103 is formed by photolithography and etching, and the depth of the groove exceeds the doped layer 102.
  • S03 Please refer to FIG. 3, fill the groove with insulating material, and planarize to form a shallow trench isolation 104. Fill the groove with an insulating material of SiO 2 and planarize the wafer surface through a polishing process to form a shallow trench isolation 104.
  • S04 Please refer to FIG. 4 to deposit the first two-dimensional crystal film, the second two-dimensional crystal film and the lower electrode on the surface separated by the doped layer and the shallow trench in sequence, wherein the first two-dimensional crystal film and the second two The dimensional crystal films are all made of two-dimensional materials.
  • the first two-dimensional crystal film and the second two-dimensional crystal film have the following two different situations:
  • a first two-dimensional crystal film 105 with N-type semiconductor properties, a second two-dimensional crystal film 106 with metal properties and a graphene lower electrode 107 are deposited on the doped layer and the shallow trench isolation surface in sequence
  • the one-dimensional crystal film, the second two-dimensional crystal film and the graphene lower electrode are deposited and grown in the same device, and chemical vapor deposition or atomic layer deposition can be used.
  • the first two-dimensional crystal film 105 is a transition metal disulfide MoS 2 with N-type semiconductor properties
  • the second two-dimensional crystal film 106 is a transition metal disulfide MoTe 2
  • the deposition equipment may be chemical vapor deposition or atomic layer deposition equipment.
  • the first two-dimensional crystal film with semiconductor properties and the second two-dimensional crystal film with metal properties form a Schottky diode with a small series resistance and a high saturation electron drift speed, which can effectively improve the driving capability of the diode.
  • a first two-dimensional crystal film 105 having N-type semiconductor properties, a second two-dimensional crystal film material 106 having P-type semiconductor properties, and a graphene lower electrode 107 are sequentially deposited on the doped layer and the shallow trench isolation surface.
  • the doping element may include As, P, and the like.
  • the doping element may include B, In, and the like.
  • the first two-dimensional crystal film 105 having N-type semiconductor properties may be in-situ P-doped silene, and the second two-dimensional crystal film 106 having P-type semiconductor properties may be black phosphorus.
  • the N-type first two-dimensional crystal film and the P-type second two-dimensional crystal film form a PN junction diode with a small series resistance and a high saturation electron drift speed, which can effectively improve the driving capability of the diode.
  • the materials selected for the first two-dimensional crystal film and the second two-dimensional crystal film may be silene, phosphorene, black phosphorus, germane, tinene, triazine-based graphite phase carbon nitride or Transition metal disulfide.
  • the transition metal disulfides include but are not limited to MoTe 2, MoS 2, MoSe 2 , WSe 2, ReSe 2, TaS 2, TaSe 2, TaTe 2, NbS 2, NbSe 2, NbTe 2, MoS 2, WTe 2 at least One kind.
  • the present invention uses graphene as the lower electrode to contact the two-dimensional crystal film. Due to the similar structure of the two-dimensional crystal film and the graphene, the contact resistance between the two is very small, which can effectively improve the electrical performance of the two-dimensional crystal diode. Moreover, graphene as the lower electrode can avoid the phenomenon that the two-dimensional crystal film of the diode diffuses into the phase change resistance. In addition, graphene has very good thermal conductivity and high carrier mobility. As the lower electrode of the phase change resistance, it can improve the heating efficiency of the phase change layer and reduce the power consumption of the device.
  • S05 Please refer to FIG. 5, and sequentially deposit sulfide with phase change ability and the upper electrode on the surface of the lower electrode.
  • the chalcogenide compound with phase transformation ability includes at least one of GeTe-Sb 2 Te 3 system, GeTe-SnTe system, Sb 2 Te system, In 3 SbTe 2 system, Sb doping system, or includes doped Sc , Ag, In, Al, In, C, S, Se, N, Cu, W element GeTe-Sb 2 Te 3 system, GeTe-SnTe system, Sb 2 Te system, In 3 SbTe 2 system, Sb doping system At least one of them.
  • a sulfide 108 and an upper electrode 109 having a phase change ability are sequentially deposited on the wafer surface.
  • the sulfide used is C-doped Ge 2 Sb 2 Te 5 and the upper electrode is TiN.
  • the upper electrode 109, the sulfide with phase change ability 108, the graphene lower electrode 107, the second two-dimensional crystal film 106 and the first two-dimensional crystal film 105 are patterned by a photolithography etching process. All the films above the shallow trench isolation (Shallow Isolation, STI) are removed, and finally a phase change memory cell 110 composed of a Schottky diode and a phase change resistor is formed between the two shallow trench isolations. The lateral dimension of the cell 110 is smaller than the distance between two shallow trench isolations.
  • a phase change memory provided in the present invention includes a substrate, a doped layer, a diode, and a phase change resistor from bottom to top, wherein the substrate is above the doped layer, and the doped layer and the substrate include at least two A shallow trench isolation, the depth of the shallow trench isolation is greater than the depth of the doped layer; the diode is located between the two shallow trench isolations, the diode includes a first two-dimensional crystal film and a second two-dimensional crystal film, and the first two The two-dimensional crystal film is in contact with the doped layer. The second two-dimensional crystal film is located above the first two-dimensional crystal film.
  • the phase change resistance includes a lower electrode, a sulfide with phase change capability, and an upper electrode. The upper electrode and the upper electrode are sequentially located above the second two-dimensional crystal film.

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Abstract

本发明公开的一种相变存储器，自下而上包括衬底、掺杂层、二极管和相变电阻，其中，所述衬底的上方为掺杂层，所述掺杂层和衬底中包括至少两个浅沟槽隔离；所述二极管位于两个浅沟槽隔离之间，所述二极管包括第一二维晶体膜和第二二维晶体膜，所述第二二维晶体膜位于所述第一二维晶体膜的上方，所述相变电阻包括下电极、具有相变能力的硫化物和上电极，其中，所述下电极、硫化物和上电极依次位于所述第二二维晶体膜上方。本发明提供的一种相变存储器及其制备方法，采用二维晶体制备的二极管和相变电阻组成的1D1R结构的相变存储器器件单元，其单元尺寸很小，可以提升相变存储器的存储密度，同时采用石墨烯作为下电极，能降低器件功耗。

Description

一种相变存储器及其制备方法
交叉引用
本申请要求2018年12月20日提交的申请号为CN 201811567463.0的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及集成电路领域，具体涉及一种相变存储器及其制备方法。
技术背景
随着大数据、物联网、云计算和移动互联网等一系列的新型信息技术的出现，对存储器提出了高读写速度、低功耗、高存储密度、长使用寿命和高可靠性等要求。目前内存的存储方式主要是DRAM+Flash，NAND Flash的集成度高、成本低，但是速度慢、寿命短。DRAM虽然速度快，寿命长，但是掉电后会丢失数据且成本高。因此研发出一种新型的存储技术成为业界近年来的研究热点，该类新型存储技术须同时拥有DRAM和NAND Flash的优点，即读写速度可与DRAM相匹敌，在成本和非易失性方面与NAND Flash相似，而相变存储器正是这类新型存储技术中的一员。
目前的相变存储器采用的结构一般是1T1R结构即1个三极管加上1个相变材料电阻，三极管作为相变材料电阻的选通器。但是，由于受到三极管的尺寸限制，无法进一步提高相变存储器的单元密度。近几年，出现1D1R的结构即采用1个二极管加上1个相变材料电阻的结构，采用垂直型二极管替代三极管作为选通器，可以大大降低相变存储器器件单元的尺寸，提高存储器的存储密度。但是，一般传统的二极管驱动电流不够大，不能满足相变单元的操作电流要求，并且制作工艺复杂。因此，需要一种新型的相变存储 单元结构，满足相变存储器器件的高密度存储的需求。
近几年来，二维晶体材料制备晶体管技术发展迅猛。二维晶体材料通常是指具有单层二维蜂窝状网格结构、有电子能带隙和高的电子迁移率的材料。二维晶体材料一般包括：硅烯，磷烯，黑磷，锗烯、锡烯、三嗪基石墨相氮化碳，过渡金属二硫化物(TMD)等。过渡金属二硫化物(Transition Metal Dichalcogenide，TMD)的化学式为MX 2型，M为金属，X代表硫族元素(如S、Se、Te)。由于TMD材料的带隙与硅很接近，近年来常被用于制备二维晶体管。采用二维晶体膜作为沟道的晶体管，其性能远超现有的硅晶体管，因而将成为7nm以下最具前景的新型晶体管。
采用二维晶体制备的二极管，其串联电阻小，饱和电子漂移速度高，能有效提高二极管的驱动能力。但是二维晶体材料与任何金属接触，其接触电阻很高，影响了二维晶体作为二极管的电学性能。因此，如何将二维晶体制备的二极管和相变电阻结合成为相变存储器器件单元是亟待解决的问题。
发明概要
本发明所要解决的技术问题是提供一种相变存储器及其制备方法，采用二维晶体制备的二极管和相变电阻组成的1D1R结构的相变存储器器件单元，其单元尺寸很小，可以提升相变存储器的存储密度，同时采用石墨烯作为下电极，能降低器件功耗。
为了实现上述目的，本发明采用如下技术方案：一种相变存储器，自下而上包括衬底、掺杂层、二极管和相变电阻，其中，所述衬底的上方为掺杂层，所述掺杂层和衬底中包括至少两个浅沟槽隔离，所述浅沟槽隔离的深度大于所述掺杂层的深度；所述二极管位于两个浅沟槽隔离之间，所述二极管 包括第一二维晶体膜和第二二维晶体膜，且所述第一二维晶体膜与所述掺杂层接触，所述第二二维晶体膜位于所述第一二维晶体膜的上方，所述相变电阻包括下电极、具有相变能力的硫化物和上电极，其中，所述下电极、硫化物和上电极依次位于所述第二二维晶体膜上方。
进一步地，所述第一二维晶体膜包括硅烯，磷烯，黑磷，锗烯、锡烯、三嗪基石墨相氮化碳或过渡金属二硫化物中的一种；所述第二二维晶体膜包括硅烯，磷烯，黑磷，锗烯、锡烯、三嗪基石墨相氮化碳或过渡金属二硫化物中的一种。
进一步地，所述过渡金属二硫化物为MoTe 2、MoS 2、MoSe 2、WSe 2、ReSe 2、TaS 2、TaSe 2、TaTe 2、NbS 2、NbSe 2、NbTe 2、MoS 2、WTe 2中的至少一种。
进一步地，所述第一二维晶体膜具有N型半导体性质，所述第二二维晶体膜具有金属性质。
进一步地，所述第一二维晶体膜具有N型半导体性质，所述第二二维晶体膜具有P型半导体性质。
进一步地，所述具有相变能力的硫化物包括以下体系中的至少一种：GeTe-Sb 2Te 3体系、掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的GeTe-Sb 2Te 3体系、GeTe-SnTe体系、掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的GeTe-SnTe体系、Sb 2Te体系、掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的Sb 2Te体系、In 3SbTe 2体系、掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的In 3SbTe 2体系、Sb掺杂体系、掺杂Sc、Ag、In、Al、In、 C、S、Se、N、Cu、W元素中至少一种的Sb掺杂体系。
进一步地，所述下电极为石墨烯电极。
本发明提供的一种制备相变存储器的方法，包括如下步骤：
S01：在衬底表面通过离子注入形成掺杂层；
S02：通过光刻刻蚀在掺杂层和衬底中形成凹槽，且凹槽的深度大于掺杂层的深度；
S03：在凹槽中填充绝缘材料，并平坦化形成浅沟槽隔离；
S04：依次在掺杂层和浅沟槽隔离的表面沉积第一二维晶体膜、第二二维晶体膜和下电极；
S05：依次在下电极的表面沉积具有相变能力的硫化物和上电极；
S06：通过光刻刻蚀工艺图形化上电极、具有相变能力的硫化物、下电极、第二二维晶体膜和第一二维晶体膜，在两个浅沟槽之间形成包括二极管和相变电阻的相变存储器单元。
进一步地，所述步骤S04中依次在掺杂层和浅沟槽隔离表面沉积具有N型半导体性质的第一二维晶体膜、具有金属性质的第二二维晶体膜和石墨烯下电极；所述第一二维晶体膜、第二二维晶体膜和下电极在相同条件下沉积生长。
进一步地，所述步骤S04中依次在掺杂层和浅沟槽隔离表面沉积具有N型半导体性质的第一二维晶体膜、具有P型半导体性质的第二二维晶体膜和石墨烯下电极。
本发明的有益效果为：本发明中采用二维晶体制备的二极管，其串联电阻小，饱和电子漂移速度高，能有效提高二极管的驱动能力。采用石墨烯作为下电极与二维晶体膜接触，由于下电极与二维晶体膜结构相似，两者接触 电阻很小，能有效提升二维晶体二极管的电学性能。并且，石墨烯作为下电极能避免二极管的二维晶体膜扩散至相变电阻的现象。另外，石墨烯具有非常好的热传导性能和很高的载流子迁移率，作为相变电阻的下电极，可以提高相变层的加热效率，降低器件功耗。因此，采用二维晶体膜制备的二极管和相变电阻组成的1D1R结构的相变存储器器件单元，其单元尺寸很小，可以提升相变存储器的存储密度，同时采用石墨烯作为下电极，能降低器件功耗。
附图说明
附图1为衬底上形成掺杂层的结构图；
附图2为掺杂层上形成凹槽的结构图；
附图3为形成浅沟槽隔离的结构图；
附图4为依次沉积第一二维晶体膜、第二二维晶体膜和下电极之后的结构图；
附图5为依次沉积具有相变能力的硫化物和上电极之后的结构图。
附图6为最终形成的相变存储器的结构图。
图中：101衬底，102掺杂层，103凹槽，104浅沟槽隔离，105第一二维晶体膜，106第二二维晶体膜，107下电极，108具有相变能力的硫化物，109上电极，110相变存储器单元。
发明内容
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式做进一步的详细说明。
请参阅附图1-6，为本发明制备相变存储器的方法，具体包括如下步骤：
S01：请参阅附图1，在衬底101表面通过离子注入形成掺杂层102。具 体地，可采用常规P型Si衬底101，在P型Si衬底101上通过离子注入，在表面形成N型的重掺杂层102。在本实施例中，注入元素可以是As。
S02：请参阅附图2，通过光刻刻蚀在掺杂层和衬底中形成凹槽103，且凹槽的深度大于掺杂层的深度。通过光刻刻蚀形成凹槽103，凹槽的深度超过掺杂层102。
S03：请参阅附图3，在凹槽中填充绝缘材料，并平坦化形成浅沟槽隔离104。在凹槽中填充绝缘材料为SiO 2，并通过抛光工艺平坦化晶片表面，形成浅沟道隔离104。
S04：请参阅附图4，依次在掺杂层和浅沟槽隔离的表面沉积第一二维晶体膜、第二二维晶体膜和下电极，其中，第一二维晶体膜和第二二维晶体膜均为二维材料制备而成。
本步骤中第一二维晶体膜和第二二维晶体膜有以下两种不同的情况：
(1)依次在掺杂层和浅沟槽隔离表面沉积具有N型半导体性质的第一二维晶体膜105、具有金属性质的第二二维晶体膜106和石墨烯下电极107，第一二维晶体膜、第二二维晶体膜和石墨烯下电极是在同一台设备中沉积生长的，可以采用化学气相沉积或者原子层沉积的方法。
具体地，第一二维晶体膜105为过渡金属二硫化物具有N型半导体性质的MoS 2，第二二维晶体膜106为过渡金属二硫化物MoTe 2，由于过渡金属二硫化物在空气中不稳定，因此需要和石墨烯在同一台沉积设备中连续生长，有效减少了二维晶体膜和石墨烯之间的界面缺陷，减低了接触电阻，提高了肖特基二极管的电学性能。沉积设备可以是化学气相沉积或者原子层沉积设备。具有半导体性质的第一二维晶体膜和具有金属性质的第二二维晶体膜形成一个肖特基二极管，其串联电阻小，饱和电子漂移速度高，能有效提高二极管的驱动能力。
(2)依次在掺杂层和浅沟槽隔离表面沉积具有N型半导体性质的第一二维晶体膜105和具有P型半导体性质的第二二维晶体膜材料106和石墨烯下电极107。
本发明中若第一二维晶体膜本身具有N型半导体性质，则可以直接沉积不做掺杂处理，若本身不具有N型半导体性质，则可以在沉积时进行N型原位掺杂来形成具有N型半导体性质的第一二维晶体膜，掺杂元素可以包括As，P等。同样地，若第二二维晶体膜本身具有P型半导体性质，则可以直接沉积不做掺杂处理，若本身不具有P型半导体性质，则可以在沉积时进行P型原位掺杂来形成具有P型半导体性质的第二二维晶体膜，掺杂元素可以包括B、In等。具体地，具有N型半导体性质的第一二维晶体膜105可以是原位P掺杂的硅烯，具有P型半导体性质的第二二维晶体膜106可以是黑磷。N型的第一二维晶体膜和P型的第二二维晶体膜形成一个PN结二极管，其串联电阻小，饱和电子漂移速度高，能有效提高二极管的驱动能力。
上述两种情况中，第一二维晶体膜和第二二维晶体膜所选用的材料均可以为硅烯，磷烯，黑磷，锗烯、锡烯、三嗪基石墨相氮化碳或过渡金属二硫化物。过渡金属二硫化物包括但不限于MoTe 2、MoS 2、MoSe 2、WSe 2、ReSe 2、TaS 2、TaSe 2、TaTe 2、NbS 2、NbSe 2、NbTe 2、MoS 2、WTe 2中的至少一种。
本发明采用石墨烯作为下电极与二维晶体膜接触，由于二维晶体膜和石墨烯结构相似，两者接触电阻很小，能有效提升二维晶体二极管的电学性能。并且，石墨烯作为下电极能避免二极管的二维晶体膜扩散至相变电阻的现象。另外，石墨烯具有非常好的热传导性能和很高的载流子迁移率，作为相变电阻的下电极，可以提高相变层的加热效率，降低器件功耗。
S05：请参阅附图5，依次在下电极的表面沉积具有相变能力的硫化物和上电极。
其中，具有相变能力的硫系化合物包括GeTe-Sb 2Te 3体系、GeTe-SnTe体系、Sb 2Te体系、In 3SbTe 2体系、Sb掺杂体系中的至少一种，或者包括掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素的GeTe-Sb 2Te 3体系、GeTe-SnTe体系、Sb 2Te体系、In 3SbTe 2体系、Sb掺杂体系中的至少一种。在本实施例中，依次在晶片表面沉积具有相变能力的硫化物108和上电极109，采用的硫化物为C掺杂的Ge 2Sb 2Te 5，上电极为TiN。
S06：请参阅附图6，通过光刻刻蚀工艺图形化上电极、具有相变能力的硫化物、下电极、第二二维晶体膜和第一二维晶体膜，在两个浅沟槽之间形成包括二极管和相变电阻的相变存储器。
在本实施例中，通过光刻刻蚀工艺图形化上电极109、具有相变能力的硫化物108、石墨烯下电极107、第二二维晶体膜106和第一二维晶体膜105，将浅沟槽隔离(Shallow Trench Isolation,STI)上方的所有膜去除，最后在两个浅沟槽隔离之间形成由一个肖特基二极管和一个相变电阻组成的相变存储器单元110，相变存储器单元110的横向尺寸小于两个浅沟槽隔离之间的距离。
本发明中提供的一种相变存储器，自下而上包括衬底、掺杂层、二极管和相变电阻，其中，衬底的上方为掺杂层，掺杂层和衬底中包括至少两个浅沟槽隔离，浅沟槽隔离的深度大于掺杂层的深度；二极管位于两个浅沟槽隔离之间，二极管包括第一二维晶体膜和第二二维晶体膜，且第一二维晶体膜与掺杂层接触，第二二维晶体膜位于第一二维晶体膜的上方，相变电阻包括下电极、具有相变能力的硫化物和上电极，其中，下电极、硫化物和上电极依次位于第二二维晶体膜上方。
以上所述仅为本发明的优选实施例，所述实施例并非用于限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明所附权利要求的保护范围内。

Claims (10)

  1. 一种相变存储器，其特征在于，自下而上包括衬底、掺杂层、二极管和相变电阻，其中，所述衬底的上方为掺杂层，所述掺杂层和衬底中包括至少两个浅沟槽隔离，所述浅沟槽隔离的深度大于所述掺杂层的深度；所述二极管位于两个浅沟槽隔离之间，所述二极管包括第一二维晶体膜和第二二维晶体膜，且所述第一二维晶体膜与所述掺杂层接触，所述第二二维晶体膜位于所述第一二维晶体膜的上方，所述相变电阻包括下电极、具有相变能力的硫化物和上电极，其中，所述下电极、硫化物和上电极依次位于所述第二二维晶体膜上方。
  2. 根据权利要求1所述的一种相变存储器，其特征在于，所述第一二维晶体膜包括硅烯，磷烯，黑磷，锗烯、锡烯、三嗪基石墨相氮化碳或过渡金属二硫化物中的一种；所述第二二维晶体膜包括硅烯，磷烯，黑磷，锗烯、锡烯、三嗪基石墨相氮化碳或过渡金属二硫化物中的一种。
  3. 根据权利要求2所述的一种相变存储器，其特征在于，所述过渡金属二硫化物为MoTe 2、MoS 2、MoSe 2、WSe 2、ReSe 2、TaS 2、TaSe 2、TaTe 2、NbS 2、NbSe 2、NbTe 2、MoS 2、WTe 2中的至少一种。
  4. 根据权利要求1所述的一种相变存储器，其特征在于，所述第一二维晶体膜具有N型半导体性质，所述第二二维晶体膜具有金属性质。
  5. 根据权利要求1所述的一种相变存储器，其特征在于，所述第一二维晶体膜具有N型半导体性质，所述第二二维晶体膜具有P型半导体性质。
  6. 根据权利要求1所述的一种相变存储器，其特征在于，所述具有相变能力的硫化物包括以下体系中的至少一种：GeTe-Sb 2Te 3体系、掺杂Sc、 Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的GeTe-Sb 2Te 3体系、GeTe-SnTe体系、掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的GeTe-SnTe体系、Sb 2Te体系、掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的Sb 2Te体系、In 3SbTe 2体系、掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的In 3SbTe 2体系、Sb掺杂体系、掺杂Sc、Ag、In、Al、In、C、S、Se、N、Cu、W元素中至少一种的Sb掺杂体系。
  7. 根据权利要求1所述的一种相变存储器，其特征在于，所述下电极为石墨烯电极。
  8. 一种制备相变存储器的方法，其特征在于，包括如下步骤：
    S01：在衬底表面通过离子注入形成掺杂层；
    S02：通过光刻刻蚀在掺杂层和衬底中形成凹槽，且凹槽的深度大于掺杂层的深度；
    S03：在凹槽中填充绝缘材料，并平坦化形成浅沟槽隔离；
    S04：依次在掺杂层和浅沟槽隔离的表面沉积第一二维晶体膜、第二二维晶体膜和下电极；
    S05：依次在下电极的表面沉积具有相变能力的硫化物和上电极；
    S06：通过光刻刻蚀工艺图形化上电极、具有相变能力的硫化物、下电极、第二二维晶体膜和第一二维晶体膜，在两个浅沟槽之间形成包括二极管和相变电阻的相变存储器单元。
  9. 根据权利要求8所述的制备相变存储器的方法，其特征在于，所述步骤S04中依次在掺杂层和浅沟槽隔离表面沉积具有N型半导体性质的第一 二维晶体膜、具有金属性质的第二二维晶体膜和石墨烯下电极；所述第一二维晶体膜、第二二维晶体膜和下电极在同一设备中沉积生长。
  10. 根据权利要求8所述的制备相变存储器的方法，其特征在于，所述步骤S04中依次在掺杂层和浅沟槽隔离表面沉积具有N型半导体性质的第一二维晶体膜、具有P型半导体性质的第二二维晶体膜和石墨烯下电极。
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