WO2023019631A1 - 拼接显示装置 - Google Patents

拼接显示装置 Download PDF

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Publication number
WO2023019631A1
WO2023019631A1 PCT/CN2021/115202 CN2021115202W WO2023019631A1 WO 2023019631 A1 WO2023019631 A1 WO 2023019631A1 CN 2021115202 W CN2021115202 W CN 2021115202W WO 2023019631 A1 WO2023019631 A1 WO 2023019631A1
Authority
WO
WIPO (PCT)
Prior art keywords
liquid crystal
crystal display
frame area
display device
spliced
Prior art date
Application number
PCT/CN2021/115202
Other languages
English (en)
French (fr)
Inventor
郑峰
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/607,249 priority Critical patent/US20240019727A1/en
Publication of WO2023019631A1 publication Critical patent/WO2023019631A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13336—Combining plural substrates to produce large-area displays, e.g. tiled displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes

Definitions

  • the present application relates to the field of display technology, in particular to a spliced display device.
  • the purpose of the present application is to provide a splicing display device capable of reducing splicing seams.
  • the present application provides a splicing display device, which includes:
  • the liquid crystal display panels include a first frame area, and the first frame areas of the two liquid crystal display panels are adjacently arranged;
  • the light emitting diode chip is arranged on the first frame area.
  • the liquid crystal display panel includes an array substrate and an opposite substrate, the array substrate is disposed opposite to the opposite substrate, the opposite substrate includes a substrate, and the light emitting diode chip is located on the The substrate is away from the surface of the array substrate.
  • the substrate is provided with a scan line and a data line, the anode of the light emitting diode chip is connected to the data line, and the cathode of the light emitting diode chip is connected to the scan line.
  • the substrate is provided with a thin film transistor array and a fan-out line connected to the thin film transistor array
  • the light emitting diode chip is located on a side of the thin film transistor array away from the substrate, and
  • the orthographic projection of the light emitting area formed by the light emitting diode chip on the plane where the thin film transistor array is located covers part of the fan-out lines.
  • the spliced display device includes a backlight module and a chip-on-chip, the backlight module is arranged on the side of the array substrate away from the opposite substrate, and the chip-on-film is located adjacent to Between the two first frame regions, one end of the COF is connected to the LED chip, and the other end is disposed on the surface of the backlight module away from the array substrate.
  • a groove is formed on the side wall of the substrate, and the spliced display device further includes a fan-out line, one end of the fan-out line is connected to the LED chip, and the other end of the fan-out line is One end extends into the groove and is connected with the COF.
  • the spliced display device includes four liquid crystal display panels, every two of the liquid crystal display panels are arranged in a row along the first direction, and every two of the liquid crystal display panels are aligned with the first direction.
  • a second direction perpendicular to one direction is arranged in columns, and the liquid crystal display panel further includes a second frame area intersecting with the first frame, and the two liquid crystal display panels spliced in the first direction.
  • the first frame area is adjacently arranged
  • the second frame area of the two liquid crystal display panels spliced in the second direction is adjacently arranged
  • the light emitting diode chip is also arranged on the second frame area .
  • the liquid crystal display panel further includes a third frame area and a fourth frame area, the third frame area is opposite to the first frame area, and the fourth frame area is opposite to the first frame area.
  • the two frame areas are opposite to each other, the third frame area is bound with a source driver, and the fourth frame area is provided with a gate drive circuit.
  • the liquid crystal display panel includes a plurality of pixels, and the distance between two adjacent light emitting diode chips is equal to the distance between two adjacent pixels in the liquid crystal display panel.
  • the light-emitting diode chip is a blue light-emitting diode chip
  • the spliced display device includes an encapsulation layer
  • the encapsulation layer encapsulates the light-emitting diode chip
  • the encapsulation layer includes a first encapsulation part and a second encapsulation part.
  • Two packaging parts the first packaging part is provided with a red quantum dot color film on the surface facing the light emitting diode chip, and the second packaging part is provided with a green quantum dot color film on the surface facing the light emitting diode chip.
  • the present application also provides a spliced display device, including:
  • the liquid crystal display panel includes a first frame area and a second frame area intersecting the first frame, and the first frame areas of the two liquid crystal display panels spliced in the first direction are arranged adjacently , the second frame regions of the two liquid crystal display panels spliced in the second direction are arranged adjacent to each other; and
  • the light emitting diode chip is arranged on the first frame area and the second frame area.
  • the splicing seam of the spliced display device is reduced by arranging light-emitting diode chips in the frame area where two liquid crystal display panels are spliced to display images.
  • FIG. 1 is a schematic top view of a spliced display device according to a first embodiment of the present application.
  • FIG. 2 is a cross-sectional view of the spliced display device in FIG. 1 along line A-A.
  • FIG. 3 is a schematic top view of two first frame regions of the spliced display device in FIG. 1 .
  • FIG. 4 is an enlarged schematic view of part O of the spliced display device in FIG. 1 .
  • FIG. 5 is a schematic structural diagram of the light emitting diode chip and the encapsulation layer of the spliced display device in FIG. 1 .
  • FIG. 6 is a schematic top view of two first frame regions of the spliced display device according to the second embodiment of the present application.
  • FIG. 7 is a schematic top view of the first frame area of the spliced display device according to the third embodiment of the present application.
  • FIG. 8 is an enlarged schematic view of part O of the spliced display device in FIG. 7 .
  • a first feature being “on” or “below” a second feature may include the first and second features directly, or may include that the first and second features are not directly connected but through another characteristic contact between them.
  • “above”, “above” and “above” the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.
  • "Below”, “beneath” and “under” the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.
  • a spliced display device 100 includes two spliced liquid crystal display panels 10 : a first liquid crystal display panel 11 and a second liquid crystal display panel 12 .
  • the liquid crystal display panel 10 is used instead of the first liquid crystal display panel 11 and the second liquid crystal display panel 12 for description.
  • the liquid crystal display panel 10 includes a display area AA and a first frame area BA1 , a second frame area BA2 , a third frame area BA3 and a fourth frame area BA4 surrounding the display area AA.
  • the first frame area BA1 is opposite to the third frame area BA3, and the second frame area BA2 is opposite to the fourth frame area BA4.
  • the second border area BA2 intersects the first border area BA1 and the third border area BA3 respectively
  • the fourth border area BA4 also intersects the first border area BA1 and the third border area BA3 respectively.
  • the first frame areas BA1 of the two liquid crystal display panels 10 are adjacently arranged. That is, the first border area BA1 is the border where the two liquid crystal display panels 10 are spliced. No driving chip or driving circuit is disposed in the first frame area BA1.
  • the second frame area BA2 is not provided with a driving chip or a driving circuit.
  • the third frame area BA3 may be provided with a gate driver circuit, for example, a GOA (Gate Driver On Array) circuit.
  • the fourth frame area BA4 can be connected with the source driver SD of the liquid crystal display panel 10 .
  • the driver chip or driver circuit can be installed in the second frame area BA2, the third frame area BA3 and the fourth frame area. In at least one of areas BA4. Since the first frame area BA1 is not provided with a driver circuit and a driver chip, its width is narrower than that of the third frame area BA3 and the fourth frame area BA4 provided with a drive circuit or a driver. Splicing is performed at the border area BA1.
  • the first liquid crystal display panel 11 and the second liquid crystal display panel 12 are arranged in the first direction D1.
  • the first direction D1 may be a horizontal direction.
  • the two spliced liquid crystal display panels 10 have a symmetrical structure.
  • the first frame area BA1 is the right frame area
  • the second frame area BA2 is the bottom frame area
  • the third frame area BA3 is the left frame area
  • the fourth frame area BA4 is the top frame area.
  • the first border area BA1 is the left border area
  • the second border area BA2 is the lower border area
  • the third border area BA3 is the right border area
  • the fourth border area BA4 is the upper border area.
  • the first liquid crystal display panel 11 and the second liquid crystal display panel 12 may also be arranged in a second direction D2 perpendicular to the first direction D1 , ie, a vertical direction.
  • the first frame area BA1 is the lower frame area
  • the third frame area BA3 is the upper frame area.
  • the second liquid crystal display panel 12 the first frame area BA1 is the upper frame area
  • the third frame area BA3 is the lower frame area.
  • the LED chip 30 is disposed on the first frame area BA1 of the spliced display device 100 provided in the present application. Specifically, the LED chip 30 may be disposed in the first frame area BA1 of the two liquid crystal display panels 10 , or the LED chip 30 may be disposed in the first frame area BA1 of one of the two liquid crystal display panels 10 .
  • the light emitting diode chip 30 cooperates with the liquid crystal display panel 10 to display a complete picture.
  • the light emitting diode chip 30 may be a mini-LED chip or a micro-LED (micro light emitting diode) chip.
  • the splicing seam of the spliced display device is reduced or even eliminated by disposing the light emitting diode chip 30 in the frame area where the two liquid crystal display panels 10 are spliced to display images.
  • the signal can be simultaneously transmitted to the liquid crystal display panel 10 and the light emitting diode chip 30 through the network cable and the receiving card, so that the light emitting diode chip 30 displays a continuous image with the display area AA of the liquid crystal display panel 10, so as to keep the displayed continuity.
  • the splicing display device 100 of the present application uses the LCD display panel as the main and a small number of light emitting diode chips 30 are arranged in the frame area, thereby obtaining a highly reliable and low-cost spliced display device 100 .
  • the liquid crystal display panel 10 includes an array substrate 11 , an opposite substrate 12 , and a sealant 13 and liquid crystal (not shown) located between the array substrate 11 and the opposite substrate 12 .
  • the array substrate 11 is opposite to the opposite substrate 12 .
  • the opposite substrate 12 includes a substrate 121 and a surface color filter layer 122 disposed on the substrate 121 close to the array substrate 11 .
  • the material of the substrate 121 can be plastic or glass.
  • the LED chip 30 is disposed on the surface of the substrate 121 away from the array substrate 11 , that is, the upper surface of the substrate 121 .
  • the light-emitting diode chip 30 When the light-emitting diode chip 30 is a mini-LED chip, it can be surface mounted (SMT) or solid crystal/chip (Die Bonding) is formed on the substrate 121 . When the light emitting diode chip 30 is a micro-LED chip, it can be fixed on the substrate 121 by mass transfer. By arranging the light emitting diode chip 30 on the glass or plastic substrate 121, the original structure of the liquid crystal display panel 10 can be used to set the light emitting diode chip 30, and because the technology of forming the light emitting diode chip 30 on glass or plastic is relatively mature , can reduce the manufacturing process difficulty of the spliced display device of the present application.
  • SMT surface mounted
  • Die Bonding die Bonding
  • the LED chip 30 may adopt a passive matrix (PM: Passive Matrix) driving mode.
  • PM Passive Matrix
  • a plurality of scan lines Scan and a plurality of data lines Data are arranged on the first frame area BA1.
  • a plurality of data lines Data extend along the first direction D1 and are arranged at intervals along the second direction D2.
  • a plurality of fan-out lines F are also arranged on the first frame area BA1.
  • Each fan-out line F is connected to a data line Data, converges around one of the fan-out lines F, and is then connected to a source driver (not shown).
  • a plurality of scan lines Scan extend along the second direction D2 and are arranged at intervals along the first direction D1.
  • a gate driver 40 for driving the LED chip 30 is also disposed on the fourth frame area BA4 .
  • a plurality of scan lines Scan is connected to the gate driver 40 .
  • the anode of the LED chip 30 is connected to the data line Data, and the cathode of the LED chip 30 is connected to the scan line Scan. Since the PM driving method does not require a thin film transistor, only data lines Data and scan lines need to be set, which greatly simplifies the driving circuit and reduces manufacturing difficulty and cost.
  • the light emitting diode chip 30 driven by PM driving mode is sufficient to meet the display resolution of the frame area.
  • the source driver SD2 of the light emitting diode chip 30 is bonded by side bonding technology.
  • the spliced display device 100 includes a backlight module 50 and a COF 60 .
  • the backlight module 50 is disposed on the side of the array substrate 11 away from the opposite substrate 12 for providing backlight to the liquid crystal display panel 10 .
  • each liquid crystal display panel 10 corresponds to a backlight module 50 .
  • the COF 60 is located between two adjacent first frame areas BA1 , that is, between two adjacent liquid crystal display panels 10 and the backlight module 50 .
  • One end of the COF 60 is connected to the LED chip 30 , and the other end is disposed on the surface of the backlight module 50 away from the array substrate 11 .
  • a groove 121a is formed on the sidewall of the first frame area BA1. More specifically, a plurality of grooves 121a are formed on the sidewall of the substrate 121 in the first frame area BA1 by laser drilling or mechanical drilling. One end of the plurality of fan-out lines F is connected to the LED chip 30 through the data line Data, and the other end extends to the edge of the first frame area BA1 , is disposed in the groove 121 a to form a bonding pad, and is connected to the COF 60 .
  • the material of the fan-out line F may be copper.
  • the chip-on-chip film 60 is connected to the bonding pad formed by the fan-out line F in the groove 121a, extends along the gap between the two first frame areas BA1, and is bent to the surface of the backlight module 50 away from the array substrate 11, Then perform the bonding of the source driver SD2 of the LED chip 30 .
  • the bonding method of the COF 60 is not limited to the above method, for example, the COF 60 may also be bonded by grinding the first frame area BA1 to expose the signal line to form a bonding pad.
  • FIG. 2 shows the binding manner of the first liquid crystal display panel 11 and the COF, and the binding manner of the second liquid crystal display panel 12 and the COF is also the same, and its description is omitted.
  • the source driver SD2 of the light-emitting diode chip 30 is bonded by side-bonding technology, which can narrow the non-display area generated by disposing the light-emitting diode chip 30 .
  • the spliced display device 100 also includes a cover plate 70 and an optical glue 80 .
  • the cover plate 70 is disposed on a side of the liquid crystal display panel 10 away from the backlight module 50 .
  • the optical adhesive 80 adheres the cover plate 70 to the liquid crystal display panel 10 and the LED chips 30 .
  • the optical adhesive 80 is a transparent colloid, and serves as a flat layer to flatten the surface of the substrate 121 on which the LED chip 30 is disposed, so as to facilitate the installation of the cover plate 70 .
  • a plurality of LED chips 30 are arranged in an array.
  • the liquid crystal display panel 10 includes a plurality of sub-pixels PX.
  • a plurality of sub-pixels PX are also arranged in an array.
  • the distance between two adjacent light emitting diode chips 30 is equal to the distance between two adjacent sub-pixels PX in the liquid crystal display panel 10 .
  • the “pitch” shown herein refers to the distance between the centers of two adjacent LED chips 30 , or the distance between the centers of two adjacent sub-pixels PX.
  • “Spacing” includes horizontal spacing and vertical spacing.
  • the lateral pitch refers to the pitch between two adjacent LED chips 30 or sub-pixels PX in the horizontal direction, that is, the first direction D1.
  • the vertical distance refers to the distance between two adjacent LED chips 30 or sub-pixels PX in the vertical direction, that is, the distance in the second direction D2.
  • the lateral pitch P1 between two adjacent LED chips 30 is equal to the lateral pitch P2 between two adjacent sub-pixels PX in the liquid crystal display panel 10 .
  • the vertical pitch P3 between two adjacent LED chips 30 is equal to the vertical pitch P4 between two adjacent sub-pixels PX in the liquid crystal display panel 10 . If the distance between two adjacent light-emitting diode chips 30 is not consistent with the distance between two adjacent sub-pixels PX of the liquid crystal display panel 10 , display mura will be generated at the joint. By keeping both at the same pitch, the mura at the splice can be reduced.
  • a plurality of LED chips 30 are arranged in a row along the first direction D1.
  • Each row of LED chips 30 is aligned with a row of sub-pixels PX of the LCD panel 10 .
  • the center of each row of light-emitting diode chips 30 is on the same straight line as the center of a row of sub-pixels PX of the liquid crystal display panel 10 , further preventing mura at the splicing seam.
  • the light emitting diode chip 30 is a blue light emitting diode chip 30 .
  • the spliced display device 100 also includes an encapsulation layer 90 .
  • the encapsulation layer 90 encapsulates the LED chip 30 .
  • the package layer 90 includes a first package part (package) 91 , a second package part 92 and a third package part 93 . Each package part surrounds one LED chip 30 from above the substrate 121 .
  • a red Quantum Dots Color Filter (QDCF) R is provided on the surface of the first packaging part 91 facing the LED chip 30
  • a green Quantum Dots Color Filter G is provided on the surface of the second packaging part 92 facing the LED chip 30 .
  • the surface of the third packaging part 93 facing the LED chip 30 is not provided with a quantum dot color film, or only provided with a transparent film layer. Due to the high cost of directly using the LED chips 30 of three colors, the present application adopts the blue LED chip 30 to cooperate with the QDCF film to convert colors and then mix colors. If the quantum dot film is used directly, because the QD film cannot achieve 100% color conversion and the color purity is not high, it needs to use the CF film to filter. This application uses QDCF film for conversion, which can improve color purity and reduce film thickness.
  • the difference between the spliced display device 100 of the second embodiment of the present application and the first embodiment is that:
  • the splicing display device 100 of the second embodiment of the present application adopts an active matrix (Active Matrix) driving mode for driving.
  • a thin film transistor array TA and a scan line Scan and a data line Data connected to the thin film transistor array TA are disposed on the substrate 121 .
  • a plurality of fan-out lines F are also provided on the upper surface of the substrate 121 . Each fan-out line F is connected to a data line Data, converges around a fan-out line F, and is then connected to a source driver (not shown).
  • the light emitting diode chip 30 is located on the side of the thin film transistor array TA away from the substrate 121 , and the orthographic projection of the light emitting area LA formed by the light emitting diode chip 30 on the plane where the thin film transistor array TA is located covers part of the fan-out line F.
  • the light-emitting diode chip 30 of this embodiment can narrow the Outer Lead Bonding (OLB) region to tens of microns by disposing part of the fan-out line F below the light-emitting area LA formed by the light-emitting diode chip 30 , thereby The non-display area generated for driving the light emitting diode chip 30 is reduced.
  • OLB Outer Lead Bonding
  • the difference between the spliced display device 100 of the third embodiment of the present application and the first embodiment is that:
  • the spliced display device 100 includes four liquid crystal display panels 10 , and the four liquid crystal display panels 10 are arranged in a 2 ⁇ 2 manner. Specifically, every two liquid crystal display panels 10 are arranged in rows along the first direction D1, and every two liquid crystal display panels 10 are arranged in columns along the second direction D2 perpendicular to the first direction D1.
  • the first frame areas BA1 of the two liquid crystal display panels 10 spliced in the first direction D1 are arranged adjacent to each other.
  • the second frame areas BA2 of the two liquid crystal display panels 10 spliced in the second direction D2 are adjacently arranged.
  • the spliced display device 100 includes a first liquid crystal display panel 11 , a second liquid crystal display panel 12 , a third liquid crystal display panel 13 and a fourth liquid crystal display panel 14 .
  • the first liquid crystal display panel 11 and the second liquid crystal display panel 12 are spliced in the first direction D1
  • the third liquid crystal display panel 13 and the fourth liquid crystal display panel 14 are spliced in the first direction D1.
  • the third liquid crystal display panel 13 is spliced with the first liquid crystal display panel 11 in the second direction D2
  • the fourth liquid crystal display panel 14 is spliced with the second liquid crystal display panel 12 in the second direction D2.
  • the first liquid crystal display panel 11 has the same structure as the fourth liquid crystal display panel 14
  • the second liquid crystal display panel 12 has the same structure as the third liquid crystal display panel 13
  • the first liquid crystal display panel 11 and the second liquid crystal display panel 12 have a symmetrical structure.
  • Neither the first frame area BA1 nor the second frame area BA2 is provided with a driving chip or a driving circuit.
  • the third border area BA3 may be provided with a gate driving circuit.
  • the fourth frame area BA4 can set a fan-out (fan-out) line of the data line Data, and bind the source driver SD.
  • the four liquid crystal display panels 10 are spliced in the frame area where no driving chip or driving circuit is provided, thereby reducing the splicing seam.
  • the light emitting diode chip 30 is also disposed on the second frame area BA2.
  • the encapsulation layer, the scanning line, the data line, etc. on the second frame area BA2 reference may be made to the structure of the first frame area BA1 described in the first embodiment.
  • the light emitting diode chip 30 on the second border area BA2 can also be driven by PM and AM, for details, please refer to the light emitting diode chip 30 in the first border area BA1 in the first embodiment and the second embodiment, which is omitted here. its description.
  • the splicing seam of the spliced display device is reduced or eliminated by arranging light-emitting diode chips in the frame area where two liquid crystal display panels are spliced to display images.
  • the light-emitting diode chip adopts a PM driving method, which can not only meet the resolution requirement of the frame area, but also simplify the driving circuit and reduce manufacturing difficulty and cost.
  • the source driver of the light emitting diode chip is bonded using a side bonding technology, which can narrow the non-display area generated by the arrangement of the light emitting diode chip.
  • the distance between two adjacent light emitting diode chips is equal to the distance between two adjacent sub-pixels in the liquid crystal display panel, which can reduce the mura at the spliced frame area.
  • the light-emitting diode chip is driven by AM, and the fan-out line is arranged under the light-emitting diode chip, which can narrow the non-display area caused by the arrangement of the light-emitting diode chip.
  • a spliced display device including four liquid crystal display panels arranged in a 2 ⁇ 2 manner can be provided.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种拼接显示装置（100），其包括拼接的两个液晶显示面板（10）和发光二极管芯片（30）。液晶显示面板（10）包括第一边框区（BA1），两个液晶显示面板（10）的第一边框区（BA1）相邻设置。发光二极管芯片（30）设置于第一边框区（BA1）上。

Description

拼接显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种拼接显示装置。
 背景技术
着眼于大数据、融媒体以及会议等高阶大屏的显示需求，各大厂商在积极布局拼接技术。有机发光二极管（Organic Light-Emitting Diode，OLED）以及次毫米发光二极管（mini-LED）等拼接屏因成本及信赖性等问题无法大规模推广，而使液晶器（Liquid Crystal Display，LCD）拼接屏成为市面上的主流产品。但，LCD的边框区无法显示画面，从而导致LCD拼接屏产生视觉上的拼接缝。因此，如何减小拼接显示屏的拼接缝已经成为各大厂商的迫切期望。
 技术问题
有鉴于此，本申请目的在于提供一种能够减小拼接缝的拼接显示装置。
 技术解决方案
本申请提供一种拼接显示装置，其包括：
拼接的两个液晶显示面板，所述液晶显示面板包括第一边框区，两个所述液晶显示面板的所述第一边框区相邻设置；以及
发光二极管芯片，设置于所述第一边框区上。
在一种实施方式中，所述液晶显示面板包括阵列基板和对向基板，所述阵列基板与所述对向基板相对设置，所述对向基板包括衬底，所述发光二极管芯片位于所述衬底远离所述阵列基板的表面。
在一种实施方式中，所述衬底上设置有扫描线和数据线，所述发光二极管芯片的阳极连接于所述数据线，所述发光二极管芯片的阴极连接于所述扫描线。
在一种实施方式中，所述衬底上设置有薄膜晶体管阵列以及连接于所述薄膜晶体管阵列的扇出线，所述发光二极管芯片位于所述薄膜晶体管阵列远离所述衬底的一侧，且所述发光二极管芯片形成的发光区域在所述薄膜晶体管阵列所在平面上的正投影覆盖部分所述扇出线。
在一种实施方式中，所述拼接显示装置包括背光模组和覆晶薄膜，所述背光模组设置于所述阵列基板远离所述对向基板的一侧，所述覆晶薄膜位于相邻两个所述第一边框区之间，并且所述覆晶薄膜的一端连接于所述发光二极管芯片，另一端设置于所述背光模组远离所述阵列基板的表面。
在一种实施方式中，所述衬底的侧壁上开设有凹槽，所述拼接显示装置还包括扇出线，所述扇出线的一端连接于所述发光二极管芯片，所述扇出线的另一端延伸至所述凹槽内，并与所述覆晶薄膜连接。
在一种实施方式中，所述拼接显示装置包括四个所述液晶显示面板，每两个所述液晶显示面板沿第一方向排列成行，且每两个所述液晶显示面板沿与所述第一方向垂直的第二方向排列成列，所述液晶显示面板还包括与所述第一边框相交的第二边框区，在所述第一方向上拼接的两个所述液晶显示面板的所述第一边框区相邻设置，在所述第二方向上拼接的两个所述液晶显示面板的所述第二边框区相邻设置，所述发光二极管芯片还设置于所述第二边框区上。
在一种实施方式中，所述液晶显示面板还包括与第三边框区和第四边框区，所述第三边框区与所述第一边框区相对，所述第四边框区与所述第二边框区相对，所述第三边框区上绑定源极驱动器，所述第四边框区中设置有栅极驱动电路。
在一种实施方式中，所述液晶显示面板包括多个像素，相邻两个所述发光二极管芯片之间的间距与所述液晶显示面板中相邻两个像素之间的间距相等。
在一种实施方式中，所述发光二极管芯片为蓝色发光二极管芯片，所述拼接显示装置包括封装层，所述封装层封装所述发光二极管芯片，所述封装层包括第一封装部和第二封装部，所述第一封装部朝向所述发光二极管芯片的表面设置有红色量子点彩膜，所述第二封装部朝向所述发光二极管芯片的表面设置有绿色量子点彩膜。
本申请还提供一种拼接显示装置，包括：
拼接的四个所述液晶显示面板，每两个所述液晶显示面板沿第一方向排列成行，且每两个所述液晶显示面板沿与所述第一方向垂直的第二方向排列成列，所述液晶显示面板包括第一边框区和与所述第一边框相交的第二边框区，在所述第一方向上拼接的两个所述液晶显示面板的所述第一边框区相邻设置，在所述第二方向上拼接的两个所述液晶显示面板的所述第二边框区相邻设置；和
发光二极管芯片，设置于所述第一边框区和所述第二边框区上。
 有益效果
根据本申请的拼接显示装置，通过在两个液晶显示面板拼接处的边框区设置发光二极管芯片以显示图像，减小拼接显示装置的拼接缝。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施方式的拼接显示装置的俯视示意图。
图2为图1的拼接显示装置沿A-A线的剖视图。
图3为图1的拼接显示装置的两个第一边框区的俯视示意图。
图4为图1的拼接显示装置的O部的放大示意图。
图5为图1的拼接显示装置的发光二极管芯片和封装层的结构示意图。
图6为本申请第二实施方式的拼接显示装置的两个第一边框区的俯视示意图。
图7为本申请第三实施方式的拼接显示装置的第一边框区的俯视示意图。
图8为图7的拼接显示装置的O部的放大示意图。
 本发明的实施方式
下面将结合本申请实施方式中的附图，对本申请中的技术方案进行清楚、完整地描述。显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接，也可以包括第一和第二特征不是直接连接而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
请参考图1，本申请第一实施方式的拼接显示装置100包括拼接的两个液晶显示面板10：第一液晶显示面板11和第二液晶显示面板12。需要说明的是，本文在描述第一液晶显示面板11和第二液晶显示面板12的共同点时，以液晶显示面板10代替第一液晶显示面板11和第二液晶显示面板12来进行描述。液晶显示面板10包括显示区AA和包围显示区AA的第一边框区BA1、第二边框区BA2、第三边框区BA3以及第四边框区BA4。第一边框区BA1与第三边框区BA3相对，第二边框区BA2与第四边框区BA4相对。第二边框区BA2与第一边框区BA1与第三边框区BA3分别相交，第四边框区BA4也与第一边框区BA1与第三边框区BA3分别相交。
两个液晶显示面板10的第一边框区BA1相邻设置。即，第一边框区BA1为两个液晶显示面板10拼接处的边框。第一边框区BA1中不设置驱动芯片或者驱动电路。第二边框区BA2不设置驱动芯片或者驱动电路。第三边框区BA3可以设置栅极驱动电路，例如，GOA（阵列基板行驱动，Gate Driver On Array）电路。第四边框区BA4可以并绑定液晶显示面板10的源极驱动器SD。可以理解，在本实施方式中，只要在第一边框区BA1中不设置驱动芯片或者驱动电路即可，驱动芯片或者驱动电路可以设置于第二边框区BA2、第三边框区BA3和第四边框区BA4的至少一个中。第一边框区BA1由于没有设置驱动电路和驱动芯片，其宽度较设置有驱动电路或者驱动器的第三边框区BA3和第四边框区BA4要窄，因而，两个液晶显示面板10可以在第一边框区BA1处进行拼接。
可选的，第一液晶显示面板11与第二液晶显示面板12在第一方向D1上排列。第一方向D1可以为水平方向。拼接的两个液晶显示面板10具有对称结构。对于第一液晶显示面板11而言，第一边框区BA1为右边框，第二边框区BA2为下边框区，第三边框区BA3为左边框区，第四边框区BA4为上边框区。对于第二液晶显示面板12而言，第一边框区BA1为左边框，第二边框区BA2为下边框区，第三边框区BA3为右边框区，第四边框区BA4为上边框区。当然，第一液晶显示面板11与第二液晶显示面板12也可以在于第一方向D1垂直的第二方向D2，即垂直方向上排列。在这种情况下，对于第一液晶显示面板11而言，第一边框区BA1为下边框，第三边框区BA3为上边框区。则对于第二液晶显示面板12而言，第一边框区BA1为上边框，第三边框区BA3为下边框区。
在显示区AA进行显示的时候，两个液晶显示面板10的两个第一边框区 BA1呈现黑色，而产生视觉上的拼接缝。对此，本申请提供的拼接显示装置100的第一边框区BA1上设置有发光二极管芯片30。具体地，可以在两个液晶显示面板10的第一边框区BA1均设置发光二极管芯片30，也可以在两个液晶显示面板10的其中一个的第一边框区BA1设置发光二极管芯片30。发光二极管芯片30与液晶显示面板10配合显示完整画面。发光二极管芯片30可以为mini-LED芯片或者micro-LED（微发光二极管）芯片。
根据本申请的拼接显示装置100，通过在两个液晶显示面板10拼接处的边框区设置发光二极管芯片30以显示图像，减小甚至消除拼接显示装置的拼接缝。可选的，可以通过网线及接收卡将信号同时传输到液晶显示面板10和发光二极管芯片30，以使发光二极管芯片30显示与液晶显示面板10的显示区AA显示连续的图像，以保持显示的连续性。由于LCD显示面板的信赖性比OLED、micro-LED和mini-LED显示面板好，且成本比OLED、micro-LED和mini-LED显示面板低，本申请的拼接显示装置100使用LCD显示面板作为主要的显示面板，并在边框区设置少量的发光二极管芯片30，从而获得了信赖性高，且成本低的拼接显示装置100。
请参考图2，液晶显示面板10包括阵列基板11、对向基板12以及位于阵列基板11与对向基板12之间的框胶13和液晶（未图示）。阵列基板11与对向基板12相对设置。对向基板12包括衬底121和设置于衬底121靠近阵列基板11的表面彩膜层122等。衬底121的材料可以为塑料或者玻璃。发光二极管芯片30设置于衬底121远离阵列基板11的表面，即，衬底121的上表面。当发光二极管芯片30为mini-LED芯片时，可以通过表面贴装（SMT）或者固晶/贴片（Die Bonding）方式形成在衬底121上。当发光二极管芯片30为micro-LED芯片时，可以通过巨量转移方式固定到衬底121上。通过将发光二极管芯片30设置在玻璃或者塑料的衬底121上，能够利用液晶显示面板10原有的结构来设置发光二极管芯片30，并且由于在玻璃或者塑料上形成发光二极管芯片30的技术较为成熟，能够降低本申请的拼接显示装置的制程难度。
可选的，请参考图3，发光二极管芯片30可以采用被动矩阵（PM：Passive Matrix）驱动模式。具体地，第一边框区BA1上设置有多条扫描线Scan和多条数据线Data。多条数据线Data沿第一方向D1延伸，且沿第二方向D2间隔设置。第一边框区BA1上还设置有多条扇出线F。每一扇出线F连接于一条数据线Data，并以其中一条扇出线F为中心汇聚，再连接于源极驱动器（未图示）。多条扫描线Scan沿第二方D2向延伸，且沿第一方向D1间隔设置。第四边框区BA4上还设置有用于驱动发光二极管芯片30的栅极驱动器40。多条扫描线Scan连接至栅极驱动器40。发光二极管芯片30的阳极连接于数据线Data，发光二极管芯片30的阴极连接于扫描线Scan。由于PM驱动方式不需要设置薄膜晶体管，只需要设置数据线Data和扫描线Scan，大大简化了驱动电路，降低了制造难度和制造成本。另一方面，以PM驱动方式驱动的发光二极管芯片30就足以满足边框区的显示分辨率。
请再次参考图2，发光二极管芯片30的源极驱动器SD2采用侧绑定技术进行绑定。具体地，拼接显示装置100包括背光模组50和覆晶薄膜60。背光模组50设置于阵列基板11远离对向基板12的一侧，用于对液晶显示面板10提供背光。具体地，每一液晶显示面板10对应于一个背光模组50。覆晶薄膜60位于相邻两个第一边框区BA1之间，即位于相邻两个液晶显示面板10与背光模组50之间。覆晶薄膜60的一端连接于发光二极管芯片30，另一端设置于背光模组50远离阵列基板11的表面。可选的，第一边框区BA1的侧壁上开设有凹槽121a。更具体的，通过激光打孔或者机械钻孔的方式在第一边框区BA1的衬底121的侧壁上形成多个凹槽121a。多条扇出线F的一端经由数据线Data连接至发光二极管芯片30，另一端延伸至第一边框区BA1的边缘，设置于凹槽121a内形成绑定垫，并与覆晶薄膜60连接。扇出线F的材料可以为铜。覆晶薄膜60与凹槽121a中的由扇出线F形成的绑定垫连接，并沿两个第一边框区BA1之间的空隙延伸，弯折至背光模组50远离阵列基板11的表面，再进行发光二极管芯片30的源极驱动器SD2的绑定。可以理解，覆晶薄膜60的绑定方式不限于上述方式，例如，也可以采用研磨第一边框区BA1暴露出信号线以形成绑定垫的方式来绑定覆晶薄膜60。图2中示出了第一液晶显示面板11与覆晶薄膜的绑定方式，第二液晶显示面板12与覆晶薄膜的绑定方式也是一样的，省略其说明。在本实施方式中，发光二极管芯片30的源极驱动器SD2采用侧绑定技术进行绑定，能够缩窄由于设置发光二极管芯片30而产生的非显示区。
进一步，拼接显示装置100还包括盖板70和光学胶80。盖板70设置于液晶显示面板10远离背光模组50的一侧。光学胶80贴合盖板70与液晶显示面板10和发光二极管芯片30。光学胶80为透明胶体，并作为平坦层，使衬底121设置有发光二极管芯片30的表面平坦化，便于设置盖板70。
请参考图4，可选的，多个发光二极管芯片30呈阵列排布。液晶显示面板10包括多个子像素PX。多个子像素PX也呈阵列排布。相邻两个发光二极管芯片30之间的间距与液晶显示面板10中相邻两个子像素PX之间的间距相等。本文中所示的“间距”是指相邻两个发光二极管芯片30的中心之间的间距，或者相邻两个子像素PX之间的中心之间的间距。“间距”包括横向间距和纵向间距。横向间距是指相邻两个发光二极管芯片30或者子像素PX在水平方向，即第一方向D1上的间距。纵向间距是指相邻两个发光二极管芯片30或者子像素PX在竖直方向，即第二方向D2上的间距。相邻两个发光二极管芯片30之间的横向间距P1与液晶显示面板10中相邻两个子像素PX之间的横向间距P2相等。相邻两个发光二极管芯片30之间的纵向间距P3与液晶显示面板10中相邻两个子像素PX之间的纵向间距P4相等。如果相邻两个发光二极管芯片30之间的间距与液晶显示面板10的相邻两个子像素PX之间的间距不一致，则会导致拼接处产生显示mura。通过使二者保持相同间距，能够减小拼接处的mura。进一步，多个发光二极管芯片30沿第一方向D1排列成行。每一行发光二极管芯片30与液晶显示面板10的一行子像素PX对齐。具体地，每一行发光二极管芯片30的中心与液晶显示面板10的一行子像素PX的中心在同一条直线上，进一步防止拼接缝处的mura。
可选的，请参考图5，发光二极管芯片30为蓝色发光二极管芯片30。拼接显示装置100还包括封装层90。封装层90封装发光二极管芯片30。封装层90包括第一封装部（package）91、第二封装部92以及第三封装部93。每一封装部从衬底121的上方包围一个发光二极管芯片30。第一封装部91朝向发光二极管芯片30的表面设置有红色量子点彩膜（Quantum Dots Color Filter，QDCF）R，第二封装部92朝向发光二极管芯片30的表面设置有绿色量子点彩膜G。第三封装部93朝向发光二极管芯片30的表面不设置量子点彩膜，或者仅设置透明膜层。由于直接使用三种颜色的发光二极管芯片30成本高，本申请采用蓝色发光二极管芯片30配合QDCF膜转换颜色再进行混色。如果直接用量子点膜，因为QD膜无法实现百分之百颜色转换，色纯度不高，需要用到CF膜去过滤。本申请使用QDCF膜进行转换，能够提高色纯度，并降低膜层厚度。
请参考图6，本申请第二实施方式的拼接显示装置100与第一实施方式的不同之处在于：
本申请第二实施方式的拼接显示装置100采用主动矩阵（Active Matrix）驱动模式进行驱动。衬底121上设置有薄膜晶体管阵列TA以及连接于薄膜晶体管阵列TA的扫描线Scan和数据线Data。衬底121的上表面还设置有多条扇出线F。每一扇出线F连接于一条数据线Data，并以一条扇出线F为中心汇聚，再连接于源极驱动器（未图示）。发光二极管芯片30位于薄膜晶体管阵列TA远离衬底121的一侧，且发光二极管芯片30形成的发光区域LA在薄膜晶体管阵列TA所在平面上的正投影覆盖部分扇出线F。
本实施方式的发光二极管芯片30通过将部分扇出线F设置于发光二极管芯片30形成的发光区域LA的下方，能够将外引脚结合（Outer Lead Bonding，OLB）区缩窄至几十微米，从而减小了为了驱动发光二极管芯片30而产生的非显示区。
请参考图7和图8，本申请第三实施方式的拼接显示装置100与第一实施方式的不同之处在于：
拼接显示装置100包括四个液晶显示面板10，且四个液晶显示面板10以2×2的方式排列。具体地，每两个液晶显示面板10沿第一方向D1排列成行，且每两个液晶显示面板10沿与第一方向D1垂直的第二方向D2排列成列。在第一方向D1上拼接的两个液晶显示面板10的第一边框区BA1相邻设置。在第二方向D2上拼接的两个液晶显示面板10的第二边框区BA2相邻设置。具体地，拼接显示装置100包括第一液晶显示面板11、第二液晶显示面板12第三液晶显示面板13以及第四液晶显示面板14。第一液晶显示面板11与第二液晶显示面板12在第一方向D1上拼接，第三液晶显示面板13与第四液晶显示面板14在第一方向D1上拼接。第三液晶显示面板13与第一液晶显示面板11在第二方向D2上拼接，第四液晶显示面板14与第二液晶显示面板12在第二方向D2上拼接。第一液晶显示面板11与第四液晶显示面板14具有相同结构，第二液晶显示面板12与第三液晶显示面板13具有相同结构。第一液晶显示面板11与第二液晶显示面板12具有对称结构。第一边框区BA1和第二边框区BA2中均不设置驱动芯片或者驱动电路。第三边框区BA3可以设置栅极驱动电路。第四边框区BA4可以设置数据线Data的扇出（fan-out）线，并绑定源极驱动器SD。由此，四个液晶显示面板10在没有设置驱动芯片或者驱动电路的边框区进行拼接，从而减小拼接缝。另外，发光二极管芯片30还设置于第二边框区BA2上。第二边框区BA2上的发光二极管芯片30、封装层、扫描线、数据线结构等可以参考第一实施方式中描述的第一边框区BA1的结构。并且，第二边框区BA2上的发光二极管芯片30也可以采用PM驱动和AM驱动，具体可以参考第一实施方式和第二实施方式中的第一边框区BA1的发光二极管芯片30，在此省略其说明。
根据本申请的拼接显示装置，通过在两个液晶显示面板拼接处的边框区设置发光二极管芯片以显示图像，减小或者消除拼接显示装置的拼接缝。
根据本申请的一个实施方式，发光二极管芯片采用PM驱动方式，既能满足边框区的分辨率要求，又能简化驱动电路，降低制造难度和制造成本。
根据本申请的一个实施方式，发光二极管芯片的源极驱动器采用侧绑定技术进行绑定，能够缩窄由于设置发光二极管芯片而产生的非显示区。
根据本申请的一个实施方式，相邻两个发光二极管芯片之间的间距与液晶显示面板中相邻两个子像素之间的间距相等，能够减小拼接的边框区处的mura。
根据本申请的一个实施方式，发光二极管芯片采用AM驱动，并使扇出线部分设置于发光二极管芯片下方，能够缩窄由于设置发光二极管芯片而产生的非显示区。
根据本申请的一个实施方式，能够提供一种包括以2×2的方式排列的四个液晶显示面板的拼接显示装置。
以上对本申请实施方式提供了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种拼接显示装置，包括：
    拼接的两个液晶显示面板，所述液晶显示面板包括第一边框区，两个所述液晶显示面板的所述第一边框区相邻设置；以及
    发光二极管芯片，设置于所述第一边框区上。
  2. 如权利要求1所述的拼接显示装置，其中，所述液晶显示面板包括阵列基板和对向基板，所述阵列基板与所述对向基板相对设置，所述对向基板包括衬底，所述发光二极管芯片位于所述衬底远离所述阵列基板的表面。
  3. 如权利要求2所述的拼接显示装置，其中，所述衬底上设置有扫描线和数据线，所述发光二极管芯片的阳极连接于所述数据线，所述发光二极管芯片的阴极连接于所述扫描线。
  4. 如权利要求2所述的拼接显示装置，其中，所述衬底上设置有薄膜晶体管阵列以及连接于所述薄膜晶体管阵列的扇出线，所述发光二极管芯片位于所述薄膜晶体管阵列远离所述衬底的一侧，且所述发光二极管芯片形成的发光区域在所述薄膜晶体管阵列所在平面上的正投影覆盖部分所述扇出线。
  5. 如权利要求2所述的拼接显示装置，其中，所述拼接显示装置包括背光模组和覆晶薄膜，所述背光模组设置于所述阵列基板远离所述对向基板的一侧，所述覆晶薄膜位于相邻两个所述第一边框区之间，并且所述覆晶薄膜的一端连接于所述发光二极管芯片，另一端设置于所述背光模组远离所述阵列基板的表面。
  6. 如权利要求5所述的拼接显示装置，其中，所述衬底的侧壁上开设有凹槽，所述拼接显示装置还包括扇出线，所述扇出线的一端连接于所述发光二极管芯片，所述扇出线的另一端延伸至所述凹槽内，并与所述覆晶薄膜连接。
  7. 如权利要求1所述的拼接显示装置，其中，所述拼接显示装置包括四个所述液晶显示面板，每两个所述液晶显示面板沿第一方向排列成行，且每两个所述液晶显示面板沿与所述第一方向垂直的第二方向排列成列，所述液晶显示面板还包括与所述第一边框相交的第二边框区，在所述第一方向上拼接的两个所述液晶显示面板的所述第一边框区相邻设置，在所述第二方向上拼接的两个所述液晶显示面板的所述第二边框区相邻设置，所述发光二极管芯片还设置于所述第二边框区上。
  8. 如权利要求7所述的拼接显示装置，其中，所述液晶显示面板还包括与第三边框区和第四边框区，所述第三边框区与所述第一边框区相对，所述第四边框区与所述第二边框区相对，所述第三边框区上绑定有源极驱动器，所述第四边框区中设置有栅极驱动电路。
  9. 如权利要求1所述的拼接显示装置，其中，所述液晶显示面板包括多个像素，相邻两个所述发光二极管芯片之间的间距与所述液晶显示面板中相邻两个像素之间的间距相等。
  10. 如权利要求1所述的拼接显示装置，其中，所述发光二极管芯片为蓝色发光二极管芯片，所述拼接显示装置包括封装层，所述封装层封装所述发光二极管芯片，所述封装层包括第一封装部和第二封装部，所述第一封装部朝向所述发光二极管芯片的表面设置有红色量子点彩膜，所述第二封装部朝向所述发光二极管芯片的表面设置有绿色量子点彩膜。
  11. 一种拼接显示装置，包括：
    拼接的四个所述液晶显示面板，每两个所述液晶显示面板沿第一方向排列成行，且每两个所述液晶显示面板沿与所述第一方向垂直的第二方向排列成列，所述液晶显示面板包括第一边框区和与所述第一边框相交的第二边框区，在所述第一方向上拼接的两个所述液晶显示面板的所述第一边框区相邻设置，在所述第二方向上拼接的两个所述液晶显示面板的所述第二边框区相邻设置；和
    发光二极管芯片，设置于所述第一边框区和所述第二边框区上。
  12. 如权利要求11所述的拼接显示装置，其中，所述液晶显示面板包括阵列基板和对向基板，所述阵列基板与所述对向基板相对设置，所述对向基板包括衬底，所述发光二极管芯片位于所述衬底远离所述阵列基板的表面。
  13. 如权利要求12所述的拼接显示装置，其中，所述衬底上设置有扫描线和数据线，所述发光二极管芯片的阳极连接于所述数据线，所述发光二极管芯片的阴极连接于所述扫描线。
  14. 如权利要求12所述的拼接显示装置，其中，所述衬底上设置有薄膜晶体管阵列以及连接于所述薄膜晶体管阵列的扇出线，所述发光二极管芯片位于所述薄膜晶体管阵列远离所述衬底的一侧，且所述发光二极管芯片形成的发光区域在所述薄膜晶体管阵列所在平面上的正投影覆盖部分所述扇出线。
  15. 如权利要求12所述的拼接显示装置，其中，所述拼接显示装置包括背光模组和覆晶薄膜，所述背光模组设置于所述阵列基板远离所述对向基板的一侧，所述覆晶薄膜位于相邻两个所述第一边框区之间，并且所述覆晶薄膜的一端连接于所述发光二极管芯片，另一端设置于所述背光模组远离所述阵列基板的表面。
  16. 如权利要求15所述的拼接显示装置，其中，所述衬底的侧壁上开设有凹槽，所述拼接显示装置还包括扇出线，所述扇出线的一端连接于所述发光二极管芯片，所述扇出线的另一端延伸至所述凹槽内，并与所述覆晶薄膜连接。
  17. 如权利要求11所述的拼接显示装置，其中，所述液晶显示面板还包括与第三边框区和第四边框区，所述第三边框区与所述第一边框区相对，所述第四边框区与所述第二边框区相对，所述第三边框区上绑定有源极驱动器，所述第四边框区中设置有栅极驱动电路。
  18. 如权利要求11所述的拼接显示装置，其中，所述液晶显示面板包括多个像素，相邻两个所述发光二极管芯片之间的间距与所述液晶显示面板中相邻两个像素之间的间距相等。
  19. 如权利要求11所述的拼接显示装置，其中，所述发光二极管芯片为蓝色发光二极管芯片，所述拼接显示装置包括封装层，所述封装层封装所述发光二极管芯片，所述封装层包括第一封装部和第二封装部，所述第一封装部朝向所述发光二极管芯片的表面设置有红色量子点彩膜，所述第二封装部朝向所述发光二极管芯片的表面设置有绿色量子点彩膜。
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