WO2023019598A1 - 显示装置、显示面板及其驱动方法 - Google Patents

显示装置、显示面板及其驱动方法 Download PDF

Info

Publication number
WO2023019598A1
WO2023019598A1 PCT/CN2021/113910 CN2021113910W WO2023019598A1 WO 2023019598 A1 WO2023019598 A1 WO 2023019598A1 CN 2021113910 W CN2021113910 W CN 2021113910W WO 2023019598 A1 WO2023019598 A1 WO 2023019598A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
display panel
chip
data signal
pixels
Prior art date
Application number
PCT/CN2021/113910
Other languages
English (en)
French (fr)
Inventor
李秀玲
谷其兵
胡国锋
付宝
黄文杰
时凌云
Original Assignee
京东方科技集团股份有限公司
京东方晶芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 京东方晶芯科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/914,180 priority Critical patent/US20240221606A1/en
Priority to KR1020237026174A priority patent/KR20240046105A/ko
Priority to PCT/CN2021/113910 priority patent/WO2023019598A1/zh
Priority to CN202180002239.0A priority patent/CN116235237A/zh
Priority to EP21953839.4A priority patent/EP4276810A4/en
Priority to JP2023546315A priority patent/JP2024528762A/ja
Publication of WO2023019598A1 publication Critical patent/WO2023019598A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device, a display panel and a driving method thereof.
  • micro light emitting diode refers to shrinking the size of LED to less than 300 microns, and fixing thousands, tens of thousands or even more micro light emitting diodes on the substrate. In order to perform more detailed local dimming, it presents a display screen with high contrast and high color expression.
  • the micro light-emitting diode display device adopts a passive addressing (Passive Matrix, PM) driving method, which consumes a lot of power.
  • PM Passive Matrix
  • the purpose of the present disclosure is to provide a display device, a display panel and a driving method thereof, which can reduce power consumption.
  • a display panel comprising:
  • a pixel array disposed on the base substrate, and includes a pixel group, and the pixel group includes a plurality of pixels;
  • a plurality of pixel driving chips are arranged on the base substrate and are used to drive the pixel array for display, and the pixel driving chips include a data signal terminal for receiving a data signal and a control signal for receiving a control signal end;
  • a plurality of the pixels in the pixel group are connected to the same pixel driving chip.
  • the plurality of pixels in the pixel group are distributed along one direction.
  • multiple pixels in the pixel group are located in the same pixel row in the pixel array.
  • multiple pixels in the pixel group are located in the same pixel column in the pixel array.
  • the plurality of pixel driving chips include at least one chip column, the chip column is parallel to the pixel columns in the pixel array, and the chip column is located between two adjacent pixel columns.
  • two adjacent pixel columns form a plurality of pixel groups, and the plurality of pixel groups are distributed along the extension direction of the pixel columns, and all pixels located between adjacent two pixel columns
  • a plurality of the pixel driving chips in the chip column are connected to a plurality of the pixel groups in a one-to-one correspondence.
  • a plurality of pixel driving chips constitute a plurality of chip columns, and there are two pixel columns between two adjacent chip columns.
  • the pixel includes a first sub-pixel
  • the display panel further includes:
  • the first sub-pixels in the two pixel columns located between two adjacent chip columns are connected to the same power signal line.
  • the display panel also includes:
  • the power signal line is connected with the pixel.
  • the pixel includes a sub-pixel, the sub-pixel includes a light-emitting diode, the power signal line is connected to the anode of the light-emitting diode, and the pixel driving chip is connected to the cathode of the light-emitting diode.
  • the display panel also includes:
  • the data signal line is connected to the data signal end.
  • the number of the data signal lines is multiple, and the multiple pixel driving chips include at least one chip column, and the data signal terminals of the multiple pixel driving chips in the chip column are connected to the same The data signal line.
  • the display panel also includes:
  • a control signal line is connected to the control signal terminal.
  • the number of the control signal lines is multiple, the multiple pixel driving chips include at least one chip row, and the control signal terminals of the multiple pixel driving chips in the chip row are connected to the same The control signal line.
  • the display panel also includes:
  • a control chip connected to the control signal line and the data signal line, is used to provide control signals to the control signal lines and to provide data signals to the data signal lines.
  • the display panel includes a display area and a peripheral area surrounding the display area, the pixel driving chip is located in the display area, and the control chip is located in the peripheral area.
  • the pixel driving chip further includes a supply voltage terminal and/or a ground terminal.
  • the numbers of the pixel rows and the pixel columns are both even numbers.
  • a plurality of the pixel driving chips are distributed in an array.
  • a display device including the above-mentioned display panel.
  • a method for driving a display panel is provided.
  • a display frame of the display panel includes an address allocation phase and a data signal transmission phase, and the driving method includes:
  • a second data signal is input to the data signal terminal.
  • the control signal is input to the control signal terminal of the pixel driving chip, the first data signal is input to the data signal terminal; and the data signal of the pixel driving chip is input Input the second data signal to the end, so that each pixel driver chip provides the data signal to the corresponding pixel, thereby realizing the driving mode of active addressing, and because multiple pixels in the pixel group are connected to the same pixel driver chip, Therefore, the number of signal traces on the base substrate is reduced, the difficulty of the process is reduced, and the driving power consumption and driving cost of the overall display module are reduced, and the competitive advantage of the product is greatly improved.
  • FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the display area in FIG. 1 .
  • FIG. 3 is a schematic diagram of the distribution of the column of pixels and the pixel driving chips in FIG. 2 .
  • FIG. 4 is a schematic diagram of a pixel group and a pixel driving chip in FIG. 2 .
  • FIG. 5 is another schematic diagram of a pixel group and a pixel driving chip in a display panel according to an embodiment of the present disclosure.
  • FIG. 6 is another schematic diagram of a pixel group and a pixel driving chip in a display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic connection diagram of a pixel driving chip without a power supply voltage terminal according to an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram corresponding to the driving method of the display panel according to the embodiment of the present disclosure.
  • FIG. 9 is a timing diagram of a signal channel end of a pixel driving chip according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of encoding of a data signal according to an embodiment of the present disclosure.
  • the display panel may include a base substrate, a pixel array, and a pixel driver chip 2, wherein:
  • the pixel array is arranged on the base substrate.
  • the pixel array comprises pixel groups 8 .
  • the pixel group 8 includes a plurality of pixels 1 .
  • a plurality of pixel driving chips 2 are arranged on the base substrate, and are used to drive the pixel array for display.
  • the pixel driving chip 2 includes a data signal terminal 4 for receiving a data signal and a control signal terminal 3 for receiving a control signal.
  • multiple pixels 1 in the pixel group 8 are connected to the same pixel driving chip 2 .
  • the control signal is input to the control signal terminal 3 of the pixel driving chip 2, and the first data signal is input to the data signal terminal 4 of the pixel driving chip 2;
  • the data signal terminal 4 inputs the second data signal, so that each pixel driving chip 2 provides the data signal to the corresponding pixel 1, thereby realizing the driving mode of active addressing, and because the plurality of pixels 1 in the pixel group 8 are connected
  • the number of signal lines on the substrate is reduced, the process difficulty is reduced, and the driving power consumption and driving cost of the overall display module are reduced, which greatly improves the competitive advantage of the product.
  • the base substrate may be a rigid base substrate, and the material includes, for example, glass, quartz, PMMA (Polymethyl methacrylate, polymethyl methacrylate), plastic, etc., but this is not particularly limited in the embodiments of the present disclosure.
  • the material includes, for example, glass, quartz, PMMA (Polymethyl methacrylate, polymethyl methacrylate), plastic, etc., but this is not particularly limited in the embodiments of the present disclosure.
  • the pixel array is arranged on the base substrate.
  • the display panel may include a display area 10 and a peripheral area 11 surrounding the display area 10 .
  • the pixel array can be located in the display area 10 of the display panel.
  • the pixel array may include a plurality of pixel rows 300 and a plurality of pixel columns 100 .
  • the pixel row 300 may extend along a first direction
  • the pixel column 100 may extend along a second direction.
  • the first direction may be perpendicular to the second direction.
  • the number of the pixel rows 300 may be an even number, but the present disclosure is not limited thereto, and may also be an odd number.
  • the number of the pixel columns 100 may also be an even number, but the present disclosure is not limited thereto, and may also be an odd number.
  • the pixel row 300 may include a plurality of pixels 1 .
  • the pixel row 100 may include a plurality of pixels 1 .
  • the pixel 1 may include a plurality of sub-pixels. The colors of the light emitted by the plurality of sub-pixels may be different, or they may also be the same.
  • the plurality of sub-pixels may include a first sub-pixel 101 , a second sub-pixel 102 and a third sub-pixel 103 .
  • the first sub-pixel 101 may be a red sub-pixel, of course, may also be a blue sub-pixel, but the present disclosure is not limited thereto, and may also be a green sub-pixel.
  • the second sub-pixel 102 may be a red sub-pixel, of course, may also be a blue sub-pixel, but the present disclosure is not limited thereto, and may also be a green sub-pixel.
  • the third sub-pixel 103 may be a red sub-pixel, of course, may also be a blue sub-pixel, but the present disclosure is not limited thereto, and may also be a green sub-pixel.
  • the first sub-pixel 101 is a red sub-pixel for emitting red light
  • the second sub-pixel 102 is a blue sub-pixel for emitting blue light
  • the third sub-pixel 103 is a green sub-pixel for emitting green light.
  • Each subpixel may include one or more light emitting diodes.
  • the light emitting diode can be a Mini LED, and of course, the light emitting diode can be a Micro LED, but the embodiments of the present disclosure are not limited thereto.
  • the sub-pixel including two light emitting diodes as an example, the two light emitting diodes are connected in parallel and have the same color.
  • the orthographic projection of the light emitting diode on the base substrate may be a quadrilateral, with a width of 70 ⁇ m-100 ⁇ m and a length of 120 ⁇ m-180 ⁇ m.
  • the light emitting diode is an independent component, which can be disposed on the substrate by surface mount technology (SMT) or mass transfer technology.
  • the pixel array can include a pixel group 8, of course, the pixel array can also include a plurality of pixel groups 8, that is to say, a plurality of pixels 1 in the pixel array can be divided into a plurality of pixel groups 8. At least one pixel group 8 includes a plurality of pixels 1 among the plurality of pixel groups 8 . Taking the number of pixel groups 8 as an example, the number of pixels 1 in multiple pixel groups 8 may be the same, and of course, the number of pixels 1 in two pixel groups 8 may also be different.
  • the plurality of pixels 1 in the pixel group 8 there are a plurality of pixels 1 that can be located in different pixel rows 300 in the pixel array, that is, there are at least two pixels 1 in the plurality of pixels 1 in the pixel group 8 that can be located in the pixel array. 300 rows of different pixels.
  • the different pixel rows 300 may be sequentially arranged pixel rows 300 , but this is not particularly limited in the embodiments of the present disclosure.
  • n is an integer greater than or equal to 1
  • the nth pixel row 300 and the (n+1)th pixel row 300 are pixel rows 300 arranged in sequence.
  • each of the four pixels 1 is located in a different pixel row 300 , for example, the four pixels 1 are located in the same pixel column 100 .
  • the plurality of pixels 1 of the pixel group 8 there may also be a plurality of pixels 1 located in different pixel columns 100 in the pixel array, that is to say, among the plurality of pixels 1 of the pixel group 8, at least two pixels 1 may be Located in different pixel columns 100 in the pixel array.
  • the different pixel columns 100 may be sequentially arranged pixel columns 100 , but this is not particularly limited in the embodiments of the present disclosure.
  • the pixel group 8 including four pixels 1 there are two pixels 1 located in different pixel columns 100 among the four pixels 1, one pixel 1 of the two pixels 1 is located in the mth pixel column 100, and the other pixel 1 1 is located in the (m+1)th pixel row 100, m is an integer greater than or equal to 1, and the mth pixel row 100 and the (m+1)th pixel row 100 are pixel rows 100 arranged in sequence.
  • each of the four pixels 1 is located in a different pixel column 100 , for example, the four pixels 1 are located in the same pixel row 300 .
  • a plurality of pixels 1 of the pixel group 8 may also be distributed along the same direction.
  • the plurality of pixels 1 of the pixel group 8 may be located in the same pixel row 300 in the pixel array, and the plurality of pixels 1 in the same pixel row 300 are arranged sequentially.
  • the four pixels 1 in FIG. 5 are numbered sequentially from left to right, and the distance between the second pixel 1 and the third pixel 1 closest to the pixel driver chip 2 is slightly larger than the first pixel 1 and the third pixel 1.
  • the distance between the two pixels 1 is larger than the distance between the third pixel 1 and the fourth pixel 1 .
  • any two pixels 1 may also be arranged at equal intervals in the row direction, which is not limited in the embodiment of the present disclosure, and the pixel driver chip 2 does not affect the display of all pixels 1 in actual design. The effect shall prevail.
  • the multiple pixels 1 of the pixel group 8 may be located in the same pixel column 100 in the pixel array, and the multiple pixels 1 located in the same pixel column 100 are arranged sequentially. .
  • the four pixels 1 in FIG. 6 are numbered sequentially from top to bottom, and the distance between the second pixel 1 and the third pixel 1 closest to the pixel driver chip 2 is slightly larger than the first pixel 1 and the third pixel 1.
  • any two pixels 1 may also be arranged at equal intervals in the column direction, which is not limited in the embodiment of the present disclosure, and the pixel driving chip 2 does not affect all pixels 1 in the actual design.
  • the display effect shall prevail.
  • the pixel driving chip 2 is disposed on the base substrate.
  • the pixel driving chip 2 and the pixel 1 can be disposed on the same side of the base substrate, and of course, the pixel driving chip 2 and the pixel 1 can be disposed on opposite sides of the base substrate.
  • the pixel driving chip 2 is connected to the pixel 1 .
  • the pixel driving chip 2 may be connected to multiple sub-pixels in the pixel 1 .
  • the signal terminal of the pixel driving chip 2 may include multiple signal channel terminals 7 , and the multiple signal channel terminals 7 of the pixel driving chip 2 are connected to multiple sub-pixels in the pixel 1 in one-to-one correspondence.
  • the signal channel end 7 may be connected to the first electrode of the light emitting diode.
  • the first electrode can be a negative electrode, and of course, the first electrode can also be a positive electrode.
  • the signal terminals of the pixel driving chip 2 include a data signal terminal 4 and a control signal terminal 3 .
  • the data signal terminal 4 is used for receiving data signals
  • the control signal terminal 3 is used for receiving control signals.
  • the data signal may include a first data signal and a second data signal.
  • the signal terminal of the pixel driving chip 2 may also include a supply voltage terminal 5 and/or a ground terminal 6 .
  • the maximum number of signal terminals located in the row direction is a
  • the maximum number of signal terminals located in the column direction is b
  • a, b, and X are all integers
  • the product of a and b is less than or equal to X.
  • the absolute value of the difference between a and b is the smallest.
  • Such setting can avoid the pixel driving chip 2 from being too large in a single direction, and solve the problem that the distance between multiple pixels 1 in a single direction is too large due to the pixel driving chip 2 being too large in a single direction. .
  • the number of signal terminals in the row direction and the number of signal terminals in the column direction are both 4.
  • the orthographic projection of the pixel driving chip 2 on the base substrate may be a quadrangle with a width of 350 ⁇ m-450 ⁇ m and a length of 350 ⁇ m-450 ⁇ m.
  • the length and width of the orthographic projection of the pixel driving chip 2 on the base substrate may be the same, but this disclosure does not specifically limit it.
  • the area of the orthographic projection of the pixel driving chip 2 on the substrate may be 8 times to 15 times the area of the orthographic projection of the light emitting diode in the pixel 1 on the substrate.
  • the pixel driving chip 2 is an independent component, which can be assembled on the base substrate by surface mount technology (SMT).
  • the base substrate is provided with pads, and the signal terminal of the pixel drive chip 2 is fixedly connected to the pads during the process of assembling the pixel drive chip 2 on the base substrate by surface mount technology.
  • the number of the pixel driving chips 2 is multiple, and the pixel driving chips 2 work together to drive the pixel array for display.
  • a plurality of pixels 1 in the pixel group 8 are connected to the same pixel driving chip 2, that is to say, a plurality of sub-pixels in the plurality of pixels 1 are all connected to the same pixel driving chip 2 .
  • the three sub-pixels in the four pixels 1 are all connected to the same pixel driving chip 2, that is, the pixel driving chip 2 and twelve sub-pixels Connection; the pixel driving chip 2 may include twelve signal channel terminals 7 , and the twelve signal channel terminals 7 are connected to the first electrodes of the light emitting diodes of each sub-pixel in one-to-one correspondence.
  • the plurality of pixel driving chips 2 are used to drive the plurality of pixel groups 8 for display in one-to-one correspondence.
  • a plurality of pixel driving chips 2 of the present disclosure may be distributed in an array to form a plurality of chip columns 200 and a plurality of chip rows 400 .
  • the chip row 400 may be parallel to the aforementioned pixel row 300 .
  • the array of chips 200 may be parallel to the array of pixels 100 described above.
  • the number of pixel driving chips 2 in the chip row 200 can be less than or equal to the number of pixels 1 in the pixel row 100.
  • the plurality of chip columns 200 at least one chip column 200 is located between two adjacent pixel columns 100, and the chip column 200 located between the adjacent two pixel columns 100 is used to drive the two adjacent pixel columns Column 100 is displayed. Wherein, there is only one chip column 200 between the two adjacent pixel columns 100 .
  • the two adjacent pixel columns 100 can form a plurality of pixel groups 8, the number of pixels 1 included in each pixel group 8 can be the same or different, and the plurality of pixel groups 8 are distributed along the extension direction of the pixel columns 100 .
  • each pixel column 100 including six rows of pixels 1 and each pixel group 8 including four pixels 1 as an example, for the two adjacent pixel columns 100, two pixels 1 in the first row and two pixels 1 in the second row Pixel 1 can form a pixel group 8, two pixel 1 in the third row and two pixel 1 in the fourth row can form another pixel group 8, two pixel 1 in the fifth row and two pixel 1 in the sixth row A further pixel group 8 may be formed.
  • the plurality of pixel driving chips 2 in the chip row 200 between the two adjacent pixel rows 100 are connected to the plurality of pixel groups 8 in a one-to-one correspondence.
  • the plurality of pixel driving chips 2 in the present disclosure may not be distributed in an array, as long as one pixel driving chip 2 is connected to a plurality of pixels 1 in the pixel group 8, the number of signal wires on the substrate can be reduced.
  • a plurality of pixel driving chips 2 form a plurality of chip rows 400 , but do not form a chip column 200 , and the number of pixel driving chips 2 in each chip row 400 may be equal.
  • a plurality of pixel driving chips 2 form a plurality of chip columns 200 , but do not form a chip row 400 , and the number of pixel driving chips 2 in each chip column 200 may be equal.
  • the display panel in the embodiment of the present disclosure further includes a plurality of power signal lines.
  • the power signal line can be arranged parallel to the pixel column 100 .
  • the power signal line is connected to the pixel 1 .
  • the power signal line is connected to the sub-pixels in the pixel 1 .
  • the power signal line is connected to the second electrode of the light emitting diode of the sub-pixel. Taking the first electrode of the light emitting diode as the negative pole as an example, the second electrode may be the positive pole; taking the first electrode of the light emitting diode as the positive pole as an example, the second electrode may be the negative pole.
  • the first sub-pixels 101 in the two pixel columns 100 are connected to the same power signal line, thereby reducing the power supply.
  • the power signal line may include a first power signal line VR and a second power signal line VGB.
  • the red sub-pixel in each pixel 1 can be connected to the first power signal line VR, and the green sub-pixel and blue sub-pixel in each pixel 1 are both connected to the second power signal line VGB.
  • the (2k-1) chip row 200 is arranged between the (4k-3)th pixel row 100 and the (4k-2) pixel row 100, the (4k-2)th pixel row 100 and the (4k-2)th pixel row 100 and the (4k-2)th pixel row 100
  • the 2k chip row 200 is arranged between the (4k-1) pixel row 100 and the 4k pixel row 100
  • the (2k-1) chip row Between 200 and the 2k chip column 200, the (4k-2) pixel column 100 and the (4k-1) pixel column 100 are arranged; wherein, the (2k-1) chip column 200 is used to drive the (4k-3) pixel column ) pixel column 100 and the (4k-2) pixel column 100 for display, the 2k chip column 200 is used to drive the (4k-1) pixel column 100 and the 4k pixel column 100 for display; the (4k-2) pixel
  • the distance between the (4k-3)th pixel column 100 and the (4k-2)th pixel column 100 may be greater than the distance between the (4k-2)th pixel column 100 and the (4k-1)th pixel column 100
  • the distance between the (4k-1)th pixel column 100 and the 4kth pixel column 100 may also be greater than the distance between the (4k-2)th pixel column 100 and the (4k-1)th pixel column 100 .
  • a pixel driving chip 2 is arranged between two adjacent pixel rows 300, and there is no pixel driving chip 2 between two adjacent pixel rows 300; The distance between two adjacent pixel rows 300 is greater than the distance between two adjacent pixel rows 300 not provided with the pixel driving chip 2 .
  • a pixel driver chip 2 is arranged between two adjacent pixel rows 100, and there is no pixel driver chip 2 between two adjacent pixel rows 100; two adjacent pixel driver chips 2 are arranged between them.
  • the distance between two pixel columns 100 is greater than the distance between two adjacent pixel columns 100 not provided with the pixel driving chip 2 .
  • any two adjacent pixel rows 300 may be arranged at equal intervals in the column direction, and any two adjacent pixel columns 100 may be arranged at equal intervals in the row direction.
  • the disclosed embodiments do not limit this, and the actual design is based on the fact that the pixel driving chip 2 does not affect the display effect of all the pixels 1 .
  • the display panel in the embodiment of the present disclosure may further include a plurality of data signal lines DATA.
  • the data signal line DATA may be arranged parallel to the pixel column 100 .
  • the data signal line DATA can be connected to the data signal terminal 4 of the pixel driving chip 2 .
  • the data signal terminal 4 of each pixel driving chip 2 in the above-mentioned chip array 200 may be connected to the same data signal line DATA, but this is not particularly limited in the embodiments of the present disclosure.
  • the display panel of the embodiment of the present disclosure may further include a plurality of control signal lines DE.
  • the control signal line DE may be arranged parallel to the pixel row 300 in the pixel array.
  • the control signal line DE can be connected to the control signal terminal 3 of the pixel driving chip 2 .
  • the control signal terminals 3 of the pixel driving chips 2 in the above-mentioned chip row 400 may be connected to the same control signal line DE, but this is not particularly limited in the embodiments of the present disclosure.
  • the display panel in the embodiment of the present disclosure may further include a control chip 9 .
  • the control chip 9 can be connected to the control signal line DE and the data signal line DATA for providing control signals to the control signal line DE and for providing data signals to the data signal line DATA.
  • the control chip 9 can be located in the peripheral area 11 of the display panel.
  • the display panel in the embodiment of the present disclosure may further include a plurality of supply voltage lines VCC.
  • the supply voltage line VCC may be arranged parallel to the above-mentioned pixel column 100 .
  • the supply voltage line VCC can be connected to the supply voltage terminal 5 of the pixel driving chip 2 .
  • the power supply voltage terminal 5 of each pixel driving chip 2 in the above-mentioned chip array 200 may be connected to the same power supply voltage line VCC, but this is not particularly limited in the embodiments of the present disclosure.
  • the display panel of the embodiment of the present disclosure may further include a plurality of ground lines GND.
  • the ground line GND may be arranged parallel to the above-mentioned pixel column 100 .
  • the ground line GND can be connected to the ground terminal 6 of the pixel driving chip 2 .
  • the ground terminal 6 of each pixel driving chip 2 in the above-mentioned chip array 200 may be connected to the same ground line GND, but this is not particularly limited in the embodiments of the present disclosure.
  • the power supply voltage terminal 5 of the present disclosure is used to receive the power supply voltage
  • the control signal terminal 3 is used to receive the control signal
  • the power supply voltage and the control signal are respectively received through the two signal ports, so that the pixel driver chip 2 can be prevented from being damaged due to incorrect reading of the control signal. This causes the pixel driving chip 2 to appear in an abnormal working state, preventing the display effect from being affected.
  • signal lines such as the first power signal line VR, the second power signal line VGB, the control signal line DE, the data signal line DATA, the ground line GND, and the power supply voltage line VCC in the present disclosure can be directly formed on the base substrate
  • it can be prepared by processes such as film formation and patterning.
  • the pixel driving chip 2 can be assembled on the base substrate after the signal lines are formed through processes such as film formation and patterning.
  • the orthographic projection of the pixel driving chip 2 on the base substrate and the orthographic projection of a part of the signal line on the base substrate have an overlapping area, which can maximize the rational use of wiring space and increase the pixel arrangement density.
  • the power supply voltage and the address signal can be input from the same signal terminal of the pixel driving chip 2 , for example, input from the control signal terminal 3 .
  • the present disclosure can distinguish the control function and the power supply function by the signal amplitude of the signal received by the control signal terminal 3 .
  • the control function is performed when the signal amplitude is higher than a certain preset level; the power supply function is performed when the signal amplitude is lower than a certain preset level.
  • the embodiment of the present disclosure can reduce the number of wires by half; two pixel columns located between two adjacent chip columns 200 100 can share the first power signal line VR and the second power signal line VGB, that is, for the display panel in FIG.
  • the second power signal line VGB, the pixel columns 100 between the left and right sides of the pixel columns 100 will share the first power signal line VR and the second power signal line VGB, so that the first power signal line VR and the second power signal line There are 81 VGBs each, which greatly reduces the number of wires on the display panel, reduces the production cost, and greatly improves the competitive advantage of the product.
  • the display panel needs 40 data signal lines DATA, 180 control signal lines DE, 40 There are 1 ground line GND, 40 supply voltage lines VCC, 160 first power signal lines VR and 160 second power signal lines VGB.
  • the display panel needs 160 data signal lines DATA, 45 control signal lines DE, 160 There are 1 ground wires GND, 160 power supply voltage wires VCC, 160 first power signal wires VR and 160 second power signal wires VGB.
  • the embodiment of the present disclosure also provides a display device.
  • the display device may include the display panel described in any of the foregoing implementation manners.
  • the display device can be applied to any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. Since the display panel included in the display device is the same as the display panel in the above-mentioned embodiment of the display panel, it has the same beneficial effects, and the present disclosure will not repeat them here.
  • the embodiments of the present disclosure also provide a driving method of the display panel.
  • the display panel may be the display panel described in any one of the above implementation modes. Taking each pixel driver chip 2 in the display panel as an example to drive a pixel group 8, each pixel group 8 includes four pixels 1 as an example, the display panel is provided with 4M*N pixels 1 in an array, and N rows and M columns of pixels Driver chip 2, where M and N are both positive integers.
  • one frame may include an address allocation phase and a data signal transmission phase.
  • the driving method of the display panel may include an S1 stage and an S3 stage, wherein:
  • the stage of allocating addresses to each pixel driving chip 2 is the S1 stage.
  • the control signal terminal 3 of each pixel driving chip 2 in the same chip row 400 is connected to a control signal line DE, and the data signal terminal 4 of each pixel driving chip 2 in the same chip column 200 is connected to a data signal line DATA as an example.
  • the control chip 9 inputs the first data signal to the plurality of chip columns 200 through the plurality of data signal lines DATA, and the control chip 9 supplies the first data signal to the plurality of chip rows 400 through the plurality of control signal lines DE.
  • the control signals are sequentially input to control the data signal terminals 4 of the pixel driving chips 2 located in the same chip row 400 to simultaneously receive the first data signals transmitted from different data signal lines.
  • the display panel includes N chip rows 400 and N control signal lines.
  • each data signal line DATA transmits different first data signals to the pixel driver chips 2 located in different chip columns 200 in the first chip row 400 at the same time, and each column pixel driver in the first chip row 400 Chip 2 receives the first data signal;
  • the control chip 9 transmits the control signal through the Nth control signal line DEN , the pixel driver chip 2 in the Nth chip row 400 is triggered, and the remaining chip rows 400 are not triggered, and each data
  • the signal line DATA simultaneously transmits different first data signals to the pixel driver chips 2 located in different chip columns 200 in the Nth chip row 400 , and the pixel driver chips 2 in each column in the Nth chip row 400 receive the first data signals.
  • the first data signal may be a digital signal, and specifically may include a start instruction SoT, an address information ID, an interval instruction DCX, and an end instruction EoT arranged in sequence. Since the address information ID is included in the first data signal, the address information ID can be set for the pixel driving chip 2 .
  • the length of the first data signal can be set to 12 bits, wherein the start command SoT can be set to 1 bit, the address information ID can be set to 8 bits, the interval command DCX can be set to 1 bit, and the end command EoT can be set to 2 bits.
  • each pixel driving chip 2 After receiving the first data signal, each pixel driving chip 2 stores the address information ID therein in each pixel driving chip 2 .
  • the pixel driving chip 2 of the present disclosure may be in a sleep state, which is a low power consumption working mode or a non-working state.
  • the power supply voltage is input to the power supply voltage terminal 5 of the pixel driving chip 2 through the power supply voltage line VCC to release the pixel driving chip 2 from the sleep state, that is, the S0 stage in FIG. 8 .
  • stage S3 which is also called the data signal transmission stage.
  • the above-mentioned control chip 9 inputs the second data signal to the plurality of chip arrays 200 through the plurality of data signal lines DATA.
  • the second data signal is input to a plurality of arrays 200 at the same time.
  • Each second data signal has a plurality of sub data information Subdata_1, Subdata_2...Subdata_N.
  • Each sub-data information includes address information ID and pixel data information.
  • the sub-data information may be a digital signal, specifically, may include: start instruction SoT, address information ID, data transmission instruction DCX, interval instruction IoT, pixel data information and end instruction EoT.
  • the pixel driving chip 2 When the pixel driving chip 2 recognizes that the value of DCX is 1, it transmits the pixel data information in the sub-data information to the corresponding pixel.
  • the sub-pixel data Rda 1 , Rda 2 , Rda 3 , and Rda 4 represent the data information required for each red sub-pixel in the four pixels 1 connected to the pixel driver chip 2 to emit light, and the sub-pixel data Gda 1 , Gda 2 , Gda 3.
  • Gda 4 represents the data information required for each green sub-pixel in the 4 pixels 1 connected to the pixel driver chip 2 to emit light
  • the sub-pixel data Bda 1 , Bda 2 , Bda 3 , and Bda 4 represent information related to the pixel driver chip 2. 2
  • the length of each sub-data information can be set to 63 bits, wherein, the start instruction SoT occupies 1 bit, the address information ID occupies 8 bits, the data transmission instruction DCX occupies 1 bit, the interval instruction IoT occupies 1 bit, and the sub-pixel data Rda 1 , Rda 2 , Rda 3 , Rda 4 occupy 16 bits in total, sub-pixel data Gda 1 , Gda 2 , Gda 3 , Gda 4 occupy 16 bits in total, sub-pixel data Bda 1 , Bda 2 , Bda 3 , Bda 4 occupy 16 bits in total, end command EoT occupies 2 bits.
  • an interval instruction IoT can be set between any two adjacent sub-data messages. It can be understood that, since one pixel driving chip 2 is used to drive a total of four pixels 1 in one pixel group 8, and the serial number relationship between the four pixels 1 connected to the pixel driving chip 2 can be determined through the pixel driving chip internal Realized by a digital logic circuit to accurately distribute each sub-pixel data in the pixel data information to the corresponding signal channel end 7.
  • each sub-data information corresponds to the address information ID received by each pixel driving chip 2 in the S1 stage
  • the pixel data information includes the address information of each pixel 1 driven by the pixel driving chip 2. Collection of data information.
  • a plurality of sub-data information can be sequentially arranged in a specific order (for example, the specific order can be the arrangement order of a plurality of pixel driver chips 2 in each chip column 200 along the column direction) to form the second data signal, and the plurality of sub-data information can also be arranged in a different order.
  • the arrangement is performed in a specific order, which is not limited in the present disclosure.
  • the second data signal is transmitted to the pixel driving chips 2 in the same column through the data signal line DATA, and each pixel driving chip 2 selectively receives the address information ID in the multiple sub-data information in the second data signal by decoding and matching Obtain the pixel data information in the sub-data information corresponding to the same address information ID received and stored in the S1 stage.
  • Each signal channel end 7 of the pixel driving chip 2 forms a signal path with its corresponding sub-pixel.
  • the pixel driving chip 2 is configured to drive four pixels 1, and each pixel 1 includes three sub-pixels of different colors. Therefore, the pixel driving chip 2 includes twelve signal channel terminals 7, and each signal channel terminal 7 Connect with different sub-pixels.
  • the pixel drive chip 2 receives and stores the data information of the four pixels 1 connected to it, and the signal channel terminals 7 connected to sub-pixels of different colors may not be opened at the same time, so that the sub-pixels of different colors are driven The time is different. Specifically, as shown in FIG. 4 , FIG. 7 and FIG.
  • the signal channel terminals 7 ( R1 ), 7 ( R2 ), 7 ( R3 ), and 7 ( R4 ) connected to the red sub-pixel can all be opened first, that is, as shown in FIG.
  • all red sub-pixel lines are driven first; compared to signal channel terminals 7(R1), 7(R2), 7(R3), and 7 (R4), the signal channel terminals 7(G1), 7(G2), 7(G3), and 7(G4) connected to the green sub-pixel can be opened with a delay of a few nanoseconds, that is, CH_G in Figure 9 appears valid later than CH_R Level, the green sub-pixel is driven during the time period when CH_G has an active level;
  • the signal channel terminals 7 (B1), 7 (B2), 7 (B3), and 7 (B4) of the blue sub-pixel can be turned on with a delay of a few nanoseconds, that is, CH_B in FIG.
  • FIG. 10 is a schematic diagram of coding of a first data signal and a second data signal according to the present disclosure.
  • the meaning of each bit in the first data signal and the second data signal can be represented by designing the duty cycle in the pulse sequence. For example, when the duty cycle of a certain pulse in the pulse sequence is 25%, it means that the bit represents 0; when the duty cycle of a certain pulse is 75%, it means that the bit represents 1; the duty cycle of a certain pulse is When it is 50%, it means that the bit is the start instruction SoT; when the duty cycle of two consecutive pulses is 50%, that is, there are two consecutive SoTs, then the meaning of the 2bit is the end instruction EoT.
  • a display frame of the display panel of the present disclosure may further include a current setting phase S2 between the address allocation phase S1 and the data signal transmission phase S3 .
  • the current setting information Co is input to the data signal terminal 4 of the pixel driving chip 2 to control the magnitude of the driving current of the pixel driving chip 2 , and further accurately control the light output brightness of the corresponding pixel 1 .
  • the length of the current setting information Co can be 63 bits, which can specifically include: 1-bit start command SoT, 8-bit address information ID, 1-bit current setting command DCX, 1-bit interval command IoT, frame start command C and 16bit data, 1bit interval instruction IoT, 16bit reserved control instruction bits, 1bit interval instruction IoT, 16bit reserved Reserve the control command bit, and the 2-bit end command EoT.
  • the current setting command DCX is a set value, it indicates that the current setting is performed, for example, when DCX is 0, it indicates that the current setting is performed.
  • the display panel may only execute stages S0, S0, and stage S1, stage S2, and stage S3, and before displaying the frames after the first frame, the display panel may only execute stage S2 and stage S3, or even only execute stage S3.
  • the embodiment of the present disclosure is described by taking a pixel driver chip as an example to provide signals to a pixel group with four pixels. If the display panel includes pixels in odd rows or columns, the embodiment provided in the present disclosure can also be used for implementation. Design and drive, wherein, part of the signal channel ends of some pixel driver chips can be suspended (that is, not connected to any components), or a pixel driver chip that provides signals to a pixel group with an odd number of pixels can be set in the display panel. Disclosure is not limited here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of El Displays (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本公开提供一种显示装置、显示面板及其驱动方法。该显示面板包括：衬底基板；像素阵列，设于衬底基板上，且包括像素组，像素组包括多个像素；多个像素驱动芯片，设于衬底基板上，且用于驱动像素阵列进行显示，像素驱动芯片包括用于接收数据信号的数据信号端以及控制信号端；像素组中的多个像素连接于同一个像素驱动芯片。显示面板的一个显示帧包括地址分配阶段和数据信号传输阶段。驱动方法包括：在地址分配阶段，向控制信号端输入控制信号，向数据信号端输入第一数据信号；在数据信号传输阶段，向数据信号端输入第二数据信号。本公开能够减少信号走线数量以及降低功耗。

Description

显示装置、显示面板及其驱动方法 技术领域
本公开涉及显示技术领域，尤其涉及一种显示装置、显示面板及其驱动方法。
背景技术
随着发光二极管(Light Emitting Diode，LED)技术的不断发展，微型发光二极管是指将LED尺寸微缩为300微米以下，将数千颗、数万颗甚至更多的微型发光二极管固定在基板上，以进行更细致的局部调光，呈现出对比度高、色彩表现度高的显示画面。微型发光二极管显示装置采用的是无源寻址(Passive Matrix，PM)的驱动方式，这种驱动方式的功耗较大。
发明内容
本公开的目的在于提供一种显示装置、显示面板及其驱动方法，能够降低功耗。
根据本公开的一个方面，提供一种显示面板，包括：
衬底基板；
像素阵列，设于所述衬底基板上，且包括像素组，所述像素组包括多个像素；
多个像素驱动芯片，设于所述衬底基板上，且用于驱动所述像素阵列进行显示，所述像素驱动芯片包括用于接收数据信号的数据信号端以及用于接收控制信号的控制信号端；
其中，所述像素组中的多个所述像素连接于同一个所述像素驱动芯片。
进一步地，所述像素组中存在多个所述像素位于所述像素阵列中不同的像素行。
进一步地，所述像素组中存在多个所述像素位于所述像素阵列中不同的像素列。
进一步地，所述像素组中的多个所述像素沿着一个方向分布。
进一步地，所述像素组中的多个像素位于所述像素阵列中的同一像素行。
进一步地，所述像素组中的多个像素位于所述像素阵列中的同一像素列。
进一步地，多个所述像素驱动芯片包括至少一个芯片列，所述芯片列与所述像素阵列中的像素列平行，所述芯片列位于相邻的两个所述像素列之间。
进一步地，相邻的两个所述像素列构成多个所述像素组，多个所述像素组沿着所述像素列的延伸方向分布，位于相邻两个所述像素列之间的所述芯片列中的多个所述像素驱动芯片一一对应地与多个所述像素组连接。
进一步地，多个所述像素驱动芯片构成多个芯片列，相邻的两个所述芯片列之间存在两个所述像素列。
进一步地，所述像素包括第一子像素，所述显示面板还包括：
多个电源信号线，位于相邻的两个所述芯片列之间的两个所述像素列中的所述第一子像素连接于同一个所述电源信号线。
进一步地，所述显示面板还包括：
电源信号线，与所述像素连接。
进一步地，所述像素包括子像素，所述子像素包括发光二极管，所述 电源信号线连接于所述发光二极管的正极，所述像素驱动芯片连接于所述发光二极管的负极。
进一步地，所述显示面板还包括：
数据信号线，与所述数据信号端连接。
进一步地，所述数据信号线的数量为多个，多个所述像素驱动芯片包括至少一个芯片列，所述芯片列中的多个所述像素驱动芯片的所述数据信号端连接于同一个所述数据信号线。
进一步地，所述显示面板还包括：
控制信号线，与所述控制信号端连接。
进一步地，所述控制信号线的数量为多个，多个所述像素驱动芯片包括至少一个芯片行，所述芯片行中的多个所述像素驱动芯片的所述控制信号端连接于同一个所述控制信号线。
进一步地，所述显示面板还包括:
数据信号线，与所述数据信号端连接；
控制芯片，与所述控制信号线以及所述数据信号线连接，用于向所述控制信号线提供控制信号，并用于向所述数据信号线提供数据信号。
进一步地，所述显示面板包括显示区以及围绕所述显示区的周边区，所述像素驱动芯片位于所述显示区，所述控制芯片位于所述周边区。
进一步地，所述像素驱动芯片还包括供电电压端和/或接地端。
进一步地，所述像素行和所述像素列的数量均为偶数。
进一步地，多个所述像素驱动芯片呈阵列分布。
根据本公开的一个方面，提供一种显示装置，包括上述的显示面板。
根据本公开的一个方面，提供一种显示面板的驱动方法，采用上述的 显示面板，所述显示面板的一个显示帧包括地址分配阶段和数据信号传输阶段，所述驱动方法包括：
在所述地址分配阶段，向所述控制信号端输入控制信号，向所述数据信号端输入第一数据信号；
在所述数据信号传输阶段，向所述数据信号端输入第二数据信号。
本公开的显示装置、显示面板及其驱动方法，在驱动过程中，向像素驱动芯片的控制信号端输入控制信号，向所述数据信号端输入第一数据信号；以及向像素驱动芯片的数据信号端输入第二数据信号，以使各像素驱动芯片将数据信号提供给对应的像素，从而实现了有源寻址的驱动方式，且由于像素组中的多个像素连接于同一个像素驱动芯片，从而减小了衬底基板上信号走线的数量，降低了工艺难度，并且降低了整体显示模组的驱动功耗和驱动成本，大大提高了产品的竞争优势。
附图说明
图1是本公开实施方式的显示面板的示意图。
图2是图1中显示区的示意图。
图3是图2中像素这列与像素驱动芯片的分布示意图。
图4是图2中像素组与像素驱动芯片的示意图。
图5是本公开实施方式的显示面板中像素组与像素驱动芯片的另一示意图。
图6是本公开实施方式的显示面板中像素组与像素驱动芯片的又一示意图。
图7是本公开实施方式的未设置供电电压端的像素驱动芯片的连接示意图。
图8是本公开实施方式的显示面板的驱动方法对应的时序图。
图9是本公开实施方式的像素驱动芯片的信号通道端的时序图。
图10是本公开实施方式的数据信号的编码示意图。
附图标记说明：1、像素；101、第一子像素；102、第二子像素；103、第三子像素；2、像素驱动芯片；3、控制信号端；4、数据信号端；5、供电电压端；6、接地端；7、信号通道端；8、像素组；9、控制芯片；10、显示区；11、周边区；100、像素列；200、芯片列；300、像素行；400、芯片行。
具体实施方式
这里将详细地对示例性实施方式进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施方式中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置的例子。
在本公开使用的术语是仅仅出于描述特定实施方式的目的，而非旨在限制本公开。除非另作定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”或者“若干”表示两个及两个以上。除非另行指出，“前部”、“后部”、“下部”和/或“上部”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接， 不管是直接的还是间接的。在本公开说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
本公开实施方式提供一种显示面板。如图1至图4所示，该显示面板可以包括衬底基板、像素阵列以及像素驱动芯片2，其中：
该像素阵列设于衬底基板上。该像素阵列包括像素组8。该像素组8包括多个像素1。该像素驱动芯片2的数量为多个。多个像素驱动芯片2设于衬底基板上，且用于驱动像素阵列进行显示。该像素驱动芯片2包括用于接收数据信号的数据信号端4以及用于接收控制信号的控制信号端3。其中，该像素组8中的多个像素1连接于同一个像素驱动芯片2。
本公开实施方式的显示面板，在驱动过程中，向像素驱动芯片2的控制信号端3输入控制信号，向像素驱动芯片2的数据信号端4输入第一数据信号；以及向像素驱动芯片2的数据信号端4输入第二数据信号，以使各像素驱动芯片2将数据信号提供给对应的像素1，从而实现了有源寻址的驱动方式，且由于像素组8中的多个像素1连接于同一个像素驱动芯片2，从而减小了衬底基板上信号走线的数量，降低了工艺难度，并且降低了整体显示模组的驱动功耗和驱动成本，大大提高了产品的竞争优势。
下面对本公开实施方式的显示面板的各部分进行详细说明：
该衬底基板可以为刚性衬底基板，材料包括例如玻璃、石英、PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)、塑料等，但本公开实施方式对此不做特殊限定。
该像素阵列设于衬底基板上。如图1所示，该显示面板可以包括显示区10以及围绕显示区10的周边区11。该像素阵列可以位于显示面板的显示区10。如图3所示，该像素阵列可以包括多个像素行300以及多个像素列100。 该像素行300可以沿着第一方向延伸，该像素列100可以沿着第二方向延伸。该第一方向可以与第二方向垂直。该像素行300的数量可以为偶数，但本公开不限于此，还可以为奇数。该像素列100的数量也可以为偶数，但本公开不限于此，还可以为奇数。该像素行300可以包括多个像素1。该像素列100可以包括多个像素1。如图4所示，该像素1可以包括多个子像素。该多个子像素的出射光的颜色可以不同，当然，也可以相同。具体地，该多个子像素可以包括第一子像素101、第二子像素102以及第三子像素103。该第一子像素101可以为红色子像素，当然，也可以为蓝色子像素，但本公开不限于此，还可以为绿色子像素。该第二子像素102可以为红色子像素，当然，也可以为蓝色子像素，但本公开不限于此，还可以为绿色子像素。该第三子像素103可以为红色子像素，当然，也可以为蓝色子像素，但本公开不限于此，还可以为绿色子像素。以多个子像素的出射光的颜色不同为例，该第一子像素101为红色子像素，用于发红色光；该第二子像素102为蓝色子像素，用于发蓝色光；该第三子像素103为绿色子像素，用于发绿色光。各子像素可以包括一个或多个发光二极管。该发光二极管可以为Mini LED，当然，该发光二极管可以为Micro LED，但本公开实施方式不限于此。以子像素包括两个发光二极管为例，该两个发光二极管并联连接，且颜色相同。此外，该发光二极管在衬底基板上的正投影可以呈四边形，其宽度可以为70μm-100μm，其长度可以为120μm-180μm。该发光二极管为独立元件，其可以通过表面贴装技术(SMT)或巨量转移技术设于衬底基板上。
如图1所示，该像素阵列可以包括一个像素组8，当然，该像素阵列也可以包括多个像素组8，也就是说，该像素阵列中的多个像素1可以分为多个像素组8。多个像素组8中存在至少一个像素组8包括多个像素1。以像素组8的数量为多个为例，多个像素组8中像素1的数量可以相同，当然，也可以存在两个像素组8中的像素1的数量不同。
该像素组8的多个像素1中存在多个像素1可以位于像素阵列中不同 的像素行300，也就是说，该像素组8的多个像素1中存在至少两个像素1可以位于像素阵列中不同的像素行300。其中，所述的不同的像素行300可以为顺序排列的像素行300，但本公开实施方式对此不做特殊限定。以像素组8中包括四个像素1为例，该四个像素1中存在两个像素1位于不同的像素行300，该两个像素1的一个像素1位于第n像素行300，另一个像素1位于第(n+1)像素行300，n为大于等于1的整数，第n像素行300和第(n+1)像素行300为顺序排列的像素行300。当然，该四个像素1中也可以存在三个像素1位于不同的像素行300，三个像素1的一个像素1位于第n像素行300，另一个像素1位于第(n+1)像素行300，剩余一个像素1位于第(n+2)像素行300。进一步地，如图6所示，该四个像素1中的各像素1位于不同的像素行300，例如四个像素1位于同一像素列100。
当然，该像素组8的多个像素1中也可以存在多个像素1位于像素阵列中不同的像素列100，也就是说，该像素组8的多个像素1中存在至少两个像素1可以位于像素阵列中不同的像素列100。其中，所述的不同的像素列100可以为顺序排列的像素列100，但本公开实施方式对此不做特殊限定。以像素组8中包括四个像素1为例，该四个像素1中存在两个像素1位于不同的像素列100，该两个像素1的一个像素1位于第m像素列100，另一个像素1位于第(m+1)像素列100，m为大于等于1的整数，第m像素列100和第(m+1)像素列100为顺序排列的像素列100。当然，该四个像素1中也可以存在三个像素1位于不同的像素列100，三个像素1的一个像素1位于第m像素列100，另一个像素1位于第(m+1)像素列100，剩余一个像素1位于第(m+2)像素列100。进一步地，如图5所示，该四个像素1中的各像素1位于不同的像素列100，例如四个像素1位于同一像素行300。
该像素组8的多个像素1也可以沿着同一方向分布。在本公开一实施方式中，如图5所示，该像素组8的多个像素1可以位于像素阵列中的同一像素行300，且位于同一像素行300中的多个像素1顺序排布。为便于描述， 对图5中四个像素1从左向右进行顺序标号，与像素驱动芯片2距离最近的第二像素1和第三像素1之间的间距，稍大于第一像素1和第二像素1之间的间距，以及大于第三像素1和第四像素1之间的间距。然而，在实际布局设计中，任意两个像素1在行方向上也可以是等间距排布的，本公开实施例对此不做限定，实际设计时以像素驱动芯片2不影响所有像素1的显示效果为准。在本公开另一实施方式中，如图6所示，该像素组8的多个像素1可以位于像素阵列中的同一像素列100，且位于同一像素列100中的多个像素1顺序排布。为便于描述，从上至下对图6中四个像素1进行顺序标号，与像素驱动芯片2距离最近的第二像素1和第三像素1之间的间距，稍大于第一像素1和第二像素1之间的间距，以及大于第三像素1和第四像素1之间的间距。然而，在实际布局设计中，任意两个像素1在列方向上也可以是等间距排布的，本公开实施例对此不做限定，实际设计时以像素驱动芯片2不影响所有像素1的显示效果为准。
如图4所示，该像素驱动芯片2设于衬底基板上。该像素驱动芯片2与像素1可以设于衬底基板的同一侧，当然，像素驱动芯片2与像素1可以设于衬底基板相反的两侧。该像素驱动芯片2与像素1连接。其中，该像素驱动芯片2可以与像素1中的多个子像素均连接。具体地，该像素驱动芯片2的信号端可以包括多个信号通道端7，且像素驱动芯片2的多个信号通道端7一一对应地与像素1中的多个子像素连接。以子像素包括发光二极管为例，该信号通道端7可以与发光二极管的第一电极连接。该第一电极可以为负极，当然，该第一电极也可以为正极。该像素驱动芯片2的信号端包括数据信号端4以及控制信号端3。该数据信号端4用于接收数据信号，该控制信号端3用于接收控制信号。该数据信号可以包括第一数据信号和第二数据信号。此外，该像素驱动芯片2的信号端还可以包括供电电压端5和/或接地端6。以像素驱动芯片2的信号端的数量为X个为例，位于行方向的信号端的最大数量为a个，位于列方向的信号端的最大数量为b个，其中，a、b、X均为整数， a与b的乘积小于等于X。需要说明的是，对于本公开的像素驱动芯片2，a与b的差值的绝对值最小。如此设置，可以避免像素驱动芯片2在单个方向上的尺寸过大，解决了由于像素驱动芯片2在单个方向上的尺寸过大所导致的多个像素1在单个方向上的间距过大的问题。以像素驱动芯片2的信号端的数量为16个为例，行方向上的信号端的数量以及列方向上的信号端的数量均为4个。
该像素驱动芯片2在衬底基板上的正投影可以呈四边形，其宽度可以为350μm-450μm，其长度可以为350μm-450μm。该像素驱动芯片2在衬底基板上的正投影的长度和宽度可以相同，但本公开对此不做特殊限定。该像素驱动芯片2在衬底基板上的正投影的面积可以为像素1中的发光二极管在衬底基板上的正投影的面积的8倍-15倍。该像素驱动芯片2为独立元件，其可以通过表面贴装技术(SMT)组装于衬底基板上。该衬底基板上设有焊盘，在通过表面贴装技术将像素驱动芯片2组装于衬底基板的过程中，该像素驱动芯片2的信号端与焊盘固定连接。
该像素驱动芯片2的数量为多个，通过多个像素驱动芯片2的共同作用以驱动像素阵列进行显示。其中，如图1和图4所示，像素组8中的多个像素1连接于同一个像素驱动芯片2，也就是说，多个像素1中的多个子像素均连接于同一像素驱动芯片2。以像素组8包括四个像素1且各像素1包括三个子像素为例，该四个像素1中的三个子像素均连接于同一像素驱动芯片2，即该像素驱动芯片2与十二个子像素连接；该像素驱动芯片2可以包括十二个信号通道端7，该十二个信号通道端7一一对应地与各子像素的发光二极管的第一电极连接。以上述像素组8的数量为多个为例，多个像素驱动芯片2一一对应地用于驱动多个像素组8进行显示。
如图3所示，本公开的多个像素驱动芯片2可以呈阵列分布，以构成多个芯片列200以及多个芯片行400。该芯片行400与上述的像素行300可以平行。该芯片列200与上述的像素列100可以平行。该芯片列200中像素驱 动芯片2的数量可以小于等于像素列100中像素1的数量。多个芯片列200中存在至少一个芯片列200位于相邻的两个像素列100之间，且位于相邻的两个像素列100之间的芯片列200用于驱动该相邻的两个像素列100进行显示。其中，所述相邻的两个像素列100之间仅存在一个芯片列200。所述相邻的两个像素列100可以构成多个像素组8，各像素组8中所包括的像素1的数量可以相同或不同，且多个像素组8沿着像素列100的延伸方向分布。以各像素列100包括六行像素1且各像素组8包括四个像素1为例，对于所述相邻的两个像素列100，第一行的两个像素1和第二行的两个像素1可以构成一个像素组8，第三行的两个像素1和第四行的两个像素1可以构成另一个像素组8，第五行的两个像素1和第六行的两个像素1可以构成又一个像素组8。此外，位于所述相邻的两个像素列100之间的芯片列200中的多个像素驱动芯片2一一对应地与多个像素组8连接。
当然，本公开的多个像素驱动芯片2也可以不呈阵列分布，只要使一个像素驱动芯片2与像素组8中的多个像素1连接，即可减小衬底基板上信号走线的数量。在一实施方式中，多个像素驱动芯片2构成多个芯片行400，但没有构成芯片列200，各芯片行400中的像素驱动芯片2的数量可以相等。在另一实施方式中，多个像素驱动芯片2构成多个芯片列200，但没有构成芯片行400，各芯片列200中的像素驱动芯片2的数量可以相等。
如图1、图2以及图3所示，本公开实施方式的显示面板还包括多个电源信号线。该电源信号线可以与像素列100平行设置。该电源信号线与像素1连接。其中，该电源信号线与像素1中的子像素连接。具体而言，该电源信号线与子像素的发光二极管的第二电极连接。以上述发光二极管的第一电极为负极为例，该第二电极可以为正极；以上述发光二极管的第一电极为正极为例，该第二电极可以为负极。其中，对于上述的位于相邻的两个芯片列200之间的两个所述像素列100，该两个像素列100中的第一子像素101连接于同一个电源信号线，从而减少了电源信号线的数量。此外，如图1和图4所示， 该电源信号线可以包括第一电源信号线VR和第二电源信号线VGB。各像素1中的红色子像素可以与第一电源信号线VR连接，各像素1中的绿色子像素和蓝色子像素均连接于第二电源信号线VGB。
如图3所示，第(4k-3)像素列100和第(4k-2)像素列100之间设有第(2k-1)芯片列200，第(4k-2)像素列100和第(4k-1)像素列100之间不存在芯片列200，第(4k-1)像素列100和第4k像素列100之间设有第2k芯片列200，该第(2k-1)芯片列200和第2k芯片列200之间设有第(4k-2)像素列100和第(4k-1)像素列100；其中，第(2k-1)芯片列200用于驱动第(4k-3)像素列100以及第(4k-2)像素列100进行显示，第2k芯片列200用于驱动第(4k-1)像素列100和第4k像素列100进行显示；第(4k-2)像素列100中的第一子像素101与第(4k-1)像素列100中的第一子像素101可以共用电源信号线，其中，k为正整数。此外，第(4k-3)像素列100和第(4k-2)像素列100之间的距离可以大于第(4k-2)像素列100和第(4k-1)像素列100之间的距离，第(4k-1)像素列100和第4k像素列100之间的距离也可以大于第(4k-2)像素列100和第(4k-1)像素列100之间的距离。
也就是说，部分相邻的两个像素行300之间设置有像素驱动芯片2，而另一部分相邻的两个像素行300之间没有像素驱动芯片2；之间设置有像素驱动芯片2的相邻的两个像素行300之间的间距，大于未设置有像素驱动芯片2的相邻的两个像素行300之间间距。部分相邻的两个像素列100之间设置有像素驱动芯片2，而另一部分相邻的两个像素列100之间没有像素驱动芯片2；之间设置有像素驱动芯片2的相邻的两个像素列100之间的间距，大于未设置有像素驱动芯片2的相邻的两个像素列100之间间距。然而，在实际布局设计中，任意两个相邻的像素行300在列方向上可以是等间距排布的，任意两个相邻的像素列100在行方向上可以是等间距排布的，本公开实施例对此不做限定，实际设计时以像素驱动芯片2不影响所有像素1的显示效果为准。
如图1、图2以及图3所示，本公开实施方式的显示面板还可以包括多个数据信号线DATA。该数据信号线DATA可以与像素列100平行设置。该 数据信号线DATA可以与像素驱动芯片2的数据信号端4连接。上述芯片列200中各像素驱动芯片2的数据信号端4可以连接于同一数据信号线DATA，但本公开实施方式对此不做特殊限定。本公开实施方式的显示面板还可以包括多个控制信号线DE。该控制信号线DE可以与像素阵列中的像素行300平行设置。该控制信号线DE可以与像素驱动芯片2的控制信号端3连接。上述芯片行400中各像素驱动芯片2的控制信号端3可以连接于同一控制信号线DE，但本公开实施方式对此不做特殊限定。如图1所示，本公开实施方式的显示面板还可以包括控制芯片9。该控制芯片9可以与控制信号线DE以及数据信号线DATA连接，用于向控制信号线DE提供控制信号，并用于向数据信号线DATA提供数据信号。该控制芯片9可以位于显示面板的周边区11。
如图1、图2以及图3所示，本公开实施方式的显示面板还可以包括多个供电电压线VCC。该供电电压线VCC可以与上述的像素列100平行设置。该供电电压线VCC可以与像素驱动芯片2的供电电压端5连接。上述芯片列200中各像素驱动芯片2的供电电压端5可以连接于同一供电电压线VCC，但本公开实施方式对此不做特殊限定。本公开实施方式的显示面板还可以包括多个接地线GND。该接地线GND可以与上述的像素列100平行设置。该接地线GND可以与像素驱动芯片2的接地端6连接。上述芯片列200中各像素驱动芯片2的接地端6可以连接于同一接地线GND，但本公开实施方式对此不做特殊限定。本公开的供电电压端5用于接收供电电压，控制信号端3用于接收控制信号，通过两个信号端口分别接收供电电压和控制信号，从而能够避免像素驱动芯片2因错误读取控制信号而导致像素驱动芯片2出现异常工作状态，防止显示效果受到影响。
需要说明的是，本公开的第一电源信号线VR、第二电源信号线VGB、控制信号线DE、数据信号线DATA、接地线GND以及供电电压线VCC等信号线可以直接形成在衬底基板上，例如可以通过成膜、图案化等工艺制备而成。本公开可以在所述的信号线通过成膜、图案化等工艺形成之后，再将像 素驱动芯片2组装于衬底基板上。其中，像素驱动芯片2在衬底基板上的正投影与信号线的部分区域在衬底基板上的正投影存在交叠区域，可以最大化合理利用布线空间，提高像素排布密度。
在本公开其它实施方式中，如图7所示，供电电压和地址信号可以由像素驱动芯片2的同一个信号端输入，例如从控制信号端3输入。举例而言，本公开可以通过控制信号端3接收信号的信号幅值来区分控制功能和供电功能。例如，信号幅值高于某一预设电平时执行控制功能；信号幅值低于某一预设电平时执行供电功能。
以分辨率为160*180的显示面板为例，在像素驱动芯片2与像素1按照图4所示结构进行连接时，该显示面板需要80个数据信号线DATA、90个控制信号线DE、80个接地线GND，相较于单颗像素驱动芯片2驱动单个像素1的驱动方案，本公开实施例可以减少一半的走线数量；位于相邻的两个芯片列200之间的两个像素列100可共用第一电源信号线VR和第二电源信号线VGB，也就是说，对于图1中的显示面板，左右两侧的像素列100不与其它像素列100共用第一电源信号线VR和第二电源信号线VGB，位于左右两侧像素列100之间的像素列100会共用第一电源信号线VR和第二电源信号线VGB，使的第一电源信号线VR和第二电源信号线VGB各自为81个，使得显示面板上的走线数量大大减少，降低了生产成本，大大提高产品的竞争优势。
以分辨率为160*180的显示面板为例，在像素驱动芯片2与像素1按照图5所示结构进行连接时，该显示面板需要40个数据信号线DATA，180个控制信号线DE，40个接地线GND，40个供电电压线VCC，第一电源信号线VR和第二电源信号线VGB各自为160个。
以显示面板的分辨率为160*180为例，在像素驱动芯片2与像素1按照图6所示结构进行连接时，该显示面板需要160个数据信号线DATA，45个控制信号线DE，160个接地线GND，160个供电电压线VCC，第一电源信 号线VR和第二电源信号线VGB各自为160个。
本公开实施方式还提供一种显示装置。该显示装置可以包括上述任一实施方式所述的显示面板。该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置所包括的显示面板同上述显示面板的实施方式中的显示面板相同，因此，其具有相同的有益效果，本公开在此不再赘述。
本公开实施方式还提供显示面板的驱动方法。该显示面板可以采用上述任一实施方式所述的显示面板。以显示面板中每个像素驱动芯片2用于驱动一个像素组8，每个像素组8包括四个像素1为例，显示面板上阵列设置有4M*N个像素1，以及N行M列像素驱动芯片2，其中M和N均为正整数。该显示面板在显示时，其一帧可以包括地址分配阶段和数据信号传输阶段。如图8所示，该显示面板的驱动方法可以包括S1阶段和S3阶段，其中：
向各像素驱动芯片2分配地址阶段为S1阶段。
同一芯片行400中各像素驱动芯片2的控制信号端3与一根控制信号线DE连接，同一芯片列200中各像素驱动芯片2的数据信号端4与一根数据信号线DATA连接为例。如图8所示，在S1阶段，控制芯片9通过多根数据信号线DATA向多个芯片列200输入第一数据信号，控制芯片9通过多个控制信号线DE向多个芯片行400逐行依次输入控制信号，以控制位于同一芯片行400的像素驱动芯片2的数据信号端4能够同时接收来自不同数据信号线传输的第一数据信号。具体地，显示面板包括N个芯片行400以及N个控制信号线，如图8所示，第一控制信号线DE 1传输控制信号时，第一芯片行400中的像素驱动芯片2被触发，其余芯片行400未被触发，各数据信号线DATA向位于第一芯片行400中不同芯片列200的像素驱动芯片2同时传输不同的第一数据信号，第一芯片行400中的各列像素驱动芯片2接收第一数据信号；在控制芯片9通过第N控制信号线DE N传输控制信号时,向第N芯片行400中的像素驱动芯片2被触发，其余芯片行400未被触发，各数据信号线DATA 向位于第N芯片行400中不同芯片列200的像素驱动芯片2同时传输不同的第一数据信号，第N芯片行400中的各列像素驱动芯片2接收第一数据信号。该第一数据信号可以为数字信号，具体可以包括依次设置的起始指令SoT、地址信息ID、间隔指令DCX及结束指令EoT。由于第一数据信号中包括地址信息ID，可以对像素驱动芯片2设定地址信息ID。该第一数据信号的长度可以设置为12bit，其中，起始指令SoT可以设为1bit，地址信息ID可以设为8bit、间隔指令DCX可以设为1bit，结束指令EoT可以设为2bit。各像素驱动芯片2接收第一数据信号后，将其中的地址信息ID存储在各像素驱动芯片2内部。
可以理解的是，在S1阶段之前，本公开的像素驱动芯片2可能处于睡眠状态，该睡眠状态为低功耗工作模式或非工作状态。通过供电电压线VCC向像素驱动芯片2的供电电压端5输入供电电压以使像素驱动芯片2解除睡眠状态，即图8中的S0阶段。
向像素驱动芯片2的数据信号端4输入第二数据信号的阶段为S3阶段，也称为数据信号传输阶段。
如图8所示，S3阶段，上述的控制芯片9通过多个数据信号线DATA向多个芯片列200输入第二数据信号。其中，本公开是同时向多个芯片列200输入第二数据信号。每个第二数据信号多个子数据信息Subdata_1、Subdata_2……Subdata_N。
每个子数据信息中包括地址信息ID和像素数据信息。其中，该子数据信息可以为数字信号，具体地，可以包括：起始指令SoT、地址信息ID、数据传输指令DCX、间隔指令IoT、像素数据信息及结束指令EoT。其中，像素数据信息包括多个子像素数据Rda 1、Rda 2、Rda 3、Rda 4、Gda 1、Gda 2、Gda 3、Gda 4、Bda 1、Bda 2、Bda 3、Bda 4；数据传输指令DCX为设定值时，表示进行数据传输，例如DCX＝1时，表示数据传输，当像素驱动芯片2识别到DCX的值为1时，将子数据信息中的像素数据信息传输给对应的像素。子像素数 据Rda 1、Rda 2、Rda 3、Rda 4表示与该像素驱动芯片2连接的4个像素1中的各个红色子像素发光所需的数据信息，子像素数据Gda 1、Gda 2、Gda 3、Gda 4表示与该像素驱动芯片2连接的4个像素1中的各个绿色子像素发光所需的数据信息，子像素数据Bda 1、Bda 2、Bda 3、Bda 4表示与该像素驱动芯片2连接的4个像素1中的各个蓝色子像素发光所需的数据信息。
在具体实施时，每个子数据信息的长度可以设置为63bit，其中，起始指令SoT占1bit，地址信息ID占8bit，数据传输指令DCX占1bit，间隔指令IoT占1bit，子像素数据Rda 1、Rda 2、Rda 3、Rda 4共占16bit，子像素数据Gda 1、Gda 2、Gda 3、Gda 4共占16bit，子像素数据Bda 1、Bda 2、Bda 3、Bda 4共占16bit，结束指令EoT占2bit，此外，任意相邻的两个子数据信息之间可以设置间隔指令IoT。可以理解的是，由于一个像素驱动芯片2用于驱动一个像素组8中共计四个像素1，而与该像素驱动芯片2连接的四个像素1之间的序号关系，可以通过像素驱动芯片内部的数字逻辑电路实现，以将像素数据信息中各子像素数据的准确分发到对应信号通道端7。
即，可以理解的是，每个子数据信息中的地址信息ID与S1阶段各像素驱动芯片2接收到的地址信息ID相对应，而像素数据信息包括该像素驱动芯片2所驱动的各个像素1的数据信息集合。
其中，多个子数据信息可以按特定顺序(例如特定顺序可以为各芯片列200中多个像素驱动芯片2沿列方向的排列顺序)依次排列构成第二数据信号，多个子数据信息也可以不按所述的特定顺序进行排列，本公开在此不做限定。
第二数据信号通过数据信号线DATA传输给同一列的像素驱动芯片2，各像素驱动芯片2通过对第二数据信号中的多个子数据信息中的地址信息ID进行解码匹配，从而选择性地接收与在S1阶段接收并存储的相同地址信息ID所对应的子数据信息，获取该子数据信息中的像素数据信息。
像素驱动芯片2的各个信号通道端7与其对应的子像素形成信号通路。具体地，像素驱动芯片2被配置为驱动四个像素1，每个像素1包括三个不同颜色的子像素，因此，像素驱动芯片2包括十二个信号通道端7，每个信号通道端7与不同的子像素连接。在S3阶段之后，像素驱动芯片2接收并存储有其所连接的四个像素1的数据信息，连接于不同颜色子像素的信号通道端7可以不同时打开，以使不同颜色子像素被驱动的的时间不同。具体地，如图4、图7以及图9所示，连接于红色子像素的信号通道端7(R1)、7(R2)、7(R3)、7(R4)可以先全部打开，即图9中的CH_R出现有效电平的时间段内，所有的红色子像素线先被驱动；相比连接于红色子像素的信号通道端7(R1)、7(R2)、7(R3)、7(R4)，连接于绿色子像素的信号通道端7(G1)、7(G2)、7(G3)、7(G4)可以延迟几纳秒打开，即图9中的CH_G晚于CH_R出现有效电平，CH_G出现有效电平的时间段内绿色子像素被驱动；相比连接于绿色子像素的信号通道端7(G1)、7(G2)、7(G3)、7(G4)，连接于蓝色子像素的信号通道端7(B1)、7(B2)、7(B3)、7(B4)可以再延迟几纳秒打开，即图9中的CH_B晚于CH_G出现有效电平，CH_B出现有效电平的时间段内蓝色子像素被驱动。如此设置，可以降低像素驱动芯片2的瞬态负载能力和瞬态噪声，且虽然各颜色子像素在时序上相互延迟几纳秒被驱动，人眼几乎察觉不到，视效上是同时亮的，从而实现全彩画面的准确显示。
图10为本公开的第一数据信号以及第二数据信号的编码示意图。如图10所示，本公开可以通过设计脉冲序列中的占空比来表示第一数据信号以及第二数据信号中各bit位的含义。例如脉冲序列中某个脉冲的占空比为25％时，表示该bit位代表0；某个脉冲的占空比为75％时，表示该bit位代表1；某个脉冲的占空比为50％时，表示该bit位为开始指令SoT；当连续两个脉冲的占空比均为50％时，即出现2个连续的SoT，则该2bit位的含义为结束指令EoT。
如图8所示，本公开显示面板的一个显示帧还可以包括位于地址分配阶段S1与数据信号传输阶段S3之间的电流设定阶段S2。在电流设定阶段S2， 向像素驱动芯片2的数据信号端4输入电流设定信息Co，以控制像素驱动芯片2的驱动电流的大小，进而进一步精确控制对应像素1的出光亮度。该电流设定信息Co的长度可以为63bit，具体可以包括：1bit的起始指令SoT、8bit的地址信息ID、1bit的电流设定指令DCX、1bit的间隔指令IoT、由帧起始指令C和控制指令(例如表示信号通道端7需要提供给发光二极管的电流幅值校正系数)共同组成的16bit数据、1bit的间隔指令IoT、16bit的预留控制指令位、1bit的间隔指令IoT、16bit的预留控制指令位，以及2bit的结束指令EoT。其中，电流设定指令DCX为设定值时表示进行电流设定，例如DCX为0时，表示进行电流设定。
可以理解的是，显示面板在逐帧显示画面的过程中，可以仅在显示第一帧画面(即CH_R、CH_G、CH_B的有效阶段，对应像素被驱动的阶段)前，需要依次执行阶段S0、阶段S1、阶段S2、阶段S3，而在显示第一帧之后的帧画面前，显示面板可以只执行阶段S2和阶段S3，甚至仅执行阶段S3。
可以理解的是，本公开实施例以一个像素驱动芯片向具有四个像素的像素组提供信号为例进行说明，如显示面板包括奇数行或奇数列像素，也可以采用本公开提供的实施例进行设计和驱动，其中，可以将部分像素驱动芯片的部分信号通道端悬空(即不与任何元器件连接)，或者在显示面板中设置向具有奇数个像素的像素组提供信号的像素驱动芯片，本公开在此不做限定。
以上所述仅是本公开的较佳实施方式而已，并非对本公开做任何形式上的限制，虽然本公开已以较佳实施方式揭露如上，然而并非用以限定本公开，任何熟悉本专业的技术人员，在不脱离本公开技术方案的范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施方式所作的任何简单修改、等同变化与修饰，均仍属于本公开技术方案的范围内。

Claims (23)

  1. 一种显示面板，其特征在于，包括：
    衬底基板；
    像素阵列，设于所述衬底基板上，且包括像素组，所述像素组包括多个像素；
    多个像素驱动芯片，设于所述衬底基板上，且用于驱动所述像素阵列进行显示，所述像素驱动芯片包括用于接收数据信号的数据信号端以及用于接收控制信号的控制信号端；
    其中，所述像素组中的多个所述像素连接于同一个所述像素驱动芯片。
  2. 根据权利要求1所述的显示面板，其特征在于，所述像素组中存在多个所述像素位于所述像素阵列中不同的像素行。
  3. 根据权利要求1所述的显示面板，其特征在于，所述像素组中存在多个所述像素位于所述像素阵列中不同的像素列。
  4. 根据权利要求1所述的显示面板，其特征在于，所述像素组中的多个所述像素沿着一个方向分布。
  5. 根据权利要求4所述的显示面板，其特征在于，所述像素组中的多个像素位于所述像素阵列中的同一像素行。
  6. 根据权利要求4所述的显示面板，其特征在于，所述像素组中的多个像素位于所述像素阵列中的同一像素列。
  7. 根据权利要求1所述的显示面板，其特征在于，多个所述像素驱动芯片包括至少一个芯片列，所述芯片列与所述像素阵列中的像素列平行，所述芯片列位于相邻的两个所述像素列之间。
  8. 根据权利要求7所述的显示面板，其特征在于，相邻的两个所述像素列构成多个所述像素组，多个所述像素组沿着所述像素列的延伸方向分布，位于相邻两个所述像素列之间的所述芯片列中的多个所述像素驱动芯片一一对应地与多个所述像素组连接。
  9. 根据权利要求7所述的显示面板，其特征在于，多个所述像素驱动芯片构成多个芯片列，相邻的两个所述芯片列之间存在两个所述像素列。
  10. 根据权利要求9所述的显示面板，其特征在于，所述像素包括第一子像素，所述显示面板还包括：
    多个电源信号线，位于相邻的两个所述芯片列之间的两个所述像素列中的所述第一子像素连接于同一个所述电源信号线。
  11. 根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括：
    电源信号线，与所述像素连接。
  12. 根据权利要求11所述的显示面板，其特征在于，所述像素包括子像素，所述子像素包括发光二极管，所述电源信号线连接于所述发光二极管的正极，所述像素驱动芯片连接于所述发光二极管的负极。
  13. 根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括：
    数据信号线，与所述数据信号端连接。
  14. 根据权利要求13所述的显示面板，其特征在于，所述数据信号线的数量为多个，多个所述像素驱动芯片包括至少一个芯片列，所述芯片列中的多个所述像素驱动芯片的所述数据信号端连接于同一个所述数据信号线。
  15. 根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括：
    控制信号线，与所述控制信号端连接。
  16. 根据权利要求15所述的显示面板，其特征在于，所述控制信号线的数量为多个，多个所述像素驱动芯片包括至少一个芯片行，所述芯片行中的多个所述像素驱动芯片的所述控制信号端连接于同一个所述控制信号线。
  17. 根据权利要求15所述的显示面板，其特征在于，所述显示面板还包括:
    数据信号线，与所述数据信号端连接；
    控制芯片，与所述控制信号线以及所述数据信号线连接，用于向所述控制信号线提供控制信号，并用于向所述数据信号线提供数据信号。
  18. 根据权利要求17所述的显示面板，其特征在于，所述显示面板包括 显示区以及围绕所述显示区的周边区，所述像素驱动芯片位于所述显示区，所述控制芯片位于所述周边区。
  19. 根据权利要求1所述的显示面板，其特征在于，所述像素驱动芯片还包括供电电压端和/或接地端。
  20. 根据权利要求1所述的显示面板，其特征在于，所述像素行和所述像素列的数量均为偶数。
  21. 根据权利要求1所述的显示面板，其特征在于，多个所述像素驱动芯片呈阵列分布。
  22. 一种显示装置，其特征在于，包括权利要求1-21任一项所述的显示面板。
  23. 一种显示面板的驱动方法，其特征在于，采用权利要求1-21任一项所述的显示面板，所述显示面板的一个显示帧包括地址分配阶段和数据信号传输阶段，所述驱动方法包括：
    在所述地址分配阶段，向所述控制信号端输入控制信号，向所述数据信号端输入第一数据信号；
    在所述数据信号传输阶段，向所述数据信号端输入第二数据信号。
PCT/CN2021/113910 2021-08-20 2021-08-20 显示装置、显示面板及其驱动方法 WO2023019598A1 (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US17/914,180 US20240221606A1 (en) 2021-08-20 2021-08-20 Display apparatuses, display panels, and methods of driving display panels
KR1020237026174A KR20240046105A (ko) 2021-08-20 2021-08-20 표시 장치, 표시 패널 및 그 구동 방법
PCT/CN2021/113910 WO2023019598A1 (zh) 2021-08-20 2021-08-20 显示装置、显示面板及其驱动方法
CN202180002239.0A CN116235237A (zh) 2021-08-20 2021-08-20 显示装置、显示面板及其驱动方法
EP21953839.4A EP4276810A4 (en) 2021-08-20 2021-08-20 DISPLAY DEVICE, DISPLAY BOARD AND CONTROL METHOD THEREFOR
JP2023546315A JP2024528762A (ja) 2021-08-20 2021-08-20 表示装置、表示パネル及びその駆動方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/113910 WO2023019598A1 (zh) 2021-08-20 2021-08-20 显示装置、显示面板及其驱动方法

Publications (1)

Publication Number Publication Date
WO2023019598A1 true WO2023019598A1 (zh) 2023-02-23

Family

ID=85239403

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/113910 WO2023019598A1 (zh) 2021-08-20 2021-08-20 显示装置、显示面板及其驱动方法

Country Status (6)

Country Link
US (1) US20240221606A1 (zh)
EP (1) EP4276810A4 (zh)
JP (1) JP2024528762A (zh)
KR (1) KR20240046105A (zh)
CN (1) CN116235237A (zh)
WO (1) WO2023019598A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024197836A1 (zh) * 2023-03-31 2024-10-03 京东方科技集团股份有限公司 显示面板和显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102077167A (zh) * 2008-06-30 2011-05-25 全球Oled科技有限责任公司 拼接电子显示器
CN102160181A (zh) * 2008-08-14 2011-08-17 全球Oled科技有限责任公司 具有嵌入的芯片驱动部的oled装置
CN102246304A (zh) * 2008-11-04 2011-11-16 全球Oled科技有限责任公司 具有小芯片和可适性互连的器件
US20140168037A1 (en) * 2012-12-17 2014-06-19 LuxVue Technology Corporation Smart pixel lighting and display microcontroller
CN111243496A (zh) * 2020-02-21 2020-06-05 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN111243497A (zh) * 2020-03-11 2020-06-05 京东方科技集团股份有限公司 像素结构、显示面板以及显示装置
CN113223443A (zh) * 2020-01-17 2021-08-06 厦门凌阳华芯科技有限公司 一种多像素led驱动芯片和led显示屏
CN114023248A (zh) * 2020-07-16 2022-02-08 华源智信半导体(深圳)有限公司 用于控制分布式驱动电路的具有二维共享线的显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015197543A (ja) * 2014-03-31 2015-11-09 ソニー株式会社 実装基板および電子機器

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102077167A (zh) * 2008-06-30 2011-05-25 全球Oled科技有限责任公司 拼接电子显示器
CN102160181A (zh) * 2008-08-14 2011-08-17 全球Oled科技有限责任公司 具有嵌入的芯片驱动部的oled装置
CN102246304A (zh) * 2008-11-04 2011-11-16 全球Oled科技有限责任公司 具有小芯片和可适性互连的器件
US20140168037A1 (en) * 2012-12-17 2014-06-19 LuxVue Technology Corporation Smart pixel lighting and display microcontroller
CN113223443A (zh) * 2020-01-17 2021-08-06 厦门凌阳华芯科技有限公司 一种多像素led驱动芯片和led显示屏
CN111243496A (zh) * 2020-02-21 2020-06-05 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN111243497A (zh) * 2020-03-11 2020-06-05 京东方科技集团股份有限公司 像素结构、显示面板以及显示装置
CN114023248A (zh) * 2020-07-16 2022-02-08 华源智信半导体(深圳)有限公司 用于控制分布式驱动电路的具有二维共享线的显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4276810A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024197836A1 (zh) * 2023-03-31 2024-10-03 京东方科技集团股份有限公司 显示面板和显示装置

Also Published As

Publication number Publication date
US20240221606A1 (en) 2024-07-04
CN116235237A (zh) 2023-06-06
EP4276810A4 (en) 2024-07-31
EP4276810A1 (en) 2023-11-15
KR20240046105A (ko) 2024-04-08
JP2024528762A (ja) 2024-08-01

Similar Documents

Publication Publication Date Title
US11645976B2 (en) Local passive matrix display
CN111243496B (zh) 一种像素电路及其驱动方法、显示装置
CN111522161B (zh) 一种阵列基板、显示面板、显示装置及驱动方法
CN201159981Y (zh) 扫描型led显示单元
CN104919900A (zh) 智能像素照明和显示微控制器
CN109872684B (zh) 一种显示面板、显示装置和显示面板的驱动方法
CN102360539A (zh) 硅基有机发光二极管微显示器驱动电路
CN102446490A (zh) 主动型硅基有机发光二级管的低功耗显示系统
US11935464B2 (en) Multi-row buffering for active-matrix cluster displays
WO2023019598A1 (zh) 显示装置、显示面板及其驱动方法
CN115968492A (zh) 显示驱动电路及方法、led显示板和显示装置
TWI792597B (zh) 陣列基板、其驅動方法及顯示裝置
CN111596780A (zh) 触控显示结构、智能设备及驱动方法
CN101246656B (zh) 一种发光元件显示单元
WO2021190182A1 (zh) 像素驱动电路、显示面板的驱动电路以及显示装置
WO2021102734A1 (zh) 显示基板及显示装置
KR20130039295A (ko) 액정 표시장치와 이의 구동방법
CN112863445A (zh) 像素驱动电路及oled显示面板、显示装置
TW202143206A (zh) 包含具有低功率操作模式的顯示螢幕的裝置
WO2022057902A1 (zh) 显示面板与半导体显示装置
CN220065729U (zh) 一种灯驱合一的led封装结构、led显示模组和led显示屏
WO2023206277A1 (zh) 电路组件、电子设备及驱动方法
WO2024113336A1 (zh) micro-LED像素的驱动电路、方法及系统
US11631376B1 (en) System architecture for high density mini/micro LED backlight application
KR200318371Y1 (ko) 삼원색 발광 다이오드 전광판 모듈을 이용한 다양한색채표현 제어회로

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17914180

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21953839

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2023546315

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2021953839

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2021953839

Country of ref document: EP

Effective date: 20230809

NENP Non-entry into the national phase

Ref country code: DE