WO2023019523A1 - 半导体器件、电子设备及制备方法 - Google Patents

半导体器件、电子设备及制备方法 Download PDF

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Publication number
WO2023019523A1
WO2023019523A1 PCT/CN2021/113595 CN2021113595W WO2023019523A1 WO 2023019523 A1 WO2023019523 A1 WO 2023019523A1 CN 2021113595 W CN2021113595 W CN 2021113595W WO 2023019523 A1 WO2023019523 A1 WO 2023019523A1
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Prior art keywords
word line
semiconductor substrate
area
etching
buried word
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PCT/CN2021/113595
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English (en)
French (fr)
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卢经文
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长鑫存储技术有限公司
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Priority to US17/651,279 priority Critical patent/US20230046960A1/en
Publication of WO2023019523A1 publication Critical patent/WO2023019523A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Definitions

  • the present disclosure relates to the field of storage technologies, and in particular to semiconductor devices, electronic equipment and manufacturing methods.
  • Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM for short) is a semiconductor storage device commonly used in computers, consisting of many repeated semiconductor devices. Each semiconductor device usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • a buried word line method can be used.
  • a general method for preparing a buried word line is as follows: providing a semiconductor substrate, forming a shallow trench isolation region on the semiconductor substrate to define an active region, and filling the shallow trench isolation region with silicon oxide. Afterwards, a word line trench passing through the silicon oxide in the active region and the shallow trench isolation region is formed by etching in the semiconductor substrate. Afterwards, a buried word line is formed in the word line trench.
  • the etching rates of the semiconductor substrate and silicon oxide are different, resulting in the unevenness of the bottom surface of the word line trench, which in turn leads to the bottom surface of the buried word line. Unevenness affects the performance and reliability of semiconductor devices.
  • the first aspect of the embodiments of the present disclosure provides a method for manufacturing a semiconductor device, which may include the following steps:
  • word line trenches forming a plurality of word line trenches on the semiconductor substrate; wherein the word line trenches extend along a first direction;
  • a word line structure is formed in each of the word line trenches; wherein, the top surface of the word line structure is flush with the top surface of the semiconductor substrate;
  • a plurality of active area mask structures are formed on the top surface of the semiconductor substrate; wherein the active area mask structures define an active area in the semiconductor substrate, and the active area mask
  • the orthographic projection of the film structure on the bottom surface of the semiconductor substrate extends along the second direction and passes through the orthographic projection of the word line structure on the bottom surface of the semiconductor substrate;
  • the word line structure and the semiconductor substrate are etched using the active area mask structure as an etching mask to form an active area and a buried word line passing through the active area.
  • the second aspect of the embodiments of the present disclosure provides a semiconductor device obtained by using the above-mentioned preparation method; the semiconductor device includes:
  • a semiconductor substrate having an isolation region formed by shallow trench isolation trenches and a plurality of active regions defined by the isolation region;
  • a plurality of buried word lines are buried in the word line grooves formed by etching the semiconductor substrate, and the buried word lines are intersected with corresponding active regions.
  • a third aspect of embodiments of the present disclosure provides electronic equipment, including the above-mentioned semiconductor device.
  • FIG. 1A is a schematic top view of a semiconductor device in the related art
  • Fig. 1B is a cross-sectional structure diagram of the semiconductor device shown in Fig. 1A in the direction of AA';
  • Fig. 1C is a cross-sectional structure diagram of the semiconductor device shown in Fig. 1A in the direction of BB';
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 3A is a schematic diagram of some structures in the process of preparing a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 3B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 3A;
  • FIG. 4A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 4B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 4A;
  • FIG. 5A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 5B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 5A;
  • FIG. 6A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 6B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 6A;
  • FIG. 7A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 7B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 7A;
  • FIG. 8A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 8B is a cross-sectional structural diagram corresponding to the schematic structural diagram shown in FIG. 8A;
  • FIG. 9A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 9B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 9A;
  • FIG. 9C is another schematic diagram of top view structures in the process of preparing semiconductor devices provided by the embodiments of the present disclosure.
  • FIG. 9D is another schematic diagram of top view structures in the process of preparing semiconductor devices provided by the embodiments of the present disclosure.
  • FIG. 10A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 10B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 10A;
  • FIG. 10C is another schematic diagram of the top view structure in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 11A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 11B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 11A;
  • FIG. 12A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 12B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 12A;
  • FIG. 13A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 13B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 13A;
  • Fig. 14A is some structural schematic diagrams of the prepared semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 14B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 14A;
  • Fig. 14C is another schematic top view structure diagram of the prepared semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 15A is another structural schematic diagram in the process of preparing a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 15B is a cross-sectional structure diagram corresponding to the structural schematic diagram shown in FIG. 15A;
  • FIG. 16A is another structural schematic diagram of the prepared semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 16B is a cross-sectional structural diagram corresponding to the schematic structural diagram shown in FIG. 16A .
  • FIG. 1A is a schematic top view of a semiconductor device in the related art.
  • Fig. 1B is a schematic cross-sectional structure diagram of the semiconductor device shown in Fig. 1A along the direction AA'.
  • Fig. 1C is a schematic cross-sectional structure diagram of the semiconductor device shown in Fig. 1A in the direction of BB'.
  • a common method for preparing a buried word line is: providing a semiconductor substrate 10 , forming a shallow trench isolation region on the semiconductor substrate 10 to define an active region 13 , and filling the shallow trench isolation region with silicon oxide 11 .
  • a word line trench passing through the silicon oxide in the active region and the shallow trench isolation region is formed by etching in the semiconductor substrate 10 .
  • buried word lines 12 are formed in the word line trenches. Since the word line trench not only passes through the semiconductor substrate 10 but also passes through the silicon oxide 11 in the shallow trench isolation region, and the etching selectivity ratios of the semiconductor substrate 10 and the silicon oxide 11 are different, so that the semiconductor substrate 10 and the silicon oxide 11 are different. The etching rate of the silicon 11 is different, resulting in the unevenness of the bottom surface of the etched word line trench, which in turn leads to the unevenness of the bottom surface of the buried word line 12, which affects the performance and reliability of the semiconductor device.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, by first forming a word line trench 101 on a semiconductor substrate 100, then forming a word line structure 130 in the word line trench 101, and then forming an active region .
  • the word line trench 101 can pass through the semiconductor substrate 100 without making the word line trench 101 pass through other materials. Since the material of the semiconductor substrate 100 is uniform, there is no problem of etching selectivity, so that the bottom surface of the formed word line trench 101 can be flat.
  • the word line structure 130 is formed in the word line trench 101, the word line structure 130 can be directly contacted with the semiconductor substrate 100 without making the word line structure 130 contact with other materials, so that the word line structure 130 can be made The bottom surface can be flat. Therefore, the bottom surface of the formed buried word line can also be flush, thereby improving the performance and reliability of the semiconductor device.
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure.
  • 3A to 14B are schematic structural views of the semiconductor device provided by the embodiments of the present disclosure after performing various steps.
  • the method for preparing a semiconductor device provided in the present disclosure specifically in this embodiment, includes the following steps:
  • the material of the semiconductor substrate 100 may include silicon, germanium, or silicon-on-insulator (SOI) semiconductors, or germanium-silicon compounds, silicon carbide, or other known materials, such as III and V group compounds such as gallium arsenide. . Certain dopant ions may also be implanted into the semiconductor substrate 100 according to design requirements to change electrical parameters.
  • the semiconductor substrate 100 may be a silicon substrate.
  • step S10 forming a plurality of word line trenches 101 on the semiconductor substrate 100 may specifically include the following steps: first, forming a trench mask layer covering the semiconductor substrate 100 on the semiconductor substrate 100 .
  • the trench mask layer may use one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide/nitride/oxide materials.
  • a layer of silicon nitride is deposited at a set deposition rate as the trench mask layer.
  • deposition method those skilled in the art can choose from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes , the present disclosure is not limited thereto.
  • deposition rate and the thickness of the trench mask layer those skilled in the art can also select other appropriate rates and thicknesses according to actual needs.
  • the trench mask layer is patterned to form a plurality of strip-shaped trench mask structures 200 extending along the first direction F1 .
  • a vapor phase etching process may be used to remove the trench mask layer on the area where the word line trench 101 to be formed is located, and retain the trench mask layer in the remaining area, so as to form stripes along the first direction F1.
  • the plurality of trench mask structures 200 are extended so that the gaps between adjacent trench mask structures 200 can expose the semiconductor substrate 100 where the word line trench 101 needs to be formed.
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the trench mask layer can be etch.
  • the semiconductor substrate 100 at the gap between adjacent trench mask structures 200 with a set distance is removed to form a plurality of word line trenches 101 extending along the first direction F1 .
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the The semiconductor substrate 100 exposed in the gap between adjacent trench mask structures 200 is etched. Furthermore, the semiconductor substrate 100 is etched at a set distance to form word line trenches 101 .
  • each word line trench 101 can be formed in the semiconductor substrate 100 without passing through other materials, so that each word line trench 101
  • the depths H1 of the word line trenches 101 are substantially equal, thereby making the bottom surface S1 of the word line trench 101 as flat as possible.
  • the bottom surface S1 of the word line trench 101 may not be completely flush, and there may be some deviations. Therefore, the bottom surface S1 of the word line trench 101 As long as the leveling relationship of s roughly satisfies the above conditions, all of them belong to the protection scope of the present disclosure.
  • the flatness of the bottom surface S1 of the above-mentioned word line trench 101 may be within an allowable error range.
  • the trench mask structure 200 is removed by etching.
  • the top surface of the word line structure 130 is flush with the top surface of the semiconductor substrate 100 , and the bottom surface of the word line structure 130 is formed on the bottom surface S1 of the word line trench 101 , so that A bottom surface of the word line structure 130 may be brought into contact with the semiconductor substrate 100 . In this way, the bottom surface of the word line structure 130 can be as flat as possible.
  • the word line structure 130 may include: a gate dielectric layer 131 formed on the sidewall of the word line trench 101, a buried word line filled in the word line trench 101 having the gate dielectric layer 131 132 and the insulating layer 133 filled on the buried word line 132 in the word line trench 101 .
  • the bottom surface of the word line trench 101 is as smooth as possible, the bottom surface of the word line trench 101 with the gate dielectric layer attached to the side wall is also as smooth as possible, so that the bottom surface of the buried word line 132 formed As flush as possible, which can reduce interference, performance and reliability of semiconductor devices.
  • step S20, forming the word line structure 130 in each word line trench 101 may specifically include the following steps: first, referring to FIG. 6A and FIG. Dielectric layer 131.
  • the gate dielectric layer 131 may include one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide/nitride/oxide, and high dielectric materials.
  • atomic layer deposition can be used to cover the sidewall of the word line trench 101 with silicon oxide to form the gate dielectric layer 131 .
  • the buried word line 132 is filled in the word line trench 101 formed with the gate dielectric layer 131, and the top surface WS1 of the formed buried word line 132 is lower than the semiconductor substrate.
  • the material of the buried word line 132 may include one or more of Ti, TiN, Ta, TaN, W, WN, TiSiN and WSiN.
  • the deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition process, in the word line trench TiN/W is formed in the trench 101 .
  • the TiN/W formed in the word line trench 101 is etched to a required height by an etching process to form a buried word line 132 whose top surface WS1 is lower than the top surface BS1 of the semiconductor substrate 100 .
  • an insulating layer 133 is filled on the buried word line 132 in the word line trench 101, and the top surface of the formed insulating layer 133 is flush with the top surface BS1 of the semiconductor substrate 100.
  • the material of the insulating layer 133 may include one or a combination of two or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxynitride.
  • the deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition process, in forming buried Silicon nitride is formed on the word line trench 101 of the embedded word line 132 or on the semiconductor substrate 100 as the insulating layer 133 .
  • the insulating layer 133 is etched by an etching process, so that the top surface of the insulating layer 133 is flat with the top surface BS1 of the semiconductor substrate 100 .
  • both the insulating layer 133 and the semiconductor substrate 100 may be etched, so that the entire upper surface of the etched insulating layer 133 and the semiconductor substrate 100 is The surface can be as flat as possible.
  • the active region mask structure 300 defines an active region in the semiconductor substrate 100 , that is, the active region mask structure 300 defines the active region on the bottom surface of the semiconductor substrate 100
  • the orthographic projection overlaps with the orthographic projection of the active region on the bottom surface of the semiconductor substrate 100, so that when the semiconductor substrate 100 in the non-masked region is etched later, the semiconductor substrate under the active region mask structure 300 can be retained 100, to be used as an active area.
  • the orthographic projection of the active region mask structure 300 on the bottom surface of the semiconductor substrate 100 extends along the second direction F2 and passes through the word line structure 130 on the bottom surface of the semiconductor substrate 100. Orthographic projection, such that the resulting active area is penetrated by the buried word line 132 to form a transistor.
  • the angle between the second direction F2 and the first direction F1 is greater than 0° and less than 90°, so that the active region and the buried word line 132 have an angle greater than 0° and less than 90° .
  • the angle between the active region and the buried word line 132 can be selected by those skilled in the art according to actual needs, and is not limited here.
  • step S30, forming a plurality of active region mask structures 300 on the top surface of the semiconductor substrate 100 specifically includes the following steps: first, forming an etching layer covering the semiconductor substrate 100 on the semiconductor substrate 100 masking layer and etch stop layer.
  • the etch mask layer and the etch stop layer may use one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide/nitride/oxide materials.
  • the materials of the etch mask layer and the etch stop layer may be different based on the etch selectivity ratio.
  • a layer of silicon nitride is deposited at a set deposition rate as an etching mask layer.
  • a layer of silicon oxide at a set deposition rate as an etch stop layer.
  • deposition method those skilled in the art can choose from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes , the present disclosure is not limited thereto.
  • the selection of the deposition rate and the thickness of the etching mask layer those skilled in the art can also select other appropriate rates and thicknesses according to actual needs.
  • the etch stop layer is patterned to form a plurality of strip-shaped etch stop isolation structures 310 extending along the second direction F2 .
  • a vapor phase etching process may be used to remove part of the etch barrier layer to form a plurality of strip-shaped etch barrier isolation structures 310 extending along the second direction F2, and these etch barrier isolation structures 310 can block the
  • the etching mask layer corresponds to the area where the active region is located, so that the gap between adjacent etch-stop isolation structures 310 can expose the area where the etching mask layer needs to be etched away.
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the etching mask layer can be etch.
  • the etching mask layer is patterned to form a plurality of strip-shaped etching barriers extending along the second direction F2.
  • Mask the isolation structure 320 a vapor phase etching process may be used to remove the etch mask layer in the gap between the etch barrier isolation structures 310, and retain the etch mask layer in the remaining areas, so as to form strips along the second direction F2.
  • a plurality of etching mask isolation structures 320 are extended, so that the gaps between adjacent etching mask isolation structures 320 can expose the region where the semiconductor substrate 100 needs to be etched and removed.
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the etching mask layer can be etch.
  • the etch-stop isolation structure 310 is patterned again, and the strip-shaped etch-stop isolation structure 310 is divided into a plurality of etch-stop isolation structure segments.
  • a vapor phase etching process may be used to remove the middle part of the etch-stop isolation structure 310 , so as to divide the strip-shaped etch-stop isolation structure 310 into two or more etch-stop isolation structure segments.
  • each etch stop isolation structure segment covers multiple active regions.
  • the region where the etch mask layer to be etched and removed is located is exposed.
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the etching mask layer can be etch.
  • the etch mask isolation structure 320 is patterned by using the etch barrier isolation structure segment as an etch mask, and the strip-shaped etch mask isolation structure 320 is divided into a plurality of etch mask isolation structures.
  • the etch mask isolates the structure segment 321 .
  • a vapor phase etching process may be used to remove the etch mask layer in the gap between the etch stop isolation structure segments 311 in the same etch stop isolation structure 310, and retain the etch mask layer in the remaining regions,
  • a vapor phase etching process may be used to remove the etch mask layer in the gap between the etch stop isolation structure segments 311 in the same etch stop isolation structure 310, and retain the etch mask layer in the remaining regions,
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the etching mask layer can be etch.
  • each etch-stop isolation structure segment is patterned again, and each etch-stop isolation structure segment is divided into two or more etch-stop isolation structure sub-segments.
  • a vapor phase etching process may be used to remove the middle part of the etch-stop isolation structure segment, so as to divide the etch-stop isolation structure segment into two etch-stop isolation structure sub-segments.
  • each etch stop isolation structure subsection covers an active area.
  • the region where the etching mask layer needs to be removed by etching is exposed.
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the etching mask layer can be etch.
  • the etching mask isolation structure segment 321 is divided into a plurality of active area masks by using the etching barrier isolation structure subsection as an etching mask to pattern the etching mask layer.
  • Membrane structure 300 is used to divide the etching mask isolation structure segment 321 into a plurality of active area masks by using the etching barrier isolation structure subsection as an etching mask to pattern the etching mask layer.
  • a vapor phase etching process may be used to remove the etch mask layer in the gap between the subsections of the etch stop isolation structure in the same etch stop isolation structure 310, and retain the etch mask layer in the remaining regions,
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the etching mask layer can be etch.
  • step S40, etching the word line structure 130 and the semiconductor substrate 100 to form the active region and the buried word line 132 passing through the active region may specifically include the following steps: first, etching The semiconductor substrate, the insulating layer and the gate dielectric layer in the non-masked area expose the buried word lines in the non-masked area, and the semiconductor substrate in the non-masked area is connected to the The bottom surfaces of the buried word lines are flush; wherein, the non-masking area is the area except the area where the masking structure of the active area is located.
  • etching the semiconductor substrate at a set depth in the non-masked area so that the plane where the semiconductor substrate is located in the non-masked area and the plane where the bottom surface of the buried word line is located have the set depth. depth.
  • the etching of the semiconductor substrate, insulating layer and gate dielectric layer in the non-masked area exposes the buried word line in the non-masked area, and makes the etched semiconductor substrate The bottom is flush with the bottom surface of the buried word line.
  • it may include: first, using the active region mask structure as an etching mask to etch the semiconductor substrate and the insulating layer in the non-masked region.
  • the active region mask structure as an etching mask, etch the semiconductor substrate and the gate dielectric layer in the non-masked region, exposing the buried type in the non-masked region line, and make the top surface of the semiconductor substrate in the non-masked region flush with the bottom surface of the buried word line.
  • the exposing the buried word line in the non-masked region may specifically include: using the active region mask structure as an etching mask to etch the semiconductor in the non-masked region
  • the substrate and the gate dielectric layer expose the buried word line in the non-masked area, and make the height of the buried word line in the non-masked area equal to the active area mask structure The height of the buried word line in the area.
  • step S40 may be as follows:
  • the semiconductor substrate 100, the insulating layer 133 and the gate dielectric in the non-masking area are etched using the area other than the area where the active region mask structure 300 is located as the non-masking area.
  • the top surfaces of the lines 132 are flush.
  • the semiconductor substrate 100 and the insulating layer 133 in the non-masked region can be etched using a vapor phase etching process, using the active region mask structure 300 as an etching mask, so that the semiconductor substrate 100 and the insulating layer 133 in the non-masked region The top surface of the substrate 100 is flush with the top surface of the buried wordline 132 .
  • the semiconductor substrate 100 and the gate dielectric layer 131 in the non-masked region are etched to expose the Buried word lines 132, and make the top surface of the semiconductor substrate 100 in the non-masked area flush with the bottom surface of the buried word lines 132, and make the height of the buried word lines 132 in the non-masked area It may be equal to the height of the buried word line 132 in the region where the active region mask structure 300 is located.
  • the semiconductor substrate between the plane where the bottom surface of the active region mask structure 300 is located ie, the plane BS1 where the uppermost surface of the semiconductor substrate is located
  • the plane WS2 where the bottom surface of the buried word line 132 is located The bottom 100 is oxidized to form an oxidation protection layer on the surface of the semiconductor substrate 100 between the plane BS1 where the bottom surface of the active region mask structure 300 is located and the plane WS2 where the bottom surface of the buried word line 132 is located.
  • a plasma oxidation process may be used to oxidize the surface of the semiconductor substrate 100 between the plane BS1 where the bottom surface of the active region mask structure 300 is located and the plane WS2 where the bottom surface of the buried word line 132 is located.
  • the plasma oxidation gas can be a mixed gas of O 2 and N 2
  • the temperature can be 600°C-800°C
  • the plasma intensity can be 600W-2000W
  • the pressure can be 1Pa-10Pa.
  • those skilled in the art can also select other appropriate parameters according to actual needs.
  • the semiconductor substrate 100 at a set depth in the non-masked region is etched, so that the plane where the semiconductor substrate 100 is located in the non-masked region and the plane where the bottom surface of the buried word line 132 is located have the same Set depth HA1.
  • the semiconductor substrate 100 at a set depth HA1 is etched using the active region mask structure 300 and the buried word line 132 as an etching mask, so that the etched The plane where the semiconductor substrate 100 is located and the plane where the bottom surface of the buried word line 132 is located have a predetermined depth HA1.
  • the semiconductor substrate 100 in the set depth HA1 and located in the region where the buried word line 132 is located can be preferentially etched, so that when the semiconductor substrate 100 is subsequently etched, the semiconductor substrate 100 can be preferentially etched first.
  • the processed semiconductor substrate 100 is etched without affecting the semiconductor substrate 100 under the active region mask structure 300 .
  • the semiconductor substrate 100 that has been preferentially etched is removed by etching, and the shallow trench isolation trench 120 can be formed to define the active region 110 through the shallow trench isolation trench.
  • the active region 110 and the buried word line 132 passing through the active region 110 may further include: depositing an isolation layer 400 on the semiconductor substrate 100, so that The isolation layer 400 is flush with the top surface of the semiconductor substrate 100 . Furthermore, the isolation layer 400 is etched by vapor phase to expose the buried word line and the active region for subsequent electrical connection.
  • the isolation layer may use one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide/nitride/oxide materials. Exemplarily, a layer of silicon oxide is deposited at a set deposition rate as the isolation layer.
  • the etching gas may be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the isolation layer can be etched.
  • a plurality of bit line structures intersecting with corresponding active regions 110 may also be formed on the semiconductor substrate 100, so that one source/drain region of the transistor (that is, two adjacent word lines on the semiconductor substrate 100 The portions between structures 130) are electrically connected to corresponding bit line structures.
  • the semiconductor device can be DRAM. See Figures 14A-14C.
  • the semiconductor device provided in the present disclosure may include: a semiconductor substrate 100 and a word line structure 130 .
  • the semiconductor substrate 100 has an isolation region 120 formed by a shallow trench isolation trench (STI) and a plurality of active regions 110 defined by the isolation region 120 .
  • a memory cell of a memory such as a DRAM may be formed in each active region 110 .
  • Word line structures 130 intersecting the corresponding active regions 110 and buried in the semiconductor substrate 100 are formed in the semiconductor substrate 100 .
  • the word line structure 130 is in contact with the semiconductor substrate 100 .
  • the word line structure 130 may include: a gate dielectric layer 131 , a plurality of buried word lines 132 and an insulating layer 133 .
  • the gate dielectric layer 131, the buried word line 132, and the insulating layer 133 covering the buried word line 132 can be sequentially formed in the word line trench 101. .
  • the buried word line 132 extends along the first direction F1
  • the orthographic projection of the active region on the bottom surface of the semiconductor substrate 100 extends along the second direction F2 and passes through the buried word line 132 on the bottom surface of the semiconductor substrate 100
  • the orthographic projection of the insulating layer 133 and the gate dielectric layer 131 on the bottom surface of the semiconductor substrate 100 is located within the orthographic projection of the active region on the bottom surface of the semiconductor substrate 100 .
  • the insulating layer 133 is located on the buried word line 132
  • the orthographic projection of the insulating layer 133 located in the active region and the buried word line 132 on the bottom surface of the semiconductor substrate 100 overlaps.
  • the insulating layer 133 located in the active region has the orthographic projection of the gate dielectric layer 131 on the bottom surface of the semiconductor substrate 100 on both sides of the orthographic projection of the bottom surface of the semiconductor substrate 100 .
  • the buried word line 132 in the word line structure 130 can be used as a gate of a transistor in the memory, and the source/drain regions of the transistor can be located in the active region 110 on both sides of the word line structure 130 .
  • one of the source/drain regions can be used as the source of the corresponding transistor, and in another source/drain region, such as the word line structure 130 and the isolation region
  • the source/drain region between 120 can be used as the drain of the corresponding transistor.
  • the active regions are arranged in repeating units along the third direction F3, and the repeating units are arranged in the first direction F1; wherein, the active regions in every two adjacent repeating units are staggered. .
  • the active regions in the repeating unit DZ1 and the repeating unit DZ2 are misaligned
  • the active regions in the repeating unit DZ2 and the repeating unit DZ3 are misaligned
  • the active regions in the repeating unit DZ3 and the repeating unit DZ4 are misaligned
  • repeat The active regions of the unit DZ4 and the repeating unit DZ5 are misaligned
  • the active regions of the repeating unit DZ5 and the repeating unit DZ6 are misaligned.
  • the repeating units of odd columns (such as DZ1, DZ3, DZ5) are arranged in the same pattern along the first direction F1
  • the repeating units of even columns (such as DZ2, DZ4, DZ6) are arranged in the same pattern along the first direction F1.
  • one active region may be crossed by two buried word lines 132 .
  • each active area is crossed by two buried word lines 132 .
  • each buried word line 132 may alternately pass through the active regions in the odd-numbered repeating units and the even-numbered repeating units.
  • the remaining area except the area where the active area is located is used as the non-active area, and the height of the buried word line 132 in the non-active area can be equal to that of the active area.
  • Embodiments of the present disclosure also provide other manufacturing methods of semiconductor devices, which are modified for the implementation manners in the above embodiments. Differences between this embodiment and the foregoing embodiments will be described below, and the similarities will not be repeated here.
  • the height of the buried word line 132 in the non-active region can be made smaller than the height of the buried word line 132 in the active region 110 .
  • the relative area between the buried word lines 132 in the non-active area can be reduced, thereby reducing the coupling capacitance between the buried word lines 132 in the non-active area, and further reducing signal interference.
  • the heights of the buried word lines 132 in the active region may be made equal.
  • the heights of the buried word lines 132 in the non-active area may be made equal.
  • the semiconductor substrate 100 and the gate dielectric layer 131 in the non-masked region are etched, so that the semiconductor substrate 100 in the non-masked region
  • the top surface is flush with the bottom surface of the buried word line 132, and the height of the buried word line 132 in the non-masked area is smaller than the height of the buried word line 132 in the area where the active region mask structure 300 is located .
  • step S40 may also be as follows:
  • the semiconductor substrate 100, the insulating layer 133 and the gate dielectric in the non-masking area are etched using the area other than the area where the active region mask structure 300 is located as the non-masking area.
  • the top surfaces of the lines 132 are flush.
  • the semiconductor substrate 100 and the insulating layer 133 in the non-masked region can be etched using a vapor phase etching process, using the active region mask structure 300 as an etching mask, so that the semiconductor substrate 100 and the insulating layer 133 in the non-masked region The top surface of the substrate 100 is flush with the top surface of the buried wordline 132 .
  • the semiconductor substrate 100 and the gate dielectric layer 131 in the non-masked region are etched to expose the Buried word lines 132, and make the top surface of the semiconductor substrate 100 in the non-masked area flush with the bottom surface of the buried word lines 132, and make the height of the buried word lines 132 in the non-masked area It may be equal to the height of the buried word line 132 in the region where the active region mask structure 300 is located.
  • the buried word line 132 in the non-masked area is etched using the active area mask structure 300 as an etching mask, so that the buried word line 132 in the non-masked area
  • the height of the line 132 is smaller than the height of the buried word line 132 in the area where the active area mask structure 300 is located.
  • a vapor phase etching process may be used to remove part of the buried word line 132 in the non-masked area, so that the height of the buried word line 132 in the non-masked area is smaller than the mask structure 300 in the active area.
  • the height of the buried word line 132 in the region may be used to remove part of the buried word line 132 in the non-masked area, so that the height of the buried word line 132 in the non-masked area is smaller than the mask structure 300 in the active area.
  • the etching gas may be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the buried word line can be etch.
  • the height of the buried word line 132 in the non-masked area can be set according to the actual application environment, and is not limited here.
  • the semiconductor substrate 100 between the plane where the bottom surface of the active region mask structure 300 is located and the plane where the bottom surface of the buried word line 132 is located is oxidized, so that the active region mask structure 300
  • An oxidation protection layer is formed on the surface of the semiconductor substrate 100 between the plane where the bottom surface is located and the plane where the bottom surface of the buried word line 132 is located.
  • a plasma oxidation process may be used to oxidize the surface of the semiconductor substrate 100 between the plane where the bottom surface of the active region mask structure 300 is located and the plane where the bottom surface of the buried word line 132 is located.
  • the plasma oxidation gas can be a mixed gas of O 2 and N 2 , the temperature can be 600°C-800°C, the plasma intensity can be 600W-2000W, and the pressure can be 1Pa-10Pa.
  • the parameters of the plasma oxidation process those skilled in the art can also select other appropriate parameters according to actual needs.
  • etch the semiconductor substrate 100 at a set depth in the non-masked area so that the plane where the semiconductor substrate 100 is located in the non-masked area and the plane where the bottom surface of the buried word line 132 is located have a set plane.
  • Depth HA1 Exemplarily, referring to FIG. 13A and FIG. 13B , the semiconductor substrate 100 at a set depth HA1 is etched using the active region mask structure 300 and the buried word line 132 as an etching mask, so that the etched The plane where the semiconductor substrate 100 is located and the plane where the bottom surface of the buried word line 132 is located have a predetermined depth HA1.
  • the semiconductor substrate 100 in the set depth HA1 and located in the region where the buried word line 132 is located can be preferentially etched, so that when the semiconductor substrate 100 is subsequently etched, the semiconductor substrate 100 can be preferentially etched first.
  • the processed semiconductor substrate 100 is etched without affecting the semiconductor substrate 100 under the active region mask structure 300 .
  • the semiconductor substrate 100 that has been preferentially etched is removed by etching, and the shallow trench isolation trench 120 can be formed to define the active region 110 through the shallow trench isolation trench.
  • an isolation layer is deposited on the semiconductor substrate 100 such that the isolation layer is flush with the top surface of the semiconductor substrate 100 . Furthermore, the isolation layer 400 is etched by vapor phase to expose the buried word line and the active region for subsequent electrical connection.
  • the isolation layer may use one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide/nitride/oxide materials. Exemplarily, a layer of silicon oxide is deposited at a set deposition rate as the isolation layer.
  • the etching gas may be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar, so as to achieve a certain etching selectivity, so that the isolation layer can be etched.
  • Embodiments of the present disclosure also provide some electronic devices.
  • the electronic device may include the above-mentioned semiconductor device provided by the embodiments of the present disclosure.
  • the problem-solving principle of the electronic device is similar to that of the above-mentioned semiconductor device, so the implementation of the electronic device can refer to the implementation of the above-mentioned semiconductor device, and the repetition will not be repeated here.
  • the electronic device may be any product or component with a storage function such as a mobile phone and a tablet computer.
  • a storage function such as a mobile phone and a tablet computer.
  • the other essential components of the electronic device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be regarded as limitations on the present invention.

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Abstract

本公开公开了一种半导体器件、电子设备及制备方法，通过在半导体衬底上先形成字线沟槽，之后在字线沟槽中形成字线结构，之后再形成有源区。这样可以使字线沟槽穿过半导体衬底，而不需要使字线沟槽穿过其他材料。由于半导体衬底的材料均一，从而不存在刻蚀选择比的问题，进而使形成的字线沟槽的底面可以平整。在字线沟槽中形成字线结构时，可以使字线结构与半导体衬底直接接触，而不需要使字线结构与其他材料进行接触，从而可以使字线结构的底面可以平整，进而提高半导体器件的性能和可靠性。

Description

半导体器件、电子设备及制备方法
相关申请的交叉引用
本申请要求在2021年08月16日提交中国专利局、申请号为202110934847.7、申请名称为“半导体器件、电子设备及制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及存储技术领域，特别涉及半导体器件、电子设备及制备方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称：DRAM)是计算机中常用的半导体存储器件，由许多重复的半导体器件组成。每一个半导体器件通常包括电容器和晶体管；晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
目前，针对字线之间的干扰，可以采用埋入式字线方式。通常制备埋入式字线的方法为：提供半导体衬底，在半导体衬底上形成浅沟槽隔离区定义出有源区，在浅沟槽隔离区中填充了氧化硅。之后在半导体衬底中刻蚀形成穿过有源区及浅沟槽隔离区中的氧化硅的字线沟槽。之后，在字线沟槽中形成埋入式字线。然而，由于半导体衬底和氧化硅的刻蚀选择比不同，这样使得半导体衬底和氧化硅的刻蚀速率不同，从而导致字线沟槽的底面出现凹凸不平，进而导致埋入式字线底面不平整，影响半导体器件的性能和可靠性。
发明内容
根据一些实施例，本公开实施例第一方面提供半导体器件的制备方法， 可以包括如下步骤：
在半导体衬底上形成多个字线沟槽；其中，所述字线沟槽沿第一方向延伸；
在各所述字线沟槽内形成字线结构；其中，所述字线结构的顶面和所述半导体衬底的顶面齐平；
在所述半导体衬底的顶面上形成多个有源区掩膜结构；其中，所述有源区掩膜结构在所述半导体衬底中界定出有源区，且所述有源区掩膜结构在所述半导体衬底的底面的正投影沿第二方向延伸且穿过所述字线结构在所述半导体衬底的底面的正投影；
以所述有源区掩膜结构为刻蚀掩膜，对所述字线结构和所述半导体衬底进行刻蚀，形成有源区和穿过所述有源区的埋入式字线。
根据一些实施例，本公开实施例第二方面提供半导体器件，采用上述制备方法得到；所述半导体器件包括：
半导体衬底，具有由浅沟道隔离槽形成的隔离区以及由隔离区界定出的多个有源区；
多条埋入式字线，埋置于通过刻蚀所述半导体衬底形成的字线沟槽中，且所述埋入式字线与相应的有源区相交设置。
根据一些实施例，本公开实施例第三方面提供电子设备，包括上述半导体器件。
附图说明
图1A是相关技术中的半导体器件的俯视结构示意图；
图1B是图1A所示的半导体器件在AA’方向上的剖视结构图；
图1C是图1A所示的半导体器件在BB’方向上的剖视结构图；
图2为本公开实施例提供的半导体器件的制备方法的流程图；
图3A为本公开实施例提供的制备半导体器过程中的一些结构示意图；
图3B为图3A所示的结构示意图对应的剖视结构图；
图4A为本公开实施例提供的制备半导体器过程中的另一些结构示意图；
图4B为图4A所示的结构示意图对应的剖视结构图；
图5A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图5B为图5A所示的结构示意图对应的剖视结构图；
图6A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图6B为图6A所示的结构示意图对应的剖视结构图；
图7A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图7B为图7A所示的结构示意图对应的剖视结构图；
图8A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图8B为图8A所示的结构示意图对应的剖视结构图；
图9A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图9B为图9A所示的结构示意图对应的剖视结构图；
图9C为本公开实施例提供的制备半导体器过程中的又一些俯视结构示意图；
图9D为本公开实施例提供的制备半导体器过程中的又一些俯视结构示意图；
图10A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图10B为图10A所示的结构示意图对应的剖视结构图；
图10C为本公开实施例提供的制备半导体器过程中的又一些俯视结构示意图；
图11A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图11B为图11A所示的结构示意图对应的剖视结构图；
图12A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图12B为图12A所示的结构示意图对应的剖视结构图；
图13A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图13B为图13A所示的结构示意图对应的剖视结构图；
图14A为本公开实施例提供的制备得到的半导体器的一些结构示意图；
图14B为图14A所示的结构示意图对应的剖视结构图；
图14C为本公开实施例提供的制备得到的半导体器的又一些俯视结构示意图；
图15A为本公开实施例提供的制备半导体器过程中的又一些结构示意图；
图15B为图15A所示的结构示意图对应的剖视结构图；
图16A为本公开实施例提供的制备得到的半导体器的又一些结构示意图；
图16B为图16A所示的结构示意图对应的剖视结构图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
针对字线之间的干扰，可以采用埋入式字线132方式。参见图1A至图1C。图1A是相关技术中的半导体器件的俯视结构示意图。图1B是图1A所示的半导体器件在AA’方向上的剖视结构示意图。图1C是图1A所示的半导 体器件在BB’方向上的剖视结构示意图。目前，通常制备埋入式字线的方法为：提供半导体衬底10，在半导体衬底10上形成浅沟槽隔离区定义出有源区13，在浅沟槽隔离区中填充氧化硅11。之后，在半导体衬底10中刻蚀形成穿过有源区及浅沟槽隔离区中的氧化硅的字线沟槽。之后，在字线沟槽中形成埋入式字线12。由于字线沟槽不仅穿过半导体衬底10还穿过浅沟槽隔离区中的氧化硅11，而半导体衬底10和氧化硅11的刻蚀选择比不同，这样使得半导体衬底10和氧化硅11的刻蚀速率不同，从而导致刻蚀出的字线沟槽的底面出现凹凸不平，进而导致埋入式字线12底面不平整，影响半导体器件的性能和可靠性。
基于此，本公开实施例提供了半导体器件的制备方法，通过在半导体衬底100上先形成字线沟槽101，之后在字线沟槽101中形成字线结构130，之后再形成有源区。这样可以使字线沟槽101穿过半导体衬底100，而不需要使字线沟槽101穿过其他材料。由于半导体衬底100的材料均一，从而不存在刻蚀选择比的问题，进而使形成的字线沟槽101的底面可以平整。在字线沟槽101中形成字线结构130时，可以使字线结构130与半导体衬底100直接接触，而不需要使字线结构130与其他材料进行接触，从而可以使字线结构130的底面可以平整。从而可以使形成的埋入式字线的底面也可以齐平，进而提高半导体器件的性能和可靠性。
参见图2、图3A至图14C。图2为本公开实施例提供的半导体器件的制备方法的流程图。图3A至图14B为本公开实施例提供的半导体器件的进行各步骤之后的结构示意图。本公开提供的半导体器件的制备方法，具体到本实施例中，包括如下步骤：
S10、在半导体衬底100上形成多个字线沟槽101。
在一些示例中，半导体衬底100的材质可以包括硅、锗或绝缘体上硅(SOI)的半导体，或者包括锗硅化合物、碳化硅或者其他已知材料，例如砷化镓等Ⅲ、Ⅴ族化合物。在半导体衬底100中还可以根据设计需求注入一定的掺杂离子以改变电学参数。示例性地，半导体衬底100可以为硅衬底。
在一些示例中，步骤S10，在半导体衬底100上形成多个字线沟槽101，具体可以包括如下步骤：首先，在半导体衬底100上形成覆盖半导体衬底100的沟槽掩膜层。其中，沟槽掩膜层可以采用氧化硅、氮化硅、氮氧化物、硅氮化物、氧化物/氮化物/氧化物材料中的一种或多种。示例性地，以设定的沉积速率沉积一层氮化硅作为沟槽掩膜层。沉积方式的选择上本领域技术人员可以从化学气相沉积、物理气相沉积、原子层沉积、高密度等离子化学气相沉积、金属有机化学气相沉积、等离子体增强化学气相沉积或其他适合的沉积工艺中选择，本公开并不以此为限。同样的，沉积速率以及沟槽掩膜层的厚度的选择上，本领域技术人员也可根据实际需要选择其他合适的速率以及厚度。需要说明的是，下述的沉积方式的选择上本领域技术人员也可以从化学气相沉积、物理气相沉积、原子层沉积、高密度等离子化学气相沉积、金属有机化学气相沉积、等离子体增强化学气相沉积或其他适合的沉积工艺中选择，在此不作赘述。
之后，参见图3A和图3B，对沟槽掩膜层进行图形化，形成条状的沿第一方向F1延伸的多个沟槽掩膜结构200。示例性地，可以采用气相刻蚀工艺，去除将要形成的字线沟槽101所在区域上的沟槽掩膜层，保留其余区域的沟槽掩膜层，以形成条状的沿第一方向F1延伸的多个沟槽掩膜结构200，从而使相邻的沟槽掩膜结构200之间的间隙可以将需要形成字线沟槽101所在区域的半导体衬底100暴露出来。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对沟槽掩膜层进行刻蚀。
之后，参见图4A和图4B，去除相邻沟槽掩膜结构200之间的间隙处且具有设定距离的半导体衬底100，形成沿第一方向F1延伸的多个字线沟槽101。示例性地，采用气相刻蚀工艺，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对相邻的沟槽掩膜结构200之间的间隙处暴露出的半导体衬底100进行刻蚀。并且，刻蚀设定距离的半导体衬底100，以形成字线沟槽101。
其中，由于采用气相刻蚀工艺对半导体衬底100进行刻蚀，可以使各字线沟槽101形成于半导体衬底100内，而不需要穿过其他材料，从而可以使各字线沟槽101的深度H1基本相等，进而可以使字线沟槽101的底面S1尽可能的平整。
需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，字线沟槽101的底面S1可能并不会完全齐平，可能会有一些偏差，因此字线沟槽101的底面S1的平整关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，上述字线沟槽101的底面S1的平整可以是在误差允许范围之内所允许的即可。
之后，参见图5A和图5B，刻蚀去除沟槽掩膜结构200。
S20、在各字线沟槽101内形成字线结构130。这样可以使形成的字线结构130的底面尽可能的齐平。
在一些示例中，参见图6A至图8B，字线结构130的顶面和半导体衬底100的顶面齐平，且字线结构130的底面形成在字线沟槽101的底面S1上，这样可以使字线结构130的底面与半导体衬底100接触。这样可以使字线结构130的底面尽可能的平整。
在一些示例中，字线结构130可以包括：形成于字线沟槽101侧壁上的栅极介质层131、填充于具有栅极介质层131的字线沟槽101内的埋入式字线132以及填充于字线沟槽101内的埋入式字线132上的绝缘层133。其中，由于字线沟槽101的底面尽可能的平整，侧壁附着有栅极介质层的字线沟槽101的底面也尽可能的平整，这样可以使形成的埋入式字线132的底面尽可能的齐平，从而可以降低干扰，半导体器件的性能和可靠性。
在一些示例中，步骤S20，在各字线沟槽101内形成字线结构130，具体可以包括如下步骤：首先，参见图6A和图6B，在字线沟槽101的侧壁上覆盖栅极介质层131。示例性地，栅极介质层131可以包括氧化硅、氮化硅、氮氧化物、硅氮化物、氧化物/氮化物/氧化物以及高电介质材料中的一种或多种。例如，可以采用原子层沉积，在字线沟槽101的侧壁上覆盖氧化硅，以形成 栅极介质层131。
之后，参见图7A和图7B，在形成有栅极介质层131的字线沟槽101内填充埋入式字线132，并使形成的埋入式字线132的顶面WS1低于半导体衬底100的顶面BS1。示例性地，埋入式字线132的材料可以包括Ti、TiN、Ta、TaN、W、WN、TiSiN以及WSiN中的一种或多种。例如，可以从化学气相沉积、物理气相沉积、原子层沉积、高密度等离子化学气相沉积、金属有机化学气相沉积、等离子体增强化学气相沉积或其他适合的沉积工艺中选择沉积工艺，在字线沟槽101内形成TiN/W。并且通过刻蚀工艺将字线沟槽101内形成的TiN/W刻蚀到所需要的高度，以形成顶面WS1低于半导体衬底100的顶面BS1的埋入式字线132。
之后，参见图8A和图8B，在字线沟槽101内的埋入式字线132上填充绝缘层133，并使形成的绝缘层133的顶面与半导体衬底100的顶面BS1齐平。示例性地，绝缘层133的材料可以包括氧化硅、氮化硅、氮氧化硅以及硅氮氧化物中的一种或两种以上的组合。例如，可以从化学气相沉积、物理气相沉积、原子层沉积、高密度等离子化学气相沉积、金属有机化学气相沉积、等离子体增强化学气相沉积或其他适合的沉积工艺中选择沉积工艺，在形成有埋入式字线132的字线沟槽101或半导体衬底100上形成氮化硅，作为绝缘层133。并且，通过刻蚀工艺对绝缘层133进行刻蚀，以使绝缘层133的顶面与半导体衬底100的顶面BS1平整。或者，为了使半导体衬底100和绝缘层133的顶面平整，可以对绝缘层133和半导体衬底100均进行刻蚀，以使刻蚀后的绝缘层133和半导体衬底100这个整体的上表面可以尽可能的平整。
S30、在半导体衬底100的顶面上形成多个有源区掩膜结构300。
在一些示例中，参见图9A至图10C，有源区掩膜结构300在半导体衬底100中界定出有源区，也就是说，有源区掩膜结构300在半导体衬底100的底面的正投影与有源区在半导体衬底100的底面的正投影重叠，这样在后面刻蚀非掩膜区域的半导体衬底100的时候，可以保留下有源区掩膜结构300下 方的半导体衬底100，以作为有源区使用。
在一些示例中，参见图10A至图10C，有源区掩膜结构300在半导体衬底100的底面的正投影沿第二方向F2延伸且穿过字线结构130在半导体衬底100的底面的正投影，这样可以使得到的有源区被埋入式字线132穿过，以形成晶体管。其中，第二方向F2与第一方向F1之间的夹角大于0°且小于90°，这样可以使有源区与埋入式字线132之间具有大于0°且小于90°的夹角。有源区与埋入式字线132之间的夹角的选择上本领域技术人员可以根据实际需要选择，在此不作限定。
在一些示例中，步骤S30，在半导体衬底100的顶面上形成多个有源区掩膜结构300，具体包括如下步骤：首先，在半导体衬底100上形成覆盖半导体衬底100的刻蚀掩膜层和刻蚀阻挡层。其中，刻蚀掩膜层和刻蚀阻挡层可以采用氧化硅、氮化硅、氮氧化物、硅氮化物、氧化物/氮化物/氧化物材料中的一种或多种。并且，基于刻蚀选择比可以使刻蚀掩膜层和刻蚀阻挡层的材料不同。示例性地，以设定的沉积速率沉积一层氮化硅作为刻蚀掩膜层。以及，以设定的沉积速率沉积一层氧化硅作为刻蚀阻挡层。沉积方式的选择上本领域技术人员可以从化学气相沉积、物理气相沉积、原子层沉积、高密度等离子化学气相沉积、金属有机化学气相沉积、等离子体增强化学气相沉积或其他适合的沉积工艺中选择，本公开并不以此为限。同样的，沉积速率以及刻蚀掩膜层的厚度的选择上，本领域技术人员也可根据实际需要选择其他合适的速率以及厚度。
之后，参见图9A和图9B，对刻蚀阻挡层进行图形化，形成条状的沿第二方向F2延伸的多个刻蚀阻挡隔离结构310。示例性地，可以采用气相刻蚀工艺，去除部分刻蚀阻挡层，形成条状的沿第二方向F2延伸的多个刻蚀阻挡隔离结构310，这些刻蚀阻挡隔离结构310可以遮挡将要形成的有源区所在区域对应的刻蚀掩膜层，以使相邻的刻蚀阻挡隔离结构310之间的间隙可以将需要刻蚀去除的刻蚀掩膜层所在区域暴露出来。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比， 从而可以对刻蚀掩膜层进行刻蚀。
之后，参见图9A至图9C，以条状的刻蚀阻挡隔离结构310作为刻蚀掩膜，对刻蚀掩膜层进行图形化，形成条状的沿第二方向F2延伸的多个刻蚀掩膜隔离结构320。示例性地，可以采用气相刻蚀工艺，去除刻蚀阻挡隔离结构310之间的间隙中的刻蚀掩膜层，保留其余区域的刻蚀掩膜层，以形成条状的沿第二方向F2延伸的多个刻蚀掩膜隔离结构320，从而使相邻的刻蚀掩膜隔离结构320之间的间隙可以将需要刻蚀去除的半导体衬底100所在区域暴露出来。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对刻蚀掩膜层进行刻蚀。
之后，再次对刻蚀阻挡隔离结构310进行图形化，将条状的刻蚀阻挡隔离结构310分成多个刻蚀阻挡隔离结构段。示例性地，可以采用气相刻蚀工艺，去除刻蚀阻挡隔离结构310中间的部分，以将条状的刻蚀阻挡隔离结构310分割成两段或多段刻蚀阻挡隔离结构段。其中，每一个刻蚀阻挡隔离结构段覆盖多个有源区。并且，同一个刻蚀阻挡隔离结构310中的刻蚀阻挡隔离结构段之间，将需要刻蚀去除的刻蚀掩膜层所在区域暴露出来。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对刻蚀掩膜层进行刻蚀。
之后，参见图9A至图9C，以刻蚀阻挡隔离结构段为刻蚀掩膜，对刻蚀掩膜隔离结构320进行图形化，将条状的刻蚀掩膜隔离结构320分割成多个刻蚀掩膜隔离结构段321。示例性地，可以采用气相刻蚀工艺，去除同一刻蚀阻挡隔离结构310中的刻蚀阻挡隔离结构段311之间的间隙中的刻蚀掩膜层，保留其余区域的刻蚀掩膜层，以将一个刻蚀掩膜隔离结构320分割成多个刻蚀掩膜隔离结构段321，从而使同一个刻蚀掩膜隔离结构320中的刻蚀掩膜隔离结构段321之间的间隙可以将需要刻蚀去除的半导体衬底100所在区域暴露出来。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对刻蚀掩膜层进行刻蚀。
之后，再次对刻蚀阻挡隔离结构段进行图形化，将每个刻蚀阻挡隔离结 构段分成两个或多个刻蚀阻挡隔离结构子段。示例性地，可以采用气相刻蚀工艺，去除刻蚀阻挡隔离结构段中间的部分，以将刻蚀阻挡隔离结构段分割成两个刻蚀阻挡隔离结构子段。其中，每一个刻蚀阻挡隔离结构子段覆盖一个有源区。并且，同一个刻蚀阻挡隔离结构段中的刻蚀阻挡隔离结构子段之间，将需要刻蚀去除的刻蚀掩膜层所在区域暴露出来。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对刻蚀掩膜层进行刻蚀。
之后，参见图10A至图10C，以刻蚀阻挡隔离结构子段为刻蚀掩膜，对刻蚀掩膜层进行图形化，将刻蚀掩膜隔离结构段321分割成多个有源区掩膜结构300。示例性地，可以采用气相刻蚀工艺，去除同一刻蚀阻挡隔离结构310中的刻蚀阻挡隔离结构子段之间的间隙中的刻蚀掩膜层，保留其余区域的刻蚀掩膜层，以将一个刻蚀掩膜隔离结构段321分割成两个有源区掩膜结构300，从而使同一个刻蚀掩膜隔离结构段321中的有源区掩膜结构300之间的间隙可以将需要刻蚀去除的半导体衬底100所在区域暴露出来。其中，一个有源区掩膜结构300覆盖一个有源区。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对刻蚀掩膜层进行刻蚀。
S40、以有源区掩膜结构300为刻蚀掩膜，对字线结构130和半导体衬底100进行刻蚀，形成有源区110和穿过有源区110的埋入式字线132。
在一些示例中，步骤S40，对字线结构130和半导体衬底100进行刻蚀，形成有源区和穿过有源区的埋入式字线132，具体可以包括如下步骤：首先，刻蚀非掩膜区域中的半导体衬底、绝缘层以及栅极介质层，暴露出所述非掩膜区域中的埋入式字线，以及使所述非掩膜区域中的半导体衬底与所述埋入式字线的底面齐平；其中，所述非掩膜区域为除所述有源区掩膜结构所在区域之外的区域。之后，刻蚀所述非掩膜区域中设定深度的半导体衬底，使所述非掩膜区域中的半导体衬底所在平面与所述埋入式字线的底面所在平面具有所述设定深度。示例性地，所述刻蚀非掩膜区域中的半导体衬底、绝缘层 以及栅极介质层，暴露出所述非掩膜区域中的埋入式字线，以及使刻蚀后的半导体衬底与所述埋入式字线的底面齐平，具体可以包括：首先，以所述有源区掩膜结构为刻蚀掩膜，刻蚀所述非掩膜区域中的半导体衬底和绝缘层，使所述非掩膜区域中的半导体衬底的顶面与所述埋入式字线的顶面齐平。之后，以所述有源区掩膜结构为刻蚀掩膜，刻蚀所述非掩膜区域中的半导体衬底和栅极介质层，暴露出所述非掩膜区域中的埋入式字线，并使所述非掩膜区域中的半导体衬底的顶面与所述埋入式字线的底面齐平。其中，所述暴露出所述非掩膜区域中的埋入式字线，具体可以包括：以所述有源区掩膜结构为刻蚀掩膜，刻蚀所述非掩膜区域中的半导体衬底和栅极介质层，暴露出所述非掩膜区域中的埋入式字线，并使所述非掩膜区域中的埋入式字线的高度等于所述有源区掩膜结构所在区域中的埋入式字线的高度。
示例性地，步骤S40的实现方式可以如下：
首先，参见图11A和图11B，以除有源区掩膜结构300所在区域之外的区域作为非掩膜区域，刻蚀非掩膜区域中的半导体衬底100、绝缘层133以及栅极介质层131，保留有源区掩膜结构300所在区域中的半导体衬底100和绝缘层133以及栅极介质层131，并使非掩膜区域中的半导体衬底100的顶面与埋入式字线132的顶面齐平。示例性地，可以采用气相刻蚀工艺，以有源区掩膜结构300为刻蚀掩膜，刻蚀非掩膜区域中的半导体衬底100和绝缘层133，使非掩膜区域中的半导体衬底100的顶面与埋入式字线132的顶面齐平。
之后，参见图12A和图12B，以有源区掩膜结构300为刻蚀掩膜，刻蚀非掩膜区域中的半导体衬底100和栅极介质层131，暴露出非掩膜区域中的埋入式字线132，并使非掩膜区域中的半导体衬底100的顶面与埋入式字线132的底面齐平，以及使非掩膜区域中的埋入式字线132的高度可以等于有源区掩膜结构300所在区域中的埋入式字线132的高度。
之后，参见图12A和图12B，对有源区掩膜结构300的底面所在平面(即半导体衬底的最上表面所在平面BS1)与埋入式字线132的底面所在平面WS2之间的半导体衬底100进行氧化处理，使有源区掩膜结构300的底面所在平 面BS1与埋入式字线132的底面所在平面WS2之间的半导体衬底100表面形成氧化保护层。示例性地，可以采用等离子氧化工艺对有源区掩膜结构300的底面所在平面BS1与埋入式字线132的底面所在平面WS2之间的半导体衬底100表面进行氧化处理。并且，等离子氧化工艺中，等离子氧化气体可以为O 2和N 2的混合气体，温度可以为600℃～800℃，等离子强度可以为600W～2000W，压力可以为1Pa～10Pa。同样的，等离子氧化工艺的参数的选择上，本领域技术人员也可根据实际需要选择其他合适的参数。
之后，参见图13A和图13B，刻蚀非掩膜区域中设定深度的半导体衬底100，使非掩膜区域中的半导体衬底100所在平面与埋入式字线132的底面所在平面具有设定深度HA1。示例性地，参见图13A和图13B，先以有源区掩膜结构300和埋入式字线132为刻蚀掩膜，刻蚀设定深度HA1的半导体衬底100，使刻蚀后的半导体衬底100所在平面与埋入式字线132的底面所在平面具有设定深度HA1。之后，可以对处于设定深度HA1中且位于埋入式字线132所在区域内的半导体衬底100进行优先刻蚀处理，以在后续刻蚀半导体衬底100时，可以先对进行优先刻蚀处理后的半导体衬底100进行刻蚀，而不影响有源区掩膜结构300下方的半导体衬底100。这样刻蚀去除进行优先刻蚀处理后的半导体衬底100，可以形成浅沟道隔离槽120，以通过浅沟道隔离槽将有源区110限定出来。
在一些示例中，参见图14A和图14B，在形成有源区110和穿过有源区110的埋入式字线132之后，还可以包括：在半导体衬底100上沉积隔离层400，使隔离层400与半导体衬底100的顶面齐平。并且，通过气相刻蚀隔离层400，以将埋入式字线和有源区暴露出来，以用于后续进行电连接。其中，隔离层可以采用氧化硅、氮化硅、氮氧化物、硅氮化物、氧化物/氮化物/氧化物材料中的一种或多种。示例性地，以设定的沉积速率沉积一层氧化硅作为隔离层。沉积方式的选择上本领域技术人员可以从化学气相沉积、物理气相沉积、原子层沉积、高密度等离子化学气相沉积、金属有机化学气相沉积、等离子体增强化学气相沉积或其他适合的沉积工艺中选择，本公开并不以此 为限。同样的，沉积速率以及隔离层的厚度的选择上，本领域技术人员也可根据实际需要选择其他合适的速率以及厚度。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对隔离层进行刻蚀。
示例性地，在半导体衬底100上还可以形成与相应的有源区110相交的多个位线结构，以使晶体管的一个源/漏区(即半导体衬底100上两相邻的字线结构130之间的部分)与对应的位线结构电连接。
应用上述制备方法，本公开提供了一种半导体器件。例如可以是DRAM。参见图14A至图14C。本公开提供的半导体器件，可以包括：半导体衬底100、字线结构130。其中，半导体衬底100具有由浅沟道隔离槽(STI)形成的隔离区120以及由隔离区120界定出的多个有源区110。在每个有源区110可以形成存储器例如DRAM的存储单元。在半导体衬底100中形成了与相应的有源区110相交的且埋置于半导体衬底100中的字线结构130。其中，字线结构130与半导体衬底100接触。并且，字线结构130可以包括：栅极介质层131、多条埋入式字线132以及绝缘层133。例如，在字线沟槽101内形成字线结构130时，可在字线沟槽101中依次形成栅极介质层131、埋入式字线132以及覆盖埋入式字线132的绝缘层133。其中，埋入式字线132沿第一方向F1延伸，有源区在半导体衬底100的底面的正投影沿第二方向F2延伸且穿过埋入式字线132在半导体衬底100的底面的正投影；绝缘层133和栅极介质层131在半导体衬底100的底面的正投影位于有源区在半导体衬底100的底面的正投影内。并且，绝缘层133位于埋入式字线132上，且位于有源区内的绝缘层133和埋入式字线132在半导体衬底100的底面的正投影重叠。以及，位于有源区内的绝缘层133在半导体衬底100的底面的正投影的两侧具有栅极介质层131在半导体衬底100的底面的正投影。例如，字线结构130中的埋入式字线132可作为存储器中晶体管的栅极，晶体管的源/漏区可以位于字线结构130两侧的有源区110内。例如，可以在其中一个源/漏区，如两字线结构130之间的源/漏区，作为相应的晶体管的源极，并在另一源/漏区，如字线 结构130和隔离区120之间的源/漏区，可作为相应的晶体管的漏极。
在一些示例中，参见图13A至图14C，有源区沿第三方向F3排列成重复单元，重复单元沿第一方向F1排列；其中，每相邻两个重复单元中的有源区错位排列。示例性地，重复单元DZ1与重复单元DZ2中的有源区错位排列，重复单元DZ2与重复单元DZ3中的有源区错位排列，重复单元DZ3与重复单元DZ4中的有源区错位排列，重复单元DZ4与重复单元DZ5中的有源区错位排列，重复单元DZ5与重复单元DZ6中的有源区错位排列。示例性地，第奇数列重复单元(如DZ1、DZ3、DZ5)沿第一方向F1排列的图案相同，第偶数列重复单元(如DZ2、DZ4、DZ6)沿第一方向F1排列的图案相同。
在一些示例中，参见图13A至图14C，可以使一个有源区被两条埋入式字线132穿过。例如，每一个有源区被两条埋入式字线132穿过。示例性地，可以使每一条埋入式字线132交替穿过第奇数个重复单元和第偶数个重复单元中的有源区。
在一些示例中，参见图13A至图14B，以除有源区所在区域之外的其余区域作为非有源区，该非有源区内的埋入式字线132的高度可以等于有源区内的埋入式字线132的高度。这样可以使各个部位的埋入式字线132均匀分布。
本公开实施例还提供了另一些半导体器件的制备方法，其针对上述实施例中的实施方式进行了变形。下面说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参见图15A至图16B，在本公开实施例提供的半导体器件中，可以使非有源区内的埋入式字线132的高度小于有源区110内的埋入式字线132的高度。这样可以使非有源区中的埋入式字线132之间的相对面积减小，从而可以降低非有源区中埋入式字线132之间的耦合电容，进一步降低信号干扰。示例性地，可以使有源区中的埋入式字线132的高度相等。示例性地，可以使非有源区中的埋入式字线132的高度相等。示例性地，以有源区掩膜结构300为刻蚀掩膜，刻蚀非掩膜区域中的半导体衬底100和栅极介质层131，以 使非掩膜区域中的半导体衬底100的顶面与埋入式字线132的底面齐平，以及使非掩膜区域中的埋入式字线132的高度小于有源区掩膜结构300所在区域中的埋入式字线132的高度。
在一些示例中，步骤S40的实现方式也可以如下：
首先，参见图11A和图11B，以除有源区掩膜结构300所在区域之外的区域作为非掩膜区域，刻蚀非掩膜区域中的半导体衬底100、绝缘层133以及栅极介质层131，保留有源区掩膜结构300所在区域中的半导体衬底100和绝缘层133以及栅极介质层131，并使非掩膜区域中的半导体衬底100的顶面与埋入式字线132的顶面齐平。示例性地，可以采用气相刻蚀工艺，以有源区掩膜结构300为刻蚀掩膜，刻蚀非掩膜区域中的半导体衬底100和绝缘层133，使非掩膜区域中的半导体衬底100的顶面与埋入式字线132的顶面齐平。
之后，参见图12A和图12B，以有源区掩膜结构300为刻蚀掩膜，刻蚀非掩膜区域中的半导体衬底100和栅极介质层131，暴露出非掩膜区域中的埋入式字线132，并使非掩膜区域中的半导体衬底100的顶面与埋入式字线132的底面齐平，以及使非掩膜区域中的埋入式字线132的高度可以等于有源区掩膜结构300所在区域中的埋入式字线132的高度。
之后，参见图15A和图15B，以有源区掩膜结构300为刻蚀掩膜，刻蚀非掩膜区域中的埋入式字线132，以使非掩膜区域中的埋入式字线132的高度小于有源区掩膜结构300所在区域中的埋入式字线132的高度。示例性地，可以采用气相刻蚀工艺，去除非掩膜区域中的部分埋入式字线132，以使非掩膜区域中的埋入式字线132的高度小于有源区掩膜结构300所在区域中的埋入式字线132的高度。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对埋入式字线进行刻蚀。需要说明的是，非掩膜区域中的埋入式字线132的高度可以根据实际应用环境进行设定，在此不作限定。
之后，参见上述制备方法，对有源区掩膜结构300的底面所在平面与埋入式字线132的底面所在平面之间的半导体衬底100进行氧化处理，使有源 区掩膜结构300的底面所在平面与埋入式字线132的底面所在平面之间的半导体衬底100表面形成氧化保护层。示例性地，可以采用等离子氧化工艺对有源区掩膜结构300的底面所在平面与埋入式字线132的底面所在平面之间的半导体衬底100表面进行氧化处理。并且，等离子氧化工艺中，等离子氧化气体可以为O 2和N 2的混合气体，温度可以为600℃～800℃，等离子强度可以为600W～2000W，压力可以为1Pa～10Pa。同样的，等离子氧化工艺的参数的选择上，本领域技术人员也可根据实际需要选择其他合适的参数。
之后，参见上述制备方法，刻蚀非掩膜区域中设定深度的半导体衬底100，使非掩膜区域中的半导体衬底100所在平面与埋入式字线132的底面所在平面具有设定深度HA1。示例性地，参见图13A和图13B，先以有源区掩膜结构300和埋入式字线132为刻蚀掩膜，刻蚀设定深度HA1的半导体衬底100，使刻蚀后的半导体衬底100所在平面与埋入式字线132的底面所在平面具有设定深度HA1。之后，可以对处于设定深度HA1中且位于埋入式字线132所在区域内的半导体衬底100进行优先刻蚀处理，以在后续刻蚀半导体衬底100时，可以先对进行优先刻蚀处理后的半导体衬底100进行刻蚀，而不影响有源区掩膜结构300下方的半导体衬底100。这样刻蚀去除进行优先刻蚀处理后的半导体衬底100，可以形成浅沟道隔离槽120，以通过浅沟道隔离槽将有源区110限定出来。
在一些示例中，参见图16A和图16B，在半导体衬底100上沉积隔离层，使隔离层与半导体衬底100的顶面齐平。并且，通过气相刻蚀隔离层400，以将埋入式字线和有源区暴露出来，以用于后续进行电连接。其中，隔离层可以采用氧化硅、氮化硅、氮氧化物、硅氮化物、氧化物/氮化物/氧化物材料中的一种或多种。示例性地，以设定的沉积速率沉积一层氧化硅作为隔离层。沉积方式的选择上本领域技术人员可以从化学气相沉积、物理气相沉积、原子层沉积、高密度等离子化学气相沉积、金属有机化学气相沉积、等离子体增强化学气相沉积或其他适合的沉积工艺中选择，本公开并不以此为限。同样的，沉积速率以及隔离层的厚度的选择上，本领域技术人员也可根据实际 需要选择其他合适的速率以及厚度。示例性地，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，从而可以对隔离层进行刻蚀。
本公开实施例还提供了一些电子设备。该电子设备可以包括本公开实施例提供的上述半导体器件。该电子设备解决问题的原理与前述半导体器件相似，因此该电子设备的实施可以参见前述半导体器件的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，电子设备可以为：手机、平板电脑等任何具有存储功能的产品或部件。对于该电子设备的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种半导体器件的制备方法，包括：
    在半导体衬底上形成多个字线沟槽；其中，所述字线沟槽沿第一方向延伸；
    在各所述字线沟槽内形成字线结构；其中，所述字线结构的顶面和所述半导体衬底的顶面齐平；
    在所述半导体衬底的顶面上形成多个有源区掩膜结构；其中，所述有源区掩膜结构在所述半导体衬底中界定出有源区，且所述有源区掩膜结构在所述半导体衬底的底面的正投影沿第二方向延伸且穿过所述字线结构在所述半导体衬底的底面的正投影；
    以所述有源区掩膜结构为刻蚀掩膜，对所述字线结构和所述半导体衬底进行刻蚀，形成有源区和穿过所述有源区的埋入式字线。
  2. 如权利要求1所述的半导体器件的制备方法，其中，所述在各所述字线沟槽内形成字线结构，包括：
    在所述字线沟槽的侧壁上覆盖栅极介质层；
    在形成有所述栅极介质层的所述字线沟槽内填充埋入式字线；其中，所述埋入式字线的顶面低于所述半导体衬底的顶面；
    在所述字线沟槽内的所述埋入式字线上填充绝缘层；其中，所述绝缘层的顶面与所述半导体衬底的顶面齐平。
  3. 如权利要求2所述的半导体器件的制备方法，其中，所述对所述字线结构和所述半导体衬底进行刻蚀，形成有源区和穿过所述有源区的埋入式字线，包括：
    刻蚀非掩膜区域中的半导体衬底、绝缘层以及栅极介质层，暴露出所述非掩膜区域中的埋入式字线，以及使所述非掩膜区域中的半导体衬底与所述埋入式字线的底面齐平；其中，所述非掩膜区域为除所述有源区掩膜结构所在区域之外的区域；
    刻蚀所述非掩膜区域中设定深度的半导体衬底，使所述非掩膜区域中的半导体衬底的顶面与所述埋入式字线的底面具有所述设定深度。
  4. 如权利要求3所述的半导体器件的制备方法，其中，所述刻蚀非掩膜区域中的半导体衬底、绝缘层以及栅极介质层，暴露出所述非掩膜区域中的埋入式字线，以及使刻蚀后的半导体衬底与所述埋入式字线的底面齐平，包括：
    以所述有源区掩膜结构为刻蚀掩膜，刻蚀所述非掩膜区域中的半导体衬底和绝缘层，使所述非掩膜区域中的半导体衬底的顶面与所述埋入式字线的顶面齐平；
    以所述有源区掩膜结构为刻蚀掩膜，刻蚀所述非掩膜区域中的半导体衬底和栅极介质层，暴露出所述非掩膜区域中的埋入式字线，并使所述非掩膜区域中的半导体衬底的顶面与所述埋入式字线的底面齐平。
  5. 如权利要求4所述的半导体器件的制备方法，其中，所述暴露出所述非掩膜区域中的埋入式字线，包括：
    以所述有源区掩膜结构为刻蚀掩膜，刻蚀所述非掩膜区域中的半导体衬底和栅极介质层，暴露出所述非掩膜区域中的埋入式字线，并使所述非掩膜区域中暴露的埋入式字线的高度等于所述有源区掩膜结构所在区域中的埋入式字线的高度。
  6. 如权利要求4所述的半导体器件的制备方法，其中，所述暴露出所述非掩膜区域中的埋入式字线，包括：
    以所述有源区掩膜结构为刻蚀掩膜，刻蚀所述非掩膜区域中的半导体衬底和栅极介质层，暴露出所述非掩膜区域中的埋入式字线，并使所述非掩膜区域中的半导体衬底的顶面与所述埋入式字线的底面齐平，以及使所述非掩膜区域中暴露的埋入式字线的高度等于所述有源区掩膜结构所在区域中的埋入式字线的高度；
    以所述有源区掩膜结构为刻蚀掩膜，刻蚀所述非掩膜区域中的埋入式字线，以使所述非掩膜区域中的埋入式字线的高度小于所述有源区掩膜结构所 在区域中的埋入式字线的高度。
  7. 如权利要求3所述的半导体器件的制备方法，其中，在所述使刻蚀后的半导体衬底与所述埋入式字线的底面齐平之后，且在所述使刻蚀后的半导体衬底的顶面与所述埋入式字线的底面具有所述设定深度之前，还包括：
    对所述有源区掩膜结构的底面所在平面与所述埋入式字线的底面所在平面之间的半导体衬底进行氧化处理，使所述半导体衬底表面形成氧化保护层。
  8. 如权利要求7所述的半导体器件的制备方法，其中，所述刻蚀所述非掩膜区域中设定深度的半导体衬底，使所述非掩膜区域中的半导体衬底的顶面与所述埋入式字线的底面具有所述设定深度，包括：
    以所述有源区掩膜结构和所述埋入式字线为刻蚀掩膜，刻蚀所述设定深度的半导体衬底，使刻蚀后的半导体衬底的顶面与所述埋入式字线的底面具有所述设定深度；
    对处于所述设定深度中且位于所述埋入式字线所在区域内的半导体衬底进行刻蚀处理；
    刻蚀去除进行所述刻蚀处理后的半导体衬底，形成浅沟道隔离槽。
  9. 如权利要求1至8任一项所述的半导体器件的制备方法，其中，所述在半导体衬底上形成多个字线沟槽，包括：
    在所述半导体衬底上形成覆盖所述半导体衬底的沟槽掩膜层；
    对所述沟槽掩膜层进行图形化，形成条状的多个沟槽掩膜结构；
    去除相邻沟槽掩膜结构之间的间隙处设定深度的半导体衬底，形成所述多个字线沟槽。
  10. 如权利要求1至8任一项所述的半导体器件的制备方法，其中，在所述形成有源区和穿过所述有源区的埋入式字线之后，还包括：
    在所述半导体衬底上沉积隔离层，使所述隔离层与所述半导体衬底的顶面齐平。
  11. 一种半导体器件，采用如权利要求1至10任一项所述的制备方法得到；
    所述半导体器件包括：
    半导体衬底，具有由浅沟道隔离槽形成的隔离区以及由隔离区界定出的多个有源区；
    多条埋入式字线，埋置于通过刻蚀所述半导体衬底形成的字线沟槽中，且所述埋入式字线与相应的有源区相交设置。
  12. 如权利要求11所述的半导体器件，其中，以除所述有源区之外的其余区域作为非有源区，所述非有源区内的埋入式字线的高度小于或等于所述有源区内的埋入式字线的高度。
  13. 如权利要求11所述的半导体器件，其中，所述有源区对应的半导体衬底的顶面所在平面与所述埋入式字线的底面所在平面之间的半导体衬底的表面形成有氧化保护层。
  14. 如权利要求11所述的半导体器件，其中，所述有源区沿第三方向排列成重复单元，所述重复单元沿第一方向排列；其中，每相邻两个重复单元中的有源区错位排列；
    每一条所述埋入式字线交替穿过第奇数个重复单元和第偶数个重复单元中的有源区。
  15. 一种电子设备，包括如权利要求11至14任一项所述的半导体器件。
PCT/CN2021/113595 2021-08-16 2021-08-19 半导体器件、电子设备及制备方法 WO2023019523A1 (zh)

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CN102214578A (zh) * 2010-04-07 2011-10-12 海力士半导体有限公司 半导体器件及其制造方法
US20120039104A1 (en) * 2010-08-12 2012-02-16 Yung-Chang Lin Method and apparatus for buried word line formation
CN105097641A (zh) * 2014-05-09 2015-11-25 华邦电子股份有限公司 埋入式字线及其隔离结构的制造方法
CN109148376A (zh) * 2017-06-28 2019-01-04 长鑫存储技术有限公司 存储器及其形成方法、半导体器件
CN111048467A (zh) * 2018-10-11 2020-04-21 长鑫存储技术有限公司 半导体器件位线形成方法、半导体器件

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CN102214578A (zh) * 2010-04-07 2011-10-12 海力士半导体有限公司 半导体器件及其制造方法
US20120039104A1 (en) * 2010-08-12 2012-02-16 Yung-Chang Lin Method and apparatus for buried word line formation
CN105097641A (zh) * 2014-05-09 2015-11-25 华邦电子股份有限公司 埋入式字线及其隔离结构的制造方法
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