WO2023015646A1 - 显示面板及显示面板制作方法 - Google Patents

显示面板及显示面板制作方法 Download PDF

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Publication number
WO2023015646A1
WO2023015646A1 PCT/CN2021/116989 CN2021116989W WO2023015646A1 WO 2023015646 A1 WO2023015646 A1 WO 2023015646A1 CN 2021116989 W CN2021116989 W CN 2021116989W WO 2023015646 A1 WO2023015646 A1 WO 2023015646A1
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Prior art keywords
layer
display panel
electrode
color
disposed
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Ceased
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PCT/CN2021/116989
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English (en)
French (fr)
Inventor
朱茂霞
徐洪远
孙宇成
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Priority to US17/600,118 priority Critical patent/US12078901B2/en
Publication of WO2023015646A1 publication Critical patent/WO2023015646A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a method for manufacturing the display panel.
  • liquid crystal displays widely use frequency conversion display technology, which can well solve the communication problem between the processor and the display, eliminate image tearing and fluctuation, and achieve smooth display effect.
  • the pixel electrode of the liquid crystal display has a leakage state for a long time, which eventually leads to a decrease in the voltage of the pixel electrode, which in turn affects the deflection angle of the liquid crystal and makes the display brightness low, and switches between high and low frequencies. There is a brightness change during the process, which causes flickering problems on the displayed screen.
  • the present application provides a display panel and a manufacturing method of the display panel, which are used to alleviate the technical problem of pixel electrode leakage in current liquid crystal displays.
  • the application provides a display panel, which includes:
  • a driving circuit layer including common wiring
  • a color-resist layer disposed on the driving circuit layer, and the color-resist layer includes a plurality of color-resistors;
  • a common electrode layer disposed on the color resistance layer, the common electrode layer includes a transparent electrode, and the transparent electrode is electrically connected to the common wiring;
  • a pixel electrode layer is disposed on the insulating layer, and the pixel electrode layer includes a pixel electrode.
  • an orthographic projection of at least a partial area of the pixel electrode on the common electrode layer coincides with at least a partial area of the transparent electrode.
  • the display panel has a display area, and the transparent electrode is disposed corresponding to the display area.
  • the display panel further includes a first passivation layer disposed between the color resist layer and the common electrode layer.
  • the display panel further includes a connecting electrode, one end of the connecting electrode is electrically connected to the transparent electrode through a via hole on the insulating layer, and the other end of the connecting electrode is connected through the The via holes on the first passivation layer and the insulating layer are electrically connected to the common wiring.
  • the driving circuit layer includes: a gate, a gate insulating layer disposed on the gate, a semiconductor layer disposed on the gate insulating layer, a gate insulating layer disposed on the semiconductor layer The source and drain electrodes on the top, and the second passivation layer disposed on the source and drain electrodes.
  • the gate is disposed on the same layer as the common wiring, and the pixel electrode is electrically connected to one of the source and drain electrodes.
  • the transparent electrode is connected to the common path through the gap between two adjacent color resistors and the via hole on the second passivation layer and the gate insulating layer. electrical connection.
  • the display panel further includes a plurality of scan lines, a plurality of data lines, and a plurality of thin film transistors.
  • the color resistance includes red resistance, green resistance, blue resistance and white resistance.
  • the transparent electrodes include indium tin oxide electrodes.
  • the display panel further includes a liquid crystal layer disposed on the pixel electrode layer, and a counter substrate disposed on the liquid crystal layer.
  • the present application also provides a method for manufacturing a display panel, which includes:
  • a pixel electrode layer including a pixel electrode is fabricated on the insulating layer.
  • the step of manufacturing a common electrode layer including a transparent electrode on the color resist layer further includes:
  • a first passivation layer is formed on the color resist layer, the common electrode layer is formed on the first passivation layer, and the common electrode layer is patterned to form the transparent electrode.
  • Via holes are formed on the insulating layer, the first passivation layer, and the color resist layer, so that a part of the transparent electrode and a part of the common wiring pass through the insulating layer, the first passivation layer, and the first passivation layer.
  • a passivation layer and the via hole on the color resistance layer are exposed, and one of the source and drain electrodes is exposed through the insulating layer, the first passivation layer and the via hole on the color resistance layer.
  • the step of manufacturing a pixel electrode layer including a pixel electrode on the insulating layer includes:
  • connection electrode is electrically connected to the transparent electrode through the via hole on the insulating layer.
  • connection electrode is electrically connected to the common wiring through the first passivation layer and the via hole on the insulating layer.
  • the step of manufacturing the driving circuit layer including common wiring includes:
  • the driving circuit layer includes: the gate and the common wiring arranged on the base substrate, and the grid covering the gate and the common wiring A gate insulating layer, a semiconductor layer disposed on the gate insulating layer, a source-drain electrode disposed on the semiconductor layer, and a second passivation layer disposed on the source-drain electrode.
  • the step of fabricating a color-resist layer comprising a plurality of color-resistors on the driving circuit layer includes:
  • the color resistance layer including red resistance, green resistance, blue resistance and white resistance is fabricated on the driving circuit layer.
  • the step of manufacturing a common electrode layer including a transparent electrode on the color resist layer includes:
  • a common electrode layer including indium tin oxide electrodes is formed on the color resistance layer, and the indium tin oxide electrodes are electrically connected to the common wiring.
  • the present application also provides a display panel, which includes:
  • a driving circuit layer comprising a gate, a gate insulating layer disposed on the gate, a semiconductor layer disposed on the gate insulating layer, and a source-drain electrode disposed on the semiconductor layer , a second passivation layer disposed on the source and drain electrodes, and a common wiring disposed on the same layer as the gate;
  • a color-resist layer disposed on the driving circuit layer, and the color-resist layer includes a plurality of color-resistors;
  • the common electrode layer is arranged on the color resistance layer, the common electrode layer includes a transparent electrode, and the transparent electrode passes through the gap between two adjacent color resistances, the second passivation layer and the The via hole on the gate insulating layer is electrically connected to the common wiring;
  • a pixel electrode layer is disposed on the insulating layer, and the pixel electrode layer includes a pixel electrode.
  • the present application provides a display panel and a method for manufacturing the display panel.
  • the display panel includes a driving circuit layer, a color resistance layer disposed on the driving circuit layer, a common electrode layer disposed on the color resistance layer, and a
  • the driving circuit layer is provided with a common wiring
  • the common electrode layer is provided with a transparent electrode
  • the transparent electrode is electrically connected to the common wiring
  • the pixel The electrode layer is provided with pixel electrodes.
  • a transparent electrode is arranged between the color resistance layer and the pixel electrode layer, so that the transparent electrode and the pixel electrode form a storage capacitor, thereby maintaining the voltage state of the pixel electrode when the display panel is in low-frequency display, and effectively alleviating the problem of pixel electrode leakage.
  • the display quality of the display panel is improved, and the transparent electrode allows light to pass through without adversely affecting the display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a pixel unit in a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a partial film layer structure of the first display panel provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of the film layer structure of the first display panel provided by the embodiment of the present application, including the opposite substrate and the liquid crystal layer.
  • FIG. 5 is a schematic diagram of a partial film layer structure of a second display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of the film layer structure of the second display panel provided by the embodiment of the present application, including the opposite substrate and the liquid crystal layer.
  • FIG. 7 is a schematic diagram of the structure after the color-resist layer is manufactured by the first display panel manufacturing method provided in the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram after the common electrode layer is fabricated by the first display panel fabrication method provided in the embodiment of the present application.
  • FIG. 9 is a schematic structural view after the pixel electrode layer is fabricated by the first display panel fabrication method provided in the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram after the first display panel manufacturing method provided by the embodiment of the present application is completed.
  • FIG. 11 is a schematic structural diagram after the first passivation layer is fabricated by the second display panel fabrication method provided in the embodiment of the present application.
  • FIG. 12 is a schematic structural view of the second display panel manufacturing method provided by the embodiment of the present application after the insulating layer is manufactured.
  • FIG. 13 is a schematic structural diagram after the pixel electrode layer is fabricated by the second display panel fabrication method provided in the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram after the first display panel manufacturing method provided in the embodiment of the present application is completed.
  • the embodiment of the present application provides a display panel and a method for manufacturing the display panel
  • the display panel includes a driving circuit layer, a color resistance layer disposed on the driving circuit layer, a common electrode layer disposed on the color resistance layer, and a pixel electrode layer disposed on the common electrode layer
  • the driving circuit layer is provided with a common wiring
  • the common electrode layer is provided with a transparent electrode
  • the transparent electrode is electrically connected to the common wiring, so
  • the pixel electrode layer is provided with pixel electrodes.
  • a transparent electrode is provided between the color resist layer and the pixel electrode layer, so that the transparent electrode and the pixel electrode form a storage capacitor, thereby maintaining the voltage state of the pixel electrode when the display panel is in low-frequency display, and effectively alleviating the leakage of the pixel electrode.
  • the problem is to improve the display quality of the display panel, and the transparent electrode allows light to pass through without adversely affecting the display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a pixel unit in the display panel provided by an embodiment of the present application.
  • the embodiment of the present application provides a display panel 10, the display panel 10 has a display area AA, the display panel 10 is provided with a plurality of pixel units 11 in the area corresponding to the display area AA, each of the pixel units 11 A driving circuit, a color resistor, a pixel electrode, etc. are correspondingly arranged inside, and the pixel unit 11 is a basic repeating unit on the display panel 10 .
  • the display panel 10 includes a plurality of scan lines S, a plurality of data lines D, and a plurality of TFTs T.
  • the scan line S is used to provide a scan signal to control the on and off state of the thin film transistor T;
  • the data line D is used to provide a data signal and transmit the data signal to the thin film transistor T,
  • the thin film transistor T further transmits the data signal to the pixel electrode 112 under the control of the scan signal.
  • FIG. 3 is a schematic diagram of a partial film layer structure of the first display panel provided by the embodiment of the present application.
  • the display panel 10 includes a base substrate 101, a driving circuit layer disposed on the base substrate 101, a color resistance layer disposed on the driving circuit layer, and a common electrode layer disposed on the color resistance layer. , an insulating layer 111 disposed on the common electrode layer, and a pixel electrode layer disposed on the insulating layer 111 .
  • the base substrate 101 may include a substrate layer and a buffer layer on the substrate layer.
  • the substrate layer can be made of one or more materials such as glass and polyimide;
  • the buffer layer includes a buffer material, such as polyimide, etc., and the buffer layer is used to relieve the gap between the substrate layer and the substrate layer. Stress mismatch between the above film layers.
  • the driving circuit layer includes: a gate 102 and a common wiring 103 arranged on the base substrate 101, a gate insulating layer 104 covering the gate 102 and the common wiring 103, and a gate insulating layer 104 arranged on the The semiconductor layer 105 on the gate insulating layer 104 , the source-drain electrodes 106 disposed on the semiconductor layer 105 , and the second passivation layer 107 disposed on the source-drain electrodes 106 .
  • the gate 102 is electrically connected to the scanning line S, and receives the scanning signal provided by the scanning line S; the common wiring 103 is electrically connected to a constant voltage supply terminal for transmitting the constant voltage A constant voltage signal provided by a voltage supply end;
  • the semiconductor layer 105 may include a low-temperature polysilicon semiconductor or a metal oxide semiconductor, and the opposite ends of the semiconductor layer 105 form a source doped region and a drain doped region;
  • the source The drain electrode 106 includes a source and a drain, the source is set corresponding to the source doped region of the semiconductor layer 105, and the drain is set corresponding to the drain doped region of the semiconductor layer 105; the gate Both the insulating layer 104 and the second passivation layer 107 can be made of inorganic insulating materials.
  • the gate 102 , the semiconductor layer 105 and the source-drain electrodes 106 constitute the TFT T.
  • the color resist layer includes a plurality of color resists 108 disposed on the second passivation layer 107 , each of the color resists 108 corresponds to one of the pixel units 11 .
  • the plurality of color resistors 108 include red resistors, green resistors, blue resistors and white resistors.
  • the common electrode layer includes a transparent electrode 110 disposed on the color resistance 108, and the transparent electrode 110 is electrically connected to the common wiring 103, and the common wiring 103 provides a constant voltage to the transparent electrode 110. voltage signal.
  • the transparent electrode 110 is connected to the common wiring through the gap between two adjacent color resistors 108 and the via holes on the second passivation layer 107 and the gate insulating layer 104 .
  • 103 forms an electrical connection.
  • the transparent electrode 110 is disposed corresponding to the display area AA of the display panel 10 and covers at least one pixel unit 11 .
  • the transparent electrode 110 may be selected from transparent electrodes such as indium tin oxide electrodes, so that the transparent electrode 110 has light transmittance.
  • the transparent electrode 110 disposed on the common electrode layer is configured to be light-transmissive, so that the transparent electrode 110 located in the display area AA of the display panel 10 will not adversely affect light passing through the display panel 10 .
  • the insulating layer 111 covers the transparent electrode 110 and the color resist 108 , and the insulating layer 111 can be made of inorganic insulating materials such as silicon nitride and silicon oxide.
  • the pixel electrode layer includes a pixel electrode 112 disposed on the insulating layer 111 and electrically insulated from the transparent electrode 110 .
  • the pixel electrode 112 is electrically connected to the source-drain electrode 106 through the insulating layer 111 and the via hole on the second passivation layer 107, so as to receive the transmission from the data line D through the thin film transistor T. data signal.
  • the orthographic projection of at least a partial area of the pixel electrode 112 on the common electrode layer coincides with at least a partial area of the transparent electrode 110 .
  • the pixel electrode 112 and the transparent electrode 110 form a storage capacitor. Since the voltage of the transparent electrode 110 is constant, when the pixel electrode 112 is charged, the storage capacitor will store a part of the electricity, thereby maintaining the pixel electrode for a certain period of time.
  • the voltage state of 112 prevents the voltage of the display panel 10 from being low due to the leakage of the pixel electrode 112 in the low-frequency display mode, thereby alleviating the flickering problem of the display panel 10 when switching between high and low frequencies, which is conducive to improving the display quality of the display panel 10 .
  • the pixel electrodes 112 are arranged corresponding to the display area of the display panel 10 , and the display panel 10 includes a plurality of the pixel electrodes 112 , and each of the pixel electrodes 112 is arranged corresponding to one of the pixel units 11 .
  • the pixel electrode 112 is an indium tin oxide electrode.
  • FIG. 4 is a schematic diagram of the layer structure of the first display panel provided in the embodiment of the present application, including the opposite substrate and the liquid crystal layer.
  • the display panel 10 further includes a liquid crystal layer 114 disposed on the pixel electrodes 112 , and a counter substrate 115 disposed on the liquid crystal layer 114 .
  • Liquid crystals are disposed in the liquid crystal layer 114
  • opposite electrodes are disposed in the opposite substrate 115
  • the opposite electrodes have a constant voltage.
  • the liquid crystal is deflected at a specific angle under the action of the electric field formed by the pixel electrode 112 and the opposite electrode, so that the display panel 10 presents various display gray scales.
  • the opposite electrode is disposed on a side of the opposite substrate 115 close to the liquid crystal layer 114; a layer of insulating material may also be disposed between the pixel electrode 112 and the liquid crystal layer 114, so as to The electrical insulation between the pixel electrode 112 and the liquid crystal is maintained.
  • FIG. 5 is a schematic diagram of a partial film layer structure of a second display panel provided in an embodiment of the present application. It should be noted that the display panel provided by this embodiment has the same or similar structure as the display panel provided by the above-mentioned embodiments. The structural features of the display panel provided by this embodiment will be described below. For details that are not described, please refer to the above Description of Examples.
  • the display panel 10 includes a base substrate 101, a driving circuit layer disposed on the base substrate 101, a color resistance layer disposed on the driving circuit layer, and a first passivation layer disposed on the color resistance layer. layer 109, a common electrode layer disposed on the first passivation layer 109, an insulating layer 111 disposed on the common electrode layer, and a pixel electrode layer disposed on the insulating layer 111.
  • the driving circuit layer includes: a gate 102 and a common wiring 103 arranged on the base substrate 101, a gate insulating layer 104 covering the gate 102 and the common wiring 103, and a gate insulating layer 104 arranged on the The semiconductor layer 105 on the gate insulating layer 104 , the source-drain electrodes 106 disposed on the semiconductor layer 105 , and the second passivation layer 107 disposed on the source-drain electrodes 106 .
  • the gate 102 is electrically connected to the scanning line S, and receives the scanning signal provided by the scanning line S; the common wiring 103 is electrically connected to a constant voltage supply terminal for transmitting the constant voltage
  • the gate 102 , the semiconductor layer 105 and the source-drain electrodes 106 constitute the TFT T.
  • the color resist layer includes a plurality of color resists 108 disposed on the second passivation layer 107 , each of the color resists 108 corresponds to one of the pixel units 11 .
  • the plurality of color resistors 108 include red resistors, green resistors, blue resistors and white resistors.
  • the first passivation layer 109 covers a plurality of color resists 108 in the color resist layer, and the first passivation layer 109 can be made of inorganic insulating material.
  • the common electrode layer includes a transparent electrode 110 disposed on the first passivation layer 109, and the transparent electrode 110 is electrically connected to the common wiring 103, and the common wiring 103 connects to the transparent electrode. 110 provides a constant voltage signal.
  • the display panel further includes a connection electrode 113 , and the transparent electrode 110 is electrically connected to the common wiring 103 through the connection electrode 113 .
  • one end of the connecting electrode 113 is electrically connected to the transparent electrode 110 through the via hole on the insulating layer 111, and the other end of the connecting electrode 113 is connected through the gate insulating layer 104, the second A passivation layer 109 and via holes on the insulating layer 111 are electrically connected to the common wiring 103 , thereby forming an electrical connection between the transparent electrode 110 and the common wiring 103 .
  • the transparent electrode 110 is disposed corresponding to the display area AA of the display panel 10 and covers at least one pixel unit 11 .
  • the transparent electrode 110 may be selected from transparent electrodes such as indium tin oxide electrodes, so that the transparent electrode 110 has light transmittance.
  • the transparent electrode 110 disposed on the common electrode layer is configured to be light-transmissive, so that the transparent electrode 110 located in the display area AA of the display panel 10 will not adversely affect light passing through the display panel 10 .
  • the pixel electrode layer includes a pixel electrode 112 disposed on the insulating layer 111 and electrically insulated from the transparent electrode 110 .
  • the pixel electrode 112 is electrically connected to the source-drain electrode 106 through the via holes on the insulating layer 111, the first passivation layer 109 and the second passivation layer 107, so as to receive the data The data signal transmitted by the line D through the thin film transistor T.
  • the orthographic projection of at least a partial area of the pixel electrode 112 on the common electrode layer coincides with at least a partial area of the transparent electrode 110 .
  • the pixel electrode 112 and the transparent electrode 110 form a storage capacitor. Since the voltage of the transparent electrode 110 is constant, when the pixel electrode 112 is charged, the storage capacitor will store a part of the electricity, thereby maintaining the pixel electrode for a certain period of time.
  • the voltage state of 112 prevents the voltage of the display panel 10 from being low due to the leakage of the pixel electrode 112 in the low-frequency display mode, thereby alleviating the flickering problem of the display panel 10 when switching between high and low frequencies, which is conducive to improving the display quality of the display panel 10 .
  • the pixel electrodes 112 are arranged corresponding to the display area of the display panel 10 , and the display panel 10 includes a plurality of the pixel electrodes 112 , and each of the pixel electrodes 112 is arranged corresponding to one of the pixel units 11 .
  • the pixel electrode 112 is an indium tin oxide electrode.
  • FIG. 6 is a schematic diagram of the layer structure of the second display panel provided by the embodiment of the present application, including the opposite substrate and the liquid crystal layer.
  • the display panel 10 further includes a liquid crystal layer 114 disposed on the pixel electrodes 112 , and a counter substrate 115 disposed on the liquid crystal layer 114 .
  • Liquid crystals are disposed in the liquid crystal layer 114
  • opposite electrodes are disposed in the opposite substrate 115
  • the opposite electrodes have a constant voltage.
  • the liquid crystal is deflected at a specific angle under the action of the electric field formed by the pixel electrode 112 and the opposite electrode, so that the display panel 10 presents various display gray scales.
  • the opposite electrode is disposed on a side of the opposite substrate 115 close to the liquid crystal layer 114; a layer of insulating material may also be disposed between the pixel electrode 112 and the liquid crystal layer 114, so as to The electrical insulation between the pixel electrode 112 and the liquid crystal is maintained.
  • the display panel provided by the embodiment of the present application includes a driving circuit layer, a color resistance layer disposed on the driving circuit layer, a common electrode layer disposed on the color resistance layer, and a color resistance layer disposed on the common electrode layer.
  • the pixel electrode layer on the electrode layer, the drive circuit layer is provided with a common wiring
  • the common electrode layer is provided with a transparent electrode
  • the transparent electrode is electrically connected to the common wiring
  • the pixel electrode layer is provided with pixel electrodes.
  • a transparent electrode is provided between the color resist layer and the pixel electrode layer, so that the transparent electrode and the pixel electrode form a storage capacitor, thereby maintaining the voltage state of the pixel electrode when the display panel is in low-frequency display, and effectively alleviating the leakage of the pixel electrode.
  • the problem is to improve the display quality of the display panel, and the transparent electrode allows light to pass through without adversely affecting the display effect of the display panel.
  • Another embodiment of the present application also provides a method for manufacturing a display panel, which includes the steps of forming a transparent electrode on the color-resist layer of the display panel, and making the transparent electrode and the pixel electrode form a storage capacitor.
  • the pixel electrode of the manufactured display panel has leakage problem, and the process is simple and easy to realize.
  • the manufacturing method of the display panel includes the following steps:
  • Step S101 fabricating a driving circuit layer including a common wire 103 .
  • the driving circuit layer is fabricated on a base substrate 101, and the driving circuit layer includes: a gate 102 and the common wiring 103 arranged on the base substrate 101, covering the gate 102 and the gate insulating layer 104 of the common wiring 103, the semiconductor layer 105 disposed on the gate insulating layer 104, the source and drain electrodes 106 disposed on the semiconductor layer 105, and the source and drain electrodes 106 disposed on the source A second passivation layer 107 on the drain electrode 106 .
  • the common wiring 103 is electrically connected to a constant voltage supply terminal for transmitting a constant voltage signal provided by the constant voltage supply terminal.
  • Step S102 fabricating a color-resist layer including a plurality of color-resistors 108 on the driving circuit layer.
  • the plurality of color resists 108 in the color resist layer are formed by coating and patterning processes.
  • the plurality of color resists 108 may include red resists, green resists, blue resists and white resists.
  • Step S103 forming a common electrode layer including a transparent electrode 110 on the color resist layer, and the transparent electrode 110 is electrically connected to the common wiring 103 .
  • the step S103 further includes: forming via holes on the second passivation layer 107 , the gate insulating layer 104 and the color resist layer through an etching process.
  • the method for making the transparent electrode 110 may be a physical vapor deposition method; in the process of making the transparent electrode 110, the formed transparent electrode 110 passes through the second passivation layer 107, the gate insulating layer 104 and The via holes on the color resistance layer are electrically connected to the common wiring 103 .
  • the transparent electrode 110 may be selected from transparent electrodes such as indium tin oxide electrodes, so that the transparent electrode 110 has light transmittance.
  • Step S104 forming an insulating layer 111 on the common electrode layer.
  • the insulating layer 111 may be a silicon nitride or silicon oxide film formed by a vapor deposition process.
  • the insulating layer 111 covers the transparent electrode 110 and the color resist 108 .
  • the display panel manufacturing method further includes forming via holes on the insulating layer 111, the second passivation layer 107, and the color resist layer through processes such as exposure, development, and etching, so that One of the source-drain electrodes 106 is exposed through via holes on the insulating layer 111 , the second passivation layer 107 and the color resist layer.
  • Step S105 forming a pixel electrode layer including the pixel electrode 112 on the insulating layer 111 .
  • the pixel electrode 112 may be an indium tin oxide film layer formed by a patterned deposition process, or an indium tin oxide film layer formed by processing the fabricated pixel electrode layer by a patterning process, and the formed The pixel electrode 112 is electrically connected to the source-drain electrode 106 through the via hole on the insulating layer 111 and the second passivation layer 107 .
  • the display panel manufacturing method further includes: manufacturing a liquid crystal layer 114 containing liquid crystals on the pixel electrode layer, and setting a counter substrate 115 on the side of the liquid crystal layer 114 away from the pixel electrode layer, so
  • the opposite substrate 115 includes an opposite electrode.
  • the liquid crystal is deflected at a specific angle under the action of the electric field formed by the pixel electrode 112 and the opposite electrode, so that the manufactured display panel presents various display gray scales.
  • the manufacturing method of the display panel further includes: forming a layer of insulating material on the pixel electrode 112 to ensure electrical insulation between the pixel electrode 112 and the liquid crystal fabricated later.
  • the manufacturing method of the display panel includes the following steps:
  • Step S101 fabricating a driving circuit layer including a common wiring 103 .
  • the driving circuit layer is fabricated on the base substrate 101, and the driving circuit layer includes: the gate 102 and the common wiring 103 arranged on the base substrate 101, covering the gate electrode 102 and the gate insulating layer 104 of the common wiring 103, the semiconductor layer 105 disposed on the gate insulating layer 104, the source-drain electrode 106 disposed on the semiconductor layer 105, and the The second passivation layer 107 on the source and drain electrodes 106 .
  • the common wiring 103 is electrically connected to a constant voltage supply terminal for transmitting a constant voltage signal provided by the constant voltage supply terminal.
  • Step S102 fabricating a color-resist layer including a plurality of color-resistors 108 on the driving circuit layer.
  • the plurality of color resists 108 in the color resist layer are formed by coating and patterning processes.
  • the plurality of color resists 108 may include red resists, green resists, blue resists and white resists.
  • the step S102 further includes: forming a first passivation layer 109 on the color-resist layer, so that the first passivation layer 109 covers a plurality of color-resistors 108 in the color-resist layer.
  • the first passivation layer 109 may be an inorganic insulating layer made by a vapor deposition process.
  • Step S103 forming a common electrode layer including the transparent electrode 110 on the first passivation layer 109 .
  • the transparent electrode 110 can be fabricated through a patterned deposition process.
  • the transparent electrode 110 may be selected from transparent electrodes such as indium tin oxide electrodes, so that the transparent electrode 110 has light transmittance.
  • Step S104 forming an insulating layer 111 on the common electrode layer.
  • the insulating layer 111 may be a silicon nitride or silicon oxide film formed by a vapor deposition process.
  • the insulating layer 111 covers the transparent electrode 110 .
  • step S104 it also includes:
  • Via holes are formed on the insulating layer 111, the first passivation layer 109, the second passivation layer 107, and the color resist layer through processes such as exposure, development, and etching, so that the source leakage
  • the pole 106 is exposed through the via holes on the insulating layer 111, the first passivation layer 109, the second passivation layer 107 and the color resistance layer; and via holes are formed on the insulating layer 111,
  • the transparent electrode 110 is exposed through the via hole on the insulating layer 111; and the insulating layer 111, the first passivation layer 109, the second passivation layer 107, the gate insulating layer 104 and the color resistance layer to form via holes, so that the common wiring 103 passes through the insulating layer 111, the first passivation layer 109, the second passivation layer 107, the gate insulating layer 104 and the via holes on the color resist layer are exposed.
  • the above-mentioned via holes can be made by the same process.
  • Step S105 forming a pixel electrode layer including the pixel electrode 112 on the insulating layer 111 .
  • the step S105 includes: forming the pixel electrode 112 and the connecting electrode 113 on the insulating layer 111, making one end of the connecting electrode 113 connect to the transparent electrode through the via hole on the insulating layer 111. 110, and the other end of the connection electrode 113 is connected to the via holes on the insulating layer 111, the first passivation layer 109, the second passivation layer 107 and the gate insulating layer 104.
  • the common wiring 103 is electrically connected.
  • the pixel electrode 112 and the connection electrode 113 may be an indium tin oxide film layer formed by a patterned deposition process, or an indium tin oxide film layer formed by processing the fabricated pixel electrode layer by a patterning process, and formed
  • the pixel electrode 112 is electrically connected to the source-drain electrode 106 through the via holes on the insulating layer 111 , the first passivation layer 109 and the second passivation layer 107 .
  • the display panel manufacturing method further includes: manufacturing a liquid crystal layer 114 containing liquid crystals on the pixel electrode layer, and setting a counter substrate 115 on the side of the liquid crystal layer 114 away from the pixel electrode layer, so
  • the opposite substrate 115 includes an opposite electrode.
  • the liquid crystal is deflected at a specific angle under the action of the electric field formed by the pixel electrode 112 and the opposite electrode, so that the manufactured display panel presents various display gray scales.
  • the manufacturing method of the display panel further includes: forming a layer of insulating material on the pixel electrode 112 to ensure electrical insulation between the pixel electrode 112 and the liquid crystal fabricated later.
  • the display panel manufacturing method includes the steps of forming a transparent electrode on the color resist layer of the display panel, and making the transparent electrode and the pixel electrode form a storage capacitor. This method can ease the production of the display panel. Leakage problem occurs in the pixel electrode, and the process is simple and easy to realize.

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Abstract

一种显示面板(10)及显示面板(10)制作方法。显示面板(10)包括驱动电路层、设置于驱动电路层上的色阻层、设置于色阻层上的公共电极层、以及设置于公共电极层上的像素电极层，驱动电路层设置有公共走线(103)，公共电极层设置有透明电极(110)，透明电极(110)与公共走线(103)电性连接，像素电极层设置有像素电极(112)。

Description

显示面板及显示面板制作方法
本申请要求于2021年08月09日提交中国专利局、申请号为202110907228.9、发明名称为“显示面板及显示面板制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示面板制作方法。
 背景技术
目前，液晶显示器广泛采用变频显示技术，该技术可以很好的解决处理器和显示器之间的通信问题，消除图像撕裂和波动，实现流畅的显示效果。但是在低频显示模式下，液晶显示器的像素电极存在一段较长时间的漏电状态，该漏电状态最终导致像素电极的电压降低，进而影响液晶的偏转角度而使显示亮度偏低，并且在高低频切换过程中存在亮度变化而导致显示的画面出现闪烁问题。
 技术问题
目前的液晶显示器存在像素电极漏电的技术问题。
 技术解决方案
本申请提供一种显示面板及显示面板制作方法，用于缓解目前液晶显示器存在的像素电极漏电的技术问题。
本申请提供一种显示面板，其包括：
驱动电路层，所述驱动电路层包括公共走线；
色阻层，设置于所述驱动电路层上，所述色阻层包括多个色阻；
公共电极层，设置于所述色阻层上，所述公共电极层包括透明电极，所述透明电极与所述公共走线电性连接；
绝缘层，设置于所述公共电极层上；
像素电极层，设置于所述绝缘层上，所述像素电极层包括像素电极。
在本申请的显示面板中，所述像素电极的至少部分区域在所述公共电极层上的正投影与所述透明电极的至少部分区域重合。
在本申请的显示面板中，所述显示面板具有显示区，所述透明电极对应所述显示区设置。
在本申请的显示面板中，所述显示面板还包括设置于所述色阻层与所述公共电极层之间的第一钝化层。
在本申请的显示面板中，所述显示面板还包括连接电极，所述连接电极的一端通过所述绝缘层上的过孔与所述透明电极电性连接，所述连接电极的另一端通过所述第一钝化层和所述绝缘层上的过孔与所述公共走线电性连接。
在本申请的显示面板中，所述驱动电路层包括：栅极、设置于所述栅极上的栅极绝缘层、设置于所述栅极绝缘层上的半导体层、设置于所述半导体层上的源漏电极、以及设置于所述源漏电极上的第二钝化层。
在本申请的显示面板中，所述栅极与所述公共走线同层设置，所述像素电极与所述源漏电极的其中一者电性连接。
在本申请的显示面板中，所述透明电极通过相邻两个所述色阻之间的间隙、以及所述第二钝化层和所述栅极绝缘层上的过孔与所述公共走线电性连接。
在本申请的显示面板中，所述显示面板还包括多条扫描线、多条数据线、以及多个薄膜晶体管。
在本申请的显示面板中，所述色阻包括红色阻、绿色阻、蓝色阻和白色阻。
在本申请的显示面板中，所述透明电极包括氧化铟锡电极。
在本申请的显示面板中，所述显示面板还包括设置于所述像素电极层上的液晶层、以及设置于所述液晶层上的对置基板。
本申请还提供一种显示面板制作方法，其包括：
制作包括公共走线的驱动电路层；
在所述驱动电路层上制作包括多个色阻的色阻层；
在所述色阻层上制作包括透明电极的公共电极层，所述透明电极与所述公共走线电性连接；
在所述公共电极层上制作绝缘层；
在所述绝缘层上制作包括像素电极的像素电极层。
在本申请的显示面板制作方法中，所述在所述色阻层上制作包括透明电极的公共电极层的步骤，还包括：
在所述色阻层上制作第一钝化层，在所述第一钝化层上制作所述公共电极层，图案化所述公共电极层形成所述透明电极。
在本申请的显示面板制作方法中，所述在所述公共电极层上制作绝缘层的步骤之后，还包括：
在所述绝缘层、所述第一钝化层和所述色阻层上形成过孔，使所述透明电极的部分区域和所述公共走线的部分区域通过所述绝缘层、所述第一钝化层和所述色阻层上过孔暴露，并使所述源漏电极的其中一者通过所述绝缘层、所述第一钝化层和所述色阻层上过孔暴露。
在本申请的显示面板制作方法中，所述在所述绝缘层上制作包括像素电极的像素电极层的步骤，包括：
在所述绝缘层上制作像素电极层，并图案化所述像素电极层形成所述像素电极和连接电极，所述连接电极的一端通过所述绝缘层上的过孔与所述透明电极电性连接，所述连接电极的另一端通过所述第一钝化层和所述绝缘层上的过孔与所述公共走线电性连接。
在本申请的显示面板制作方法中，所述制作包括公共走线的驱动电路层的步骤，包括：
在一衬底基板上制作所述驱动电路层，所述驱动电路层包括：设置于所述衬底基板上的栅极和所述公共走线、覆盖所述栅极和所述公共走线的栅极绝缘层、设置于所述栅极绝缘层上的半导体层、设置于所述半导体层上的源漏电极、以及设置于所述源漏电极上的第二钝化层。
在本申请的显示面板制作方法中，所述在所述驱动电路层上制作包括多个色阻的色阻层的步骤，包括：
在所述驱动电路层上制作包括红色阻、绿色阻、蓝色阻和白色阻的所述色阻层。
在本申请的显示面板制作方法中，所述在所述色阻层上制作包括透明电极的公共电极层的步骤，包括：
在所述色阻层上制作包括氧化铟锡电极的公共电极层，所述氧化铟锡电极与所述公共走线电性连接。
本申请还提供一种显示面板，其包括：
驱动电路层，所述驱动电路层包括栅极、设置于所述栅极上的栅极绝缘层、设置于所述栅极绝缘层上的半导体层、设置于所述半导体层上的源漏电极、设置于所述源漏电极上的第二钝化层、以及与所述栅极同层设置的公共走线；
色阻层，设置于所述驱动电路层上，所述色阻层包括多个色阻；
公共电极层，设置于所述色阻层上，所述公共电极层包括透明电极，所述透明电极通过相邻两个所述色阻之间的间隙、以及所述第二钝化层和所述栅极绝缘层上的过孔与所述公共走线电性连接；
绝缘层，设置于所述公共电极层上；
像素电极层，设置于所述绝缘层上，所述像素电极层包括像素电极。
 有益效果
本申请提供一种显示面板及显示面板制作方法，所述显示面板包括驱动电路层、设置于所述驱动电路层上的色阻层、设置于所述色阻层上的公共电极层、以及设置于所述公共电极层上的像素电极层，所述驱动电路层设置有公共走线，所述公共电极层设置有透明电极，所述透明电极与所述公共走线电性连接，所述像素电极层设置有像素电极。本申请通过在色阻层与像素电极层之间设置透明电极，使透明电极与像素电极形成存储电容，从而在显示面板处于低频显示时维持像素电极的电压状态，有效缓解像素电极漏电的问题，提升显示面板的显示品质，并且透明电极允许光线穿过而不会对显示面板的显示效果产生不利影响。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板的结构示意图。
图2是本申请实施例提供的显示面板中的一个像素单元的结构示意图。
图3是本申请实施例提供的第一种显示面板的局部膜层结构示意图。
图4是本申请实施例提供的第一种显示面板包括对置基板和液晶层的膜层结构示意图。
图5是本申请实施例提供的第二种显示面板的局部膜层结构示意图。
图6是本申请实施例提供的第二种显示面板包括对置基板和液晶层的膜层结构示意图。
图7是本申请实施例提供的第一种显示面板制作方法制作完色阻层后的结构示意图。
图8是本申请实施例提供的第一种显示面板制作方法制作完公共电极层后的结构示意图。
图9是本申请实施例提供的第一种显示面板制作方法制作完像素电极层后的结构示意图。
图10是本申请实施例提供的第一种显示面板制作方法制作完成后的结构示意图。
图11是本申请实施例提供的第二种显示面板制作方法制作完第一钝化层后的结构示意图。
图12是本申请实施例提供的第二种显示面板制作方法制作完绝缘层后的结构示意图。
图13是本申请实施例提供的第二种显示面板制作方法制作完像素电极层后的结构示意图。
图14是本申请实施例提供的第一种显示面板制作方法制作完成后的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供一种显示面板及显示面板制作方法，所述显示面板包括驱动电路层、设置于所述驱动电路层上的色阻层、设置于所述色阻层上的公共电极层、以及设置于所述公共电极层上的像素电极层，所述驱动电路层设置有公共走线，所述公共电极层设置有透明电极，所述透明电极与所述公共走线电性连接，所述像素电极层设置有像素电极。本申请实施例通过在色阻层与像素电极层之间设置透明电极，使透明电极与像素电极形成存储电容，从而在显示面板处于低频显示时维持像素电极的电压状态，有效缓解像素电极漏电的问题，提升显示面板的显示品质，并且透明电极允许光线穿过而不会对显示面板的显示效果产生不利影响。
下面结合具体实施例对本申请提供的显示面板进行说明。
请参阅图1和图2，图1是本申请实施例提供的显示面板的结构示意图，图2是本申请实施例提供的显示面板中的一个像素单元的结构示意图。
本申请实施例提供一种显示面板10，所述显示面板10具有显示区AA，所述显示面板10在对应所述显示区AA的区域设置有多个像素单元11，每个所述像素单元11内对应设置有驱动电路、色阻、像素电极等，所述像素单元11是所述显示面板10上的基本重复单元。
所述显示面板10包括多条扫描线S、多条数据线D、以及多个薄膜晶体管T。所述扫描线S用于提供扫描信号，以控制所述薄膜晶体管T的导通和断开的状态；所述数据线D用于提供数据信号，并将数据信号传输至所述薄膜晶体管T，所述薄膜晶体管T在扫描信号的控制下进一步将数据信号传输至像素电极112。
请进一步参阅图3，图3是本申请实施例提供的第一种显示面板的局部膜层结构示意图。所述显示面板10包括衬底基板101、设置于所述衬底基板101上的驱动电路层、设置于所述驱动电路层上的色阻层、设置于所述色阻层上的公共电极层、设置于所述公共电极层上的绝缘层111、以及设置于所述绝缘层111上的像素电极层。
所述衬底基板101可以包括基板层和位于所述基板层上的缓冲层。所述基板层可以由玻璃、聚酰亚胺等材料中的一种或多种构成；所述缓冲层包括缓冲材料，例如聚酰亚胺等，所述缓冲层用于缓解基板层与基板层以上膜层之间的应力不匹配性。
所述驱动电路层包括：设置于所述衬底基板101上的栅极102和公共走线103、覆盖所述栅极102和所述公共走线103的栅极绝缘层104、设置于所述栅极绝缘层104上的半导体层105、设置于所述半导体层105上的源漏电极106、以及设置于所述源漏电极106上的第二钝化层107。其中，所述栅极102与所述扫描线S电性连接，并接收所述扫描线S提供的扫描信号；所述公共走线103电性连接至一个恒定电压供应端，用于传输该恒定电压供应端提供的恒定电压信号；所述半导体层105可以包括低温多晶硅半导体或金属氧化物半导体，所述半导体层105的相对两端形成源极掺杂区和漏极掺杂区；所述源漏电极106包括源极和漏极，所述源极对应所述半导体层105的源极掺杂区设置，所述漏极对应所述半导体层105的漏极掺杂区设置；所述栅极绝缘层104和所述第二钝化层107均可以采用无机绝缘材料制作而成。所述栅极102、所述半导体层105和所述源漏电极106构成所述薄膜晶体管T。
所述色阻层包括多个设置于所述第二钝化层107上的色阻108，每个所述色阻108对应一个所述像素单元11。可选地，多个所述色阻108包括红色阻、绿色阻、蓝色阻和白色阻。
所述公共电极层包括设置于所述色阻108上的透明电极110，并且所述透明电极110与所述公共走线103电性连接，所述公共走线103向所述透明电极110提供恒定电压信号。
具体地，所述透明电极110通过相邻两个所述色阻108之间的间隙、以及所述第二钝化层107和所述栅极绝缘层104上的过孔与所述公共走线103形成电性连接。所述透明电极110对应所述显示面板10的显示区AA设置，且至少覆盖一个所述像素单元11。
可选地，所述透明电极110可以选自氧化铟锡电极等透明电极，从而使所述透明电极110具有光线透过性。本实施例将设置于所述公共电极层的透明电极110设置为具有透光性，使得位于显示面板10的显示区AA内的透明电极110不会对光线穿过显示面板10内部产生不利影响。
所述绝缘层111覆盖所述透明电极110及所述色阻108，所述绝缘层111可以由氮化硅、氧化硅等无机绝缘材料制作而成。
所述像素电极层包括像素电极112，所述像素电极112设置于所述绝缘层111上，且与所述透明电极110保持电性绝缘。所述像素电极112通过所述绝缘层111和所述第二钝化层107上的过孔与所述源漏电极106保持电性连接，以接收所述数据线D通过所述薄膜晶体管T传输的数据信号。
进一步地，所述像素电极112的至少部分区域在所述公共电极层上的正投影与所述透明电极110的至少部分区域重合。所述像素电极112与所述透明电极110形成存储电容，由于所述透明电极110的电压恒定，所述像素电极112被充电时，该存储电容会存储一部分电量，从而在一定时间内维持像素电极112的电压状态，防止显示面板10在低频显示模式时因像素电极112漏电而导致其电压偏低，进而缓解显示面板10在高低频切换时出现闪烁的问题，有利于提升显示面板10的显示品质。
所述像素电极112对应所述显示面板10的显示区设置，且所述显示面板10包括多个所述像素电极112，每个所述像素电极112对应一个所述像素单元11设置。可选地，所述像素电极112为氧化铟锡电极。
请进一步参阅图4，图4是本申请实施例提供的第一种显示面板包括对置基板和液晶层的膜层结构示意图。所述显示面板10还包括设置于所述像素电极112上的液晶层114、以及设置于所述液晶层114上的对置基板115。所述液晶层114中设置有液晶，所述对置基板115中设置有对置电极，所述对置电极具有恒定电压。所述液晶在所述像素电极112和所述对置电极形成的电场作用下产生特定角度的偏转，从而使所述显示面板10呈现多种显示灰阶。
可选地，所述对置电极设置于所述对置基板115的靠近所述液晶层114的一侧；所述像素电极112与所述液晶层114之间还可以设置有一层绝缘材料，以保持所述像素电极112与所述液晶之间的电性绝缘。
在另一种实施例中，请参阅图1、图2和图5，图5是本申请实施例提供的第二种显示面板的局部膜层结构示意图。需要说明的是，本实施例提供的显示面板与上述实施例提供的显示面板具有相同或相似的结构，下面对本实施例提供的显示面板的结构特征进行说明，其中未详述之处请参阅上述实施例的记载。
所述显示面板10包括衬底基板101、设置于所述衬底基板101上的驱动电路层、设置于所述驱动电路层上的色阻层、设置于所述色阻层上的第一钝化层109、设置于所述第一钝化层109上的公共电极层、设置于所述公共电极层上的绝缘层111、以及设置于所述绝缘层111上的像素电极层。
所述驱动电路层包括：设置于所述衬底基板101上的栅极102和公共走线103、覆盖所述栅极102和所述公共走线103的栅极绝缘层104、设置于所述栅极绝缘层104上的半导体层105、设置于所述半导体层105上的源漏电极106、以及设置于所述源漏电极106上的第二钝化层107。其中，所述栅极102与所述扫描线S电性连接，并接收所述扫描线S提供的扫描信号；所述公共走线103电性连接至一个恒定电压供应端，用于传输该恒定电压供应端提供的恒定电压信号；所述半导体层105的相对两端形成源极掺杂区和漏极掺杂区；所述源漏电极106包括源极和漏极，所述源极对应所述半导体层105的源极掺杂区设置，所述漏极对应所述半导体层105的漏极掺杂区设置；所述栅极绝缘层104和所述第二钝化层107均可以采用无机绝缘材料制作而成。所述栅极102、所述半导体层105和所述源漏电极106构成所述薄膜晶体管T。
所述色阻层包括多个设置于所述第二钝化层107上的色阻108，每个所述色阻108对应一个所述像素单元11。可选地，多个所述色阻108包括红色阻、绿色阻、蓝色阻和白色阻。
所述第一钝化层109覆盖所述色阻层中的多个色阻108，所述第一钝化层109可以采用无机绝缘材料制作。
所述公共电极层包括设置于所述第一钝化层109上的透明电极110，并且所述透明电极110与所述公共走线103电性连接，所述公共走线103向所述透明电极110提供恒定电压信号。
具体地，所述显示面板还包括连接电极113，所述透明电极110通过所述连接电极113与所述公共走线103保持电性连接。
进一步地，所述连接电极113的一端通过所述绝缘层111上的过孔与所述透明电极110电性连接，所述连接电极113的另一端通过所述栅极绝缘层104、所述第一钝化层109和所述绝缘层111上的过孔与所述公共走线103电性连接，从而形成所述透明电极110与所述公共走线103的电性连接。
所述透明电极110对应所述显示面板10的显示区AA设置，且至少覆盖一个所述像素单元11。可选地，所述透明电极110可以选自氧化铟锡电极等透明电极，从而使所述透明电极110具有光线透过性。
本实施例将设置于所述公共电极层的透明电极110设置为具有透光性，使得位于显示面板10的显示区AA内的透明电极110不会对光线穿过显示面板10内部产生不利影响。
所述像素电极层包括像素电极112，所述像素电极112设置于所述绝缘层111上，且与所述透明电极110保持电性绝缘。所述像素电极112通过所述绝缘层111、所述第一钝化层109和所述第二钝化层107上的过孔与所述源漏电极106保持电性连接，以接收所述数据线D通过所述薄膜晶体管T传输的数据信号。
进一步地，所述像素电极112的至少部分区域在所述公共电极层上的正投影与所述透明电极110的至少部分区域重合。所述像素电极112与所述透明电极110形成存储电容，由于所述透明电极110的电压恒定，所述像素电极112被充电时，该存储电容会存储一部分电量，从而在一定时间内维持像素电极112的电压状态，防止显示面板10在低频显示模式时因像素电极112漏电而导致其电压偏低，进而缓解显示面板10在高低频切换时出现闪烁的问题，有利于提升显示面板10的显示品质。
所述像素电极112对应所述显示面板10的显示区设置，且所述显示面板10包括多个所述像素电极112，每个所述像素电极112对应一个所述像素单元11设置。可选地，所述像素电极112为氧化铟锡电极。
请进一步参阅图6，图6是本申请实施例提供的第二种显示面板包括对置基板和液晶层的膜层结构示意图。所述显示面板10还包括设置于所述像素电极112上的液晶层114、以及设置于所述液晶层114上的对置基板115。所述液晶层114中设置有液晶，所述对置基板115中设置有对置电极，所述对置电极具有恒定电压。所述液晶在所述像素电极112和所述对置电极形成的电场作用下产生特定角度的偏转，从而使所述显示面板10呈现多种显示灰阶。
可选地，所述对置电极设置于所述对置基板115的靠近所述液晶层114的一侧；所述像素电极112与所述液晶层114之间还可以设置有一层绝缘材料，以保持所述像素电极112与所述液晶之间的电性绝缘。
综上所述，本申请实施例提供的显示面板包括驱动电路层、设置于所述驱动电路层上的色阻层、设置于所述色阻层上的公共电极层、以及设置于所述公共电极层上的像素电极层，所述驱动电路层设置有公共走线，所述公共电极层设置有透明电极，所述透明电极与所述公共走线电性连接，所述像素电极层设置有像素电极。本申请实施例通过在色阻层与像素电极层之间设置透明电极，使透明电极与像素电极形成存储电容，从而在显示面板处于低频显示时维持像素电极的电压状态，有效缓解像素电极漏电的问题，提升显示面板的显示品质，并且透明电极允许光线穿过而不会对显示面板的显示效果产生不利影响。
本申请另一实施例还提供一种显示面板制作方法，该显示面板制作方法包括在显示面板的色阻层上形成透明电极，并使透明电极与像素电极形成存储电容的步骤，该方法可以缓解制作的显示面板的像素电极出现漏电问题，而且工艺简单，易于实现。
下面结合具体实施例对本申请提供的显示面板制作方法进行说明。
在一种实施例中，请参阅图7至图10，所述显示面板的制作方法包括以下步骤：
步骤S101，制作包括公共走线103的驱动电路层。具体地，所述驱动电路层制作于一衬底基板101上，所述驱动电路层包括：设置于所述衬底基板101上的栅极102和所述公共走线103、覆盖所述栅极102和所述公共走线103的栅极绝缘层104、设置于所述栅极绝缘层104上的半导体层105、设置于所述半导体层105上的源漏电极106、以及设置于所述源漏电极106上的第二钝化层107。所述公共走线103电性连接至一个恒定电压供应端，用于传输该恒定电压供应端提供的恒定电压信号。
步骤S102，在所述驱动电路层上制作包括多个色阻108的色阻层。具体地，所述色阻层中的多个所述色阻108是通过涂布并图案化的工艺形成。多个所述色阻108可以包括红色阻、绿色阻、蓝色阻和白色阻。
步骤S103，在所述色阻层上制作包括透明电极110的公共电极层，所述透明电极110与所述公共走线103电性连接。
具体地，所述步骤S103还包括：通过刻蚀工艺，在所述第二钝化层107、所述栅极绝缘层104和所述色阻层上形成过孔。制作所述透明电极110的方法可以是物理气相沉积法；制作所述透明电极110过程中，将形成的所述透明电极110通过所述第二钝化层107、所述栅极绝缘层104和所述色阻层上的过孔与所述公共走线103形成电性连接。
可选地，所述透明电极110可以选自氧化铟锡电极等透明电极，从而使所述透明电极110具有光线透过性。
步骤S104，在所述公共电极层上制作绝缘层111。具体地，所述绝缘层111可以是通过气相沉积工艺形成的氮化硅或氧化硅膜层。所述绝缘层111覆盖所述透明电极110及所述色阻108。
所述步骤S104之后，所述显示面板制作方法还包括通过曝光、显影、刻蚀等工艺在所述绝缘层111、所述第二钝化层107和所述色阻层上形成过孔，使得所述源漏电极106的其中一者通过所述绝缘层111、所述第二钝化层107和所述色阻层上的过孔暴露。
步骤S105，在所述绝缘层111上制作包括像素电极112的像素电极层。具体地，所述像素电极112可以是通过图案化沉积工艺形成的氧化铟锡膜层，还可以是将制作的像素电极层通过图案化工艺处理形成的氧化铟锡膜层，并且形成的所述像素电极112通过所述绝缘层111和所述第二钝化层107上的过孔与所述源漏电极106电性连接。
进一步地，所述显示面板制作方法还包括：在所述像素电极层上制作包含液晶的液晶层114，并在所述液晶层114远离所述像素电极层的一侧设置对置基板115，所述对置基板115包括对置电极。所述液晶在所述像素电极112和所述对置电极形成的电场作用下产生特定角度的偏转，从而使制得的显示面板呈现多种显示灰阶。
可选地，所述显示面板制作方法还包括：在所述像素电极112上制作一层绝缘材料，以保证所述像素电极112与后面制作的液晶之间电性绝缘。
在另一种实施例中，请参阅图11至图14，所述显示面板的制作方法包括以下步骤：
步骤S101，制作包括公共走线103的驱动电路层。具体地，所述驱动电路层制作于所述衬底基板101上，所述驱动电路层包括：设置于所述衬底基板101上的栅极102和所述公共走线103、覆盖所述栅极102和所述公共走线103的栅极绝缘层104、设置于所述栅极绝缘层104上的半导体层105、设置于所述半导体层105上的源漏电极106、以及设置于所述源漏电极106上的第二钝化层107。所述公共走线103电性连接至一个恒定电压供应端，用于传输该恒定电压供应端提供的恒定电压信号。
步骤S102，在所述驱动电路层上制作包括多个色阻108的色阻层。具体地，所述色阻层中的多个所述色阻108是通过涂布并图案化的工艺形成。多个所述色阻108可以包括红色阻、绿色阻、蓝色阻和白色阻。
进一步地，所述步骤S102还包括：在所述色阻层上制作第一钝化层109，使所述第一钝化层109覆盖所述色阻层中的多个色阻108。所述第一钝化层109可以是通过气相沉积工艺制作的无机绝缘层。
步骤S103，在所述第一钝化层109上制作包括透明电极110的公共电极层。具体地，所述透明电极110可以通过图案化沉积工艺制作而成。
可选地，所述透明电极110可以选自氧化铟锡电极等透明电极，从而使所述透明电极110具有光线透过性。
步骤S104，在所述公共电极层上制作绝缘层111。
可选地，所述绝缘层111可以是通过气相沉积工艺形成的氮化硅或氧化硅膜层。所述绝缘层111覆盖所述透明电极110。
进一步地，所述步骤S104之后还包括：
通过曝光、显影、刻蚀等工艺，在所述绝缘层111、所述第一钝化层109、所述第二钝化层107和所述色阻层上形成过孔，使得所述源漏电极106通过所述绝缘层111、所述第一钝化层109、所述第二钝化层107和所述色阻层上的过孔暴露；并在所述绝缘层111上形成过孔，使得所述透明电极110通过所述绝缘层111上的过孔暴露；并在所述绝缘层111、所述第一钝化层109、所述第二钝化层107、所述栅极绝缘层104和所述色阻层上形成过孔，使得所述公共走线103通过所述绝缘层111、所述第一钝化层109、所述第二钝化层107、所述栅极绝缘层104和所述色阻层上的过孔暴露。其中，上述过孔可以通过同一工艺制作而成。
步骤S105，在所述绝缘层111上制作包括像素电极112的像素电极层。
具体地，所述步骤S105包括：在所述绝缘层111上制作所述像素电极112和连接电极113，使所述连接电极113的一端通过所述绝缘层111上的过孔与所述透明电极110电性连接，所述连接电极113的另一端通过所述绝缘层111、所述第一钝化层109、所述第二钝化层107和所述栅极绝缘层104上的过孔与所述公共走线103电性连接。
所述像素电极112和所述连接电极113可以是通过图案化沉积工艺形成的氧化铟锡膜层，还可以是将制作的像素电极层通过图案化工艺处理形成的氧化铟锡膜层，并且形成的所述像素电极112通过所述绝缘层111、所述第一钝化层109和所述第二钝化层107上的过孔与所述源漏电极106电性连接。
进一步地，所述显示面板制作方法还包括：在所述像素电极层上制作包含液晶的液晶层114，并在所述液晶层114远离所述像素电极层的一侧设置对置基板115，所述对置基板115包括对置电极。所述液晶在所述像素电极112和所述对置电极形成的电场作用下产生特定角度的偏转，从而使制得的显示面板呈现多种显示灰阶。
可选地，所述显示面板制作方法还包括：在所述像素电极112上制作一层绝缘材料，以保证所述像素电极112与后面制作的液晶之间电性绝缘。
综上所述，本申请实施例提供的该显示面板制作方法包括在显示面板的色阻层上形成透明电极，并使透明电极与像素电极形成存储电容的步骤，该方法可以缓解制作的显示面板的像素电极出现漏电问题，而且工艺简单，易于实现。
需要说明的是，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，包括：
    驱动电路层，所述驱动电路层包括公共走线；
    色阻层，设置于所述驱动电路层上，所述色阻层包括多个色阻；
    公共电极层，设置于所述色阻层上，所述公共电极层包括透明电极，所述透明电极与所述公共走线电性连接；
    绝缘层，设置于所述公共电极层上；
    像素电极层，设置于所述绝缘层上，所述像素电极层包括像素电极。
  2. 根据权利要求1所述的显示面板，其中，所述像素电极的至少部分区域在所述公共电极层上的正投影与所述透明电极的至少部分区域重合。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板具有显示区，所述透明电极对应所述显示区设置。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板还包括设置于所述色阻层与所述公共电极层之间的第一钝化层。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括连接电极，所述连接电极的一端通过所述绝缘层上的过孔与所述透明电极电性连接，所述连接电极的另一端通过所述第一钝化层和所述绝缘层上的过孔与所述公共走线电性连接。
  6. 根据权利要求1所述的显示面板，其中，所述驱动电路层包括：栅极、设置于所述栅极上的栅极绝缘层、设置于所述栅极绝缘层上的半导体层、设置于所述半导体层上的源漏电极、以及设置于所述源漏电极上的第二钝化层。
  7. 根据权利要求6所述的显示面板，其中，所述栅极与所述公共走线同层设置，所述像素电极与所述源漏电极的其中一者电性连接。
  8. 根据权利要求6所述的显示面板，其中，所述透明电极通过相邻两个所述色阻之间的间隙、以及所述第二钝化层和所述栅极绝缘层上的过孔与所述公共走线电性连接。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多条扫描线、多条数据线、以及多个薄膜晶体管。
  10. 根据权利要求1所述的显示面板，其中，所述色阻包括红色阻、绿色阻、蓝色阻和白色阻。
  11. 根据权利要求1所述的显示面板，其中，所述透明电极包括氧化铟锡电极。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板还包括设置于所述像素电极层上的液晶层、以及设置于所述液晶层上的对置基板。
  13. 一种显示面板制作方法，其中，包括：
    制作包括公共走线的驱动电路层；
    在所述驱动电路层上制作包括多个色阻的色阻层；
    在所述色阻层上制作包括透明电极的公共电极层，所述透明电极与所述公共走线电性连接；
    在所述公共电极层上制作绝缘层；
    在所述绝缘层上制作包括像素电极的像素电极层。
  14. 根据权利要求13所述显示面板制作方法，其中，所述在所述色阻层上制作包括透明电极的公共电极层的步骤，还包括：
    在所述色阻层上制作第一钝化层，在所述第一钝化层上制作所述公共电极层，图案化所述公共电极层形成所述透明电极。
  15. 根据权利要求14所述显示面板制作方法，其中，所述在所述公共电极层上制作绝缘层的步骤之后，还包括：
    在所述绝缘层、所述第一钝化层和所述色阻层上形成过孔，使所述透明电极的部分区域和所述公共走线的部分区域通过所述绝缘层、所述第一钝化层和所述色阻层上过孔暴露，并使所述源漏电极的其中一者通过所述绝缘层、所述第一钝化层和所述色阻层上过孔暴露。
  16. 根据权利要求15所述显示面板制作方法，其中，所述在所述绝缘层上制作包括像素电极的像素电极层的步骤，包括：
    在所述绝缘层上制作像素电极层，并图案化所述像素电极层形成所述像素电极和连接电极，所述连接电极的一端通过所述绝缘层上的过孔与所述透明电极电性连接，所述连接电极的另一端通过所述第一钝化层和所述绝缘层上的过孔与所述公共走线电性连接。
  17. 根据权利要求13所述显示面板制作方法，其中，所述制作包括公共走线的驱动电路层的步骤，包括：
    在一衬底基板上制作所述驱动电路层，所述驱动电路层包括：设置于所述衬底基板上的栅极和所述公共走线、覆盖所述栅极和所述公共走线的栅极绝缘层、设置于所述栅极绝缘层上的半导体层、设置于所述半导体层上的源漏电极、以及设置于所述源漏电极上的第二钝化层。
  18. 根据权利要求13所述显示面板制作方法，其中，所述在所述驱动电路层上制作包括多个色阻的色阻层的步骤，包括：
    在所述驱动电路层上制作包括红色阻、绿色阻、蓝色阻和白色阻的所述色阻层。
  19. 根据权利要求13所述显示面板制作方法，其中，所述在所述色阻层上制作包括透明电极的公共电极层的步骤，包括：
    在所述色阻层上制作包括氧化铟锡电极的公共电极层，所述氧化铟锡电极与所述公共走线电性连接。
  20. 一种显示面板，其中，包括：
    驱动电路层，所述驱动电路层包括栅极、设置于所述栅极上的栅极绝缘层、设置于所述栅极绝缘层上的半导体层、设置于所述半导体层上的源漏电极、设置于所述源漏电极上的第二钝化层、以及与所述栅极同层设置的公共走线；
    色阻层，设置于所述驱动电路层上，所述色阻层包括多个色阻；
    公共电极层，设置于所述色阻层上，所述公共电极层包括透明电极，所述透明电极通过相邻两个所述色阻之间的间隙、以及所述第二钝化层和所述栅极绝缘层上的过孔与所述公共走线电性连接；
    绝缘层，设置于所述公共电极层上；
    像素电极层，设置于所述绝缘层上，所述像素电极层包括像素电极。
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