WO2023015586A1 - 半导体结构的制备方法及半导体结构 - Google Patents

半导体结构的制备方法及半导体结构 Download PDF

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Publication number
WO2023015586A1
WO2023015586A1 PCT/CN2021/113310 CN2021113310W WO2023015586A1 WO 2023015586 A1 WO2023015586 A1 WO 2023015586A1 CN 2021113310 W CN2021113310 W CN 2021113310W WO 2023015586 A1 WO2023015586 A1 WO 2023015586A1
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substrate
layer
top surface
semiconductor structure
active
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PCT/CN2021/113310
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English (en)
French (fr)
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王晓玲
洪海涵
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长鑫存储技术有限公司
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Priority to US17/453,046 priority Critical patent/US20230049203A1/en
Publication of WO2023015586A1 publication Critical patent/WO2023015586A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

Definitions

  • the present disclosure relates to but is not limited to a method for preparing a semiconductor structure and the semiconductor structure.
  • Dynamic Random Access Memory is small in size, highly integrated, low in power consumption, and faster than all read-only memories (ROM, Read Only Memory).
  • ROM Read Only Memory
  • optimizing integration is one of the main goals of circuit design.
  • the size of transistors is getting smaller and smaller, and its gate control ability is weakened. become more and more apparent, thereby degrading the performance of the semiconductor structure.
  • the disclosure provides a method for preparing a semiconductor structure and the semiconductor structure.
  • the first aspect of the embodiments of the present disclosure provides a method for preparing a semiconductor structure, the method for preparing the semiconductor structure includes:
  • Active pillars are formed on the substrate, the active pillars are arranged in an array, the vertical section is taken as a plane perpendicular to the substrate, and the projection shape of the active pillars on the longitudinal section includes ten Font;
  • first oxide layer covering the top surface of the substrate and the sidewalls and top surfaces of the active pillars on the substrate, wherein filling regions are formed between adjacent active pillars in the same row ;
  • Capacitive structures are formed on the contact layer.
  • the second aspect of the embodiments of the present disclosure provides a semiconductor structure prepared by the above method for preparing the semiconductor structure, the semiconductor structure comprising:
  • Active columns are arranged in an array on the substrate, take a plane perpendicular to the substrate as a longitudinal section, and the projection shape of the active columns on the longitudinal section includes a cross shape.
  • the specific surface area of the gate structure is increased, thereby effectively improving the gate control capability and performance of the semiconductor structure.
  • Fig. 1 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a schematic diagram of forming a first groove in a substrate in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 3 is a schematic diagram of forming an insulating dielectric layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 4 is a schematic diagram of forming a bit line in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram of forming a first dielectric layer, a first photoresist layer and a second photoresist layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 6 is a schematic diagram of forming a second groove in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 7 is a schematic diagram of forming silicon pillars in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 8 is a schematic diagram of forming an active pillar in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 9 is a schematic diagram of forming a first oxide layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 10 is a schematic diagram of forming a word line in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 11 is a schematic diagram of forming a dielectric layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 12 is a schematic diagram of removing a part of the dielectric layer and a part of the first oxide layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 13 is a schematic diagram of forming an initial metal layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 14 is a schematic diagram of forming a contact layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 15 is a schematic diagram of forming a capacitor structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 16 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • the first photoresist layer 60.
  • the second photoresist layer 60.
  • Capacitor structure 601. Mask plate;
  • the size of the transistor is getting smaller and smaller, its gate control ability is weakened, and the short channel effect is becoming more and more obvious, which in turn reduces the performance of the semiconductor structure.
  • the method for preparing a semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure can effectively improve the gate control capability of the semiconductor structure by increasing the surface area of the active pillar, thereby increasing the specific surface area of the gate structure. and performance.
  • FIG. 1 is a flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Fig. 2- Fig. 15 are schematic diagrams of various stages in the method for preparing a semiconductor structure, and the method for preparing a semiconductor structure will be described in detail below in conjunction with Fig. 2- Fig. 15 introduction.
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM). However, this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • a method for preparing a semiconductor structure includes the following steps:
  • Step S100 providing a substrate.
  • Step S110 forming active pillars on the substrate, the active pillars are arranged in an array, the vertical section is taken as a plane perpendicular to the substrate, and the projection shape of the active pillars on the longitudinal section includes a cross shape.
  • Step S120 forming a first oxide layer covering the top surface of the substrate and the sidewalls and top surfaces of the active pillars on the substrate, wherein filling regions are formed between adjacent active pillars in the same row.
  • Step S130 sequentially forming a word line and a dielectric layer in the filling area.
  • Step S140 removing part of the first oxide layer and part of the dielectric layer to expose the top surface of the active pillar.
  • Step S150 forming a contact layer on the top surface of the active pillar.
  • Step S160 forming a capacitor structure on the contact layer.
  • the substrate 10 is used as a supporting component of the reservoir for supporting other components disposed thereon.
  • the substrate 10 can be made of semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compound and silicon-carbon compound.
  • the first dielectric layer 40 may include a silicon oxide layer and a silicon nitride layer, and the sensitivity of the first photoresist layer 50 is higher than that of the second photoresist layer 60 .
  • the second groove 70 As shown in FIG. 6, part of the second photoresist layer 60, the first photoresist layer 50 and the first dielectric layer 40 are removed to form a second groove 70, wherein the bottom of the second groove 70 exposes the substrate The top surface of the bottom 10. Taking a plane perpendicular to the substrate 10 as a longitudinal section, the formed second groove 70 has a projection shape on the longitudinal section including a cross.
  • a silicon pillar 80 is formed in the second groove 70 , wherein the top surface of the silicon pillar 80 is flush with the top surface of the second photoresist layer 60 .
  • the silicon column 80 may be formed by silicon epitaxial growth along the inner wall of the cross-shaped longitudinal section of the second groove 70, and the outer layer of the silicon column 80 forms a cross-shaped structure along the inner wall of the cross, so that The surface area of the subsequently formed active pillar 90 is effectively increased, thereby increasing the specific surface area of the subsequently formed gate structure, and improving the gate control capability and performance of the semiconductor structure.
  • the top surface of the silicon pillar 80 is ion-doped by ion implantation technology to form the active pillar 90 .
  • the dopant ions include one of nitrogen ions, phosphorus ions, boron ions or germanium ions.
  • the remaining second photoresist layer 60 , first photoresist layer 50 and first dielectric layer 40 are removed by plasma etching.
  • the etching gas includes at least one of oxygen, helium, argon, nitrogen and nitrogen tetrafluoride.
  • a layer of first oxide layer 100 is formed on the top surface and sidewall of the active pillar 90 and the top surface of the substrate 10 by atomic layer deposition process.
  • the first oxide layer includes a silicon dioxide layer.
  • Filling regions 904 are formed between adjacent active pillars 90 covered with the first oxide layer 100 .
  • word lines 110 are formed in the filling region 904 .
  • the word line 110 is a metal layer, and the metal layer includes at least one of a tungsten layer, a copper layer or a titanium nitride layer.
  • the top surface of the formed word line 110 is lower than the top surface of the active pillar 90 .
  • a dielectric layer 120 is formed on the word line 110 , and the dielectric layer 120 covers the top surface of the word line 110 and the top surface and sidewalls of the first oxide layer 100 .
  • the material of the dielectric layer 120 includes materials such as silicon dioxide.
  • step S140 as shown in FIG. 12 , part of the first oxide layer 100 and part of the dielectric layer 120 may be removed by chemical mechanical polishing, and the top surface of the active pillar 90 may be exposed.
  • step S150 a physical vapor deposition process is used to form an initial metal layer 131 on the top surface of the remaining dielectric layer 120 and the top surface of the active pillar 90 .
  • Part of the initial metal layer 131 is removed, and the corresponding initial metal layer 131 on the top surface of the active pillar 90 remains, so as to form the metal layer 130 .
  • the metal layer 130 is tempered at a high temperature to form a metal silicide, that is, the contact layer 140 .
  • the metal layer 130 includes at least one of a cobalt layer, a nickel layer or a platinum layer.
  • the contact layer 140 includes at least one of cobalt compound, nickel compound, or platinum compound.
  • a capacitive structure 150 is formed on the contact layer 140 , wherein the capacitive structure 150 may include a columnar capacitive structure, a cup capacitive structure or a trench capacitive structure.
  • the specific surface area of the gate structure is increased by increasing the surface area of the active pillar, thereby effectively improving the gate control capability and performance of the semiconductor structure.
  • this embodiment is an illustration of the implementation of forming the second groove 70 in step S110 of the above-mentioned embodiment.
  • Step S111 removing part of the second photoresist layer by plasma etching process, and the remaining second photoresist layer forms the upper groove.
  • a mask plate 601 with openings is provided on the second photoresist layer 60 , and a mask pattern is formed on the second photoresist layer 60 by exposure or development and etching.
  • the second photoresist layer 60 exposed in the mask pattern is etched, and the efficiency is retained.
  • the second photoresist layer 60 forms an upper groove 701 .
  • the etching gas includes at least one of oxygen, helium, argon, nitrogen and carbon tetrafluoride.
  • Step S112 removing part of the first photoresist layer, and the remaining first photoresist layer forms a middle groove.
  • the first photoresist layer 50 is continuously etched by the above-mentioned etching gas, and the remaining first photoresist layer 50 forms a middle groove 702 .
  • the first photoresist layer 50 and the second photoresist layer 60 are affected by the above-mentioned etching gas.
  • the etched area in the first photoresist layer 50 is larger than the etched area in the second photoresist layer 60 . That is, taking a plane perpendicular to the substrate as a longitudinal section, the length of the etched region in the first photoresist layer 50 is greater than the length of the etched region in the second photoresist layer 60 .
  • Step S113 removing part of the first dielectric layer, the remaining first dielectric layer forms a lower groove, and the bottom surface of the lower groove exposes the top surface of the bit line.
  • the first dielectric layer 40 is continuously etched by the above-mentioned etching gas, and the remaining first dielectric layer 40 forms a lower groove 703 .
  • the length of the etched region in the first dielectric layer 40 is equal to the length of the etched region in the second photoresist layer 60 .
  • the upper groove 701 , the middle groove 702 and the lower groove 703 are sequentially connected to form the second groove 70 .
  • the projected area of the middle groove 702 on the substrate 10 is larger than the projected area of the upper groove 701 on the substrate 10, and the projected area of the middle groove 702 on the substrate 10 is larger than that of the lower groove 703 on the substrate 10 shadow area.
  • the projection shape of the second groove 70 on the longitudinal section perpendicular to the plane of the substrate 10 forms a cross shape, so as to effectively increase the surface area of the subsequently formed active column, thereby increasing the controllability of the gate of the semiconductor structure, and improving Properties of semiconductor structures.
  • FIG. 16 shows a flowchart of a method for fabricating a semiconductor structure provided according to this embodiment, which includes:
  • Step S200 providing a substrate.
  • Step S210 forming bit lines in the substrate, the bit lines are arranged at intervals in the substrate along the row direction of the active pillars, wherein the top surface of the bit lines is flush with the top surface of the substrate.
  • Step S220 forming active pillars on the substrate, the active pillars are arranged in an array, the vertical section is taken as a plane perpendicular to the substrate, and the projection shape of the active pillars on the longitudinal section includes a cross shape.
  • Step S230 forming a first oxide layer covering the top surface of the substrate and the sidewalls and top surfaces of the active pillars on the substrate, wherein filling regions are formed between adjacent active pillars in the same row.
  • Step S240 sequentially forming a word line and a dielectric layer in the filling area.
  • Step S250 removing part of the first oxide layer and part of the dielectric layer to expose the top surface of the active pillar.
  • Step S260 forming a contact layer on the top surface of the active pillar.
  • Step S270 forming a capacitor structure on the contact layer.
  • bit line in step S210 includes the following steps:
  • Step S211 forming a plurality of first grooves arranged at intervals along the row direction of the active pillars in the substrate.
  • a mask layer may be formed on the substrate 10 through a deposition process, and then patterned to form a plurality of mask openings arranged at intervals along the row direction of the active pillars on the mask layer.
  • a third photoresist layer may be formed on the mask layer, and a mask pattern is formed on the third photoresist layer by exposure or development etching, using the third photoresist layer with the mask pattern as a mask plate, removing part of the mask layer to form a plurality of mask openings arranged at intervals.
  • the mask pattern can be transferred to the mask layer, and then the mask layer can be used as a mask to etch the substrate 10, which can improve the precision of pattern transfer and improve the performance of the semiconductor structure.
  • the substrate 10 exposed in each mask opening is removed by using etching solution or etching gas, so as to form a plurality of first grooves 101 on the substrate 10 .
  • the remaining mask layer on the top surface of the substrate 10 is removed.
  • Step S212 forming an insulating dielectric layer in the first groove, the top surface of the insulating dielectric layer is flush with the top surface of the substrate, wherein the area between adjacent insulating dielectric layers constitutes an active region.
  • an insulating dielectric layer 30 is formed in the first groove 101 by physical vapor deposition, chemical vapor deposition, spin coating or a combination thereof, wherein the top surface of the insulating dielectric layer 30 is in contact with the top surface of the substrate 10 flush.
  • the material forming the insulating dielectric layer 30 can be, for example, silicon oxide, silicon oxynitride, or other suitable insulating substances (such as organic polymer compounds) or a combination of the above materials.
  • the area between adjacent insulating dielectric layers 30 constitutes an active area.
  • Step S213 performing ion doping on the active region by ion implantation technology to form bit lines.
  • dopant ions may be implanted into the active region by ion implantation technology, and the dopant ions include one of nitrogen ions, phosphorus ions, boron ions, or germanium ions to form bit lines 20 .
  • the specific surface area of the gate structure is increased by increasing the surface area of the active pillar, thereby effectively improving the gate control capability and performance of the semiconductor structure.
  • an embodiment of the present disclosure also provides a semiconductor structure, the semiconductor structure includes a substrate 10 and active pillars 90, and the active pillars 90 are arranged in an array on the substrate 10 so as to be perpendicular to the substrate.
  • the plane of 10 is a longitudinal section, and the projection shape of the active column 90 on the longitudinal section includes a cross.
  • the active column 90 includes a first segment 901, a second segment 902 and a third segment 903 connected sequentially, the first segment 901 is connected to the substrate 10, wherein the second segment 902 is connected to the substrate 10
  • the projected area on the substrate 10 is larger than the projected area of the first segment 901 on the substrate 10
  • the projected area of the second segment 902 on the substrate 10 is larger than the projected area of the third segment 903 on the substrate 10 .
  • the projected area of the first segment 901 on the substrate 10 is equal to the projected area of the third segment 903 on the substrate 10; or,
  • the projected area of the first segment 901 on the substrate 10 is larger or smaller than the projected area of the third segment 903 on the substrate 10 .
  • the semiconductor structure further includes bit lines 20 in the substrate 10, the bit lines 20 are arranged at intervals along the row direction of the active pillars 90, that is, the X direction shown in FIG. 15 , the top surface of the bit lines 20 It is connected to the bottom surface of the active pillar 90 .
  • the semiconductor structure further includes word lines 110 arranged at intervals along the column direction of the active pillars 90, and the word lines 110 are connected to the active pillars 90 in the same row, wherein the column direction of the active pillars 90 is the same as that shown in FIG.
  • the X directions of are perpendicular to each other, and the X direction and the column direction are on the same horizontal plane.
  • a contact layer 140 is disposed on the top surface of the active pillar 90 , and the capacitor structure 150 is connected to the contact layer 140 .
  • the shape of the capacitive structure 150 includes a columnar or cylindrical shape, for example, the capacitive structure 150 may include a columnar capacitive structure, a cup-shaped capacitive structure or a trench capacitive structure.
  • the specific surface area of the gate structure is increased, thereby effectively improving the gate control capability and performance of the semiconductor structure.

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Abstract

本公开提供一种半导体结构的制备方法及半导体结构，涉及半导体技术领域，该半导体结构的制备方法包括提供衬底；在衬底上形成阵列排布的有源柱，有源柱的纵截面的投影形状包括十字形；在衬底上形成第一氧化层，同一行中相邻有源柱间形成填充区；在填充区内依次形成字线和介质层；暴露出有源柱的顶面；在有源柱上形成接触层；在接触层上形成电容结构。

Description

半导体结构的制备方法及半导体结构
本公开基于申请号为202110926432.5，申请日为2021年08月12日，申请名称为“半导体结构的制备方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制备方法及半导体结构。
背景技术
动态随机存取存储器(DRAM，Dynamic Random Access Memory)体积小、集成度高、功耗低，同时速度比所有只读存储器(ROM，Read Only Memory)快。随着半导体行业的发展，优化集成度是电路设计的主要目标之一，但伴随着DRAM等器件特征尺寸不断缩放，晶体管的尺寸也越来越小，其栅极控制能力减弱，短沟道效应越来越明显，进而降低了半导体结构的性能。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的制备方法及半导体结构。
本公开实施例的第一方面提供了一种半导体结构的制备方法，所述半导体结构的制备方法包括：
提供衬底；
在所述衬底上形成有源柱，所述有源柱成阵列排布，以垂直于所述衬底的平面为纵截面，所述有源柱在所述纵截面上的投影形状包括十字形；
在所述衬底上形成覆盖所述衬底的顶面和所述有源柱的侧壁和顶面的第一氧化层，其中同一行中相邻的所述有源柱之间形成填充区；
在所述填充区内依次形成字线和介质层；
去除部分所述第一氧化层和部分所述介质层，暴露出所述有源柱的顶面；
在所述有源柱的顶面上形成接触层；
在所述接触层上形成电容结构。
本公开实施例的第二方面提供了一种半导体结构，通过上述半导体结构的制备方法制备得到，所述半导体结构包括：
衬底；
有源柱，所述有源柱成阵列排布在所述衬底上，以垂直于衬底的平面为纵截面，所述有源柱在所述纵截面上的投影形状包括十字形。
本公开实施例所提供的半导体结构的制备方法及半导体结构中，通过增大有源柱的表面积，进而增大栅极结构的比表面积，从而有效提高半导体结构的栅极控制能力和性能。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的一种半导体结构的制备方法的流程图。
图2是根据一示例性实施例示出的半导体结构的制备方法中在衬底中形成第一凹槽的示意图。
图3是根据一示例性实施例示出的半导体结构的制备方法中形成绝缘介质层的示意图。
图4是根据一示例性实施例示出的半导体结构的制备方法中形成位线 的示意图。
图5是根据一示例性实施例示出的半导体结构的制备方法中形成第一介质层、第一光刻胶层和第二光刻胶层的示意图。
图6是根据一示例性实施例示出的半导体结构的制备方法中形成第二凹槽的示意图。
图7是根据一示例性实施例示出的半导体结构的制备方法中形成硅柱的示意图。
图8是根据一示例性实施例示出的半导体结构的制备方法中形成有源柱的示意图。
图9是根据一示例性实施例示出的半导体结构的制备方法中形成第一氧化层的示意图。
图10是根据一示例性实施例示出的半导体结构的制备方法中形成字线的示意图。
图11是根据一示例性实施例示出的半导体结构的制备方法中形成介质层的示意图。
图12是根据一示例性实施例示出的半导体结构的制备方法中去除部分介质层和部分第一氧化层的示意图。
图13是根据一示例性实施例示出的半导体结构的制备方法中形成初始金属层的示意图。
图14是根据一示例性实施例示出的半导体结构的制备方法中形成接触层的示意图。
图15是根据一示例性实施例示出的半导体结构的制备方法中形成电容结构的示意图。
图16是根据一示例性实施例示出的一种半导体结构的制备方法的流程图。
附图说明：
10、衬底；                  20、位线；
30、绝缘介质层；            40、第一介质层；
50、第一光刻胶层；          60、第二光刻胶层；
70、第二凹槽；                80、硅柱；
90、有源柱；                  100、第一氧化层；
110、字线；                   101、第一凹槽；
120、介质层；                 130、金属层；
131、初始金属层；             140、接触层；
150、电容结构；               601、掩膜版；
701、上部凹槽；               702、中间凹槽；
703、下部凹槽；               901、第一段；
902、第二段；                 903、第三段；
904、填充区。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在半导体结构中，伴随着DRAM等器件特征尺寸不断减放，晶体管的尺寸也越来越小，其栅极控制能力减弱，短沟道效应越来越明显，进而降低了半导体结构的性能。
针对上述的技术问题，本公开实施例提供的半导体结构的制备方法及半导体结构，通过增大有源柱的表面积，进而增大栅极结构的比表面积，从而有效提高半导体结构的栅极控制能力和性能。
图1是本公开实施例提供的半导体结构的制备方法的流程图，图2-图15为半导体结构的制备方法中各个阶段的示意图，下面结合图2-图15对半导体结构的制备方法进行详细的介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导 体结构还可以为其他的结构。
如图2所示，本公开实施例提供的一种半导体结构的制备方法，包括以下的步骤：
步骤S100：提供衬底。
步骤S110：在衬底上形成有源柱，有源柱成阵列排布，以垂直于衬底的平面为纵截面，有源柱在纵截面上的投影形状包括十字形。
步骤S120：在衬底上形成覆盖衬底的顶面和有源柱的侧壁和顶面的第一氧化层，其中，同一行中相邻的所述有源柱之间形成填充区。
步骤S130：在填充区内依次形成字线和介质层。
步骤S140：去除部分第一氧化层和部分介质层，暴露出有源柱的顶面。
步骤S150：在有源柱的顶面上形成接触层。
步骤S160：在接触层上形成电容结构。
示例性地，在步骤S100中，如图2所示，衬底10作为储存器的支撑部件，用于支撑设在其上的其他部件。衬底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
示例性地，在步骤S110中，如图5所示，可以通过原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺在衬底10上形成依次层叠设置的第一介质层40、第一光刻胶层50和第二光刻胶层60。其中，第一介质层40可以包括硅氧化物层和硅氮化物层，且第一光刻胶层50的感光度高于第二光刻胶层60的感光度。
如图6所示，去除部分第二光刻胶层60、第一光刻胶层50和第一介质层40，以形成第二凹槽70，其中，第二凹槽70的底部暴露出衬底10的顶面。以垂直于衬底10的平面为纵截面，则形成的第二凹槽70在纵截面上的投影形状包括十字形。
示例性地，如图7所示，在第二凹槽70内形成硅柱80，其中，硅柱80的顶面与第二光刻胶层60的顶面平齐。在一些实施例中，可以沿第二凹槽70的纵截面形成为十字形的内壁通过硅外延生长形成硅柱80，硅柱80的外 表层顺着十字形的内壁形成十字形的结构，以有效增大后续形成的有源柱90的表面积，进而增大后续所形成的栅极结构的比表面积，提高半导体结构的栅极控制能力和性能。
如图8所示，通过离子注入技术对硅柱80的顶面进行离子掺杂，以形成有源柱90。掺杂离子包括氮离子、磷离子、硼离子或锗离子等其中的一种。
参照图6，通过等离子体刻蚀去除被保留下来的第二光刻胶层60、第一光刻胶层50和第一介质层40。刻蚀气体包括氧气、氦气、氩气、氮气和四氟化氮中的至少一种。
示例性地，在步骤S120中，如图9所示，通过原子层沉积工艺在有源柱90的顶面和侧壁以及衬底10的顶面上形成一层第一氧化层100。第一氧化层包括二氧化硅层。相邻的覆盖有第一氧化层100的有源柱90之间形成填充区904。
示例性地，在步骤S130中，如图10所示，在填充区904内形成字线110。其中，字线110为一层金属层，该金属层的包括钨层、铜层或氮化钛层中的至少一种。形成的字线110的顶面低于有源柱90的顶面。
如图11所示，在字线110上形成介质层120，介质层120覆盖在字线110的顶面以及第一氧化层100的顶面和侧壁上。介质层120的材质包括二氧化硅等材质。
示例性地，在步骤S140中，如图12所示，可以通过化学机械研磨去除部分第一氧化层100和部分介质层120，并暴露出有源柱90的顶面。
示例性地，在步骤S150中，如图13所示，采用物理气相沉积工艺在被保留下来的介质层120的顶面上和有源柱90的顶面上形成初始金属层131。
去除部分初始金属层131，保留位于有源柱90顶面上对应的初始金属层131，以形成金属层130。
如图14所示，对金属层130进行高温回火，以形成金属硅化物，即接触层140。其中，金属层130包括钴层、镍层或铂层中的至少一种。接触层140包括钴化物、镍化物或铂化合物中的至少一种。
示例性地，在步骤S160中，如图15所示，在接触层140上形成电容结构150，其中，电容结构150可以包括柱状电容结构、杯状电容结构或沟槽 式电容结构。
本公开实施例提供的半导体结构的制备方法中，通过增大有源柱的表面积，进而增大栅极结构的比表面积，从而有效提高半导体结构的栅极控制能力和性能。
根据一个示例性实施例，如图6和图7所示，本实施例是对上述实施例步骤S110中形成第二凹槽70的实施方式的说明。
步骤S111：通过等离子体刻蚀工艺去除部分第二光刻胶层，被保留下来的第二光刻胶层形成上部凹槽。
参照图6和图7，在第二光刻胶层60上设置具有开口的掩膜版601，通过曝光或显影刻蚀的方式在第二光刻胶层60上形成掩膜图案。
以第二光刻胶层60上的掩膜图案为掩膜版，采用刻蚀液或者刻蚀气体，对暴露在掩膜图案中的第二光刻胶层60进行刻蚀，被保留效率的第二光刻胶层60形成上部凹槽701。其中，刻蚀气体包括氧气、氦气、氩气、氮气和四氟化碳中的至少一种。
步骤S112：去除部分第一光刻胶层，被保留下来的第一光刻胶层形成中间凹槽。
参照图7，通过上述刻蚀气体继续刻蚀第一光刻胶层50，被保留下来的第一光刻胶层50形成中间凹槽702。需要说明的是，由于第一光刻胶层50的感光度高于第二光刻胶层60的感光度，通过上述刻蚀气体对第一光刻胶层50和第二光刻胶层60进行刻蚀时，会使第一光刻胶层50内刻蚀区域大于在第二光刻胶层60内刻蚀区域。即，以垂直于衬底的平面为纵截面，在第一光刻胶层50内刻蚀区域的长度大于在第二光刻胶层60内刻蚀区域的长度。
步骤S113：去除部分第一介质层，被保留下来的第一介质层形成下部凹槽，下部凹槽的底面暴露出位线的顶面。
参照图7，通过上述刻蚀气体继续刻蚀第一介质层40，被保留下来的第一介质层40形成下部凹槽703。其中，以垂直于衬底的平面为纵截面，在第一介质层40内刻蚀区域的长度等于在第二光刻胶层60内刻蚀区域的长度。
如图7所示，上部凹槽701、中间凹槽702和下部凹槽703顺序连通并形成第二凹槽70。中间凹槽702在衬底10上的投影面积大于上部凹槽701在衬底10上的投影面积，且中间凹槽702在衬底10上的投影面积大于下部凹槽703在衬底10上的投影面积。使得第二凹槽70在以垂直于衬底10的平面的纵截面上的投影形状构成十字形，以有效增加后续形成的有源柱的表面积，进而增加半导体结构的栅极的控制能力，提高半导体结构的性能。
根据一个示例性实施例，如图16所示，图16示出了根据本实施例提供的半导体结构的制备方法的流程图，其包括：
步骤S200：提供衬底。
步骤S210：在衬底内形成位线，位线在衬底内沿有源柱的行方向间隔排布，其中，位线的顶面与衬底的顶面平齐。
步骤S220：在衬底上形成有源柱，有源柱成阵列排布，以垂直于衬底的平面为纵截面，有源柱在纵截面上的投影形状包括十字形。
步骤S230：在衬底上形成覆盖衬底的顶面和有源柱的侧壁和顶面的第一氧化层，其中，同一行中相邻的所述有源柱之间形成填充区。
步骤S240：在填充区内依次形成字线和介质层。
步骤S250：去除部分第一氧化层和部分介质层，暴露出有源柱的顶面。
步骤S260：在有源柱的顶面上形成接触层。
步骤S270：在接触层上形成电容结构。
示例性地，在步骤S210中形成位线包括以下步骤：
步骤S211：在衬底内形成多个沿有源柱的行方向间隔排布的第一凹槽。
参照图2，可以通过沉积工艺在衬底10上形成掩膜层，然后图形化掩膜层，以在掩膜层上形成多个沿有源柱的行方向间隔排布的掩膜开口。
可以在掩膜层上形成第三光刻胶层，通过曝光或显影刻蚀的方式在第三光刻胶层上形成掩膜图案，以具有掩膜图案的第三光刻胶层为掩膜版，去除部分掩膜层，以形成多个间隔设置的掩膜开口。
本实施例中可通过将掩膜图案转移到掩膜层，再以掩膜层作为掩膜版， 刻蚀衬底10，可以提高图案化转移的精度，提高半导体结构的性能。
待形成掩膜开口之后，采用刻蚀液或者刻蚀气体，去除暴露在每个掩膜开口内的衬底10，以在衬底10上形成多个第一凹槽101。
在形成多个第一凹槽101之后，去除衬底10顶面上被保留下来的掩膜层。
步骤S212：在第一凹槽内形成绝缘介质层，绝缘介质层的顶面与衬底的顶面平齐，其中，相邻的绝缘介质层之间的区域构成有源区。
如图3所示，通过物理气相沉积、化学气相沉积、旋涂法或其组合在第一凹槽101内形成绝缘介质层30，其中，绝缘介质层30的顶面与衬底10的顶面平齐。形成绝缘介质层30的材料例如可为：氧化硅、氮氧化硅或者其他适合的绝缘物质(例如有机高分子化合物)或上述材料的组合。相邻的绝缘介质层30之间的区域构成有源区。
步骤S213：通过离子注入技术对有源区进行离子掺杂，以形成位线。
如图4所示，可以通过离子注入技术将掺杂离子注入到有源区中，掺杂离子包括氮离子、磷离子、硼离子或锗离子等其中的一种，从而形成位线20。
本公开实施例提供的半导体结构的制备方法中，通过增大有源柱的表面积，进而增大栅极结构的比表面积，从而有效提高半导体结构的栅极控制能力和性能。
如图16所示，本公开实施例还提供了一种半导体结构，该半导体结构包括衬底10和有源柱90，有源柱90成阵列排布在衬底10上，以垂直于衬底10的平面为纵截面，有源柱90在纵截面上的投影形状包括十字形。
在一些实施例中，有源柱90包括依次顺序连接的第一段901、第二段902和第三段903，第一段901与衬底10连接，其中，第二段902在衬底10上的投影面积大于第一段901在衬底10上的投影面积，第二段902在衬底10上的投影面积大于第三段903在衬底10上的投影面积。通过第一段901、第二段902和第三段903的结构设计，以增加有源柱90的表面积，进而增大栅极结构的比表面积，从而有效提高半导体结构的栅极控 制能力和性能。
在一些实施例中，第一段901在衬底10上的投影面积等于第三段903在衬底10上的投影面积；或者，
第一段901在衬底10上的投影面积大于或小于第三段903在衬底10上的投影面积。
在一些实施例中，半导体结构还包括在衬底10中的位线20，位线20沿有源柱90的行方向间隔设置，即图15中所示的X方向，位线20的顶面与有源柱90的底面连接。
在一些实施例中，半导体结构还包括沿有源柱90的列方向间隔设置的字线110，字线110连接同一行中的有源柱90，其中有源柱90的列方向与图15中的X方向相互垂直，且X方向与列方向处于同一水平面。
在一些实施例中，有源柱90的顶面上设有接触层140，接触层140上连接有电容结构150。其中，电容结构150的形状包括柱状或圆筒状，例如，电容结构150可以包括柱状电容结构、杯状电容结构或沟槽式电容结构。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替 换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的制备方法及半导体结构中，通过增大有源柱的表面积，进而增大栅极结构的比表面积，从而有效提高半导体结构的栅极控制能力和性能。

Claims (16)

  1. 一种半导体结构的制备方法，包括：
    提供衬底；
    在所述衬底上形成有源柱，所述有源柱成阵列排布，以垂直于所述衬底的平面为纵截面，所述有源柱在所述纵截面上的投影形状包括十字形；
    在所述衬底上形成覆盖所述衬底的顶面和所述有源柱的侧壁和顶面的第一氧化层，其中同一行中相邻的所述有源柱之间形成填充区；
    在所述填充区内依次形成字线和介质层；
    去除部分所述第一氧化层和部分所述介质层，暴露出所述有源柱的顶面；
    在所述有源柱的顶面上形成接触层；
    在所述接触层上形成电容结构。
  2. 根据权利要求1所述的半导体结构的制备方法，所述有源柱包括依次顺序连接的第一段、第二段和第三段，所述第一段与所述衬底连接，其中，所述第二段在所述衬底上的投影面积大于所述第一段在所述衬底上的投影面积，所述第二段在所述衬底上的投影面积大于所述第三段在所述衬底上的投影面积。
  3. 根据权利要求1所述的半导体结构的制备方法，所述在提供衬底的步骤之后，在所述衬底上形成有源柱的步骤之前，所述制备方法还包括：
    在所述衬底内形成位线，所述位线在所述衬底内沿所述有源柱的行方向间隔排布，其中所述位线的顶面与所述衬底的顶面平齐。
  4. 根据权利要求3所述的半导体结构的制备方法，所述在所述衬底内形成位线的步骤中，包括：
    在所述衬底内形成沿所述有源柱的行方向间隔排布的第一凹槽；
    在所述第一凹槽内形成绝缘介质层，所述绝缘介质层的顶面与所述 衬底的顶面平齐，其中，相邻的所述绝缘介质层之间的区域构成有源区；
    通过离子注入技术对所述有源区进行离子掺杂，以形成所述位线。
  5. 根据权利要求4所述的半导体结构的制备方法，所述在所述衬底上形成多个有源柱的步骤中，包括：
    在所述衬底上依次形成层叠设置的第一介质层、第一光刻胶层和第二光刻胶层，其中，所述第一光刻胶层的感光度高于所述第二光刻胶层的感光度；
    去除部分所述第二光刻胶层、部分所述第一光刻胶层和部分所述第一介质层，被保留下来的所述第二光刻胶层、所述第一光刻胶层和所述第一介质层形成间隔设置的第二凹槽，每个所述第二凹槽暴露出所述位线的顶面；
    在所述第二凹槽内形成有源柱，其中，所述有源柱的顶面与所述第二光刻胶层的顶面平齐。
  6. 根据权利要求5所述的半导体结构的制备方法，去除部分所述第二光刻胶层、部分所述第一光刻胶层和部分所述第一介质层，被保留下来的所述第二光刻胶层、所述第一光刻胶层和所述第一介质层形成间隔设置的第二凹槽，所述第二凹槽暴露出所述位线的顶面的步骤中，包括：
    通过等离子体刻蚀工艺去除部分所述第二光刻胶层，被保留下来的所述第二光刻胶层形成上部凹槽；
    去除部分所述第一光刻胶层，被保留下来的所述第一光刻胶层形成中间凹槽；
    去除部分所述第一介质层，被保留下来的所述第一介质层形成下部凹槽，所述下部凹槽的底面暴露出所述位线的顶面；
    其中，所述上部凹槽、所述中间凹槽和所述下部凹槽依次顺序连通，并形成所述第二凹槽，所述中间凹槽在所述衬底上的投影面积大于所述上部凹槽在所述衬底上的投影面积，且所述中间凹槽在所述衬底上的投影面积大于所述下部凹槽在所述衬底上的投影面积。
  7. 根据权利要求6所述的半导体结构的制备方法，所述在所述第二凹槽内形成有源柱的步骤中，包括：
    沿所述第二凹槽的内壁通过硅外延生长形成硅柱，所述硅柱的顶面与所述第二光刻胶层的顶面平齐；
    通过离子注入技术对所述硅柱的顶面进行离子掺杂，以形成所述有源柱；
    去除被保留下来的所述第二光刻胶层、被保留下来的第一光刻胶层和被保留下来的所述第一介质层。
  8. 根据权利要求1所述的半导体结构的制备方法，所述在去除部分所述第一氧化层和部分所述介质层，暴露出所述有源柱的顶面，其中被保留下来的所述介质层的顶面与所述有源柱的顶面平齐的步骤之后，在所述有源柱的顶面上形成接触层的步骤之前，所述制备方法还包括：
    在被保留下来的所述介质层的顶面上和所述有源柱的顶面上形成初始金属层；
    去除部分所述初始金属层，保留位于所述有源柱顶面上对的所述初始金属层，以形成所述金属层；
    对所述金属层进行高温回火处理，以形成所述接触层。
  9. 根据权利要求8所述的半导体结构的制备方法，所述金属层包括钴层、镍层或铂层中的至少一种；
    所述接触层的材料包括钴化物、镍化物或铂化合物中的至少一种。
  10. 一种半导体结构，通过权利要求1-9任一项所述方法制备得到，其包括：
    衬底；
    有源柱，所述有源柱成阵列排布在所述衬底上，以垂直于衬底的平面为纵截面，所述有源柱在所述纵截面上的投影形状包括十字形。
  11. 根据权利要求10所述的半导体结构，所述有源柱包括依次顺序连接的第一段、第二段和第三段，所述第一段与所述衬底连接，其中，所述第二段在所述衬底上的投影面积大于所述第一段在所述衬底上的投影面积，所述第二段在所述衬底上的投影面积大于所述第三段在所述衬 底上的投影面积。
  12. 根据权利要求11所述的半导体结构，所述第一段在所述衬底上的投影面积等于所述第三段在所述衬底上的投影面积；或者，
    所述第一段在所述衬底上的投影面积大于或小于所述第三段在所述衬底上的投影面积。
  13. 根据权利要求10所述的半导体结构，所述半导体结构还包括在所述衬底中的位线，所述位线沿所述有源柱的行方向间隔设置，所述位线的顶面与所述有源柱的底面连接。
  14. 据权利要求10所述的半导体结构，所述半导体结构还包括沿所述有源柱的列方向间隔设置的字线，所述字线连接同一行中的所述有源柱。
  15. 根据权利要求10-14任一项所述的半导体结构，所述有源柱的顶面上设有接触层，所述接触层上连接有电容结构。
  16. 根据权利要求15所述的半导体结构，所述电容结构的形状包括柱状或圆筒状。
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