WO2023015502A1 - 一种接触孔制备方法、半导体结构及电子设备 - Google Patents

一种接触孔制备方法、半导体结构及电子设备 Download PDF

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Publication number
WO2023015502A1
WO2023015502A1 PCT/CN2021/112142 CN2021112142W WO2023015502A1 WO 2023015502 A1 WO2023015502 A1 WO 2023015502A1 CN 2021112142 W CN2021112142 W CN 2021112142W WO 2023015502 A1 WO2023015502 A1 WO 2023015502A1
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Prior art keywords
layer
target
contact hole
insulating layer
oxide layer
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PCT/CN2021/112142
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English (en)
French (fr)
Inventor
李冉
马经纶
段蕾蕾
韩欣茹
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/574,652 priority Critical patent/US12154953B2/en
Publication of WO2023015502A1 publication Critical patent/WO2023015502A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the present application relates to the field of semiconductor production, in particular to a method for preparing a contact hole, a semiconductor structure and electronic equipment.
  • DRAM Dynamic Random Access Memory
  • the process integration of the semiconductor process is increased, and it is more and more difficult to reduce the size of the device.
  • the line width is gradually reduced, and the height of the storage capacitor in DRAM is continuously increased. In this way, some contact holes need to be made deeper.
  • the process window of contact holes with high aspect ratio Relatively narrow if the size of the contact hole is too large, it will easily lead to a short circuit, and if the size of the contact hole is too small, it will easily cause the risk of insufficient etching.
  • the embodiment of the present application provides a method for preparing a contact hole, which is applied to a semiconductor structure
  • the semiconductor structure includes an array region and a peripheral region
  • the substrate of the array region includes a buried word line, a first insulating layer
  • the first insulating layer has a storage capacitor array and a contact layer in a direction away from the buried word line
  • the contact layer covers the storage capacitor array
  • the base of the peripheral region is provided with an active region
  • the isolation layer includes a lower structure, a middle structure and an upper structure, and the two sides of the gate structure Including the zeroth layer contact, the top of the zeroth layer contact is lower than the upper end surface of the upper layer structure, and has a first oxide layer in a direction away from the contact layer and the upper layer structure
  • the method includes:
  • the contact hole preparation method is applied to a semiconductor structure.
  • the semiconductor structure includes an array region and a peripheral region.
  • the substrate of the array region includes a buried word line, a first insulating layer, and the first insulating layer
  • the direction of the word line has a storage capacitor array and a contact layer
  • the contact layer covers the storage capacitor array
  • the base of the peripheral area is provided with an active area
  • the isolation layer covers the gate structure
  • the isolation layer includes a lower layer structure, a middle layer structure and an upper layer structure
  • the two sides of the gate structure include the zeroth layer contact
  • the top of the zeroth layer contact is lower than the upper end surface of the upper layer structure
  • the preparation method of the contact hole specifically includes: generating a mask layer on the upper surface of the first oxide layer, exposing the target contact hole pattern on the mask layer, and
  • the above-mentioned contact hole preparation method provided in the embodiment of the present application can deposit an insulating layer without reducing the key dimensions of the contact hole openings in the array region and the peripheral region of the semiconductor structure. And a layer of oxide layer to reduce the critical size of the contact hole, so that the critical size of the contact hole opening can be controlled more reasonably, not only to avoid the short circuit problem caused by the excessive size of the contact hole, but also to avoid the problem caused by the excessive size of the contact hole.
  • the risk of insufficient etching caused by small size reduces the difficulty of semiconductor manufacturing process.
  • the embodiment of the present application provides a method for preparing a contact hole, which is applied to a semiconductor structure, and the base of the semiconductor structure is prepared with bit lines, word lines, active regions, and contact holes between adjacent active regions.
  • the isolation structure has an isolation layer and a gate structure in a direction away from the active region, the isolation layer covers the gate structure, and the isolation layer includes a lower structure, a middle structure and an upper structure;
  • a mask layer is generated on the corresponding upper end surface of the target, and a target contact hole pattern is exposed on the mask layer, and the target contact hole includes a target bit line contact hole, a target word line contact hole, a target an active area contact hole and a target gate contact hole, the target bit line contact hole characterizing a contact hole for connecting to the bit line, the target word line contact hole characterizing a contact hole for connecting to the word line
  • the target active region contact hole represents a contact hole for connecting to the active region
  • the target gate contact hole represents a contact for connecting to the gate of the gate structure hole;
  • Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, and the target contact surface includes an end surface on a target bit line, an end surface on a target word line, and an upper end surface on a target active region and the upper surface of the target grid;
  • Another contact hole preparation method provided in the embodiment of the present application is applied to a semiconductor structure.
  • Bit lines, word lines, active regions, and isolation structures between adjacent active regions are prepared on the substrate of the semiconductor structure.
  • the direction of the active region has an isolation layer and a gate structure.
  • the isolation layer covers the gate structure.
  • the isolation layer includes a lower structure, a middle structure and an upper structure.
  • the contact hole preparation method is as follows: for the contact hole to be prepared, in the corresponding target A mask layer is generated on the upper surface, and a target contact hole pattern is exposed on the mask layer.
  • the target contact hole includes a target bit line contact hole, a target word line contact hole, a target active area contact hole and a target gate contact hole.
  • the target bit line represents the contact hole used to connect to the bit line
  • the target word line contact hole represents the contact hole used to connect to the word line
  • the target active area contact hole represents the contact hole used to connect to the active area
  • the target gate contact hole represents the contact hole used to connect with the gate of the gate structure; etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the target contact hole position, the target contact surface includes the target position The end face of the line, the end face of the target word line, the upper end face of the target active region and the upper end face of the target gate; after the etching, the first insulating layer is deposited on the surface, and the first oxide layer is deposited on the first insulating layer; the deposition is removed After finishing the first insulating layer and the first oxide layer on the parts above the upper end faces of each level, so as to expose the target contact faces.
  • the above-mentioned contact hole preparation method provided in the embodiment of the present application can, without reducing the key dimensions of the bit line contact hole, the word line contact hole, the active region contact hole and the gate contact hole in the semiconductor structure, By depositing a layer of insulating layer and a layer of oxide layer to reduce the critical size of the above-mentioned contact holes, it is possible to control the critical size of the opening of the above-mentioned contact holes more reasonably, which can not only avoid the short circuit problem caused by the excessive size of the contact hole , and also avoid the risk of insufficient etching caused by the too small size of the contact hole, and reduce the difficulty of the semiconductor manufacturing process.
  • the embodiment of the present application provides a semiconductor structure, and the semiconductor structure is a semiconductor structure prepared according to the contact hole preparation method provided in the embodiment of the present application.
  • the embodiment of the present application provides an electronic device, including the semiconductor structure provided in the embodiment of the present application.
  • FIG. 1 is a cross-sectional view of an initial structure of a semiconductor structure in an embodiment of the present application
  • FIG. 2 is a schematic flow diagram of the implementation process of the contact hole preparation method provided in the embodiment of the present application
  • Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are cross-sectional views of the semiconductor structure corresponding to each step of the contact hole preparation method provided by the embodiment of the present application;
  • FIG. 7 is a schematic flow diagram of another contact hole preparation method provided in the embodiment of the present application.
  • FIG. 8 is an initial cross-sectional view of a semiconductor structure for preparing a bit line contact hole provided by an embodiment of the present application
  • FIG. 9 is a schematic diagram of an implementation process for preparing a bit line contact hole provided in an embodiment of the present application.
  • FIG. 10 , FIG. 11 , FIG. 12 and FIG. 13 are cross-sectional views of the semiconductor structure corresponding to each step of preparing a bit line contact hole provided by the embodiment of the present application;
  • FIG. 14 is an initial cross-sectional view of a semiconductor structure for preparing a word line contact hole provided by an embodiment of the present application
  • FIG. 15 is a schematic diagram of an implementation process for preparing a word line contact hole provided in an embodiment of the present application.
  • FIG. 16, FIG. 17, FIG. 18 and FIG. 19 are cross-sectional views of the semiconductor structure corresponding to each step of preparing a word line contact hole provided by the embodiment of the present application;
  • FIG. 20 is an initial cross-sectional view of a semiconductor structure for preparing a contact hole in an active region provided by an embodiment of the present application;
  • FIG. 21 is a schematic diagram of the implementation process for preparing contact holes in the active region provided by the embodiment of the present application.
  • Fig. 22, Fig. 23, Fig. 24 and Fig. 25 are cross-sectional views of the semiconductor structure corresponding to each step of preparing the contact hole in the active region provided by the embodiment of the present application;
  • FIG. 26 is an initial cross-sectional view of a semiconductor structure for preparing a gate contact hole provided by an embodiment of the present application.
  • FIG. 27 is a schematic diagram of the implementation process for preparing a gate contact hole provided by the embodiment of the present application.
  • FIG. 28 , FIG. 29 , FIG. 30 and FIG. 31 are cross-sectional views of the semiconductor structure corresponding to each step of preparing the contact hole in the active region provided by the embodiment of the present application.
  • the process integration of the semiconductor process has been increased, and it is becoming more and more difficult to reduce the size of the device.
  • the line width is gradually reduced, and the height of the storage capacitor in DRAM is continuously increased. In this way, some contact holes need to be made deeper.
  • the process window of contact holes with high aspect ratio It is relatively narrow. If the size of the contact hole is too large, it will easily lead to a short circuit. If the size of the contact hole is too small, it will easily cause the risk of insufficient etching. Based on this, the embodiment of the present application provides a contact hole preparation method, a semiconductor structure and an electronic device. equipment.
  • An embodiment of the present application provides a contact hole preparation method.
  • the contact hole preparation method is applied to a semiconductor structure, and the semiconductor structure is a dynamic random access memory.
  • the semiconductor structure before the contact hole is prepared, the initial As shown in FIG. 1, the semiconductor structure includes an array region 11 and a peripheral region 12.
  • the substrate of the array region 11 includes a buried word line 111, a first insulating layer 112, and the first insulating layer 112 is far away from the buried word line.
  • the direction of the word line 111 has a storage capacitor array 113 and a contact layer 114, the contact layer 114 covers the storage capacitor array 113, the base of the peripheral area 12 is provided with an active area 121, and has an isolation layer 122 and a gate in a direction away from the active area 121.
  • An isolation structure 14 located between adjacent active areas (Active Area, AA) 121 is also provided on the substrate of the array region 11 and the substrate of the peripheral region 12, and the isolation structure 14 is used to isolate multiple components on the substrate of the semiconductor structure.
  • active region 121 wherein the upper end surface of the first insulating layer 112 in the array region 11 is flush with the upper end surface of the upper layer structure 122 - 3 of the isolation layer 122 in the peripheral region 12 .
  • the substrate of the array region 11 and the substrate of the peripheral region 12 can be made of silicon (Si), and the materials of the first insulating layer 112, the upper structure 122-3 of the isolation layer 122, and the lower structure 122-1 of the isolation layer 122 are the same.
  • the insulating material can be silicon nitride (SiN).
  • the material of the middle layer structure 122-2 of the isolation layer 122 is oxide, which can be silicon dioxide (SiO2).
  • the material of the first oxide layer 13 and the middle layer of the isolation layer 122 The material of the structure 122-2 is the same as silicon dioxide, the material of the contact layer 114 can be polysilicon (Poly), and the material of the zeroth layer contact 124 is a metal pad, and its material can be metal tungsten (W).
  • FIG. 2 it is a schematic flow chart of a contact hole preparation method provided in the embodiment of the present application.
  • the contact hole preparation method may include the following steps:
  • a mask layer 15 is formed on the upper surface of the first oxide layer 13, and target contact hole patterns 16-1 and 16-2 are exposed on the mask layer 15, wherein the mask layer 15 It may include a first mask layer 15-1 and a second mask layer 15-2, the target contact hole pattern 16-1 is a pattern corresponding to the contact hole to be prepared in the array area 11, and the target contact hole pattern 16-2 is the peripheral The pattern corresponding to the contact hole to be prepared in area 12.
  • the first mask layer 15-1 is deposited on the end face of the first oxide layer 13, and the second mask layer 15-2 is deposited on the end face of the first mask layer 15-1.
  • 17 Expose the target contact hole patterns 16-1 and 16-2 on the second mask layer 15-2.
  • the size (that is, the diameter) of 16-2 is set to be slightly larger than the existing process size, so that the opening size of the corresponding target contact hole (ie, the diameter of the contact hole) is larger than the existing process size, and the size can be set according to the actual situation
  • the setting is not limited in this embodiment of the present application, so that the process difficulty can be reduced.
  • the material of the first mask layer 15 - 1 can be carbon
  • the material of the second mask layer 15 - 2 can be silicon oxynitride (SiON).
  • the first oxide layer 13 is etched according to the target contact hole patterns 16-1 and 16-2 to form the target contact hole 17-1 in the array area 11 and the contact hole in the peripheral area 12.
  • the target contact hole 17-2 exposes the upper end surface of the contact layer 114 corresponding to the target contact hole 17-1, and the upper end surface of the upper structure 122-3 of the isolation layer 122 corresponding to the target contact hole 17-2.
  • a second insulating layer 18 is deposited on the surface after etching, and a second oxide layer 19 is deposited on the surface of the second insulating layer 18 to reduce the target contact hole 17-1 and
  • the target contact hole 17-2 in the peripheral region 12 can reduce the direct parasitic capacitance of the target contact hole.
  • the second insulating layer 18 is deposited on the upper end surface and each side surface of the first oxide layer 13 after etching, the exposed upper end surface of the contact layer 114, and the upper end surface of the exposed upper layer structure 122-3 of the isolation layer 122. , and deposit a second oxide layer 19 on the second insulating layer 18 .
  • the second insulating layer 18 is made of the same material as the first insulating layer 112, the upper structure 122-3 of the isolation layer 122, and the lower structure 122-1 of the isolation layer 122, and silicon nitride can be used.
  • the materials of the oxide layer 19 and the first oxide layer 13 are the same, and both can be silicon dioxide, which is not limited in this embodiment of the present application.
  • the second insulating layer 18 and the second oxide layer 19 above the upper end surface of the first oxide layer 13 can be removed by a dry etching process, and the exposed contacts from the array region 11 can be removed.
  • the upper end of the layer 114 is etched downward to remove part of the contact layer 114, and the upper end of the upper structure 122-3 of the isolation layer 122 exposed in the peripheral region 12 is etched downward to expose the upper end of the zeroth layer contact 124, thereby generating an array
  • the semiconductor structure also includes bit lines (not shown in FIGS. 2-6 above).
  • the size of the target contact hole is first enlarged, and then an insulating layer (ie, the second insulating layer 18) and an oxide layer (ie, the second oxide layer 19) are deposited.
  • the size of the target contact hole is reduced in a manner that not only avoids the risk of insufficient etching due to the size of the contact hole being too small, but also avoids the problem of shorting the zero-level contact 124 due to the size of the contact hole being too large , and reduce the difficulty of semiconductor manufacturing process.
  • the embodiment of the present application provides another method for preparing a contact hole, which is applied to a semiconductor structure.
  • the semiconductor structure is a dynamic random access memory, and a bit line 31, a word line 32, and an active region 33 are prepared on the substrate of the semiconductor structure.
  • the isolation structure 33-1 between the adjacent active regions 33 has an isolation layer 34 and a gate structure 35 in a direction away from the active area 33, the isolation layer 34 covers the gate structure 35, and the isolation layer 34 includes the underlying structure 34-1, middle structure 34-2 and superstructure 34-3.
  • the material of the substrate can be silicon
  • the upper structure 34-3 of the isolation layer 34 is made of the same material as the lower structure 34-1 of the isolation layer 34, both are insulating materials, and silicon nitride can be used
  • the middle structure 34-2 of the isolation layer 34 The material is oxide, which can be silicon dioxide.
  • FIG. 7 The implementation flow diagram of the contact hole preparation method is shown in Figure 7, which may include the following steps:
  • the target contact hole includes a target bit line contact hole, a target word line contact hole, a target active area contact hole and a target gate contact hole, and the target bit line contact hole represents a contact hole for connecting with a bit line
  • the target word line contact hole represents the contact hole for connecting to the word line
  • the target active area contact hole represents the contact hole for connecting to the active area
  • the target gate contact hole represents the contact hole for connecting to the gate structure. pole-to-pole contact holes.
  • the target contact surface includes: an end surface on a target bit line, an end surface on a target word line, an upper end surface on a target active region, and an upper end surface on a target gate.
  • the material of the upper structure 34-3 of the first insulating layer and the isolation layer 34, and the lower structure 34-1 of the isolation layer 34 are the same, and silicon nitride can be used, and the material of the first oxide layer is oxide, which can be Silicon dioxide is used, which is not limited in the embodiment of the present application.
  • the implementation process of the corresponding contact hole preparation methods will be introduced below for the target contact holes to be prepared, namely the target bit line contact hole, the target word line contact hole, the target active region contact hole and the target gate contact hole.
  • the semiconductor structure also includes a second insulating layer 36 disposed on the top and sides of the bit line 31, a second oxide layer 37 is disposed on the base of the semiconductor structure, and the second oxide layer 37 covers the second insulating layer 36 and the bit line 36.
  • the upper end surface of the dioxide layer 36 is higher than the upper end surface of the second insulating layer 36 .
  • the target contact hole to be prepared is the target bit line contact hole
  • the corresponding initial cross-sectional view of the semiconductor structure for preparing the bit line contact hole is shown in Figure 8
  • the bit line contact hole can be prepared according to the process shown in Figure 9 . Include the following steps:
  • a mask layer 38 is formed on the upper surface of the second oxide layer 37, and a target bit line contact hole pattern 39 is exposed on the mask layer 38, wherein the mask layer 38 may include a first Mask layer 38-1 and second mask layer 38-2.
  • the first mask layer 38-1 is deposited on the end face of the second oxide layer 37
  • the second mask layer 38-2 is deposited on the end face of the first mask layer 38-1.
  • 310 exposes the target bit line contact hole pattern 39 on the second mask layer 38-2.
  • the size (ie diameter) of the target bit line contact hole pattern 39 can be set to slightly Larger than the existing process size, so that the opening size of the corresponding target bit line contact hole (ie, the diameter of the bit line contact hole) is larger than the existing process size, and the setting of the size can be set according to the actual situation, so that the process difficulty can be reduced.
  • the material of the first mask layer 38 - 1 can be carbon
  • the material of the second mask layer 38 - 2 can be silicon oxynitride.
  • the second oxide layer 37 is etched according to the target bit line contact hole pattern 39 to form a target bit line contact hole 311 to expose the end surface of the target bit line.
  • a first insulating layer 312 is deposited on the surface after etching, and a first oxide layer 313 is deposited on the surface of the first insulating layer to reduce the size of the target bit line contact hole 311 and reduce the target bit line.
  • the parasitic capacitance of the wire contact hole directly.
  • the first insulating layer 312 is made of the same material as the upper structure 34-3 of the isolation layer 34 and the upper structure 34-1 of the isolation layer 34, both of which can be made of silicon nitride.
  • the first oxide layer 313 and the second oxide layer 37 The material is the same, and silicon dioxide can be used, which is not limited in this embodiment of the present application.
  • the first insulating layer 312 and the first oxide layer 313 above the upper end faces of each level after deposition are removed, and the first insulating layer 312 and the first oxide layer 313 on each side are retained to expose
  • the target bit line contact hole 314 is formed, and the target bit line contact hole 314 communicates with the target bit line.
  • the word line 32 is embedded in the isolation structure 33 - 1 , and has a third insulating layer 315 in a direction away from the isolation structure 33 - 1 .
  • the target contact hole to be prepared is the target word line contact hole
  • the corresponding initial cross-sectional view of the semiconductor structure for preparing the word line contact hole is shown in Figure 14, and the word line contact hole can be prepared according to the process shown in Figure 15. Include the following steps:
  • a mask layer 316 is formed on the upper end surface of the third insulating layer 315, and a target word line contact hole pattern 317 is exposed on the mask layer 316.
  • the mask layer 316 includes a first mask layer 316-1 and a second mask layer 316-2.
  • the first mask layer 316-1 is deposited on the end face of the third insulating layer 315
  • the second mask layer 316-2 is deposited on the end face of the first mask layer 316-1, using photoresist 318 exposes the target word line contact hole pattern 317 on the second mask layer 316-2.
  • the size (ie diameter) of the target word line contact hole pattern 317 can be set to slightly Larger than the existing process size, so that the opening size of the corresponding target word line contact hole (that is, the diameter of the word line contact hole) is larger than the existing process size, the setting of the size can be set according to the actual situation, so that the process difficulty can be reduced .
  • the material of the first mask layer 316-1 can be carbon
  • the material of the second mask layer 316-2 can be silicon oxynitride.
  • etching is performed downward from the third insulating layer 315 according to the target word line contact hole pattern 317 to form a target word line contact hole 319 to expose the end surface of the target word line.
  • a first insulating layer 320 is deposited on the surface after etching, and a first oxide layer 321 is deposited on the surface of the first insulating layer to reduce the size of the target bit line contact hole 319 and reduce the target bit line.
  • the parasitic capacitance of the wire contact hole directly.
  • the first insulating layer 320 is made of the same material as the upper structure 34-3 of the isolation layer 34 and the upper structure 34-1 of the isolation layer 34, both of which can be made of silicon nitride.
  • the first oxide layer 321 and the second oxide layer 37 The material is the same, and silicon dioxide can be used, which is not limited in this embodiment of the present application.
  • the material of the third insulating layer 315 is the same as that of the first insulating layer 320 , the upper structure 34 - 3 of the isolation layer 34 , and the upper structure 34 - 1 of the isolation layer 34 , which can be silicon nitride.
  • the first insulating layer 320 and the first oxide layer 321 above the horizontal end faces after deposition are removed, and the first insulating layer 320 and the first oxide layer 321 on each side are retained to expose
  • the target word line contact hole 322 is formed so that the target word line contact hole 322 communicates with the target word line.
  • the target contact hole to be prepared is the target active area contact hole
  • the corresponding initial cross-sectional view of the semiconductor structure for preparing the active area contact hole is shown in Figure 20, and the active area contact is prepared according to the process shown in Figure 21 hole, may include the following steps:
  • a mask layer 323 is formed on the upper end surface of the upper layer structure 34-3 of the isolation layer 34, and the target active region contact hole pattern 324 is exposed on the mask layer 323.
  • the mask layer 323 It includes a first mask layer 323-1 and a second mask layer 323-2.
  • a first mask layer 323-1 is deposited on the upper end surface of the upper structure 34-3 of the isolation layer 34, and a second mask layer 323-2 is deposited on the upper end surface of the first mask layer 323-1.
  • the size of the target word line contact hole pattern 324 can be (i.e., the diameter) is set to be slightly larger than the existing process size, so that the opening size of the corresponding target active area contact hole (ie, the diameter of the active area contact hole) is larger than the existing process size, and the setting of the size can be based on the actual situation. Set up by yourself, so that the process difficulty can be reduced.
  • the material of the first mask layer 323-1 can be carbon
  • the material of the second mask layer 323-2 can be silicon oxynitride.
  • the upper layer structure 34-3 of the isolation layer 34, the middle layer structure 34-2 of the isolation layer 34, and the lower layer structure 34-1 of the isolation layer 34 are carried out according to the target active region contact hole pattern 324. Etching to form a target active region contact hole 326 to expose the target active region contact upper end surface.
  • a first insulating layer 327 is deposited on the surface after etching, and a first oxide layer 328 is deposited on the surface of the first insulating layer to reduce the size of the target active region contact hole 326 and reduce the target Active area contact hole direct parasitic capacitance.
  • the first insulating layer 327 is made of the same material as the upper structure 34-3 of the isolation layer 34 and the upper structure 34-1 of the isolation layer 34, both of which can be made of silicon nitride.
  • the first oxide layer 328 and the second oxide layer 37 The material is the same, and silicon dioxide can be used, which is not limited in this embodiment of the present application.
  • the first insulating layer 327 and the first oxide layer 328 above the horizontal end faces after deposition are removed, and the first insulating layer 327 and the first oxide layer 328 on each side are retained to expose
  • the target active area contacts the upper end surface, thereby generating a target active area contact hole 329, so that the target active area contact hole 329 communicates with the target active area.
  • the top surface and sidewalls of the gate structure 35 of the semiconductor structure further include an insulating capping layer 330 .
  • the target contact hole to be prepared is the target gate contact hole
  • the corresponding initial cross-sectional view of the semiconductor structure for preparing the gate contact hole is shown in Figure 26, and the gate contact hole can be prepared according to the process shown in Figure 27. Include the following steps:
  • a mask layer is formed on the upper end surface of the upper structure of the isolation layer, and a target gate contact hole pattern is exposed on the mask layer.
  • a mask layer 331 is formed on the upper end surface of the upper layer structure 34-3 of the isolation layer 34, and a target gate contact hole pattern 332 is exposed on the mask layer 331.
  • the mask layer 331 includes The first mask layer 331-1 and the second mask layer 331-2.
  • a first mask layer 331-1 is deposited on the upper end surface of the upper structure 34-3 of the isolation layer 34, and a second mask layer 331-2 is deposited on the upper end surface of the first mask layer 331-1.
  • the resist 333 exposes the target gate contact hole pattern 332 on the second mask layer 331-2.
  • the size (ie diameter) of the target gate contact hole pattern 332 can be set In order to be slightly larger than the existing process size, so that the opening size of the corresponding target gate contact hole (ie the diameter of the gate contact hole) is larger than the existing process size, the setting of the size can be set by itself according to the actual situation, so that Reduce process difficulty.
  • the material of the first mask layer 331-1 can be carbon
  • the material of the second mask layer 331-2 can be silicon oxynitride.
  • the upper layer structure 34-3 and the insulating cover layer 330 of the isolation layer 34 are etched according to the target gate contact hole pattern 332 to form the target gate contact hole 334 to expose the target gate. Extremely top end.
  • a first insulating layer 335 is deposited on the surface after etching, and a first oxide layer 336 is deposited on the surface of the first insulating layer to reduce the size of the target gate contact hole 334 and lower the target gate.
  • Pole contact hole direct parasitic capacitance.
  • the first insulating layer 335, the insulating cover layer 330, the upper layer structure 34-3 of the isolation layer 34, and the upper layer structure 34-1 of the isolation layer 34 are made of the same material, and silicon nitride can be used for the first oxide layer 336 and the second layer.
  • the material of the dioxide layer 37 is the same, and both can be silicon dioxide, which is not limited in this embodiment of the present application.
  • the first insulating layer 335 and the first oxide layer 336 above the horizontal end faces after deposition are removed, and the first insulating layer 335 and the first oxide layer 336 on each side are retained to expose The upper end surface of the target gate is exposed to form a contact hole 337 in the active area of the target gate, so that the target gate contact hole 337 is connected with the target gate.
  • the size of the target contact hole is first enlarged, and then the deposition method is used.
  • the method of layering an insulating layer and a layer of oxide layer reduces the size of the target contact hole, thus avoiding the risk of insufficient etching caused by the size of the contact hole being too small, and avoiding the risk of insufficient etching caused by the size of the contact hole being too large. Short circuit problem, and reduce the difficulty of semiconductor manufacturing process, and effectively reduce the damage to the silicon in the active region during the process.
  • an embodiment of the present application further provides a semiconductor structure, and the semiconductor structure is a semiconductor structure prepared according to the contact hole preparation method provided in the embodiment of the present application.
  • an embodiment of the present application further provides an electronic device, including the above-mentioned semiconductor structure provided in the embodiment of the present application.

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Abstract

本申请公开了一种接触孔制备方法、半导体结构及电子设备，所述方法，包括：在半导体结构的第一氧化层上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形；按照所述目标接触孔图形对所述第一氧化层进行刻蚀，以裸露出所述目标接触孔位置对应的接触层上端面，以及所述目标接触孔位置对应的上层结构上端面；在刻蚀后表面沉积第二绝缘层，并在所述第二绝缘层之上沉积第二氧化层；去除所述第一氧化层上端面以上部分的第二绝缘层和第二氧化层，并从裸露出的所述接触层上端面向下刻蚀以去除部分所述接触层，以及从裸露出的所述上层结构上端面向下刻蚀以裸露出第零层接触上端面。

Description

一种接触孔制备方法、半导体结构及电子设备
相关申请的交叉引用
本申请要求在2021年08月09日提交中国专利局、申请号为202110906602.3、申请名称为“一种接触孔制备方法、半导体结构及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体生产领域，尤其涉及一种接触孔制备方法、半导体结构及电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)制程工艺进入20nm以后，增加了半导体制程的工艺集成度，缩小器件尺寸的难度越来越高。随着半导体集成电路器件技术的不断发展，线宽逐渐减小，DRAM中的存储电容的高度不断增大，这样需将一些接触孔做得比较深，然而，高深宽比的接触孔的制程窗口比较窄，若接触孔的尺寸太大易导致短路，若接触孔的尺寸太小则易引起刻蚀不足的风险。
发明内容
第一方面，本申请实施例提供了一种接触孔制备方法，应用于半导体结构，所述半导体结构包括阵列区和外围区，所述阵列区的基底上包括埋入式字线、第一绝缘层、所述第一绝缘层在远离所述埋入式字线的方向具有存储电容阵列和接触层，所述接触层覆盖所述存储电容阵列，所述外围区的基底设置有有源区，在远离所述有源区的方向具有隔离层和栅极结构，所述隔离层覆盖所述栅极结构，所述隔离层包括下层结构、中层结构和上层结构，所述栅极结构的两侧包括第零层接触，所述第零层接触顶部低于所述上层结构上端面，在远离所述接触层和所述上层结构的方向具有第一氧化层，所述方 法，包括：
在所述第一氧化层上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形；
按照所述目标接触孔图形对所述第一氧化层进行刻蚀，以裸露出所述目标接触孔位置对应的所述接触层上端面，以及所述目标接触孔位置对应的所述上层结构上端面；
在刻蚀后表面沉积第二绝缘层，并在所述第二绝缘层之上沉积第二氧化层；
去除所述第一氧化层上端面以上部分的第二绝缘层和第二氧化层，并从裸露出的所述接触层上端面向下刻蚀以去除部分所述接触层，以及从裸露出的所述上层结构上端面向下刻蚀以裸露出所述第零层接触上端面。
本申请实施例提供的接触孔制备方法应用于半导体结构，半导体结构包括阵列区和外围区，阵列区的基底上包括埋入式字线、第一绝缘层、第一绝缘层在远离埋入式字线的方向具有存储电容阵列和接触层，接触层覆盖存储电容阵列，外围区的基底设置有有源区，在远离有源区的方向具有隔离层和栅极结构，隔离层覆盖栅极结构，隔离层包括下层结构、中层结构和上层结构，栅极结构的两侧包括第零层接触，第零层接触顶部低于上层结构上端面，在远离接触层和上层结构的方向具有第一氧化层，该接触孔制备方法具体为：在第一氧化层上端面生成掩膜层，在掩膜层上曝光出目标接触孔图形，按照目标接触孔图形对第一氧化层进行刻蚀，以裸露出目标接触孔位置对应的接触层上端面，以及目标接触孔位置对应的上层结构上端面，在刻蚀后表面沉积第二绝缘层，并在第二绝缘层之上沉积第二氧化层，去除第一氧化层上端面以上部分的第二绝缘层和第二氧化层，从裸露出的接触层上端面向下刻蚀以去除部分接触层，以及从裸露出的上层结构上端面向下刻蚀以裸露出第零层接触上端面，本申请实施例提供的上述接触孔制备方法，可在不减小半导体结构中阵列区和外围区的接触孔开孔关键尺寸的前提下，通过沉积一层绝缘层和一层氧化层来缩小接触孔关键尺寸，从而，可以控制接触孔开孔关键 尺寸更加合理，不仅可避免由于接触孔的尺寸过大而导致的短路问题，还避免了由于接触孔的尺寸过小而引起的刻蚀不足的风险，并降低了半导体制程工艺难度。
第二方面，本申请实施例提供了一种接触孔制备方法，应用于半导体结构，所述半导体结构的基底上制备有位线、字线、有源区及位于相邻有源区之间的隔离结构，在远离所述有源区的方向具有隔离层和栅极结构，所述隔离层覆盖所述栅极结构，所述隔离层包括下层结构、中层结构和上层结构；
针对待制备接触孔，在对应的目标上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形，所述目标接触孔包括目标位线接触孔、目标字线接触孔、目标有源区接触孔和目标栅极接触孔，所述目标位线接触孔表征用于与所述位线相连接的接触孔，所述目标字线接触孔表征用于与所述字线相连接的接触孔，所述目标有源区接触孔表征用于与所述有源区相连接的接触孔，所述目标栅极接触孔表征用于与所述栅极结构的栅极相连接的接触孔；
按照所述目标接触孔图形进行刻蚀，以裸露出所述目标接触孔位置对应的目标接触面，所述目标接触面包括目标位线上端面、目标字线上端面、目标有源区上端面和目标栅极上端面；
在刻蚀后表面沉积第一绝缘层，并在所述第一绝缘层之上沉积第一氧化层；
去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，以裸露出所述目标接触面。
本申请实施例提供的又一种接触孔制备方法，应用于半导体结构，半导体结构的基底上制备有位线、字线、有源区及位于相邻有源区之间的隔离结构，在远离有源区的方向具有隔离层和栅极结构，隔离层覆盖栅极结构，隔离层包括下层结构、中层结构和上层结构，该接触孔制备方法具体为：针对待制备接触孔，在对应的目标上端面生成掩膜层，在掩膜层上曝光出目标接触孔图形，目标接触孔包括目标位线接触孔、目标字线接触孔、目标有源区接触孔和目标栅极接触孔，目标位线接触孔表征用于与位线相连接的接触孔， 目标字线接触孔表征用于与字线相连接的接触孔，目标有源区接触孔表征用于与有源区相连接的接触孔，目标栅极接触孔表征用于与栅极结构的栅极相连接的接触孔；按照目标接触孔图形进行刻蚀，以裸露出目标接触孔位置对应的目标接触面，目标接触面包括目标位线上端面、目标字线上端面、目标有源区上端面和目标栅极上端面；在刻蚀后表面沉积第一绝缘层，并在第一绝缘层之上沉积第一氧化层；去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，以裸露出目标接触面。本申请实施例提供的上述接触孔制备方法，可在不减小半导体结构中的位线接触孔、字线接触孔、有源区接触孔以及栅极接触孔的开孔关键尺寸的前提下，通过沉积一层绝缘层和一层氧化层来缩小上述各接触孔关键尺寸，从而，可以控制上述各接触孔开孔关键尺寸更加合理，不仅可避免由于接触孔的尺寸过大而导致的短路问题，还避免了由于接触孔的尺寸过小而引起的刻蚀不足的风险，并降低了半导体制程工艺难度。
第三方面，本申请实施例提供了一种半导体结构，所述半导体结构为根据本申请实施例提供的接触孔制备方法制备的半导体结构。
第四方面，本申请实施例提供了一种电子设备，包括本申请实施例提供的所述半导体结构。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本申请实施例中半导体结构的初始结构截面图；
图2为本申请实施例提供的接触孔制备方法的实施流程示意图；
图3、图4、图5和图6为本申请实施例提供的接触孔制备方法的各步骤对应的半导体结构截面图；
图7为本申请实施例提供的又一接触孔制备方法的实施流程示意图；
图8为本申请实施例提供的制备位线接触孔的半导体结构的初始截面图；
图9为本申请实施例提供的制备位线接触孔的实施流程示意图；
图10、图11、图12和图13为本申请实施例提供的制备位线接触孔的各步骤对应的半导体结构截面图；
图14为本申请实施例提供的制备字线接触孔的半导体结构的初始截面图；
图15为本申请实施例提供的制备字线接触孔的实施流程示意图；
图16、图17、图18和图19为本申请实施例提供的制备字线接触孔的各步骤对应的半导体结构截面图；
图20为本申请实施例提供的制备有源区接触孔的半导体结构的初始截面图；
图21为本申请实施例提供的制备有源区接触孔的实施流程示意图；
图22、图23、图24和图25为本申请实施例提供的制备有源区接触孔的各步骤对应的半导体结构截面图；
图26为本申请实施例提供的制备栅极接触孔的半导体结构的初始截面图；
图27为本申请实施例提供的制备栅极接触孔的实施流程示意图；
图28、图29、图30和图31为本申请实施例提供的制备有源区接触孔的各步骤对应的半导体结构截面图。
具体实施方式
DRAM制程工艺进入20nm以后，增加了半导体制程的工艺集成度，缩小器件尺寸的难度越来越高。随着半导体集成电路器件技术的不断发展，线宽逐渐减小，DRAM中的存储电容的高度不断增大，这样需将一些接触孔做得比较深，然而，高深宽比的接触孔的制程窗口比较窄，若接触孔的尺寸太 大易导致短路，若接触孔的尺寸太小则易引起刻蚀不足的风险，基于此，本申请实施例提供了一种接触孔制备方法、半导体结构及电子设备。
以下结合说明书附图对本申请的优选实施例进行说明，应当理解，此处所描述的优选实施例仅用于说明和解释本申请，并不用于限定本申请，并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本申请一实施例提供了一种接触孔制备方法，所述接触孔制备方法应用于半导体结构，半导体结构为动态随机存取存储器，本申请实施例中，在制备接触孔之前，半导体结构的初始结构截面图如图1所示，半导体结构包括阵列区11和外围区12，阵列区11的基底上包括埋入式字线111、第一绝缘层112、第一绝缘层112在远离埋入式字线111的方向具有存储电容阵列113和接触层114，接触层114覆盖存储电容阵列113，外围区12的基底设置有有源区121，在远离有源区121的方向具有隔离层122和栅极结构123，隔离层122覆盖栅极结构123，隔离层122包括下层结构122-1、中层结构122-2和上层结构122-3，栅极结构123的两侧包括第零层接触124，第零层接触124顶部低于上层结构122-3上端面，在远离接触层114和上层结构122-3的方向具有第一氧化层13。阵列区11的基底上和外围区12的基底上还设置有位于相邻有源区(Active Area，AA)121之间的隔离结构14，隔离结构14用于隔离出半导体结构的基底上的多个有源区121，其中，阵列区11中的第一绝缘层112的上端面与外围区12中的隔离层122的上层结构122-3上端面平齐。阵列区11的基底和外围区12的基底的材料可采用硅(Si)，第一绝缘层112、隔离层122的上层结构122-3和隔离层122的下层结构122-1材质相同，均为绝缘材料，均可采用氮化硅(SiN)，隔离层122的中层结构122-2的材质为氧化物，可为二氧化硅(SiO2)，第一氧化层13的材质与隔离层122的中层结构122-2的材质相同，也为二氧化硅，接触层114的材质可为多晶硅(Poly)，第零层接触124为金属衬垫，其材质可为金属钨(W)。
如图2所示，其为本申请实施例提供的一种接触孔制备方法的实施流程示意图，所述接触孔制备方法可包括以下步骤：
S21、在第一氧化层上端面生成掩膜层，在掩膜层上曝光出目标接触孔图形。
具体实施时，如图3所示，在第一氧化层13上端面生成掩膜层15，在掩膜层15上曝光出目标接触孔图形16-1和16-2，其中，掩膜层15可包括第一掩膜层15-1和第二掩膜层15-2，目标接触孔图形16-1为阵列区11的待制备的接触孔对应的图形，目标接触孔图形16-2为外围区12的待制备的接触孔对应的图形。
在具体实施过程中，在第一氧化层13上端面沉积第一掩膜层15-1，并在第一掩膜层15-1上端面沉积第二掩膜层15-2，利用光刻胶17在第二掩膜层15-2上曝光出目标接触孔图形16-1和16-2，在曝光目标接触孔图形16-1和16-2时，可以将目标接触孔图形16-1和16-2的尺寸(即直径)设置为稍大于现有工艺尺寸，以使得对应的目标接触孔的开孔尺寸(即接触孔的直径)大于现有工艺尺寸，尺寸的设置可根据实际情况自行设置，本申请实施例对此不作限定，这样，可降低工艺难度。第一掩膜层15-1的材质可以为碳，第二掩膜层15-2的材质可以为氮氧化硅(SiON)。
S22、按照目标接触孔图形对第一氧化层进行刻蚀，以裸露出目标接触孔位置对应的接触层上端面，以及目标接触孔位置对应的上层结构上端面。
具体实施时，如图4所示，按照目标接触孔图形16-1和16-2对第一氧化层13进行刻蚀，形成阵列区11中的目标接触孔17-1和外围区12中的目标接触孔17-2，以裸露出目标接触孔17-1位置对应的接触层114上端面，以及目标接触孔17-2位置对应的隔离层122的上层结构122-3上端面。
S23、在刻蚀后表面沉积第二绝缘层，并在第二绝缘层之上沉积第二氧化层。
具体实施时，如图5所示，在刻蚀后表面沉积第二绝缘层18，在第二绝缘层18表面沉积第二氧化层19，以缩小阵列区11中的目标接触孔17-1和外围区12中的目标接触孔17-2，这样可降低目标接触孔直接的寄生电容。
具体地，在刻蚀后的第一氧化层13的上端面及各个侧面、裸露出的接触 层114上端面、以及裸露出的隔离层122的上层结构122-3上端面沉积第二绝缘层18，并在第二绝缘层18之上沉积第二氧化层19。
在具体实施过程中，第二绝缘层18与第一绝缘层112、隔离层122的上层结构122-3、隔离层122的下层结构122-1的材质相同，均可采用氮化硅，第二氧化层19和第一氧化层13的材质相同，均可采用二氧化硅，本申请实施例对此不作限定。
S24、去除第一氧化层上端面以上部分的第二绝缘层和第二氧化层，并从裸露出的接触层上端面向下刻蚀以去除部分接触层，以及从裸露出的上层结构上端面向下刻蚀以裸露出第零层接触上端面。
具体实施时，如图6所示，可采用干法刻蚀工艺去除第一氧化层13上端面以上部分的第二绝缘层18和第二氧化层19，并从阵列区11中裸露出的接触层114上端面向下刻蚀以去除部分接触层114，从外围区12中裸露出的隔离层122的上层结构122-3上端面向下刻蚀以裸露出第零层接触124上端面，从而生成阵列区11中的接触孔20-1以及外围区12中的接触孔20-2，这样，生成的接触孔20-1可与接触层114连通，生成的接触孔20-2可与第零层接触124连通。
半导体结构还包括位线(以上图2-图6中未示出)。
本申请实施例提供的上述接触孔制备方法，首先将目标接触孔的尺寸做大，再采用沉积一层绝缘层(即第二绝缘层18)和一层氧化层(即第二氧化层19)的方式缩小目标接触孔的尺寸，这样，既避免了由于接触孔的尺寸过小而引起的刻蚀不足的风险，又避免了由于接触孔的尺寸过大而导致第零层接触124短路的问题，并降低了半导体制程工艺难度。
在实际应用中，随着外围区关键尺寸的不断减小，工艺过程中需要加强轰击作用，会对有源区的硅的损伤较多，这样针对有高度差而又要求高选择比的工艺制程极为不利。
基于此，本申请实施例提供了又一种接触孔制备方法，应用于半导体结构，半导体结构为动态随机存取存储器，半导体结构的基底上制备有位线31、 字线32、有源区33及位于相邻有源区33之间的隔离结构33-1，在远离有源区33的方向具有隔离层34和栅极结构35，隔离层34覆盖栅极结构35，隔离层34包括下层结构34-1、中层结构34-2和上层结构34-3。基底的材料可采用硅，隔离层34的上层结构34-3和隔离层34的下层结构34-1材质相同，均为绝缘材料，均可采用氮化硅，隔离层34的中层结构34-2的材质为氧化物，可为二氧化硅。
所述接触孔制备方法的实施流程示意图如图7所示，可包括以下步骤：
S41、针对待制备接触孔，在对应的目标上端面生成掩膜层，在掩膜层上曝光出目标接触孔图形。
具体实施时，目标接触孔包括目标位线接触孔、目标字线接触孔、目标有源区接触孔和目标栅极接触孔，目标位线接触孔表征用于与位线相连接的接触孔，目标字线接触孔表征用于与字线相连接的接触孔，目标有源区接触孔表征用于与有源区相连接的接触孔，目标栅极接触孔表征用于与栅极结构的栅极相连接的接触孔。
S42、按照目标接触孔图形进行刻蚀，以裸露出目标接触孔位置对应的目标接触面。
目标接触面包括：目标位线上端面、目标字线上端面、目标有源区上端面和目标栅极上端面。
S43、在刻蚀后表面沉积第一绝缘层，并在第一绝缘层之上沉积第一氧化层。
具体实施时，第一绝缘层和隔离层34的上层结构34-3、隔离层34的下层结构34-1的材质相同，均可采用氮化硅，第一氧化层的材质为氧化物，可采用二氧化硅，本申请实施例对此不作限定。
S44、去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，以裸露出目标接触面。
下面分别针对待制备的目标接触孔为目标位线接触孔、目标字线接触孔、目标有源区接触孔和目标栅极接触孔介绍各自对应的接触孔制备方法的实施 流程。
半导体结构还包括设置于位线31顶部和侧边的第二绝缘层36，半导体结构的基底上设置有第二氧化层37，第二氧化层37覆盖第二绝缘层36和位线36，第二氧化层36的上端面高于第二绝缘层36的上端面。
当待制备的目标接触孔为目标位线接触孔时，对应的制备位线接触孔的半导体结构的初始截面图如图8所示，按照如图9所示的流程制备位线接触孔，可以包括以下步骤：
S51、在第二氧化层的上端面生成掩膜层，在掩膜层上曝光出目标位线接触孔图形。
具体实施时，如图10所示，在第二氧化层37上端面生成掩膜层38，在掩膜层38上曝光出目标位线接触孔图形39，其中，掩膜层38可包括第一掩膜层38-1和第二掩膜层38-2。
在具体实施过程中，在第二氧化层37上端面沉积第一掩膜层38-1，并在第一掩膜层38-1上端面沉积第二掩膜层38-2，利用光刻胶310在第二掩膜层38-2上曝光出目标位线接触孔图形39，在曝光目标位线接触孔图形39时，可以将目标位线接触孔图形39的尺寸(即直径)设置为稍大于现有工艺尺寸，以使得对应的目标位线接触孔的开孔尺寸(即位线接触孔的直径)大于现有工艺尺寸，尺寸的设置可根据实际情况自行设置，这样，可降低工艺难度。第一掩膜层38-1的材质可以为碳，第二掩膜层38-2的材质可以为氮氧化硅。
S52、按照目标位线接触孔图形对第二氧化层和第二绝缘层进行刻蚀，以裸露出目标位线上端面。
具体实施时，如图11所示，按照目标位线接触孔图形39对第二氧化层37进行刻蚀，形成目标位线接触孔311，以裸露出目标位线上端面。
S53、在刻蚀后表面沉积第一绝缘层，并在第一绝缘层之上沉积第一氧化层。
具体实施时，如图12所示，在刻蚀后表面沉积第一绝缘层312，并在第一绝缘层表面沉积第一氧化层313，以缩小目标位线接触孔311的尺寸，降低 目标位线接触孔直接的寄生电容。其中，第一绝缘层312与隔离层34的上层结构34-3、隔离层34的上层结构34-1的材质相同，均可采用氮化硅，第一氧化层313和第二氧化层37的材质相同，均可采用二氧化硅，本申请实施例对此不作限定。
S54、去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，保留各侧面的第一绝缘层和第一氧化层，以裸露出所述目标位线上端面。
具体实施时，如图13所示，去除沉积后各水平上端面以上部分的第一绝缘层312和第一氧化层313，保留各侧面的第一绝缘层312和第一氧化层313，以裸露出各目标位线上端面，从而生成目标位线接触孔314，这样，目标位线接触孔314即与目标位线连通。
半导体结构中，字线32埋入隔离结构33-1之中，在远离隔离结构33-1的方向具有第三绝缘层315。
当待制备的目标接触孔为目标字线接触孔时，对应的制备字线接触孔的半导体结构的初始截面图如图14所示，按照如图15所示的流程制备字线接触孔，可以包括以下步骤：
S61、在第三绝缘层的上端面生成掩膜层，在掩膜层上曝光出目标字线接触孔图形。
具体实施时，如图16所示，在第三绝缘层315的上端面生成掩膜层316，在掩膜层316上曝光出目标字线接触孔图形317，掩膜层316包括第一掩膜层316-1和第二掩膜层316-2。
在具体实施过程中，在第三绝缘层315上端面沉积第一掩膜层316-1，并在第一掩膜层316-1上端面沉积第二掩膜层316-2，利用光刻胶318在第二掩膜层316-2上曝光出目标字线接触孔图形317，在曝光目标字线接触孔图形317时，可以将目标字线接触孔图形317的尺寸(即直径)设置为稍大于现有工艺尺寸，以使得对应的目标字线接触孔的开孔尺寸(即字线接触孔的直径)大于现有工艺尺寸，尺寸的设置可根据实际情况自行设置，这样，可降低工艺难度。第一掩膜层316-1的材质可以为碳，第二掩膜层316-2的材质可以为 氮氧化硅。
S62、按照目标字线接触孔图形从第三绝缘层向下进行刻蚀，以裸露出目标字线上端面。
具体实施时，如图17所示，按照目标字线接触孔图形317从第三绝缘层315向下进行刻蚀，形成目标字线接触孔319，以裸露出目标字线上端面。
S63、在刻蚀后表面沉积第一绝缘层，并在第一绝缘层之上沉积第一氧化层。
具体实施时，如图18所示，在刻蚀后表面沉积第一绝缘层320，并在第一绝缘层表面沉积第一氧化层321，以缩小目标位线接触孔319的尺寸，降低目标位线接触孔直接的寄生电容。其中，第一绝缘层320与隔离层34的上层结构34-3、隔离层34的上层结构34-1的材质相同，均可采用氮化硅，第一氧化层321和第二氧化层37的材质相同，均可采用二氧化硅，本申请实施例对此不作限定。第三绝缘层315和第一绝缘层320、隔离层34的上层结构34-3、隔离层34的上层结构34-1的材质相同，均可为氮化硅。
S64、去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，保留各侧面的第一绝缘层和第一氧化层，以裸露出目标字线上端面。
具体实施时，如图19所示，去除沉积后各水平上端面以上部分的第一绝缘层320和第一氧化层321，保留各侧面的第一绝缘层320和第一氧化层321，以裸露出目标字线上端面，从而生成目标字线接触孔322，以使目标字线接触孔322与目标字线连通。
当待制备的目标接触孔为目标有源区接触孔时，对应的制备有源区接触孔的半导体结构的初始截面图如图20所示，按照如图21所示的流程制备有源区接触孔，可以包括以下步骤：
S71、在隔离层的上层结构的上端面生成掩膜层，在掩膜层上曝光出目标有源区接触孔图形。
具体实施时，如图22所示，在隔离层34的上层结构34-3的上端面生成掩膜层323，在掩膜层323上曝光出目标有源区接触孔图形324，掩膜层323 包括第一掩膜层323-1和第二掩膜层323-2。
在具体实施过程中，在隔离层34的上层结构34-3的上端面沉积第一掩膜层323-1，并在第一掩膜层323-1上端面沉积第二掩膜层323-2，利用光刻胶325在第二掩膜层323-2上曝光出目标有源区接触孔图形324，在曝光目标有源区接触孔图形324时，可以将目标字线接触孔图形324的尺寸(即直径)设置为稍大于现有工艺尺寸，以使得对应的目标有源区接触孔的开孔尺寸(即有源区接触孔的直径)大于现有工艺尺寸，尺寸的设置可根据实际情况自行设置，这样，即可降低工艺难度。第一掩膜层323-1的材质可以为碳，第二掩膜层323-2的材质可以为氮氧化硅。
S72、按照目标有源区接触孔图形对隔离层的上层结构、隔离层的中层结构和隔离层的下层结构进行刻蚀，以裸露出目标有源区接触上端面。
具体实施时，如图23所示，按照目标有源区接触孔图形324对隔离层34的上层结构34-3、隔离层34的中层结构34-2和隔离层34的下层结构34-1进行刻蚀，形成目标有源区接触孔326，以裸露出目标有源区接触上端面。
S73、在刻蚀后表面沉积第一绝缘层，并在第一绝缘层之上沉积第一氧化层。
具体实施时，如图24所示，在刻蚀后表面沉积第一绝缘层327，并在第一绝缘层表面沉积第一氧化层328，以缩小目标有源区接触孔326的尺寸，降低目标有源区接触孔直接的寄生电容。其中，第一绝缘层327与隔离层34的上层结构34-3、隔离层34的上层结构34-1的材质相同，均可采用氮化硅，第一氧化层328和第二氧化层37的材质相同，均可采用二氧化硅，本申请实施例对此不作限定。
S74、去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，保留各侧面的第一绝缘层和第一氧化层，以裸露出目标有源区接触上端面。
具体实施时，如图25所示，去除沉积后各水平上端面以上部分的第一绝缘层327和第一氧化层328，保留各侧面的第一绝缘层327和第一氧化层328，以裸露出目标有源区接触上端面，从而生成目标有源区接触孔329，以使目标 有源区接触孔329与目标有源区连通。
半导体结构的栅极结构35的顶面和侧壁还包括绝缘盖层330。
当待制备的目标接触孔为目标栅极接触孔时，对应的制备栅极接触孔的半导体结构的初始截面图如图26所示，按照如图27所示的流程制备栅极接触孔，可以包括以下步骤：
S81、在隔离层的上层结构的上端面生成掩膜层，在掩膜层上曝光出目标栅极接触孔图形。
具体实施时，如图28所示，在隔离层34的上层结构34-3的上端面生成掩膜层331，在掩膜层331上曝光出目标栅极接触孔图形332，掩膜层331包括第一掩膜层331-1和第二掩膜层331-2。
具体地，在隔离层34的上层结构34-3的上端面沉积第一掩膜层331-1，并在第一掩膜层331-1上端面沉积第二掩膜层331-2，利用光刻胶333在第二掩膜层331-2上曝光出目标栅极接触孔图形332，在曝光目标栅极接触孔图形332时，可以将目标栅极接触孔图形332的尺寸(即直径)设置为稍大于现有工艺尺寸，以使得对应的目标栅极接触孔的开孔尺寸(即栅极接触孔的直径)大于现有工艺尺寸，尺寸的设置可根据实际情况自行设置，这样，即可降低工艺难度。第一掩膜层331-1的材质可以为碳，第二掩膜层331-2的材质可以为氮氧化硅。
S82、按照目标栅极接触孔图形对隔离层的上层结构、绝缘盖层进行刻蚀，以裸露出目标栅极上端面。
具体实施时，如图29所示，按照目标栅极接触孔图形332对隔离层34的上层结构34-3、绝缘盖层330进行刻蚀，形成目标栅极接触孔334，以裸露出目标栅极上端面。
S83、在刻蚀后表面沉积第一绝缘层，并在第一绝缘层之上沉积第一氧化层。
具体实施时，如图30所示，在刻蚀后表面沉积第一绝缘层335，并在第一绝缘层表面沉积第一氧化层336，以缩小目标栅极接触孔334的尺寸，降低 目标栅极接触孔直接的寄生电容。其中，第一绝缘层335、绝缘盖层330与隔离层34的上层结构34-3、隔离层34的上层结构34-1的材质相同，均可采用氮化硅，第一氧化层336和第二氧化层37的材质相同，均可采用二氧化硅，本申请实施例对此不作限定。
S84、去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，保留各侧面的第一绝缘层和第一氧化层，以裸露出目标栅极上端面。
具体实施时，如图31所示，去除沉积后各水平上端面以上部分的第一绝缘层335和第一氧化层336，保留各侧面的第一绝缘层335和第一氧化层336，以裸露出目标栅极上端面，从而生成目标栅极有源区接触孔337，以使目标栅极接触孔337与目标栅极相连通。
本申请实施例提供的上述位线接触孔制备方法、字线接触孔制备方法、有源区接触孔制备方法和栅极接触孔制备方法，首先将目标接触孔的尺寸做大，再采用沉积一层绝缘层和一层氧化层的方式缩小目标接触孔的尺寸，这样，既避免了由于接触孔的尺寸过小而引起的刻蚀不足的风险，又避免了由于接触孔的尺寸过大而导致的短路问题，并降低了半导体制程工艺难度，并且，有效降低了工艺过程中对有源区的硅的损伤。
基于同一发明构思，本申请实施例还提供了一种半导体结构，所述半导体结构为根据本申请实施例提供的接触孔制备方法制备的半导体结构。
基于同一技术构思，本申请实施例还提供了一种电子设备，包括本申请实施例提供的上述半导体结构。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (17)

  1. 一种接触孔制备方法，应用于半导体结构，所述半导体结构包括阵列区和外围区，所述阵列区的基底上包括埋入式字线、第一绝缘层、所述第一绝缘层在远离所述埋入式字线的方向具有存储电容阵列和接触层，所述接触层覆盖所述存储电容阵列，所述外围区的基底设置有有源区，在远离所述有源区的方向具有隔离层和栅极结构，所述隔离层覆盖所述栅极结构，所述隔离层包括下层结构、中层结构和上层结构，所述栅极结构的两侧包括第零层接触，所述第零层接触顶部低于所述上层结构上端面，在远离所述接触层和所述上层结构的方向具有第一氧化层，所述方法，包括：
    在所述第一氧化层上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形；
    按照所述目标接触孔图形对所述第一氧化层进行刻蚀，以裸露出所述目标接触孔位置对应的所述接触层上端面，以及所述目标接触孔位置对应的所述上层结构上端面；
    在刻蚀后表面沉积第二绝缘层，并在所述第二绝缘层之上沉积第二氧化层；
    去除所述第一氧化层上端面以上部分的第二绝缘层和第二氧化层，并从裸露出的所述接触层上端面向下刻蚀以去除部分所述接触层，以及从裸露出的所述上层结构上端面向下刻蚀以裸露出所述第零层接触上端面。
  2. 如权利要求1所述的方法，其中，所述掩膜层包括第一掩膜层和第二掩膜层；
    在所述第一氧化层上端面生成掩膜层，具体包括：
    在所述第一氧化层上端面生成第一掩膜层，并在所述第一掩膜层上端面生成第二掩膜层。
  3. 如权利要求2所述的方法，其中，所述第一掩膜层的材质为碳，所述第二掩膜层的材质为氮氧化硅。
  4. 如权利要求1所述的方法，其中，所述第一绝缘层、所述上层结构、所述下层结构和所述第二绝缘层的材质相同。
  5. 如权利要求1所述的方法，其中，所述第二氧化层和所述第一氧化层的材质相同。
  6. 如权利要求1所述的方法，其中，所述第二氧化层的材质为二氧化硅。
  7. 如权利要求1所述的方法，其中，所述第二绝缘层的材质为氮化硅。
  8. 如权利要求1所述的方法，其中，对所述第一绝缘层上端面以上部分的第二绝缘层和第二氧化层的去除采用干法刻蚀工艺。
  9. 一种接触孔制备方法，应用于半导体结构，所述半导体结构的基底上制备有位线、字线、有源区及位于相邻有源区之间的隔离结构，在远离所述有源区的方向具有隔离层和栅极结构，所述隔离层覆盖所述栅极结构，所述隔离层包括下层结构、中层结构和上层结构，所述方法，包括：
    针对待制备接触孔，在对应的目标上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形，所述目标接触孔包括目标位线接触孔、目标字线接触孔、目标有源区接触孔和目标栅极接触孔，所述目标位线接触孔表征用于与所述位线相连接的接触孔，所述目标字线接触孔表征用于与所述字线相连接的接触孔，所述目标有源区接触孔表征用于与所述有源区相连接的接触孔，所述目标栅极接触孔表征用于与所述栅极结构的栅极相连接的接触孔；
    按照所述目标接触孔图形进行刻蚀，以裸露出所述目标接触孔位置对应的目标接触面，所述目标接触面包括目标位线上端面、目标字线上端面、目标有源区上端面和目标栅极上端面；
    在刻蚀后表面沉积第一绝缘层，并在所述第一绝缘层之上沉积第一氧化层；
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，以裸露出所述目标接触面。
  10. 如权利要求9所述的方法，其中，所述半导体结构还包括设置于所述位线顶部和侧边的第二绝缘层，所述基底上设置有第二氧化层，所述第二 氧化层覆盖所述第二绝缘层和所述位线，所述第二氧化层的上端面高于所述第二绝缘层的上端面；
    当所述目标接触孔为目标位线接触孔时，在对应的目标上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形，具体包括：
    在所述第二氧化层的上端面生成掩膜层，在所述掩膜层上曝光出所述目标位线接触孔图形；
    按照所述目标接触孔图形进行刻蚀，以裸露出所述目标接触孔位置对应的目标接触面，具体包括：
    按照所述目标位线接触孔图形对所述第二氧化层和所述第二绝缘层进行刻蚀，以裸露出所述目标位线上端面；
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，以裸露出所述目标接触面，具体包括：
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，保留各侧面的第一绝缘层和第一氧化层，以裸露出所述目标位线上端面。
  11. 如权利要求9所述的方法，其中，所述字线埋入所述隔离结构之中，在远离所述隔离结构的方向具有第三绝缘层；
    当所述目标接触孔为目标字线接触孔时，在对应的目标上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形，具体包括：
    在所述第三绝缘层的上端面生成掩膜层，在所述掩膜层上曝光出所述目标字线接触孔图形；
    按照所述目标接触孔图形进行刻蚀，以裸露出所述目标接触孔位置对应的目标接触面，具体包括：
    按照所述目标字线接触孔图形从所述第三绝缘层向下进行刻蚀，以裸露出所述目标字线上端面；
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，以裸露出所述目标接触面，具体包括：
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，保留各 侧面的第一绝缘层和第一氧化层，以裸露出所述目标字线上端面。
  12. 如权利要求9所述的方法，其中，
    当所述目标接触孔为目标有源区接触孔时，在对应的目标上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形，具体包括：
    在所述上层结构的上端面生成掩膜层，在所述掩膜层上曝光出所述目标有源区接触孔图形；
    按照所述目标接触孔图形进行刻蚀，以裸露出所述目标接触孔位置对应的目标接触面，具体包括：
    按照所述目标有源区接触孔图形对所述上层结构、所述中层结构和所述下层结构进行刻蚀，以裸露出所述目标有源区接触上端面；
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，以裸露出所述目标接触面，具体包括：
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，保留各侧面的第一绝缘层和第一氧化层，以裸露出所述目标有源区接触上端面。
  13. 如权利要求9所述的方法，其中，所述栅极结构的顶面和侧壁还包括绝缘盖层；
    当所述目标接触孔为目标栅极接触孔时，在对应的目标上端面生成掩膜层，在所述掩膜层上曝光出目标接触孔图形，具体包括：
    在所述上层结构的上端面生成掩膜层，在所述掩膜层上曝光出所述目标栅极接触孔图形；
    按照所述目标接触孔图形进行刻蚀，以裸露出所述目标接触孔位置对应的目标接触面，具体包括：
    按照所述目标栅极接触孔图形对所述上层结构、所述绝缘盖层进行刻蚀，以裸露出所述目标栅极上端面；
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，以裸露出所述目标接触面，具体包括：
    去除沉积后各水平上端面以上部分的第一绝缘层和第一氧化层，保留各 侧面的第一绝缘层和第一氧化层，以裸露出所述目标栅极上端面。
  14. 如权利要求9～13任一项所述的方法，其中，所述第一氧化层的材质为二氧化硅。
  15. 如权利要求9～13任一项所述的方法，其中，所述第一绝缘层的材质为氮化硅。
  16. 一种半导体结构，所述半导体结构为根据权利要求1～8或9～15任一项所述的接触孔制备方法制备的半导体结构。
  17. 一种电子设备，包括如权利要求16所述的半导体结构。
PCT/CN2021/112142 2021-08-09 2021-08-11 一种接触孔制备方法、半导体结构及电子设备 Ceased WO2023015502A1 (zh)

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