WO2023010809A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023010809A1
WO2023010809A1 PCT/CN2022/070757 CN2022070757W WO2023010809A1 WO 2023010809 A1 WO2023010809 A1 WO 2023010809A1 CN 2022070757 W CN2022070757 W CN 2022070757W WO 2023010809 A1 WO2023010809 A1 WO 2023010809A1
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Prior art keywords
word line
conductive layer
layer
semiconductor structure
resistance
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PCT/CN2022/070757
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English (en)
French (fr)
Inventor
刘翔
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长鑫存储技术有限公司
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Priority to EP22712490.6A priority Critical patent/EP4152392A4/en
Priority to JP2023535878A priority patent/JP2023553175A/ja
Priority to KR1020237021809A priority patent/KR20230108343A/ko
Priority to US17/658,427 priority patent/US20230043347A1/en
Publication of WO2023010809A1 publication Critical patent/WO2023010809A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
  • DRAM Dynamic random access memory
  • each memory cell usually includes a capacitor structure and a transistor, the gate of the transistor is composed of a word line, the drain is connected to the bit line, and the source Connected to the capacitor structure; the voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor structure through the bit line, or write the data information into the capacitor structure through the bit line for storage.
  • the gate of the transistor is composed of a word line, and is buried in a word line trench in the substrate.
  • the base includes a P-type substrate and an N-type doped region located on the surface layer of the P-type substrate.
  • the part close to the word line trench is used as the channel region of the transistor, the N-type doped regions on both sides of the word line trench are the source region and the drain region of the transistor, and the gate word line and the source/drain region are respectively in the word line
  • the projected portion on the sidewall of the line trench forms an overlapping region where electrons are attracted when the gate word line of the transistor is in the on state, the larger the overlapping region, the source/drain region and the channel
  • the smaller the on-resistance of the region the larger the drive current of the transistor. correct
  • embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which can increase the driving current of the transistor and improve the GIDL leakage phenomenon, thereby improving the reliability of the semiconductor structure.
  • An embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate having several word line trenches and source/drain regions adjacent to each word line trench; a gate word line located in the word line trench;
  • the gate word line includes a first conductive layer, a single conduction layer and a second conductive layer stacked in sequence, the first conductive layer is located at the bottom of the word line trench, and the gate word line is located at the bottom of the word line trench.
  • the projection on the sidewall of the word line trench and the projection of the source/drain region on the sidewall of the word line trench have an overlapping area of a preset height, when the voltage applied to the gate word line is less than When the voltage is preset, the resistance of the single conduction layer is greater than the preset resistance, so that the first conductive layer and the second conductive layer are not conducted.
  • At least part of the projection of the second conductive layer on the sidewall of the word line trench is located within the projection of the source/drain region on the sidewall of the word line trench .
  • the top of the first conductive layer is lower than the bottom of the source/drain region.
  • the top of the second conductive layer is flush with the top of the source/drain region.
  • the projection of the source/drain region on the sidewall of the word line trench covers the projection of the second conductive layer on the sidewall of the word line trench.
  • the preset resistance is a critical resistance for conduction between the first conductive layer and the second conductive layer.
  • the single conduction layer includes a first resistance and a second resistance, the first resistance is greater than the second resistance, and when the single conduction layer is in the conduction state, the single conduction layer The resistance of the conduction layer is the second resistance; when the single conduction layer is in an off state, the resistance of the single conduction layer is the first resistance.
  • the conduction current of the single conduction layer is greater than or equal to 10 -4 A, and the conduction voltage is greater than or equal to 1.2V.
  • the single conduction layer is an OTS gate material layer.
  • the single conduction layer is a silicon telluride (SiTe) layer.
  • the thickness of the single conduction layer is 5nm-25nm.
  • the thickness of the single conduction layer is 15 nm.
  • the first conductive layer and/or the second conductive layer is a conductive metal layer.
  • the first conductive layer and/or the second conductive layer is a tungsten (W) layer.
  • the gate word line includes a first conductive layer, a single conductive layer and a second conductive layer stacked in sequence, wherein the first conductive layer is located at the bottom of the word line trench, and when the single conductive layer
  • the first conductive layer and the second conduction layer are conducted through a single conduction layer, and the overlapping region of the source/drain region and the gate word line will attract electrons in the doped region of the substrate, reducing the source /The resistance of the overlapping region of the drain region and the gate word line, thereby increasing the driving current of the transistor; and when the single conduction layer is in the off state, the first conductive layer and the second conductive layer are not conducted, so that the second conductive layer
  • the voltage of the second conductive layer is 0v, and the second conductive layer can significantly reduce the electric field strength in the overlapping area, improve the phenomenon of electron tunneling between the gate word line and the source/drain to form a current
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which includes: providing a substrate, forming several word line trenches and source/drain regions adjacent to each of the word line trenches on the substrate; A first conductive layer is formed in the word line trench; a single conduction layer is formed on the first conduction layer; a second conduction layer is formed on the single conduction layer, the first conduction layer, the The single conduction layer and the second conductive layer form a gate word line, and the projection of the gate word line on the sidewall of the word line trench is the same as that of the source/drain region on the word line The projections on the sidewalls of the grooves have an overlapping area of a predetermined height.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in the related art
  • FIG. 2 is a schematic diagram of the relationship between driving current and GIDL leakage after increasing the height of the overlapping region of the gate word line and the source/drain region in the semiconductor structure;
  • FIG. 3 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a usage state of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a usage state of the gate word line in FIG. 3;
  • FIG. 6 is a schematic diagram of another usage state of the gate word line in FIG. 3;
  • FIG. 7 is a schematic diagram of the relationship between the voltage value and the resistance value of the single conduction layer in the on-state and off-state provided by the embodiment of the present disclosure
  • FIG. 8 is a schematic flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure.
  • the reason for this problem is that as shown in FIG. 1 , the top of the gate word line 200 is reduced
  • the distance from the upper surface of the substrate 100 (represented by H in the disclosed embodiment) increases the overlapping area of the projections of the gate word line 200 and the source/drain region 102 respectively on the sidewall of the word line trench 101 ( In the embodiment of the present disclosure, the overlapping region is denoted by A).
  • the gate word line 200 is turned on, the overlapping region A will attract electrons in the doped region of the substrate 100 to reduce the source/drain region 102 and the gate word line.
  • the resistance of the overlapping area A of the line 200 increases the driving current of the transistor.
  • the gate word line includes a first conductive layer, a single conduction layer, and a second conductive layer that are sequentially stacked, wherein the first A conductive layer is located at the bottom of the word line trench.
  • the first conduction layer and the second conduction layer are conducted through the single conduction layer, and the source/drain region and the gate word line
  • the overlapping region A will attract the electrons in the base doped region, reduce the resistance of the overlapping region A between the source/drain region and the gate word line, thereby increasing the drive current of the transistor; and when the single conduction layer is in the off state, the second The first conductive layer and the second conductive layer are not conducting, so the voltage of the second conductive layer is 0v, and the second conductive layer can obviously reduce the electric field strength in the overlapping area A, and improve the connection between the gate word line and the source/drain. Electron tunneling occurs to form a current, thereby improving the GIDL leakage phenomenon.
  • FIG. 3 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a usage state of the semiconductor structure provided by an embodiment of the disclosure
  • FIG. 5 is a schematic diagram of a usage status of a gate word line in FIG. 3
  • FIG. 6 is a schematic diagram of another usage state of the gate word line in FIG. 3 .
  • the semiconductor structure provided by the embodiment of the present disclosure includes: a substrate 100 and a gate word line 200 .
  • the substrate 100 has several word line trenches 101 and source/drain regions 102 adjacent to each word line trench 101 .
  • the substrate 100 can be a crystalline semiconductor material, such as a silicon (Si) substrate 100, and the substrate 100 can also be a germanium (Ge) substrate 100, silicon on insulator (Silicon on Insulator, SOI for short), silicon germanium (SiGe) substrate 100, carbonized
  • SiC silicon on insulator
  • GaN gallium nitride
  • the substrate 100 includes a core area and a peripheral area located around the core area.
  • the core area includes multiple active areas and shallow trench isolation areas for isolating the multiple active areas.
  • the multiple active areas may be arranged in an array.
  • capacitors are subsequently formed above the core area of the substrate 100
  • peripheral circuits such as transistors, are subsequently formed above the peripheral area of the substrate 100 .
  • Word line trenches 101 are formed in each active region, and a semiconductor layer may be disposed in the substrate 100.
  • the substrate 100 includes a P-type substrate 100 and an N-type doped region located on the surface layer of the P-type substrate 100.
  • the part close to the word line groove is used as the channel region of the transistor, and the N-type doped regions on both sides of the word line groove are used as the source region and the drain region of the transistor.
  • the gate word line 200 is located in the word line trench 101; the gate word line 200 includes a first conductive layer 201, a single conductive layer 202 and a second conductive layer 203 which are stacked in sequence, and the first conductive layer 201 is located in the word line trench.
  • the projection of the gate word line 200 on the side wall of the word line trench 101 and the projection of the source/drain region 102 on the side wall of the word line trench 101 have an overlapping area A of a preset height, When the voltage applied to the gate word line 200 is less than the preset voltage, the resistance of the single conduction layer is greater than the preset resistance, so that the first conductive layer 201 and the second conductive layer 203 are not conducted.
  • the gate word line 200 and the source/drain region 102 are enlarged The height of the projected overlapping area A on the sidewall of the word line trench, thereby increasing the driving current; and when the voltage applied to the gate word line 200 is less than the preset voltage, the resistance of the single conduction layer 202 is greater than the preset resistance , as shown in FIG. 4 and FIG. 6, the single conduction layer 202 is in an off state, and the single conduction layer 202 is used to block the first conductive layer 201 and the second conductive layer 203, so that the first conductive layer 201 and the second The conductive layer 203 is not conducting.
  • the gate word line 200 in the c diagram in FIG. 6 is equivalent to the d diagram in FIG.
  • the electric field intensity of the projected overlapping area A of the gate word line 200 and the source/drain region 102 on the sidewall of the word line trench is reduced, thereby improving the GIDL leakage phenomenon.
  • the first conduction layer 201 and the second conduction layer 203 conduct through the single conduction layer 202, and the source/drain region 102 and the gate word line 200
  • the overlapping region A will attract electrons in the doped region of the substrate 100, reduce the resistance of the overlapping region A between the source/drain region 102 and the gate word line 200, thereby increasing the driving current of the transistor; state, the first conductive layer 201 and the second conductive layer 203 are not conducting, so that the voltage of the second conductive layer 203 is 0v, and the second conductive layer 203 can obviously reduce the electric field intensity in the overlapping area A, and improve the gate word Electron tunneling occurs between the line 200 and the source/drain to form a current, thereby improving the GIDL leakage phenomenon.
  • the height of the overlapping region A of the projection of the gate word line 200 and the source/drain region 102 on the side wall of the word line trench is set for the purpose of increasing the driving current of the transistor in the semiconductor structure. , and its specific size is not specifically limited in this embodiment.
  • the preset voltage can be 1.2V, when the voltage applied by the gate word line 200 is less than 1.2V, the resistance of the single conduction layer 202 is greater than the preset resistance, so that the first conductive layer 201 and the second conductive layer 203 are not conduction.
  • At least part of the projection of the second conductive layer 203 on the sidewall of the word line trench 101 is located within the projection of the source/drain region 102 on the sidewall of the word line trench 101 .
  • the second conductive layer 203 refers to part of the second conductive layer 203 or the entire conductive layer, and the overlapping area A of the gate word line 200 and the source/drain region 102 includes at least part of the second conductive layer 203 , so that when the single conduction layer 202 is in the cut-off state, the first conduction layer 201 and the second conduction layer 203 are not conducting, the voltage of the second conduction layer 203 is 0v, and the second conduction layer 203 can shield the first conduction layer
  • the electric field near 201 improves the phenomenon of electron tunneling between the gate word line 200 and the drain to form a current, thereby improving the GIDL leakage phenomenon.
  • the top of the first conductive layer 201 is lower than the bottom of the source/drain region 102 .
  • the overlapping region A of the gate word line 200 and the source/drain region 102 is the second conductive layer 203 or the second conductive layer 203 and the single conduction layer 202, when the single conduction layer 202 is in the cut-off state, the distance from the electrons near the first conductive layer 201 to the source/drain region 102 is far, and the second conduction layer
  • the layer 203 can shield the electric field near the first conductive layer 201, reduce the electric field strength in the overlapping region A between the gate word line 200 and the source/drain region 102, and avoid the formation of current by electron tunneling with the source/drain region 102 , so as to improve the GIDL leakage phenomenon while increasing the driving current of the transistor.
  • the top of the second conductive layer 203 is flush with the top of the source/drain region 102 .
  • the height of the overlapping region A between the gate word line 200 and the source/drain region 102 can be increased, thereby increasing
  • the overlapping region A mainly includes the second conductive layer 203, in this way, when the single conduction layer 202 is in the cut-off state, the distance between the electrons near the first conductive layer 201 and the source/drain region 102 Far away, and the second conductive layer 203 can shield the electric field near the first conductive layer 201, reduce the electric field intensity of the overlapping area A between the gate word line 200 and the source/drain region 102, and avoid contact with the source/drain region 102 Electron tunneling occurs to form a current, so as to improve the leakage phenomenon of GIDL while increasing the driving current of the transistor.
  • the projection of the source/drain region 102 on the sidewall of the word line trench 101 covers the projection of the second conductive layer 203 on the sidewall of the word line trench 101, thus, in increasing While reducing the drive current of the transistor, the GIDL leakage phenomenon can be improved.
  • the resistance of the single conduction layer 202 is greater than the preset resistance, so that the first conductive layer 201 and the second conductive layer 203 are not conducted.
  • the preset resistance is the critical resistance for conducting the first conductive layer 201 and the second conductive layer 203 .
  • the single conduction layer 202 includes a first resistance and a second resistance, and the resistance value of the single conduction layer 202 can vary between the first resistance and the second resistance under different voltages, wherein , the first resistance is greater than the second resistance, when the single conduction layer 202 is in the conduction state, the resistance of the single conduction layer 202 is the second resistance; when the single conduction layer 202 is in the cut-off state, the resistance of the single conduction layer 202
  • the resistor is a first resistor.
  • the first resistor is a high-resistance resistor, and the resistance value is greater than the on-resistance of the first conductive layer 201 and the second conductive layer 203, so as to The first conductive layer 201 and the second conductive layer 203 are blocked by the single conductive layer 202.
  • the voltage of the second conductive layer 203 is 0v, so that the second conductive layer 203 can be used to shield the gate word line 200 electric field, thereby reducing the electric field between the gate word line 200 and the source/drain region 102, thereby improving GIDL leakage; and when the voltage applied to the gate word line 200 is greater than a preset voltage, the second resistor is a low-resistance resistor, which The resistance value is less than the on-resistance of the first conductive layer 201 and the second conductive layer 203, so as to conduct the first conductive layer 201 and the second conductive layer 203 through the single conductive layer 202, so as to increase the connection between the gate word line 200 and the source / the height of the overlapping region A of the drain region 102, thereby increasing the driving current of the transistor.
  • the gate word line 200 when the voltage applied to the first conductive layer 201 is 3v, the single conduction layer 202 is turned on in a low-resistance state.
  • the gate word line 200 includes the first conductive layer 201, the single conduction layer 202 and The second conductive layer 203, and the first conductive layer 201 and the second conductive layer 203 are conducted through the single conductive layer 202, so as to increase the height of the overlapping area A of the gate word line 200 and the source/drain region 102, thereby Increase the drive current; and when the voltage applied to the first conductive layer 201 is -0.2v, the single conduction layer 202 is blocked in a high-resistance state, and at this time, the gate word line 200 includes the first conductive layer 201, reducing The height of the overlapping area A between the gate word line 200 and the source/drain region 102 is increased, and the second conductive layer 203 can also be used to shield the electric field of the gate word line 200, thereby reducing the contact between the
  • FIG. 7 is a schematic diagram of the relationship between the voltage value and the resistance value of the single conduction layer in the on state and the off state provided by the embodiment of the present disclosure.
  • the conduction current of the single conduction layer 202 is greater than or equal to 10 -4 A, and the conduction voltage is greater than or equal to 1.2V, so that the first conduction layer 201 and the second conduction layer 202 are conducted through the single conduction layer 202.
  • the single conduction layer 202 is a bidirectional threshold switching (Ovonic threshold switching, OTS for short) gating material layer.
  • the single conduction layer 202 may be a silicon telluride (SiTe) layer
  • the first conduction layer 201 and the second conduction layer 203 may be conduction metal layers, for example, the first conduction layer 201 and the second conduction layer 203 are Metal tungsten (W) layer.
  • the thickness of the single conduction layer 202 may be 5nm-25nm, wherein the thickness of the single conduction layer 202 is different, and its resistance value is different.
  • the resistance value of the single conduction layer 202 in the off state can be 6 times the resistance value in the state, as shown in Figure 7, the current value changes from 10 -10 A to 10 -4 A.
  • the gate word line includes a first conductive layer, a single conductive layer and a second conductive layer stacked in sequence, wherein the first conductive layer is located at the bottom of the word line trench, and when the single conductive layer When the pass layer is in the conduction state, the first conductive layer and the second conduction layer are conducted through a single conduction layer, and the overlapping region A of the source/drain region and the gate word line will attract electrons in the doped region of the base, reducing the source /The resistance of the overlapping region A of the drain region and the gate word line, thereby increasing the driving current of the transistor; and when the single conduction layer is in the cut-off state, the first conductive layer and the second conductive layer are not conducting, so, The voltage of the second conductive layer is 0v, the second conductive layer can reduce the electric field strength in the overlapping area A, improve the phenomenon of electron tunneling between the gate word line and the source/drain to form a current, thereby
  • FIG. 8 is a schematic flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a method for fabricating a semiconductor structure, the steps of which include:
  • Step S101 Provide a substrate, and form several word line trenches and source/drain regions adjacent to each word line trench on the substrate.
  • Step S102 forming a first conductive layer in the word line trench.
  • Step S103 forming a single conduction layer on the first conductive layer.
  • Step S104 forming a second conductive layer on the single conduction layer, wherein the first conductive layer, the single conduction layer and the second conductive layer form a gate word line, and the gate word line is on the sidewall of the word line trench
  • the projection of and the projection of the source/drain region on the sidewall of the word line trench have an overlap area of a preset height.
  • the single conduction layer when the voltage applied to the gate word line is less than the preset voltage, the resistance of the single conduction layer is greater than the preset resistance, and the single conduction layer is in an off state, and the single conduction layer is used to block the first conduction layer and the second conduction layer.
  • conductive layer so that the first conductive layer and the second conductive layer are not conducting; and when the voltage applied to the single conductive layer is greater than the preset voltage, the resistance of the single conductive layer is less than the preset resistance, and the single conductive layer is in the conductive state. state, the single conduction layer is used to conduct the first conduction layer and the second conduction layer.
  • the method for manufacturing a semiconductor structure includes: providing a substrate, forming several word line trenches and source/drain regions adjacent to each word line trench on the substrate; form a first conductive layer; form a single conduction layer on the first conduction layer; form a second conduction layer on the single conduction layer, the first conduction layer, the single conduction layer and the second conduction layer form a gate word line , wherein the first conductive layer is located at the bottom of the word line trench, when the single conductive layer is in the conduction state, the first conductive layer and the second conductive layer are conducted through the single conductive layer, and the source/drain region and the gate
  • the overlapping area of the pole word line will attract the electrons in the doped region of the base, reduce the resistance of the overlapping area of the source/drain area and the gate word line, thereby increasing the drive current of the transistor; and when the single conduction layer is in the off state , the first conductive layer and the second conductive layer are not conducting, so that the

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Abstract

本公开提供一种半导体结构及其制作方法，涉及半导体领域，解决漏电现象严重的问题，该半导体结构包括：基底，具有若干个字线沟槽以及与各字线沟槽相邻的源/漏极区域；栅极字线，位于字线沟槽内；栅极字线包括依次层叠设置的第一导电层、单导通层和第二导电层，第一导电层位于字线沟槽的底部，栅极字线在字线沟槽的侧壁上的投影与源/漏极区域在字线沟槽的侧壁上的投影具有预设高度的重叠区域，当栅极字线施加电压小于预设电压时，单导通层的电阻大于预设电阻，以使第一导电层和第二导电层不导通。本公开提供的半导体结构用于增大驱动电流的同时，改善漏电现象。

Description

半导体结构及其制作方法
本公开要求于2021年08月06日提交中国专利局、申请号为2021109045510、申请名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称DRAM)由多个重复的存储单元组成，每个存储单元通常包括电容结构和晶体管，晶体管的栅极由字线构成，漏极与位线相连、源极与电容结构相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容结构中的数据信息，或者通过位线将数据信息写入到电容结构中进行存储。
相关技术中，晶体管的栅极由字线构成，并埋设在基底中的字线沟槽中，基底包括P型衬底和位于P型衬底表层的N型掺杂区，P型衬底中靠近字线沟槽的部分作为晶体管的沟道区域，字线沟槽两侧的N型掺杂区为晶体管的源极区域和漏极区域，栅极字线和源/漏极区域分别在字线沟槽的侧壁上的投影部分会形成重叠区域，当晶体管的栅极字线处于导通状态时，会在该重叠区域吸引电子，该重叠区域越大，源/漏极区域和沟道区的导通电阻越小，晶体管的驱动电流越大。正确
然而，当晶体管的栅极字线处于关闭状态时，会在该重叠区域形成强电场，吸引隧穿电流，该重叠区域越大，栅诱导漏极泄露(Gate-Induced Drain Ieakage，简称GIDL)漏电的现象越严重。
发明内容
鉴于上述问题，本公开实施例提供一种半导体结构及其制作方法，该半导体结构能够增大晶体管的驱动电流的同时，改善GIDL漏电现象，从而提高半导体结构的可靠性。
为了实现上述目的，本公开实施例提供如下技术方案：
本公开实施例提供一种半导体结构，其包括：基底，具有若干个字线沟槽以及与各字线沟槽相邻的源/漏极区域；栅极字线，位于字线沟槽内；所述栅极字线包括依次层叠设置的第一导电层、单导通层和第二导电层，所述第一导电层位于所述字线沟槽的底部，所述栅极字线在所述字线沟槽的侧壁上的投影与所述源/漏极区域在所述字线沟槽的侧壁上的投影具有预设高度的重叠区域，当所述栅极字线施加电压小于预设电压时，所述单导通层的电阻大于预设电阻，以使所述第一导电层和所述第二导电层不导通。
如上所述的半导体结构，至少部分所述第二导电层在所述字线沟槽的侧壁上的投影位于所述源/漏极区域在所述字线沟槽的侧壁上的投影内。
如上所述的半导体结构，所述第一导电层的顶部低于所述源/漏极区域的底部。
如上所述的半导体结构，所述第二导电层的顶部与所述源/漏极区域的顶部平齐。
如上所述的半导体结构，所述源/漏极区域在所述字线沟槽侧壁上的投影覆盖所述第二导电层在所述字线沟槽侧壁上的投影。
如上所述的半导体结构，所述预设电阻为所述第一导电层和所述第二导电层导通的临界电阻。
如上所述的半导体结构，所述单导通层包括第一电阻和第二电阻，所述第一电阻大于所述第二电阻，当所述单导通层为导通状态时，所述单导通层的电阻为第二电阻；当所述单导通层为截止状态时，所述单导通层的电阻为第一电阻。
如上所述的半导体结构，所述单导通层的导通电流为大于等于10 -4A，导通电压为大于等于1.2V。
如上所述的半导体结构，所述单导通层为OTS选通材料层。
如上所述的半导体结构，所述单导通层为碲化硅(SiTe)层。
如上所述的半导体结构，所述单导通层的厚度为5nm～25nm。
如上所述的半导体结构，所述单导通层的厚度为15nm。
如上所述的半导体结构，所述第一导电层和/或所述第二导电层为导电 金属层。
如上所述的半导体结构，所述第一导电层和/或第二导电层为钨(W)层。
本公开实施例提供的半导体结构，至少具有如下优点：
本公开实施例提供的半导体结构，栅极字线包括依次层叠设置的第一导电层、单导通层和第二导电层，其中，第一导电层位于字线沟槽的底部，当单导通层处于导通状态时，第一导电层和第二导电层通过单导通层导通，源/漏极区域与栅极字线的重叠区域会吸引基底中掺杂区的电子，降低源/漏极区域与栅极字线的重叠区域的电阻，从而增大晶体管的驱动电流；而当单导通层处于截止状态时，第一导电层和第二导电层不导通，这样，第二导电层的电压为0v，第二导电层可以明显减小重叠区域的电场强度，改善栅极字线与源/漏极之间发生电子遂穿而形成电流的现象，从而改善GIDL漏电现象。
本公开实施例还提供一种半导体结构的制作方法，其包括：提供基底，在所述基底上形成若干个字线沟槽以及与各所述字线沟槽相邻的源/漏极区域；在所述字线沟槽中形成第一导电层；在所述第一导电层上形成单导通层；在所述单导通层上形成第二导电层，所述第一导电层、所述单导通层以及所述第二导电层形成栅极字线，所述栅极字线在所述字线沟槽的侧壁上的投影与所述源/漏极区域在所述字线沟槽的侧壁上的投影具有预设高度的重叠区域。
除了上面所描述的本公开实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本公开实施例提供的半导体结构及其制作方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在 不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中半导体结构的结构示意图；
图2为增大半导体结构中栅极字线与源/漏极区域的重叠区域的高度后，驱动电流与GIDL漏电的关系示意图；
图3为本公开实施例提供的半导体结构的结构示意图；
图4为本公开实施例提供的半导体结构的一种使用状态示意图；
图5为图3中栅极字线的一种使用状态示意图；
图6为图3中栅极字线的另一种使用状态示意图；
图7为本公开实施例提供的单导通层在导通和截止状态的电压值和电阻值的关系示意图；
图8为本公开实施例提供的半导体结构的制作方法的流程示意图。
附图标记：
100-基底；
101-字线沟槽；
102-源/漏极区域；
200-栅极字线；
201-第一导电层；
202-单导通层；
203-第二导电层。
具体实施方式
正如背景技术所述，相关技术中动态随机存储器存在GIDL漏电的现象严重的问题，经发明人研究发现，出现这种问题的原因在于：如图1所示，减小栅极字线200的顶部至基底100上表面的距离(在本公开实施例中用H表示)，增大栅极字线200与源/漏极区域102分别在字线沟槽101的侧壁上的投影的重叠区域(在本公开实施例中，重叠区域用A表示)，当栅极字线200导通时，该重叠区域A会吸引基底100掺杂区的电子，以降低源/漏极区域102与栅极字线200的重叠区域A的电阻，从而增大晶体管的驱动电流。
然而，当栅极字线处于截止状态时，在源漏极上施加工作电压，在该重叠区域A附近的电子在栅极和源/漏极之间会因为强电场发生电子遂穿形成 电流，即GIDL漏电，且该重叠区域A的尺寸越大，则GIDL漏电现象越严重，从而导致半导体结构的可靠性低的问题。如图2所示，随着重叠区域A尺寸的增大，引起驱动电流增大，GIDL漏电现象也越来越严重。
针对上述问题，本公开实施例提供一种半导体结构及其制作方法，该半导体结构中，栅极字线包括依次层叠设置的第一导电层、单导通层和第二导电层，其中，第一导电层位于字线沟槽的底部，当单导通层处于导通状态时，第一导电层和第二导电层通过单导通层导通，源/漏极区域与栅极字线的重叠区域A会吸引基底掺杂区的电子，降低源/漏极区域与栅极字线的重叠区域A的电阻，从而增大晶体管的驱动电流；而当单导通层处于截止状态时，第一导电层和第二导电层不导通，这样，第二导电层的电压为0v，第二导电层可以明显减小重叠区域A的电场强度，改善栅极字线与源/漏极之间发生电子遂穿而形成电流的现象，从而改善GIDL漏电现象。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
图3为本公开实施例提供的半导体结构的结构示意图；图4为本公开实施例提供的半导体结构的一种使用状态示意图；图5为图3中栅极字线的一种使用状态示意图；图6为图3中栅极字线的另一种使用状态示意图。
如图3至图6所示，本公开实施例提供的半导体结构，其包括：基底100和栅极字线200。
其中，基底100具有若干个字线沟槽101以及与各字线沟槽101相邻的源/漏极区域102。
基底100可以为晶体半导体材料，例如硅(Si)基底100，基底100还可以为锗(Ge)基底100、绝缘体上硅(Silicon on Insulator，简称SOI)、锗化硅(SiGe)基底100、碳化硅(SiC)或者氮化镓(GaN)基底100等，对此，本公开实施例不做具体限制。
基底100包括核心区和位于核心区外周的外围区，核心区包括多个有源区以及隔离多个有源区的浅沟槽隔离区，多个有源区可以呈阵列排布。
其中，基底100的核心区的上方后续形成有电容器，基底100外围区的上方后续形成有外围电路，例如，晶体管等。
各有源区中形成有字线沟槽101，基底100中可以设置有半导体层，例如，基底100包括P型基底100以及位于P型基底100表层的N型掺杂区，P型基底100中靠近字线沟槽的部分作为晶体管的沟道区域，字线沟槽两侧的N型掺杂区为晶体管的源极区域和漏极区域。
栅极字线200位于字线沟槽101中；栅极字线200包括依次层叠设置的第一导电层201、单导通层202和第二导电层203，第一导电层201位于字线沟槽101的底部，栅极字线200在字线沟槽101的侧壁上的投影与源/漏极区域102在字线沟槽101的侧壁上的投影具有预设高度的重叠区域A，当栅极字线200施加电压小于预设电压时，单导通层的电阻大于预设电阻，以使第一导电层201和第二导电层203不导通。
可以理解的是，如图3和图5所示，当栅极字线200施加电压大于预设电压时，单导通层202的电阻小于预设电阻，第一导电层201和第二导电层203通过单导通层202导通，此时，图5中a图中的栅极字线200等效于图5中的b图，增大了栅极字线200与源/漏极区域102分别在字线沟槽侧壁上的投影重叠区域A的高度，从而增大了驱动电流；而当栅极字线200施加电压小于预设电压时，单导通层202的电阻大于预设电阻，如图4和图6所示，单导通层202处于截止状态，单导通层202用于阻断第一导电层201和第二导电层203，以使第一导电层201和第二导电层203不导通，此时，图6中c图的栅极字线200等效于图6中的d图，这样，第二导电层203能够屏蔽第一导电层201的电场，从而减小了栅极字线200与源/漏极区域102的在字线沟槽侧壁上的投影重叠区域A的电场强度，进而改善GIDL漏电现象。
在本公开中，当单导通层202处于导通状态时，第一导电层201和第二导电层203通过单导通层202导通，源/漏极区域102与栅极字线200的重叠区域A会吸引基底100掺杂区的电子，降低源/漏极区域102与栅极字线200的重叠区域A的电阻，从而增大晶体管的驱动电流；而当单导通层202处于截止状态时，第一导电层201和第二导电层203不导通，这样，第二导电层203的电压为0v，第二导电层203可以明显减小重叠区域A的电场强度，改善栅极字线200与源/漏极之间发生电子遂穿而形成电流的现象，从而改善 GIDL漏电现象。
需要说明的是，栅极字线200与源/漏极区域102分别在字线沟槽侧壁上的投影的重叠区域A的高度是以增大半导体结构中晶体管的驱动电流为目的进行的设置，其具体尺寸在本实施例中不做具体限制。
其中，预设电压可以为1.2V，当栅极字线200施加的电压小于1.2V时，单导通层202的电阻大于预设电阻，以使第一导电层201和第二导电层203不导通。
在一些可选的实施例中，至少部分第二导电层203在字线沟槽101的侧壁上的投影位于源/漏极区域102在字线沟槽101的侧壁上的投影内。
可以理解的是，至少部分第二导电层203指的是部分第二导电层203或者全部导电层，栅极字线200和源/漏极区域102的重叠区域A包括至少部分第二导电层203，这样，当单导通层202处于截止状态时，第一导电层201和第二导电层203不导通，第二导电层203的电压为0v，第二导电层203可以屏蔽第一导电层201附近的电场，改善栅极字线200与漏极之间发生电子遂穿而形成电流的现象，从而改善GIDL漏电现象。
进一步的，第一导电层201的顶部低于源/漏极区域102的底部。
可以理解的是，通过将第一导电层201的顶部设置为低于源/漏极区域102的底部，这样，栅极字线200与源/漏极区域102的重叠区域A为第二导电层203或者第二导电层203和单导通层202组成，当单导通层202处于截止状态时，第一导电层201附近的电子至源/漏极区域102的距离较远，且第二导电层203能够屏蔽第一导电层201附近的电场，减小栅极字线200与源/漏极区域102的重叠区域A的电场强度，避免与源/漏极区域102发生电子遂穿而形成电流，以实现在增大晶体管的驱动电流的同时，改善GIDL漏电现象。
进一步的，第二导电层203的顶部与源/漏极区域102的顶部平齐。
通过将第二导电层203的顶部设置为与源/漏极区域102的顶部平齐，这样，可以增大栅极字线200与源/漏极区域102的重叠区域A的高度，从而增大晶体管的驱动电流的同时，且该重叠区域A主要包括第二导电层203，这样，当单导通层202处于截止状态时，第一导电层201附近的电子至源/漏极区域102的距离较远，且第二导电层203能够屏蔽第一导电层201附近的电场，减小栅极字线200与源/漏极区域102的重叠区域A的电场强度，避免与 源/漏极区域102发生电子遂穿而形成电流，以实现在增大晶体管的驱动电流的同时，改善GIDL漏电现象。
在另一些可选的实施例中，源/漏极区域102在字线沟槽101侧壁上的投影覆盖第二导电层203在字线沟槽101侧壁上的投影，这样，在增大晶体管的驱动电流的同时，能够改善GIDL漏电现象。
在上述实施例的基础上，当栅极字线200施加电压小于预设电压时，单导通层202的电阻大于预设电阻，以使第一导电层201和第二导电层203不导通，其中，预设电阻为第一导电层201和第二导电层203导通的临界电阻。
在本公开实施例中，单导通层202包括第一电阻和第二电阻，且单导通层202在不同的电压下，其电阻值大小可在第一电阻和第二电阻中变化，其中，第一电阻大于第二电阻，当单导通层202为导通状态时，单导通层202的电阻为第二电阻；当单导通层202为截止状态时，单导通层202的电阻为第一电阻。
可以理解的是，当栅极字线200施加的电压小于预设电压时，第一电阻为高阻态电阻，该电阻值大于第一导电层201和第二导电层203的导通电阻，以通过单导通层202阻断第一导电层201和第二导电层203，此时，第二导电层203的电压为0v，这样，第二导电层203可以用于屏蔽栅极字线200的电场，从而减小栅极字线200与源/漏极区域102的电场，进而改善GIDL漏电；而当栅极字线200施加电压大于预设电压时，第二电阻为低阻态电阻，该电阻值小于第一导电层201和第二导电层203的导通电阻，以通过单导通层202导通第一导电层201和第二导电层203，以增大栅极字线200与源/漏极区域102的重叠区域A的高度，从而增大晶体管的驱动电流。
示例性的，当第一导电层201施加的电压为3v时，单导通层202为低阻态导通，此时，栅极字线200包括第一导电层201、单导通层202和第二导电层203，且第一导电层201和第二导电层203通过单导通层202导通，以增大栅极字线200与源/漏极区域102的重叠区域A的高度，从而增大驱动电流；而当第一导电层201施加的电压为-0.2v时，单导通层202为高阻态阻断，此时，栅极字线200包括第一导电层201，减小了栅极字线200与源/漏极区域102的重叠区域A的高度，且第二导电层203还可以用于屏蔽栅极字线200的电场，从而减小栅极字线200与源/漏极区域102的重叠区域A的电场强度， 进而改善GIDL漏电现象。
图7为本公开实施例提供的单导通层在导通和截止状态的电压值和电阻值的关系示意图。
进一步的，由图7可知，单导通层202的导通电流为大于等于10 -4A，导通电压为大于等于1.2V，以通过单导通层202导通第一导电层201和第二导电层203；且当单导通层202的电压大于预设电压时，则电流显著增加，因此，为了满足单导通层202的工作可靠性，单导通层202可以选用随着电压的变化，电阻呈现高、低两种阻态的材料。
其中，单导通层202为双向阈值开关(Ovonic threshold switching，简称OTS)选通材料层。
示例性的，单导通层202可以为碲化硅(SiTe)层，第一导电层201和第二导电层203可以为导电金属层，例如，第一导电层201和第二导电层203为金属钨(W)层。
进一步的，单导通层202的厚度可以为5nm～25nm，其中，单导通层202的厚度不同，其电阻值不同。
示例性的，当单导通层202为15nm的SiTe层时，第一导电层201和第二导电层203为金属钨层时，单导通层202在截止状态时的电阻值可以为导通状态时的电阻值的6倍，如图7所示，电流值从10 -10A变化为10 -4A。
本公开实施例提供的半导体结构，栅极字线包括依次层叠设置的第一导电层、单导通层和第二导电层，其中，第一导电层位于字线沟槽的底部，当单导通层处于导通状态时，第一导电层和第二导电层通过单导通层导通，源/漏极区域与栅极字线的重叠区域A会吸引基底掺杂区的电子，降低源/漏极区域与栅极字线的重叠区域A的电阻，从而增大晶体管的驱动电流；而当单导通层处于截止状态时，第一导电层和第二导电层不导通，这样，第二导电层的电压为0v，第二导电层可以减小重叠区域A的电场强度，改善栅极字线与源/漏极之间发生电子遂穿而形成电流的现象，从而改善GIDL漏电现象。
图8为本公开实施例提供的半导体结构的制作方法的流程示意图。
如图8所示，本公开实施例还提供一种半导体结构的制作方法，其步骤包括：
步骤S101：提供基底，在基底上形成若干个字线沟槽以及与各字线沟槽 相邻的源/漏极区域。
步骤S102：在字线沟槽中形成第一导电层。
步骤S103：在第一导电层上形成单导通层。
步骤S104：在单导通层上形成第二导电层，其中，第一导电层、单导通层以及第二导电层形成栅极字线，栅极字线在字线沟槽的侧壁上的投影与源/漏极区域在字线沟槽的侧壁上的投影具有预设高度的重叠区域。
其中，当栅极字线施加的电压小于预设电压时，单导通层的电阻大于预设电阻，单导通层处于截止状态，单导通层用于阻断第一导电层和第二导电层，以使第一导电层和第二导电层不导通；而当单导通层施加的电压大于预设电压时，单导通层的电阻小于预设电阻，单导通层处于导电状态，单导通层用于导通第一导电层和第二导电层。
本公开实施例提供的半导体结构的制作方法，其步骤包括：提供基底，在基底上形成若干个字线沟槽以及与各字线沟槽相邻的源/漏极区域；在字线沟槽中形成第一导电层；在第一导电层上形成单导通层；在单导通层上形成第二导电层，第一导电层、单导通层以及第二导电层形成栅极字线，其中，第一导电层位于字线沟槽的底部，当单导通层处于导通状态时，第一导电层和第二导电层通过单导通层导通，源/漏极区域与栅极字线的重叠区域会吸引基底掺杂区的电子，降低源/漏极区域与栅极字线的重叠区域的电阻，从而增大晶体管的驱动电流；而当单导通层处于截止状态时，第一导电层和第二导电层不导通，这样，第二导电层的电压为0v，第二导电层减小重叠区域的电场强度，改善栅极字线与源/漏极之间发生电子遂穿而形成电流的现象，从而改善GIDL漏电现象。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料 或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构，包括：
    基底，具有若干个字线沟槽以及与各所述字线沟槽相邻的源/漏极区域；
    栅极字线，位于所述字线沟槽内；所述栅极字线包括依次层叠设置的第一导电层、单导通层和第二导电层，所述第一导电层位于所述字线沟槽的底部，所述栅极字线在所述字线沟槽的侧壁上的投影与所述源/漏极区域在所述字线沟槽的侧壁上的投影具有预设高度的重叠区域，当所述栅极字线施加电压小于预设电压时，所述单导通层的电阻大于预设电阻，以使所述第一导电层和所述第二导电层不导通。
  2. 根据权利要求1所述的半导体结构，其中，至少部分所述第二导电层在所述字线沟槽的侧壁上的投影位于所述源/漏极区域在所述字线沟槽的侧壁上的投影内。
  3. 根据权利要求2所述的半导体结构，其中，所述第一导电层的顶部低于所述源/漏极区域的底部。
  4. 根据权利要求2或3所述的半导体结构，其中，所述第二导电层的顶部与所述源/漏极区域的顶部平齐。
  5. 根据权利要求2所述的半导体结构，其中，所述源/漏极区域在所述字线沟槽侧壁上的投影覆盖所述第二导电层在所述字线沟槽侧壁上的投影。
  6. 根据权利要求1所述的半导体结构，其中，所述预设电阻为所述第一导电层和所述第二导电层导通的临界电阻。
  7. 根据权利要求1-3中任一项所述的半导体结构，其中，所述单导通层包括第一电阻和第二电阻，所述第一电阻大于所述第二电阻，当所述单导通层为导通状态时，所述单导通层的电阻为第二电阻；当所述单导通层为截止状态时，所述单导通层的电阻为第一电阻。
  8. 根据权利要求7所述的半导体结构，其中，所述单导通层的导通电流为大于等于10 -4A，导通电压为大于等于1.2V。
  9. 根据权利要求7所述的半导体结构，其中，所述单导通层为OTS选通材料层。
  10. 根据权利要求9所述的半导体结构，其中，所述单导通层为碲化硅(SiTe)层。
  11. 根据权利要求7所述的半导体结构，其中，所述单导通层的厚度为5nm～25nm。
  12. 根据权利要求11所述的半导体结构，其中，所述单导通层的厚度为15nm。
  13. 根据权利要求1-3中任一项所述的半导体结构，其中，所述第一导电层和/或所述第二导电层为导电金属层。
  14. 根据权利要求13所述的半导体结构，其中，所述第一导电层和/或第二导电层为钨(W)层。
  15. 一种半导体结构的制作方法，包括：
    提供基底，在所述基底上形成若干个字线沟槽以及与各所述字线沟槽相邻的源/漏极区域；
    在所述字线沟槽中形成第一导电层；
    在所述第一导电层上形成单导通层；
    在所述单导通层上形成第二导电层；其中，所述第一导电层、所述单导通层以及所述第二导电层形成栅极字线，所述栅极字线在所述字线沟槽的侧壁上的投影与所述源/漏极区域在所述字线沟槽的侧壁上的投影具有预设高度的重叠区域。
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