WO2023010635A1 - 栅极驱动电路及显示面板 - Google Patents

栅极驱动电路及显示面板 Download PDF

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Publication number
WO2023010635A1
WO2023010635A1 PCT/CN2021/115642 CN2021115642W WO2023010635A1 WO 2023010635 A1 WO2023010635 A1 WO 2023010635A1 CN 2021115642 W CN2021115642 W CN 2021115642W WO 2023010635 A1 WO2023010635 A1 WO 2023010635A1
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WO
WIPO (PCT)
Prior art keywords
electrically connected
thin film
film transistor
gate drive
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/115642
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English (en)
French (fr)
Inventor
李明月
田超
管延庆
艾飞
刘广辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
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Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US17/605,546 priority Critical patent/US12125424B2/en
Publication of WO2023010635A1 publication Critical patent/WO2023010635A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of display panel manufacturing, in particular to a gate drive circuit and a display panel.
  • the gate drive circuit also known as the GOA (Gate Driver On Array, array substrate line drive) circuit, uses the existing thin-film transistor display array (Array) substrate manufacturing process to manufacture the gate (Gate) row scanning drive signal circuit on the On the array substrate, in order to realize the driving mode of progressive scanning of Gate.
  • GOA Gate Driver On Array, array substrate line drive
  • the gate drive circuit in the traditional technical solution includes multiple cascaded gate drive units, and the gate drive unit usually includes a pull-up control module 1, a pull-up module 2, a pull-down control module 3 and a pull-down module 4.
  • the pull-up control module 1 is electrically connected to the pull-up module 2 to form a first node N1
  • the pull-down control module 3 is electrically connected to the pull-down module 4 to form a second node N2
  • the feedback module 5 is electrically connected to the first
  • the pull-up module 2 and the pull-down module 4 are electrically connected to form a third node N3, wherein the third node N3 is used to output a corresponding scan signal.
  • the gate drive unit of any stage in the above-mentioned traditional technical solutions is generally unable to output two scan signals with the same phase, or outputting two scan signals with the same phase requires a gate drive unit with a complex circuit topology, which is not conducive to Show the development needs of the industry.
  • the present application provides a gate driving circuit and a display panel to alleviate the technical problem that the circuit topology of the gate driving circuit outputting multiple same-phase driving signals is too complicated.
  • the present application provides a gate drive circuit
  • the gate drive circuit includes a plurality of cascaded gate drive modules, one of the gate drive modules includes a gate drive sub-module and a non-inverting output sub-module, the gate drive
  • the sub-module includes a first output node and a pull-down node, the first output node is used to output the first drive signal
  • the non-inverting output sub-module includes a first control node, a second control node and a second output node, the first control node and the first The output node is electrically connected, the second control node is electrically connected to the pull-down node, the second output node is used for outputting a second driving signal, and the phase of the second driving signal is the same as that of the first driving signal.
  • one of the gate driving modules further includes a first wiring, a second wiring, a third wiring and a fourth wiring, and the first wiring is electrically connected to the gate driving sub-module for used to transmit the first constant-voltage low-potential signal; the second wiring is electrically connected to the in-phase output sub-module for transmitting the second constant-voltage low-potential signal; the third wiring is electrically connected to the gate drive sub-module for The first constant-voltage high-potential signal is transmitted; the fourth wiring is electrically connected to the in-phase output sub-module for transmitting the second constant-voltage high-potential signal.
  • the gate driving sub-module includes a pull-up unit and a pull-down unit, and the output terminal of the pull-down unit is electrically connected with the output terminal of the pull-up unit and the first output node.
  • the gate driving sub-module further includes a pull-down control unit, the output terminal of the pull-down control unit is electrically connected to the control terminal of the pull-down unit and the pull-down node.
  • the present application provides a gate drive circuit.
  • the gate drive circuit includes a plurality of cascaded gate drive modules, wherein one gate drive module includes a first transistor, a second transistor, a third transistor, and a fourth transistor.
  • One of the source/drain of the first transistor is electrically connected to the first output node, and the first output node is used to output the first driving signal; one of the source/drain of the second transistor is connected to the first The output node is electrically connected, the gate of the second transistor is electrically connected to the pull-down node; the gate of the third transistor is electrically connected to the first output node, and one of the source/drain of the third transistor is connected to the second output The nodes are electrically connected, and the second output node is used to output the second driving signal; the gate of the fourth transistor is electrically connected to the pull-down node, and one of the source/drain of the fourth transistor is electrically connected to the second output node ; Wherein, the phase of the first driving signal is the same as
  • one of the gate driving modules further includes a fifth transistor, one of the source/drain of the fifth transistor is electrically connected to the gate of the first transistor.
  • one of the gate driving modules further includes a first wiring, a second wiring, a third wiring and a fourth wiring, the first wiring is connected to the source/drain of the second transistor Another electrical connection of the first constant-voltage low-potential signal; the second wiring is electrically connected to the other source/drain of the fourth transistor for transmission of the second constant-voltage low-potential signal ;
  • the third wiring is electrically connected to the gate of the fifth transistor for transmitting the first constant voltage high potential signal;
  • the fourth wiring is electrically connected to the other of the source/drain of the third transistor for for transmitting the second constant-voltage high-potential signal.
  • the present application provides a display panel, which includes the gate drive circuit in any one of the above-mentioned implementation modes, a plurality of scan lines, and a light-shielding metal layer, wherein one scan line is connected to the first output node/second output node. an electrical connection; the light-shielding metal layer includes at least one light-shielding metal block, and the at least one light-shielding metal block is electrically connected to the other of the first output node/the second output node.
  • the display panel further includes a display area and a non-display area, at least one light-shielding metal block is located in the display area; at least part of one scanning line is located in the non-display area.
  • one of the scanning lines at least partially overlaps with at least one light-shielding metal block.
  • the gate drive circuit and the display panel provided by the present application can output the first drive signal through the first output node, and can output the second drive signal with the same phase as the first drive signal through the second output node at the same time, not only can output multiple
  • the drive signals of the same phase, and the first output node and the pull-down node are shared by the gate drive sub-module and the same-phase output sub-module, which simplifies the circuit topology of the gate drive circuit and is beneficial to realize the narrow frame of the display panel.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit in a conventional technical solution.
  • FIG. 2 is a schematic diagram of a first structure of a gate driving circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a second structure of the gate driving circuit provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a third structure of the gate driving circuit provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a fourth structure of the gate driving circuit provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of a fifth structure of the gate driving circuit provided by the embodiment of the present application.
  • FIG. 7 is a schematic timing diagram of a gate driving circuit provided by an embodiment of the present application.
  • this embodiment provides a gate drive circuit
  • the gate drive circuit includes a plurality of cascaded gate drive modules, and one of the gate drive modules includes a gate
  • the driving sub-module and the non-inverting output sub-module 80 the gate driving sub-module includes a first output node R(N) and a pull-down node P(N), and the first output node R(N) is used to output the first driving signal;
  • the sub-module 80 includes a first control node, a second control node and a second output node S(N), the first control node is electrically connected to the first output node R(N), and the second control node is connected to the pull-down node P(N ), the second output node S(N) is used to output the second driving signal GLS(N), and the phase of the second driving signal GLS(N) is the same as that of the first driving signal.
  • the gate drive circuit provided in this embodiment can output the first drive signal through the first output node R(N), and at the same time can output the same phase as the first drive signal through the second output node S(N).
  • the second drive signal GLS(N) can not only output multiple drive signals with the same phase, but also share the first output node R(N) and pull-down node P(N) through the gate drive sub-module and the same-phase output sub-module 80 , which simplifies the circuit topology of the gate drive circuit, which is beneficial to realize the narrow frame of the display panel.
  • the corresponding control node may be the gate of the corresponding thin film transistor, for example, the first control node may be the gate of the first thin film transistor NT12, and the second control node may be the gate of the second thin film transistor NT12. Gate of transistor NT13.
  • the first driving signal may also be the Nth-level scanning signal G(N).
  • one of the gate driving modules further includes a first wiring, a second wiring, a third wiring and a fourth wiring, the first wiring is electrically connected to the gate driving sub-module, and is used for used to transmit the first constant-voltage low-potential signal VGL; the second wiring is electrically connected to the non-inverting output sub-module 80 for transmitting the second constant-voltage low-potential signal COM2; the third wiring is electrically connected to the gate driving sub-module , used to transmit the first constant-voltage high-potential signal VGH; the fourth wiring is electrically connected to the non-inverting output sub-module 80 and used to transmit the second constant-voltage high-potential signal COM1.
  • the gate drive sub-module and the in-phase output sub-module 80 independently use a set of constant-voltage high-potential signals and constant-voltage low-potential signals.
  • the independent adjustment of the two can be realized, which is beneficial to meet the diversified requirements of the display panel.
  • the potential of the second constant-voltage high-potential signal COM1 may be less than or equal to the potential of the first constant-voltage high-potential signal VGH.
  • the potential of the second constant-voltage low-level signal COM2 may be equal to or approximately equal to the potential of the first constant-voltage low-level signal VGL.
  • the non-inverting output sub-module 80 may include a first thin film transistor NT12 and a second thin film transistor NT13, one of the source/drain of the first thin film transistor NT12 is electrically connected to the fourth wire, and the second The gate of a thin film transistor NT12 is electrically connected to the first output node R(N), and the other of the source/drain of the first thin film transistor NT12 is connected to one of the source/drain of the second thin film transistor NT13 It is electrically connected to the second output node S(N), the gate of the second thin film transistor NT13 is electrically connected to the pull-down node P(N), and the other of the source/drain of the second thin film transistor NT13 is connected to the second The traces are electrically connected.
  • the gate driving sub-module includes a pull-up unit 20 and a pull-down unit 40 , and the output terminal of the pull-down unit 40 is electrically connected to the output terminal of the pull-up unit 20 and the first output node R(N).
  • the pull-up unit 20 includes a third thin film transistor NT9, one of the source/drain of the third thin film transistor NT9 is electrically connected to the fifth wiring, and the source/drain of the third thin film transistor NT9 The other of the drains is electrically connected to the first output node R(N).
  • the fifth wire can be used to transmit the nth clock signal CK(n), and n can be a positive integer.
  • the pull-up unit 20 further includes a fourth thin film transistor NT7, one of the source/drain of the fourth thin film transistor NT7 is electrically connected to the gate of the third thin film transistor NT9, and the fourth thin film transistor The gate of NT7 is electrically connected to the third wiring.
  • the pull-up unit 20 further includes a fifth thin film transistor NT11, one of the source/drain of the fifth thin film transistor NT11 is electrically connected to the first output node R(N), and the fifth thin film transistor The gate of NT11 is electrically connected with the sixth wire and the other of the source/drain of the fifth thin film transistor NT11.
  • the sixth wire can be used to transmit the first global control signal GAS1.
  • the pull-down unit 40 includes a sixth thin film transistor NT10, one of the source/drain of the sixth thin film transistor NT10 is electrically connected to the first output node R(N), and the sixth thin film transistor NT10 The gate is electrically connected to the pull-down node P(N), and the other of the source/drain of the sixth thin film transistor NT10 is electrically connected to the first wiring.
  • the gate driving sub-module further includes a pull-down control unit 30 , the output terminal of the pull-down control unit 30 is electrically connected to the control terminal of the pull-down unit 40 and the pull-down node P(N).
  • the pull-down control unit 30 includes a seventh thin film transistor NT3, an eighth thin film transistor NT8, and a ninth thin film transistor NT4, and one of the source/drain of the seventh thin film transistor NT3 is electrically connected to the seventh wiring.
  • the gate of the seventh thin film transistor NT3 is electrically connected to the eighth wiring
  • the other of the source/drain of the seventh thin film transistor NT3 is electrically connected to the gate of the eighth thin film transistor NT8, and the eighth One of the source/drain of the thin film transistor NT8 is electrically connected to the ninth wiring
  • the other of the source/drain of the eighth thin film transistor NT8 is electrically connected to the pull-down node P(N)
  • the ninth thin film One of the source/drain of the transistor NT4 is electrically connected to the tenth wiring
  • the other of the source/drain of the ninth thin film transistor NT4 is electrically connected to the gate of the eighth thin film transistor NT8, and the ninth thin film transistor NT8 is electrically connected to the gate.
  • the gate of the thin film transistor NT4 is electrically connected to the eleventh wire.
  • the seventh wire can be used to transmit the n+1th clock signal CK(n+1).
  • the eighth wire can be used to transmit the forward scan control signal U2D.
  • the ninth wire can be used to transmit the second global control signal GAS2.
  • the tenth wire can be used to transmit the n-1th clock signal CK(n-1).
  • the eleventh wire can be used to transmit the reverse scan control signal D2U.
  • the pull-down control unit 30 includes a tenth thin film transistor NT2 and an eleventh thin film transistor NT6, one of the source/drain of the tenth thin film transistor NT2 is electrically connected to the eleventh wiring, and the first The gate of the tenth thin film transistor NT2 is electrically connected to the twelfth wiring, and the other source/drain of the tenth thin film transistor NT2 is connected to the pull-up node Q(N) and the gate of the eleventh thin film transistor NT6 Electrically connected, one of the source/drain of the eleventh thin film transistor NT6 is electrically connected to the first wiring, and the other of the source/drain of the eleventh thin film transistor NT6 is connected to the pull-down node P(N) electrical connection.
  • the twelfth wire can be used to transmit the N+2-th level scan signal G(N+2).
  • the gate driving sub-module further includes an input unit 10 , and an output terminal of the input unit 10 is electrically connected to the pull-up node Q(N).
  • the input unit 10 includes a twelfth thin film transistor NT5, one of the source/drain of the twelfth thin film transistor NT5 is electrically connected to the eighth wiring, and the gate of the twelfth thin film transistor NT5 The pole is electrically connected to the thirteenth wiring, and the other of the source/drain of the twelfth thin film transistor NT5 is connected to the pull-up node Q(N) and the other of the source/drain of the fourth thin film transistor NT7 an electrical connection.
  • the thirteenth wiring can be used to transmit the N-2th level scan signal G(N-2).
  • the gate drive sub-module further includes a feedback unit 50, the input end of the feedback unit 50 is electrically connected to the first wiring, the control end of the feedback unit 50 is electrically connected to the pull-down node P(N), and the feedback The output end of the unit 50 is electrically connected to the pull-up node Q(N).
  • the feedback unit 50 includes a thirteenth thin film transistor NT1, one of the source/drain of the thirteenth thin film transistor NT1 is electrically connected to the first wiring, and the gate of the thirteenth thin film transistor NT1 It is electrically connected to the pull-down node P(N), and the other of the source/drain of the thirteenth thin film transistor NT1 is electrically connected to the pull-up node Q(N).
  • the gate drive sub-module further includes a first voltage stabilizing unit 60, one end of the first voltage stabilizing unit 60 is electrically connected to the first wiring, and the other end of the first voltage stabilizing unit 60 is connected to the pull-up node Q(N) is electrically connected.
  • the first voltage stabilizing unit 60 includes a first capacitor C1, one end of the first capacitor C1 is electrically connected to the first wiring, and the other end of the first capacitor C1 is electrically connected to the pull-up node Q(N). connect.
  • the gate drive sub-module further includes a second voltage stabilizing unit 70, one end of the second voltage stabilizing unit 70 is electrically connected to the first wiring, and the other end of the second voltage stabilizing unit 70 is connected to the pull-down node P (N) electrical connection.
  • the second voltage stabilizing unit 70 includes a second capacitor C2, one end of the second capacitor C2 is electrically connected to the first wiring, and the other end of the second capacitor C2 is electrically connected to the pull-down node P(N). .
  • At least one of the first thin film transistor NT12 to the thirteenth thin film transistor NT1 may be, but not limited to, an N-channel thin film transistor, and may also be correspondingly adjusted to be a P-channel thin film transistor.
  • the difference between the gate driving module shown in FIG. 3 and the gate driving module shown in FIG. 2 is that when n is equal to 1 and N is also equal to 1, the source of the third thin film transistor NT9 One of the electrodes/drains is used to access the first clock signal CK (1), one of the source/drains of the seventh thin film transistor NT3 is used to access the second clock signal CK (2), and the ninth thin film transistor NT3 is used to access the second clock signal CK (2).
  • One of the source/drain of the transistor NT4 is used to access the fourth clock signal CK (3), and the gate of the twelfth thin film transistor NT5 is used to access the first negative level scan signal G (-1).
  • the first negative level scanning signal G(-1) can be replaced by the start signal, and the gate of the tenth thin film transistor NT2 is used to access the third level scanning signal G(3).
  • the first output The first driving signal output from the node R(N) may serve as the first-level scan signal G(1)
  • the second driving signal GLS(N) output from the second output node S(N) may serve as the driving signal GLS(1).
  • the difference between the gate driving module shown in FIG. 4 and the gate driving module shown in FIG. 2 is that when n is equal to 2 and N is also equal to 2, the source of the third thin film transistor NT9 One of the electrodes/drains is used to access the second clock signal CK (2), one of the source/drains of the seventh thin film transistor NT3 is used to access the third clock signal CK (3), and the ninth thin film transistor NT3 is used to access the third clock signal CK (3).
  • One of the source/drain of the transistor NT4 is used to access the first clock signal CK (1), and the gate of the twelfth thin film transistor NT5 is used to access the zero-level scanning signal G (0).
  • the level scanning signal G(0) can also be replaced by another start signal, and the gate of the tenth thin film transistor NT2 is used to access the fourth level scanning signal G(4).
  • the first output node The first driving signal output by R(N) may be used as the second-level scanning signal G(2), and the second driving signal GLS(N) output by the second output node S(N) may be the driving signal GLS(2).
  • the difference between the gate driving module shown in FIG. 5 and the gate driving module shown in FIG. 2 is that when n is equal to 3 and N is also equal to 3, the source of the third thin film transistor NT9 One of the electrodes/drains is used to access the third clock signal CK (3), one of the source/drains of the seventh thin film transistor NT3 is used to access the fourth clock signal CK (4), and the ninth thin film transistor NT3 is used to access the fourth clock signal CK (4).
  • One of the source/drain of the transistor NT4 is used to access the second clock signal CK (2)
  • the gate of the twelfth thin-film transistor NT5 is used to access the first-level scanning signal G (1)
  • the tenth thin-film transistor NT5 The gate of transistor NT2 is used to access the fifth-level scanning signal G(5), correspondingly, at this time, the first driving signal output from the first output node R(N) can be used as the third-level scanning signal G(3)
  • the second driving signal GLS(N) output by the second output node S(N) may be the driving signal GLS( 3 ).
  • the difference between the gate driving module shown in FIG. 6 and the gate driving module shown in FIG. 2 is that when n is equal to 4, and N is also equal to 4, the source of the third thin film transistor NT9 One of the electrodes/drains is used to access the fourth clock signal CK (4), one of the source/drains of the seventh thin film transistor NT3 is used to access the first clock signal CK (1), and the ninth thin film transistor NT3 One of the source/drain of the transistor NT4 is used to access the third clock signal CK (3), the gate of the twelfth thin-film transistor NT5 is used to access the second-level scanning signal G (2), and the tenth thin-film transistor NT5 The gate of transistor NT2 is used to access the sixth-level scanning signal G(6), correspondingly, at this time, the first driving signal output from the first output node R(N) can be used as the fourth-level scanning signal G(4) , the second driving signal GLS(N) output by the second output node
  • the gate drive circuit provided by the present application can use four clock signal lines in a circular manner and can work normally, which reduces the number of clock signal lines used and is beneficial to realize narrow borders.
  • the gate driving circuit provided in the present application may also use other numbers of clock signal lines, for example, six or eight.
  • the first global control signal GAS1 may be a low potential signal
  • the second global control signal GAS2 may be a high potential signal
  • the first global control signal GAS1 may be a high potential signal
  • the second global control signal GAS2 may be a low potential signal.
  • the second constant voltage high potential signal COM1 can be continuously high potential.
  • the second constant-voltage low-level signal COM2 can also be kept at a low level.
  • the first clock signal CK(1) can be simultaneously output as the first-level scanning signal G(1) and the driving signal GLS(1) with the same phase.
  • the second clock signal CK(2) can be simultaneously output as the second-level scanning signal G(2) and the driving signal GLS(2) with the same phase.
  • the third clock signal CK( 3 ) can be simultaneously output as a third-level scanning signal G( 3 ) and a driving signal GLS( 3 ) with the same phase.
  • the fourth clock signal CK ( 4 ) can be simultaneously output as a fourth-level scanning signal G ( 4 ) and a driving signal GLS ( 4 ) with the same phase.
  • this embodiment provides a gate drive circuit
  • the gate drive circuit includes a plurality of cascaded gate drive modules, wherein one gate drive module includes a first transistor, a second transistor, a third The transistor and the fourth transistor, one of the source/drain of the first transistor is electrically connected to the first output node R(N), and the first output node R(N) is used to output the first driving signal;
  • the second transistor One of the source/drain of the transistor is electrically connected to the first output node R (N), the gate of the second transistor is electrically connected to the pull-down node P (N);
  • the gate of the third transistor is electrically connected to the first output node R(N) is electrically connected, one of the source/drain of the third transistor is electrically connected to the second output node S(N), and the second output node S(N) is used to output the second driving signal GLS( N);
  • the gate of the fourth transistor is electrically connected to the pull-down node P(N), and one of the source/drain
  • the gate drive circuit provided in this embodiment can output the first drive signal through the first output node R(N), and at the same time can output the same phase as the first drive signal through the second output node S(N).
  • the second drive signal GLS(N) can not only output multiple drive signals with the same phase, but also simplify the circuit topology of the gate drive circuit by sharing the first output node R(N) and the pull-down node P(N). , which in turn facilitates the realization of a narrow frame of the display panel.
  • the first transistor may be the third thin film transistor NT9 in the above embodiment.
  • the second transistor may be the sixth thin film transistor NT10 in the above embodiments.
  • the third transistor may be the first thin film transistor NT12 in the above embodiments.
  • the fourth transistor may be the second thin film transistor NT13 in the above embodiment.
  • one of the gate driving modules further includes a fifth transistor, one of the source/drain of the fifth transistor is electrically connected to the gate of the first transistor.
  • the fifth transistor may be the fourth thin film transistor NT7 in the above embodiment.
  • the first wiring is electrically connected to the other of the source/drain of the second transistor for transmitting the first constant voltage low potential signal VGL; the second wiring is connected to the fourth transistor Another electrical connection in the source/drain is used to transmit the second constant-voltage low-potential signal COM2; the third wiring is electrically connected to the gate of the fifth transistor and is used to transmit the first constant-voltage high-potential signal VGH; the fourth wiring is electrically connected to the other of the source/drain of the third transistor, and is used for transmitting the second constant voltage high potential signal COM1.
  • this embodiment provides a display panel, which includes the gate drive circuit in any of the above embodiments, a plurality of scan lines and a light-shielding metal layer, wherein one scan line is connected to the first output node R ( N)/one of the second output node S(N) is electrically connected; the light-shielding metal layer includes at least one light-shielding metal block, at least one light-shielding metal block is connected to the first output node R(N)/second output node S(N) ) in another electrical connection.
  • the display panel provided in this embodiment can output the first driving signal through the first output node R(N), and at the same time can output the second driving signal with the same phase as the first driving signal through the second output node S(N).
  • the second drive signal GLS(N) can not only output multiple drive signals with the same phase, but also simplifies the circuit topology of the gate drive circuit by sharing the first output node R(N) and the pull-down node P(N). It is beneficial to realize the narrow frame of the display panel.
  • the corresponding scanning line and the light-shielding metal layer are fed with the driving signal of the same phase, which can reduce the voltage difference between the two, thereby reducing the coupling effect of the corresponding light-shielding metal block, and can reduce or avoid the error of the thin film transistor corresponding to the light-shielding metal block. switching or leakage current.
  • the display panel may include an array substrate, the array substrate is provided with a plurality of thin film transistors, each thin film transistor has at least one active region, and each light-shielding metal block can be used to shield an active region, which can be The stability corresponds to the working state of the thin film transistor.
  • the display panel further includes a display area and a non-display area, at least one light-shielding metal block is located in the display area; at least part of one scanning line is located in the non-display area.
  • one of the scanning lines at least partially overlaps with at least one light-shielding metal block.

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Abstract

本申请公开了一种栅极驱动电路及显示面板，该栅极驱动电路包括多个级联的栅极驱动模块，通过第一输出节点可以输出第一驱动信号，同时通过第二输出节点可以输出与第一驱动信号相位相同的第二驱动信号，而且通过栅极驱动子模块、同相输出子模块共用第一输出节点及下拉节点，简化了栅极驱动电路的电路拓扑结构。

Description

栅极驱动电路及显示面板 技术领域
本申请涉及显示面板制造领域，尤其涉及一种栅极驱动电路及显示面板。
 背景技术
栅极驱动电路，又可以称为GOA（Gate Driver On Array，阵列基板行驱动）电路，其利用现有薄膜晶体管显示器的阵列（Array）基板制程将栅极（Gate）行扫描驱动信号电路制作在阵列基板上，以实现对Gate逐行扫描的驱动方式。
如图1所示，传统技术方案中的栅极驱动电路包括多个级联的栅极驱动单元，栅极驱动单元通常包括上拉控制模块1、上拉模块2、下拉控制模块3以及下拉模块4，其中，上拉控制模块1与上拉模块2电性连接以形成第一节点N1，下拉控制模块3与下拉模块4电性连接以形成第二节点N2，反馈模块5电连接于第一节点N1与第二节点N2之间，上拉模块2与下拉模块4电性连接以形成第三节点N3，其中，第三节点N3用于输出对应的扫描信号。
但是，上述传统技术方案中的任一级栅极驱动单元通常不能够输出相位相同的两个扫描信号，或者输出相位相同的两个扫描信号需要电路拓扑结构复杂的栅极驱动单元，如此不利于显示行业的发展需要。
需要注意的是，上述关于背景技术的介绍仅仅是为了便于清楚、完整地理解本申请的技术方案。因此，不能仅仅由于其出现在本申请的背景技术中，而认为上述所涉及到的技术方案为本领域所属技术人员所公知。
 技术问题
本申请提供一种栅极驱动电路及显示面板，以缓解输出多个同相位驱动信号的栅极驱动电路的电路拓扑结构过于复杂的技术问题。
 技术解决方案
第一方面，本申请提供一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动模块，其中一个栅极驱动模块包括栅极驱动子模块和同相输出子模块，栅极驱动子模块包括第一输出节点和下拉节点，第一输出节点用于输出第一驱动信号；同相输出子模块包括第一控制节点、第二控制节点以及第二输出节点，第一控制节点与第一输出节点电性连接，第二控制节点与下拉节点电性连接，第二输出节点用于输出第二驱动信号，且第二驱动信号的相位与第一驱动信号的相位相同。
在其中一些实施方式中，其中一个栅极驱动模块还包括第一走线、第二走线、第三走线以及第四走线，第一走线与栅极驱动子模块电性连接，用于传输第一恒压低电位信号；第二走线与同相输出子模块电性连接，用于传输第二恒压低电位信号；第三走线与栅极驱动子模块电性连接，用于传输第一恒压高电位信号；第四走线与同相输出子模块电性连接，用于传输第二恒压高电位信号。
在其中一些实施方式中，栅极驱动子模块包括上拉单元和下拉单元，下拉单元的输出端与上拉单元的输出端和第一输出节点电性连接。
在其中一些实施方式中，栅极驱动子模块还包括下拉控制单元，下拉控制单元的输出端与下拉单元的控制端和下拉节点电性连接。
第二方面，本申请提供一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动模块，其中一个栅极驱动模块包括第一晶体管、第二晶体管、第三晶体管以及第四晶体管，第一晶体管的源极/漏极中的一个与第一输出节点电性连接，第一输出节点用于输出第一驱动信号；第二晶体管的源极/漏极中的一个与第一输出节点电性连接，第二晶体管的栅极与下拉节点电性连接；第三晶体管的栅极与第一输出节点电性连接，第三晶体管的源极/漏极中的一个与第二输出节点电性连接，第二输出节点用于输出第二驱动信号；第四晶体管的栅极与下拉节点电性连接，第四晶体管的源极/漏极中的一个与第二输出节点电性连接；其中，第一驱动信号的相位与第二驱动信号的相位相同。
在其中一些实施方式中，其中一个栅极驱动模块还包括第五晶体管，第五晶体管的源极/漏极中的一个与第一晶体管的栅极电性连接。
在其中一些实施方式中，其中一个栅极驱动模块还包括第一走线、第二走线、第三走线以及第四走线，第一走线与第二晶体管的源极/漏极中的另一个电性连接，用于传输第一恒压低电位信号；第二走线与第四晶体管的源极/漏极中的另一个电性连接，用于传输第二恒压低电位信号；第三走线与第五晶体管的栅极电性连接，用于传输第一恒压高电位信号；第四走线与第三晶体管的源极/漏极中的另一个电性连接，用于传输第二恒压高电位信号。
第三方面，本申请提供一种显示面板，其包括上述任一实施方式中的栅极驱动电路、多条扫描线以及遮光金属层，其中一条扫描线与第一输出节点/第二输出节点中的一个电性连接；遮光金属层包括至少一个遮光金属块，至少一个遮光金属块与第一输出节点/第二输出节点中的另一个电性连接。
在其中一些实施方式中，显示面板还包括显示区和非显示区，至少一个遮光金属块位于显示区；其中一条扫描线的至少部分位于非显示区。
在其中一些实施方式中，在显示面板的厚度方向上，其中一条扫描线与至少一个遮光金属块至少部分重叠。
 有益效果
本申请提供的栅极驱动电路及显示面板，通过第一输出节点可以输出第一驱动信号，同时通过第二输出节点可以输出与第一驱动信号相位相同的第二驱动信号，不仅可以输出多个同相位的驱动信号，而且通过栅极驱动子模块、同相输出子模块共用第一输出节点及下拉节点，简化了栅极驱动电路的电路拓扑结构，进而有利于实现显示面板的窄边框。
 附图说明
图1为传统技术方案中的栅极驱动电路的结构示意图。
图2为本申请实施例提供的栅极驱动电路的第一种结构示意图。
图3为本申请实施例提供的栅极驱动电路的第二种结构示意图。
图4为本申请实施例提供的栅极驱动电路的第三种结构示意图。
图5为本申请实施例提供的栅极驱动电路的第四种结构示意图。
图6为本申请实施例提供的栅极驱动电路的第五种结构示意图。
图7为本申请实施例提供的栅极驱动电路的时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图2至图7，如图2所示，本实施例提供了一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动模块，其中一个栅极驱动模块包括栅极驱动子模块和同相输出子模块80，栅极驱动子模块包括第一输出节点R（N）和下拉节点P（N），第一输出节点R（N）用于输出第一驱动信号；同相输出子模块80包括第一控制节点、第二控制节点以及第二输出节点S（N），第一控制节点与第一输出节点R（N）电性连接，第二控制节点与下拉节点P（N）电性连接，第二输出节点S（N）用于输出第二驱动信号GLS（N），且第二驱动信号GLS（N）的相位与第一驱动信号的相位相同。
可以理解的是，本实施例提供的栅极驱动电路，通过第一输出节点R（N）可以输出第一驱动信号，同时通过第二输出节点S（N）可以输出与第一驱动信号相位相同的第二驱动信号GLS（N），不仅可以输出多个同相位的驱动信号，而且通过栅极驱动子模块、同相输出子模块80共用第一输出节点R（N）及下拉节点P（N），简化了栅极驱动电路的电路拓扑结构，进而有利于实现显示面板的窄边框。
需要进行说明的是，在本实施例中，对应的控制节点可以为对应薄膜晶体管的栅极，如第一控制节点可以为第一薄膜晶体管NT12的栅极，第二控制节点可以为第二薄膜晶体管NT13的栅极。其中，第一驱动信号也可以为第N级扫描信号G（N）。
在其中一个实施例中，其中一个栅极驱动模块还包括第一走线、第二走线、第三走线以及第四走线，第一走线与栅极驱动子模块电性连接，用于传输第一恒压低电位信号VGL；第二走线与同相输出子模块80电性连接，用于传输第二恒压低电位信号COM2；第三走线与栅极驱动子模块电性连接，用于传输第一恒压高电位信号VGH；第四走线与同相输出子模块80电性连接，用于传输第二恒压高电位信号COM1。
可以理解的是，在本实施例中，栅极驱动子模块、同相输出子模块80分别独立使用一组恒压高电位信号和恒压低电位信号，在两者实现同相输出的基础上，又可以实现两者的独立可调，有利于满足显示面板的多样化需求。
其中，第二恒压高电位信号COM1的电位可以小于或者等于第一恒压高电位信号VGH的电位。第二恒压低电位信号COM2的电位可以等于或者近似等于第一恒压低电位信号VGL的电位。
在其中一个实施例中，同相输出子模块80可以包括第一薄膜晶体管NT12和第二薄膜晶体管NT13，第一薄膜晶体管NT12的源极/漏极中的一个与第四走线电性连接，第一薄膜晶体管NT12的栅极与第一输出节点R（N）电性连接，第一薄膜晶体管NT12的源极/漏极中的另一个与第二薄膜晶体管NT13的源极/漏极中的一个和第二输出节点S（N）电性连接，第二薄膜晶体管NT13的栅极与下拉节点P（N）电性连接，第二薄膜晶体管NT13的源极/漏极中的另一个与第二走线电性连接。
在其中一个实施例中，栅极驱动子模块包括上拉单元20和下拉单元40，下拉单元40的输出端与上拉单元20的输出端和第一输出节点R（N）电性连接。
在其中一个实施例中，上拉单元20包括第三薄膜晶体管NT9，第三薄膜晶体管NT9的源极/漏极中的一个与第五走线电性连接，第三薄膜晶体管NT9的源极/漏极中的另一个与第一输出节点R（N）电性连接。
其中，第五走线可以用于传输第n个时钟信号CK（n），n可以为正整数。
在其中一个实施例中，上拉单元20还包括第四薄膜晶体管NT7，第四薄膜晶体管NT7的源极/漏极中的一个与第三薄膜晶体管NT9的栅极电性连接，第四薄膜晶体管NT7的栅极与第三走线电性连接。
在其中一个实施例中，上拉单元20还包括第五薄膜晶体管NT11，第五薄膜晶体管NT11的源极/漏极中的一个与第一输出节点R（N）电性连接，第五薄膜晶体管NT11的栅极与第六走线和第五薄膜晶体管NT11的源极/漏极中的另一个电性连接。
其中，第六走线可以用于传输第一全局控制信号GAS1。
在其中一个实施例中，下拉单元40包括第六薄膜晶体管NT10，第六薄膜晶体管NT10的源极/漏极中的一个与第一输出节点R（N）电性连接，第六薄膜晶体管NT10的栅极与下拉节点P（N）电性连接，第六薄膜晶体管NT10的源极/漏极中的另一个与第一走线电性连接。
在其中一个实施例中，栅极驱动子模块还包括下拉控制单元30，下拉控制单元30的输出端与下拉单元40的控制端和下拉节点P（N）电性连接。
在其中一个实施例中，下拉控制单元30包括第七薄膜晶体管NT3、第八薄膜晶体管NT8以及第九薄膜晶体管NT4，第七薄膜晶体管NT3的源极/漏极中的一个与第七走线电性连接，第七薄膜晶体管NT3的栅极与第八走线电性连接，第七薄膜晶体管NT3的源极/漏极中的另一个与第八薄膜晶体管NT8的栅极电性连接，第八薄膜晶体管NT8的源极/漏极中的一个与第九走线电性连接，第八薄膜晶体管NT8的源极/漏极中的另一个与下拉节点P（N）电性连接，第九薄膜晶体管NT4的源极/漏极中的一个与第十走线电性连接，第九薄膜晶体管NT4的源极/漏极中的另一个与第八薄膜晶体管NT8的栅极电性连接，第九薄膜晶体管NT4的栅极与第十一走线电性连接。
其中，第七走线可以用于传输第n+1个时钟信号CK（n+1）。第八走线可以用于传输正向扫描控制信号U2D。第九走线可以用于传输第二全局控制信号GAS2。第十走线可以用于传输第n-1个时钟信号CK（n-1）。第十一走线可以用于传输反向扫描控制信号D2U。
在其中一个实施例中，下拉控制单元30包括第十薄膜晶体管NT2和第十一薄膜晶体管NT6，第十薄膜晶体管NT2的源极/漏极中的一个与第十一走线电性连接，第十薄膜晶体管NT2的栅极与第十二走线电性连接，第十薄膜晶体管NT2的源极/漏极中的另一个与上拉节点Q（N）和第十一薄膜晶体管NT6的栅极电性连接，第十一薄膜晶体管NT6的源极/漏极中的一个与第一布线电性连接，第十一薄膜晶体管NT6的源极/漏极中的另一个与下拉节点P（N）电性连接。
其中，第十二走线可以用于传输第N+2级扫描信号G（N+2）。
在其中一个实施例中，栅极驱动子模块还包括输入单元10，输入单元10的输出端与上拉节点Q（N）电性连接。
在其中一个实施例中，输入单元10包括第十二薄膜晶体管NT5，第十二薄膜晶体管NT5的源极/漏极中的一个与第八走线电性连接，第十二薄膜晶体管NT5的栅极与第十三走线电性连接，第十二薄膜晶体管NT5的源极/漏极中的另一个与上拉节点Q（N）和第四薄膜晶体管NT7的源极/漏极中的另一个电性连接。
其中，第十三走线可以用于传输第N-2级扫描信号G（N-2）。
在其中一个实施例中，栅极驱动子模块还包括反馈单元50，反馈单元50的输入端与第一布线电性连接，反馈单元50的控制端与下拉节点P（N）电性连接，反馈单元50的输出端与上拉节点Q（N）电性连接。
在其中一个实施例中，反馈单元50包括第十三薄膜晶体管NT1，第十三薄膜晶体管NT1的源极/漏极中的一个与第一布线电性连接，第十三薄膜晶体管NT1的栅极与下拉节点P（N）电性连接，第十三薄膜晶体管NT1的源极/漏极中的另一个与上拉节点Q（N）电性连接。
在其中一个实施例中，栅极驱动子模块还包括第一稳压单元60，第一稳压单元60的一端与第一布线电性连接，第一稳压单元60的另一端与上拉节点Q（N）电性连接。
在其中一个实施例中，第一稳压单元60包括第一电容C1，第一电容C1的一端与第一布线电性连接，第一电容C1的另一端与上拉节点Q（N）电性连接。
在其中一个实施例中，栅极驱动子模块还包括第二稳压单元70，第二稳压单元70的一端与第一布线电性连接，第二稳压单元70的另一端与下拉节点P（N）电性连接。
在其中一个实施例中，第二稳压单元70包括第二电容C2，第二电容C2的一端与第一布线电性连接，第二电容C2的另一端与下拉节点P（N）电性连接。
在其中一个实施例中，第一薄膜晶体管NT12至第十三薄膜晶体管NT1中的至少一个可以但不限于为N沟道型薄膜晶体管，也可以对应调整为P沟道型薄膜晶体管。
在其中一个实施例中，图3所示的栅极驱动模块与图2所示的栅极驱动模块的区别在于，当n等于1时，且N也等于1时，第三薄膜晶体管NT9的源极/漏极中的一个用于接入第一时钟信号CK（1），第七薄膜晶体管NT3的源极/漏极中的一个用于接入第二时钟信号CK（2），第九薄膜晶体管NT4的源极/漏极中的一个用于接入第四时钟信号CK（3），第十二薄膜晶体管NT5的栅极用于接入第负一级扫描信号G（-1），该第负一级扫描信号G（-1）可以采用起始信号进行代替，第十薄膜晶体管NT2的栅极用于接入第三级扫描信号G（3），对应地，此时，第一输出节点R（N）输出的第一驱动信号可以作为第一级扫描信号G（1），第二输出节点S（N）输出的第二驱动信号GLS（N）可以为驱动信号GLS（1）。
在其中一个实施例中，图4所示的栅极驱动模块与图2所示的栅极驱动模块的区别在于，当n等于2时，且N也等于2时，第三薄膜晶体管NT9的源极/漏极中的一个用于接入第二时钟信号CK（2），第七薄膜晶体管NT3的源极/漏极中的一个用于接入第三时钟信号CK（3），第九薄膜晶体管NT4的源极/漏极中的一个用于接入第一时钟信号CK（1），第十二薄膜晶体管NT5的栅极用于接入第零级扫描信号G（0），该第零级扫描信号G（0）可以也可以采用另一起始信号进行代替，第十薄膜晶体管NT2的栅极用于接入第四级扫描信号G（4），对应地，此时，第一输出节点R（N）输出的第一驱动信号可以作为第二级扫描信号G（2），第二输出节点S（N）输出的第二驱动信号GLS（N）可以为驱动信号GLS（2）。
在其中一个实施例中，图5所示的栅极驱动模块与图2所示的栅极驱动模块的区别在于，当n等于3时，且N也等于3时，第三薄膜晶体管NT9的源极/漏极中的一个用于接入第三时钟信号CK（3），第七薄膜晶体管NT3的源极/漏极中的一个用于接入第四时钟信号CK（4），第九薄膜晶体管NT4的源极/漏极中的一个用于接入第二时钟信号CK（2），第十二薄膜晶体管NT5的栅极用于接入第一级扫描信号G（1），第十薄膜晶体管NT2的栅极用于接入第五级扫描信号G（5），对应地，此时，第一输出节点R（N）输出的第一驱动信号可以作为第三级扫描信号G（3），第二输出节点S（N）输出的第二驱动信号GLS（N）可以为驱动信号GLS（3）。
在其中一个实施例中，图6所示的栅极驱动模块与图2所示的栅极驱动模块的区别在于，当n等于4时，且N也等于4时，第三薄膜晶体管NT9的源极/漏极中的一个用于接入第四时钟信号CK（4），第七薄膜晶体管NT3的源极/漏极中的一个用于接入第一时钟信号CK（1），第九薄膜晶体管NT4的源极/漏极中的一个用于接入第三时钟信号CK（3），第十二薄膜晶体管NT5的栅极用于接入第二级扫描信号G（2），第十薄膜晶体管NT2的栅极用于接入第六级扫描信号G（6），对应地，此时，第一输出节点R（N）输出的第一驱动信号可以作为第四级扫描信号G（4），第二输出节点S（N）输出的第二驱动信号GLS（N）可以为驱动信号GLS（4）。
综上所述，本申请提供的栅极驱动电路可以循环使用四条时钟信号线既可以正常工作，减小了时钟信号线的使用数量，有利于实现窄边框。当然，本申请提供的栅极驱动电路也可以采用其他使用数量的时钟信号线，例如，六条或者八条等等。
如图7所示，基于上述分析，本申请提供的栅极驱动电路的工作时序可以为如下：
在栅极驱动电路的正常工作过程中，第一全局控制信号GAS1可以为低电位信号，第二全局控制信号GAS2可以为高电位信号。当显示面板进入触控阶段时，第一全局控制信号GAS1可以为高电位信号，第二全局控制信号GAS2可以为低电位信号。第二恒压高电位信号COM1可以持续为高电位。第二恒压低电位信号COM2也可以持续为低电位。
第一时钟信号CK（1）可以同时输出为相位相同的第一级扫描信号G（1）和驱动信号GLS（1）。
第二时钟信号CK（2）可以同时输出为相位相同的第二级扫描信号G（2）和驱动信号GLS（2）。
第三时钟信号CK（3）可以同时输出为相位相同的第三级扫描信号G（3）和驱动信号GLS（3）。
第四时钟信号CK（4）可以同时输出为相位相同的第四级扫描信号G（4）和驱动信号GLS（4）。
在其中一个实施例中，本实施例提供一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动模块，其中一个栅极驱动模块包括第一晶体管、第二晶体管、第三晶体管以及第四晶体管，第一晶体管的源极/漏极中的一个与第一输出节点R（N）电性连接，第一输出节点R（N）用于输出第一驱动信号；第二晶体管的源极/漏极中的一个与第一输出节点R（N）电性连接，第二晶体管的栅极与下拉节点P（N）电性连接；第三晶体管的栅极与第一输出节点R（N）电性连接，第三晶体管的源极/漏极中的一个与第二输出节点S（N）电性连接，第二输出节点S（N）用于输出第二驱动信号GLS（N）；第四晶体管的栅极与下拉节点P（N）电性连接，第四晶体管的源极/漏极中的一个与第二输出节点S（N）电性连接；其中，第一驱动信号的相位与第二驱动信号GLS（N）的相位相同。
可以理解的是，本实施例提供的栅极驱动电路，通过第一输出节点R（N）可以输出第一驱动信号，同时通过第二输出节点S（N）可以输出与第一驱动信号相位相同的第二驱动信号GLS（N），不仅可以输出多个同相位的驱动信号，而且通过共用第一输出节点R（N）及下拉节点P（N），简化了栅极驱动电路的电路拓扑结构，进而有利于实现显示面板的窄边框。
需要进行说明的是，第一晶体管可以为上述实施例中的第三薄膜晶体管NT9。第二晶体管可以为上述实施例中的第六薄膜晶体管NT10。第三晶体管可以为上述实施例中的第一薄膜晶体管NT12。第四晶体管可以为上述实施例中的第二薄膜晶体管NT13。
在其中一个实施例中，其中一个栅极驱动模块还包括第五晶体管，第五晶体管的源极/漏极中的一个与第一晶体管的栅极电性连接。
需要进行说明的是，第五晶体管可以为上述实施例中的第四薄膜晶体管NT7。
在其中一个实施例中，第一走线与第二晶体管的源极/漏极中的另一个电性连接，用于传输第一恒压低电位信号VGL；第二走线与第四晶体管的源极/漏极中的另一个电性连接，用于传输第二恒压低电位信号COM2；第三走线与第五晶体管的栅极电性连接，用于传输第一恒压高电位信号VGH；第四走线与第三晶体管的源极/漏极中的另一个电性连接，用于传输第二恒压高电位信号COM1。
在其中一个实施例中，本实施例提供一种显示面板，其包括上述任一实施例中的栅极驱动电路、多条扫描线以及遮光金属层，其中一条扫描线与第一输出节点R（N）/第二输出节点S（N）中的一个电性连接；遮光金属层包括至少一个遮光金属块，至少一个遮光金属块与第一输出节点R（N）/第二输出节点S（N）中的另一个电性连接。
可以理解的是，本实施例提供的显示面板，通过第一输出节点R（N）可以输出第一驱动信号，同时通过第二输出节点S（N）可以输出与第一驱动信号相位相同的第二驱动信号GLS（N），不仅可以输出多个同相位的驱动信号，而且通过共用第一输出节点R（N）及下拉节点P（N），简化了栅极驱动电路的电路拓扑结构，进而有利于实现显示面板的窄边框。同时，对应的扫描线和遮光金属层通入相同相位的驱动信号，可以降低两者之间的电压差，进而降低对应遮光金属块的耦合效应，可以减少或者避免遮光金属块对应的薄膜晶体管误开关或者漏电流。
需要进行说明的是，显示面板可以包括阵列基板，阵列基板设置有多个薄膜晶体管，每个薄膜晶体管具有至少一个有源区，每个遮光金属块可以用于为一个有源区进行遮光，可以稳定对应薄膜晶体管的工作状态。
在其中一个实施例中，显示面板还包括显示区和非显示区，至少一个遮光金属块位于显示区；其中一条扫描线的至少部分位于非显示区。
在其中一个实施例中，在显示面板的厚度方向上，其中一条扫描线与至少一个遮光金属块至少部分重叠。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动模块，其中一个栅极驱动模块包括：
    栅极驱动子模块，所述栅极驱动子模块包括第一输出节点和下拉节点，所述第一输出节点用于输出第一驱动信号；和
    同相输出子模块，所述同相输出子模块包括第一控制节点、第二控制节点以及第二输出节点，所述第一控制节点与所述第一输出节点电性连接，所述第二控制节点与所述下拉节点电性连接，所述第二输出节点用于输出第二驱动信号，且所述第二驱动信号的相位与所述第一驱动信号的相位相同。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述其中一个栅极驱动模块还包括：
    第一走线，与所述栅极驱动子模块电性连接，用于传输第一恒压低电位信号；
    第二走线，与所述同相输出子模块电性连接，用于传输第二恒压低电位信号；
    第三走线，与所述栅极驱动子模块电性连接，用于传输第一恒压高电位信号；以及
    第四走线，与所述同相输出子模块电性连接，用于传输第二恒压高电位信号。
  3. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动子模块包括：
    上拉单元；和
    下拉单元，所述下拉单元的输出端与所述上拉单元的输出端和所述第一输出节点电性连接。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述栅极驱动子模块还包括：
    下拉控制单元，所述下拉控制单元的输出端与所述下拉单元的控制端和所述下拉节点电性连接。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述栅极驱动子模块还包括：
    输入单元，所述输入单元的输出端与所述上拉节点电性连接。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述栅极驱动子模块还包括：
    反馈单元，所述反馈单元的输入端与第一布线电性连接，所述反馈单元的控制端与所述下拉节点电性连接，所述反馈单元的输出端与所述上拉节点电性连接。
  7. 根据权利要求6所述的栅极驱动电路，其中，所述栅极驱动子模块还包括：
    第一稳压单元，所述第一稳压单元的一端与所述第一布线电性连接，所述第一稳压单元的另一端与所述上拉节点电性连接。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述栅极驱动子模块还包括：
    第二稳压单元，所述第二稳压单元的一端与所述第一布线电性连接，所述第二稳压单元的另一端与所述下拉节点电性连接。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述同相输出子模块包括：
    第一薄膜晶体管，所述第一薄膜晶体管的源极/漏极中的一个与第四走线电性连接，所述第一薄膜晶体管的栅极与所述第一输出节点电性连接；和
    第二薄膜晶体管，所述第二薄膜晶体管的源极/漏极中的一个与所述第一薄膜晶体管的源极/漏极中的另一个和所述第二输出节点电性连接，所述第二薄膜晶体管的栅极与所述下拉节点电性连接，所述第二薄膜晶体管的源极/漏极中的另一个与第二走线电性连接。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述上拉单元包括：
    第三薄膜晶体管，所述第三薄膜晶体管的源极/漏极中的一个与第五走线电性连接，所述第三薄膜晶体管的源极/漏极中的另一个与所述第一输出节点电性连接。
  11. 根据权利要求10所述的栅极驱动电路，其中，所述上拉单元还包括：
    第四薄膜晶体管，所述第四薄膜晶体管的源极/漏极中的一个与所述第三薄膜晶体管的栅极电性连接，所述第四薄膜晶体管的栅极与第三走线电性连接。
  12. 根据权利要求11所述的栅极驱动电路，其中，所述上拉单元还包括：
    第五薄膜晶体管，所述第五薄膜晶体管的源极/漏极中的一个与所述第一输出节点电性连接，所述第五薄膜晶体管的栅极与第六走线和所述第五薄膜晶体管的源极/漏极中的另一个电性连接。
  13. 根据权利要求12所述的栅极驱动电路，其中，所述下拉单元包括：
    第六薄膜晶体管，所述第六薄膜晶体管的源极/漏极中的一个与所述第一输出节点电性连接，所述第六薄膜晶体管的栅极与所述下拉节点电性连接，所述第六薄膜晶体管的源极/漏极中的另一个与所述第一走线电性连接。
  14. 根据权利要求13所述的栅极驱动电路，其中，所述下拉控制单元包括：
    第七薄膜晶体管，所述第七薄膜晶体管的源极/漏极中的一个与第七走线电性连接，所述第七薄膜晶体管的栅极与第八走线电性连接；
    第八薄膜晶体管，所述第八薄膜晶体管的栅极与所述第七薄膜晶体管的源极/漏极中的另一个与电性连接，所述第八薄膜晶体管的源极/漏极中的一个与第九走线电性连接，所述第八薄膜晶体管的源极/漏极中的另一个与所述下拉节点电性连接；以及
    第九薄膜晶体管，所述第九薄膜晶体管的源极/漏极中的一个与第十走线电性连接，所述第九薄膜晶体管的源极/漏极中的另一个与所述第八薄膜晶体管的栅极电性连接，所述第九薄膜晶体管的栅极与第十一走线电性连接。
  15. 一种栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动模块，其中一个栅极驱动模块包括：
    第一晶体管NT9，所述第一晶体管的源极/漏极中的一个与第一输出节点电性连接，所述第一输出节点用于输出第一驱动信号；
    第二晶体管NT10，所述第二晶体管的源极/漏极中的一个与所述第一输出节点电性连接，所述第二晶体管的栅极与下拉节点电性连接；
    第三晶体管NT12，所述第三晶体管的栅极与所述第一输出节点电性连接，所述第三晶体管的源极/漏极中的一个与第二输出节点电性连接，所述第二输出节点用于输出第二驱动信号；以及
    第四晶体管NT13，所述第四晶体管的栅极与所述下拉节点电性连接，所述第四晶体管的源极/漏极中的一个与所述第二输出节点电性连接；
    其中，所述第一驱动信号的相位与所述第二驱动信号的相位相同。
  16. 根据权利要求15所述的栅极驱动电路，其中，所述其中一个栅极驱动模块还包括：
    第五晶体管，所述第五晶体管的源极/漏极中的一个与所述第一晶体管的栅极电性连接。
  17. 根据权利要求16所述的栅极驱动电路，其中，所述其中一个栅极驱动模块还包括：
    第一走线，与所述第二晶体管的源极/漏极中的另一个电性连接，用于传输第一恒压低电位信号；
    第二走线，与所述第四晶体管的源极/漏极中的另一个电性连接，用于传输第二恒压低电位信号；
    第三走线，与所述第五晶体管的栅极电性连接，用于传输第一恒压高电位信号；以及
    第四走线，与所述第三晶体管的源极/漏极中的另一个电性连接，用于传输第二恒压高电位信号。
  18. 一种显示面板，包括：
    如权利要求1所述的栅极驱动电路；
    多条扫描线，其中一条扫描线与所述第一输出节点/所述第二输出节点中的一个电性连接；以及
    遮光金属层，所述遮光金属层包括至少一个遮光金属块，所述至少一个遮光金属块与所述第一输出节点/所述第二输出节点中的另一个电性连接。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板还包括：
    显示区，所述至少一个遮光金属块位于所述显示区；和
    非显示区，所述其中一条扫描线的至少部分位于所述非显示区。
  20. 根据权利要求18所述的显示面板，其中，在所述显示面板的厚度方向上，所述其中一条扫描线与所述至少一个遮光金属块至少部分重叠。
PCT/CN2021/115642 2021-08-05 2021-08-31 栅极驱动电路及显示面板 Ceased WO2023010635A1 (zh)

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