WO2023005304A1 - 硅/钙钛矿叠层太阳能电池及其制备方法 - Google Patents

硅/钙钛矿叠层太阳能电池及其制备方法 Download PDF

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WO2023005304A1
WO2023005304A1 PCT/CN2022/089632 CN2022089632W WO2023005304A1 WO 2023005304 A1 WO2023005304 A1 WO 2023005304A1 CN 2022089632 W CN2022089632 W CN 2022089632W WO 2023005304 A1 WO2023005304 A1 WO 2023005304A1
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layer
silicon
type doped
amorphous silicon
silicon layer
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French (fr)
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薛建锋
朱茂礼
王永洁
余义
苏世杰
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通威太阳能（安徽）有限公司
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Priority to AU2022291601A priority Critical patent/AU2022291601A1/en
Priority to EP22808927.2A priority patent/EP4148813A4/en
Priority to US18/003,545 priority patent/US20240172459A1/en
Publication of WO2023005304A1 publication Critical patent/WO2023005304A1/zh

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Definitions

  • the present disclosure relates to the technical field of perovskite stacked cells, and in particular to a silicon/perovskite stacked solar cell and a preparation method thereof.
  • Perovskite laminated cells belong to the third-generation photovoltaic technology. As a new type of semiconductor material that has attracted the most attention in recent years, it has broad application prospects in many fields such as photovoltaics, detection, display, and lighting. However, perovskite laminated cells in the existing technology After the multi-layer battery is prepared, there are often problems of low open circuit voltage and low conversion efficiency.
  • the present disclosure provides a silicon/perovskite tandem solar cell, comprising a silicon bottom cell and a perovskite top cell, and seed crystals are sequentially arranged between the surface of the silicon bottom cell and the bottom surface of the perovskite top cell a silicon layer and a tunneling layer, the seed silicon layer is adjacent to the silicon bottom cell, the tunneling layer is adjacent to the perovskite top cell;
  • the seed silicon layer is an amorphous silicon layer
  • the tunneling layer is a doped microcrystalline silicon oxide layer, a doped carbonized microcrystalline silicon layer or a doped carbonized microcrystalline silicon oxide layer.
  • the thickness of the amorphous silicon layer is 1-3 nm; the thickness of the tunneling layer is 10-30 nm.
  • the silicon bottom cell includes an N-type doped amorphous silicon layer, a first intrinsic amorphous silicon layer, an N-type silicon wafer, and a second intrinsic amorphous silicon layer arranged in sequence from top to bottom. and a P-type doped amorphous silicon layer, the tunneling layer is a P-type doped microcrystalline silicon oxide layer, a P-type doped carbonized microcrystalline silicon layer or a P-type doped carbonized microcrystalline silicon oxide layer.
  • the silicon bottom cell includes a P-type doped amorphous silicon layer, a first intrinsic amorphous silicon layer, a P-type silicon wafer, and a second intrinsic amorphous silicon layer arranged in sequence from top to bottom.
  • the tunneling layer is an N-type doped microcrystalline silicon oxide layer, an N-type doped carbonized microcrystalline silicon layer or an N-type doped carbonized microcrystalline silicon oxide layer.
  • the present disclosure also provides a method for preparing the above-mentioned silicon/perovskite tandem solar cell, including:
  • the amorphous silicon layer is deposited on the upper surface of the silicon bottom cell, and the tunneling layer is deposited on the surface of the amorphous silicon layer, wherein the tunneling layer is the doped microcrystalline silicon oxide layer, doped carbonized microcrystalline silicon layer or doped carbonized microcrystalline silicon oxide layer;
  • the perovskite top cell is formed on the surface of the tunneling layer.
  • the deposition conditions of the amorphous silicon layer include: the gas source SiH 4 has a flow rate in the range of 200-1000 sccm; a gas pressure in the range of 0.3-1 mbar, and a radio frequency power in the range of 300-800 W.
  • the tunneling layer is a P-type doped microcrystalline silicon oxide layer, and the deposition condition of the tunneling layer is: the flow ratio of H 2 , SiH 4 , CO 2 , and B 2 H 6 is (200-500):(1-3):1:(1-3), air pressure range is 0.5-2mbar, RF power range is 1000-3000W;
  • the tunneling layer is a P-type doped carbonized microcrystalline silicon layer, and the deposition conditions of the tunneling layer are: the flow ratio of H 2 , SiH 4 , CH 4 , and B 2 H 6 is (200-500 ):(1-3):1:(1-3), the air pressure range is 0.5-2mbar, and the RF power range is 1000-3000W;
  • the tunneling layer is a P-type doped carbonized microcrystalline silicon oxide layer, and the deposition conditions of the tunneling layer are: the flow ratio of H 2 , SiH 4 , CO 2 , CH 4 , and B 2 H 6 is (200-500):(1-3):1:(1-3):(1-3), the air pressure range is 0.5-2mbar, and the RF power range is 1000-3000W.
  • it includes: texturizing an N-type silicon wafer; depositing a first intrinsic amorphous silicon layer on the front side of the N-type silicon wafer, and depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer. Silicon layer; an N-type doped amorphous silicon layer is formed on the surface of the first intrinsic amorphous silicon layer away from the N-type silicon wafer, and an N-type doped amorphous silicon layer is formed on the surface of the second intrinsic amorphous silicon layer away from the N-type silicon wafer. A P-type doped amorphous silicon layer is formed on the surface of the silicon wafer.
  • the tunneling layer is an N-type doped microcrystalline silicon oxide layer
  • the deposition conditions of the tunneling layer are: the flow ratio of H 2 , SiH 4 , CO 2 , and PH 3 is (200 -500):(1-3):1:(1-3), air pressure range is 0.5-2mbar, RF power range is 1000-3000W;
  • the tunneling layer is an N-type doped microcrystalline silicon carbide layer, and the deposition conditions of the tunneling layer are: the flow ratio of H 2 , SiH 4 , CH 4 , and PH 3 is (200-500): (1-3):1:(1-3), air pressure range is 0.5-2mbar, RF power range is 1000-3000W;
  • the tunneling layer is an N-type doped carbonized microcrystalline silicon oxide layer, and the deposition conditions of the tunneling layer are: the flow ratio of H 2 , SiH 4 , CO 2 , CH 4 , and PH 3 is (200 -500):(1-3):1:(1-3):(1-3), the air pressure range is 0.5-2mbar, and the RF power range is 1000-3000W.
  • the method for forming the silicon bottom cell includes: texturizing a P-type silicon wafer; depositing a first intrinsic amorphous silicon layer on the front surface of the P-type silicon wafer, and depositing a first intrinsic amorphous silicon layer on the silicon wafer A second intrinsic amorphous silicon layer is deposited on the backside of the first intrinsic amorphous silicon layer; a P-type doped amorphous silicon layer is formed on the surface of the first intrinsic amorphous silicon layer away from the P-type silicon wafer, and a P-type doped amorphous silicon layer is formed on the second intrinsic amorphous silicon layer.
  • An N-type doped amorphous silicon layer is formed on the surface of the amorphous silicon layer away from the P-type silicon sheet.
  • the deposition conditions of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer respectively include: the flow ratio of H 2 to SiH 4 is (1-15):1, and the gas pressure range 0.3-1mbar, RF power range is 300-1200W.
  • the deposition conditions of the P-type doped amorphous silicon layer 216 include: the flow ratio of H 2 , SiH 4 and B 2 H 6 is (5-10):1:(1-10), The air pressure range is 0.5-2mbar, and the RF power range is 1000-3000W.
  • the deposition conditions of the N-type doped amorphous silicon layer 212 include: the flow ratio of H 2 , SiH 4 , and PH 3 is (5-10):1:(1-10), and the gas pressure range is 0.5 -2mbar, RF power range is 1000-3000W.
  • FIG. 1 is a schematic diagram of the first structure of a silicon/perovskite tandem solar cell provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a second structure of a silicon/perovskite tandem solar cell provided by an embodiment of the present disclosure
  • Fig. 3 is the structural representation of the silicon/perovskite laminated solar cell that comparative example 1 provides;
  • Fig. 4 is the structural representation of the silicon/perovskite laminated solar cell that comparative example 2 provides;
  • Fig. 5 is the structural representation of the silicon/perovskite laminated solar cell that comparative example 3 provides;
  • Fig. 6 is the structural representation of the silicon/perovskite laminated solar cell that comparative example 4 provides;
  • Example 7 is a TEM image after step (6) of the method for preparing a silicon/perovskite tandem solar cell provided in Example 1 of the present disclosure
  • Example 8 is a Raman spectrum test chart of a doped microcrystalline silicon oxide layer prepared by the method for preparing a silicon/perovskite stacked solar cell provided in Example 1, Example 2 and Comparative Example 4 of the present disclosure.
  • Icons 116, 212-N-type doped amorphous silicon layer; 115, 215-first intrinsic amorphous silicon layer; 114-N-type silicon wafer; 113, 213-second intrinsic amorphous silicon layer, 112, 216-P-type doped amorphous silicon layer; 111,211-ITO conductive film layer; 134-transparent conductive oxide layer; 133-electron transport layer; 132-perovskite layer; 131-hole transport layer; 121,221 -seed crystal silicon layer; 122-P-type doped microcrystalline silicon oxide layer; 214-P type silicon chip; 222-N-type doped microcrystalline silicon oxide layer; 311-silicon oxide layer; 312-alumina and silicon nitride layer.
  • the general method for preparing perovskite laminated cells is: form a P-type doped amorphous silicon layer on the back of an N-type silicon wafer, and sequentially form a silicon dioxide layer and an N-type doped amorphous silicon layer on the front of an N-type silicon wafer. Silicon layer, and then use the N-type doped amorphous silicon layer as the light-receiving surface, and form a perovskite battery on it (the hole transport layer of the perovskite battery is in contact with the N-type doped amorphous silicon layer) to obtain a perovskite Laminated battery. After the perovskite laminated battery is prepared, the open circuit voltage and conversion efficiency are not high.
  • some embodiments of the present disclosure provide a silicon/perovskite stacked solar cell and a preparation method thereof, which can improve the open circuit voltage and conversion efficiency of the cell.
  • Some embodiments of the present disclosure provide two kinds of silicon/perovskite tandem solar cells.
  • Some embodiments of the present disclosure provide a silicon/perovskite tandem solar cell.
  • the silicon bottom cell of the cell is a silicon cell formed on an N-type silicon wafer. Please refer to FIG. 1 for a schematic structural diagram.
  • the silicon cell includes an N-type doped amorphous silicon layer 116, a first intrinsic amorphous silicon layer 115, an N-type silicon wafer 114, a second intrinsic amorphous silicon layer 113, a P-type doped
  • the perovskite top cell includes a transparent conductive oxide layer 134 , an electron transport layer 133 , a perovskite layer 132 and a hole transport layer 131 arranged in sequence from top to bottom.
  • the transparent conductive oxide layer 134 may be an IZO transparent conductive thin film layer, and the upper surface of the IZO transparent conductive thin film layer has a silver electrode in ohmic contact with it.
  • the electron transport layer 133 may be a SnO 2 layer, a C60 layer and a LiF layer stacked from top to bottom.
  • the material of the hole transport layer 131 is Spiro-TTB or PTAA.
  • the N-type doped amorphous silicon layer is directly in contact with the hole transport layer. Due to the high crystallinity of the N-type doped amorphous silicon layer, the hole transport The material of the layer is a P-type amorphous organic material, and the direct overlap of the two will cause the problem of lattice mismatch tunneling, which will lead to low open circuit voltage and conversion efficiency of the perovskite stacked battery.
  • a seed silicon layer 121 and a tunneling layer are sequentially arranged between the surface of the silicon bottom cell and the bottom surface of the perovskite top cell, the seed silicon layer is close to the silicon bottom cell, and the tunneling layer Close to the perovskite top cell.
  • the seed crystal silicon layer 121 is an amorphous silicon layer
  • the tunneling layer is a P-type doped microcrystalline silicon oxide layer 122, a P-type doped carbonized microcrystalline silicon layer, or a P-type doped carbonized microcrystalline silicon oxide layer.
  • layer (FIG. 1 uses the microcrystalline silicon oxide layer 122 doped with P-type as an example to illustrate the tunneling layer).
  • the seed silicon layer 121 (amorphous silicon layer), the tunneling layer (P-type doped microcrystalline silicon oxide layer 122, P Type-doped carbonized microcrystalline silicon layer or P-type doped carbonized microcrystalline silicon oxide layer), and then stack the hole transport layer 131 of the perovskite top cell on the tunneling layer.
  • the seed crystal silicon layer 121 can be used as a seed crystal silicon layer, which can induce the growth of a nucleation layer, so as to subsequently grow a large-grained microcrystalline silicon oxide layer, a carbonized microcrystalline silicon layer, or a carbonized microcrystalline silicon oxide layer, Moreover, the crystallinity of this layer is high, and more doping elements can be accommodated to make the doping concentration higher.
  • the P-type doped microcrystalline silicon oxide layer 122 compared to the N-type doped polycrystalline layer 116, the P-type doped microcrystalline silicon oxide layer 122, the P-type doped carbonized microcrystalline silicon layer, or the P-type doped carbonized microcrystalline silicon oxide layer 122
  • the crystallinity of the layer is low, the density of defect states is high, and it is convenient for the movement of carriers. It can be used as a good tunneling material, so that the tunneling between the silicon bottom cell and the perovskite top cell is easier to improve The open circuit voltage and conversion efficiency of the battery.
  • the thickness of the amorphous silicon layer is 1-3 nm; the P-type doped microcrystalline silicon oxide layer 122, the P-type doped carbonized microcrystalline silicon layer or the P-type doped carbonized microcrystalline silicon oxide layer
  • the thickness is 10-30nm.
  • the very thin amorphous silicon layer basically does not affect the thickness of the perovskite stacked battery, and can form a tunneling layer well, so that the open circuit voltage and conversion efficiency of the battery are higher.
  • the thickness of the amorphous silicon layer is, for example, 1.1-2.9nm, 1.2-2.8nm or 1.3-2.7nm, such as 1nm, 2nm or 3nm;
  • the thickness of the P-type doped microcrystalline silicon oxide layer 122 is, for example, 12-28nm, 15-25nm or 18-22nm, such as 10nm, 15nm, 20nm, 25nm or 30nm, or the thickness of the P-type doped carbonized microcrystalline silicon layer is, for example, 12-28nm, 15-25nm or 18-22nm, Such as 10nm, 15nm, 20nm, 25nm or 30nm, or the thickness of the p-type doped carbonized microcrystalline silicon oxide layer is eg 12-28nm, 15-25nm or 18-22nm, such as 10nm, 15nm, 20nm, 25nm or 30nm.
  • the preparation method of the above-mentioned silicon/perovskite laminated solar cell comprises the following steps:
  • the N-type silicon wafer 114 with a size of 156.75 mm and a thickness of 180 ⁇ m is subjected to texturing and cleaning treatments.
  • first intrinsic amorphous silicon layer 115 depositing a first intrinsic amorphous silicon layer 115 on the front surface of the N-type silicon wafer 114 , and depositing a second intrinsic amorphous silicon layer 113 on the back surface of the N-type silicon wafer 114 .
  • first intrinsic amorphous silicon layer 115 and the second intrinsic amorphous silicon layer 113 are prepared by PECVD.
  • SiH 4 or pure SiH 4 is diluted with H 2 to deposit single-layer or stacked amorphous silicon films, wherein the deposition conditions of the intrinsic amorphous silicon layer include: the flow ratio of H 2 to SiH 4 is (1-15):1, such as (2-14):1, (3-12):1 or (5-10):1; pressure range is 0.3-1mbar, such as 0.4-0.9mbar, 0.5-0.8mbar Or 0.6-0.7mbar; RF power range is 300-1200W, such as 400-1100W, 500-1000W or 600-800W.
  • the first intrinsic amorphous silicon layer 115 and the second intrinsic amorphous silicon layer 113 with a thickness of 3-10 nm.
  • an N-type doped amorphous silicon layer 116 is deposited on the surface of the first intrinsic amorphous silicon layer 115 away from the N-type silicon wafer 114 .
  • the deposition conditions of the N-type doped amorphous silicon layer 116 include: the flow ratio of H 2 , SiH 4 and PH 3 is (5-10):1:(1-10), for example (6-9):1:( 2-8), (7-8):1:(3-7) or (7-8):1:(4-6); pressure range is 0.5-2mbar, such as 0.6-1.9mbar, 0.7-1.8mbar Or 0.8-1.5mbar; RF power range is 1000-3000W, such as 1200-2800W, 1500-2500W or 1800-2200W. To obtain an N-type doped amorphous silicon layer 116 with a thickness of 10-30 nm.
  • a P-type doped amorphous silicon layer 112 on the surface of the second intrinsic amorphous silicon layer 113 away from the N-type silicon wafer 114 .
  • the P-type doped amorphous silicon layer 112 is deposited on the surface of the second intrinsic amorphous silicon layer 113 away from the N-type silicon wafer 114 .
  • the deposition conditions of the P-type doped amorphous silicon layer 112 include: the flow ratio of H 2 , SiH 4 and B 2 H 6 is (5-10):1:(1-10), for example (6-9):1 :(2-8), (7-8):1:(3-7) or (7-8):1:(4-6); pressure range is 0.5-2mbar, such as 0.6-1.9mbar, 0.7- 1.8mbar or 0.8-1.5mbar; RF power range is 1000-3000W, such as 1200-2800W, 1500-2500W or 1800-2200W. To obtain a P-type doped amorphous silicon layer 112 with a thickness of 10-30 nm.
  • steps S115 and S116 can be prepared here, or can be prepared after the step S20 is completed, which is not limited in the present disclosure.
  • a seed silicon layer 121 depositing a seed silicon layer 121 on the upper surface of the silicon bottom cell, and depositing a tunneling layer on the surface of the seed silicon layer 121, wherein the tunneling layer is a P-type doped microcrystalline silicon oxide layer 122, a P-type doped Doped carbonized microcrystalline silicon layer or P-type doped carbonized microcrystalline silicon oxide layer.
  • the tunneling layer is a P-type doped microcrystalline silicon oxide layer 122, a P-type doped Doped carbonized microcrystalline silicon layer or P-type doped carbonized microcrystalline silicon oxide layer.
  • an amorphous silicon layer is deposited on the surface of the N-type doped amorphous silicon layer 116, and a tunneling layer is deposited on the surface of the amorphous silicon layer.
  • the deposition conditions of the amorphous silicon layer are: the gas source SiH
  • the flow rate range is 200-1000sccm, such as 300-900sccm, 400-800sccm or 500-700sccm, such as 200sccm, 400sccm, 500sccm, 600sccm, 800sccm or 1000sccm ;Air pressure range of 0.3-1mbar, such as 0.4-0.9mbar, 0.5-0.8mbar or 0.6-0.7mbar, such as 0.3mbar, 0.4mbar, 0.5mbar, 0.6mbar, 0.7mbar, 0.8mbar, 0.9mbar or 1mbar, RF power
  • the range is 300-800W, eg 400-700W, 450-650W or 500-600W, such as 300W, 400W, 500W, 600W, 700W, 800W. In order to obtain an amorphous silicon layer with a thickness of 1-3nm.
  • the tunneling layer is a P-type doped microcrystalline silicon oxide layer 122, and its deposition conditions are: the flow ratio of H 2 , SiH 4 , CO 2 , and B 2 H 6 is (200-500): (1-3):1:(1-3), for example (250-450):(1.2-2.8):1:(1.2-2.8), (280-420):(1.3-2.7):1:( 1.3-2.7) or (320-380):(1.4-2.6):1:(1.4-2.6); the air pressure range is 0.5-2mbar, such as 0.8-1.8mbar, 1.0-1.6mbar or 1.2-1.4mbar, such as 0.5 mbar, 1.0mbar, 1.5mbar, 1.9mbar; RF power range is 1000-3000W, such as 1200-2800W, 1500-2500W or 1800-2200W, such as 1100W, 1300W, 1500W, 1700W, 1900W, 2100W, 2300W, 2500W, 2700W , 2900W.
  • the tunneling layer is a P-type doped carbonized microcrystalline silicon layer, and its deposition conditions are: the flow ratio of H 2 , SiH 4 , CH 4 , and B 2 H 6 is (200-500):( 1-3):1:(1-3), for example (250-450):(1.2-2.8):1:(1.2-2.8), (280-420):(1.3-2.7):1:(1.3 -2.7) or (320-380):(1.4-2.6):1:(1.4-2.6); the air pressure range is 0.5-2mbar, such as 0.7-1.9mbar, 1.0-1.6mbar or 1.2-1.4mbar, such as 0.5mbar . 2900W.
  • the carbon source is not limited to methane, but can also be ethane or propane.
  • the tunneling layer is a P-type doped carbonized microcrystalline silicon oxide layer, and its deposition conditions are: the flow ratio of H 2 , SiH 4 , CO 2 , CH 4 , and B 2 H 6 is (200- 500):(1-3):1:(1-3):(1-3), for example (250-450):(1.2-2.8):1:(1.2-2.8), (280-420): (1.3-2.7):1:(1.3-2.7) or (320-380):(1.4-2.6):1:(1.4-2.6); pressure range is 0.5-2mbar, such as 0.7-1.9mbar, 1.0-1.6 mbar or 1.2-1.4mbar, such as 0.5mbar, 1.0mbar, 1.5mbar, 1.9mbar; RF power range is 1000-3000W, such as 1200-2800W, 1500-2500W or 1800-2200W, such as 1100W, 1300W, 1500W, 1700W, 1900W, 2100W, 2300W, 2500W, 2700W,
  • a hole transport layer 131 , a perovskite layer 132 , an electron transport layer 133 and a transparent conductive oxide layer 134 are sequentially deposited on the surface of the tunneling layer.
  • a Spiro-TTB layer, a Perovskite layer, a LiF layer, a C60 layer, a SnO 2 layer, a TCO layer and a silver electrode are sequentially deposited on the surface of the tunneling layer.
  • Some embodiments of the present disclosure also provide another silicon/perovskite tandem solar cell.
  • the silicon bottom cell of this cell is a silicon cell formed on a P-type silicon wafer 214 .
  • FIG. 2 for a schematic structural diagram.
  • the silicon cell includes a P-type doped amorphous silicon layer 216, a first intrinsic amorphous silicon layer 215, a P-type silicon wafer 214, a second intrinsic amorphous silicon layer 213, an N-type doped
  • the structure of the perovskite top cell is the same as that of the perovskite top cell of the silicon bottom cell of the first silicon/perovskite tandem solar cell, and will not be repeated here.
  • the P-type doped amorphous silicon layer is directly in contact with the hole transport layer. Because the crystallinity of the P-type doped amorphous silicon layer is too high, the electron transport layer The material is an N-type amorphous material, and the direct overlap of the two will cause the problem of lattice mismatch tunneling, which will lead to low open circuit voltage and conversion efficiency of the perovskite stack cell.
  • a seed silicon layer 221 and a tunneling layer are sequentially arranged between the surface of the silicon bottom cell and the bottom surface of the perovskite top cell, the seed silicon layer is close to the silicon bottom cell, and the tunneling layer Close to the perovskite top cell.
  • the seed silicon layer 221 is an amorphous silicon layer
  • the tunneling layer is an N-type doped microcrystalline silicon oxide layer 222, an N-type doped carbonized microcrystalline silicon layer, or an N-type doped carbonized microcrystalline silicon oxide layer.
  • the tunneling layer is an N-type doped microcrystalline silicon oxide layer 222 as an example for illustration).
  • the seed silicon layer 221 (amorphous silicon layer)
  • the tunneling layer (N-type doped microcrystalline silicon oxide layer 222, N Type-doped carbonized microcrystalline silicon layer or N-type doped carbonized microcrystalline silicon oxide layer), and then stack the hole transport layer 131 of the perovskite top cell on the tunneling layer.
  • the seed crystal silicon layer 221 can be used as a seed crystal silicon layer, which can induce the growth of a nucleation layer, so as to subsequently grow a large-grained microcrystalline silicon oxide layer, a carbonized microcrystalline silicon layer, or a carbonized microcrystalline silicon oxide layer, Moreover, the crystallinity of this layer is high, and more doping elements can be accommodated to make the doping concentration higher.
  • the N-type doped microcrystalline silicon oxide layer 222 compared to the P-type doped polycrystalline layer 216, the N-type doped microcrystalline silicon oxide layer 222, the N-type doped carbonized microcrystalline silicon layer, or the N-type doped carbonized microcrystalline silicon oxide layer 222
  • the crystallinity of the layer is low, the density of defect states is high, and it is convenient for the movement of carriers. It can be used as a good tunneling material, so that the tunneling between the silicon bottom cell and the perovskite top cell is easier to improve The open circuit voltage and conversion efficiency of the battery.
  • the thickness of the amorphous silicon layer is 1-3 nm; the N-type doped microcrystalline silicon oxide layer 222, the N-type doped carbonized microcrystalline silicon layer or the N-type doped carbonized microcrystalline silicon oxide layer
  • the thickness is 10-30nm.
  • the very thin amorphous silicon layer basically does not affect the thickness of the perovskite stacked battery, and can form a tunneling layer well, so that the open circuit voltage and conversion efficiency of the battery are higher.
  • the thickness of the amorphous silicon layer is, for example, 1.1-2.9nm, 1.2-2.8nm or 1.3-2.7nm, such as 1nm, 2nm or 3nm;
  • the thickness of the N-type doped microcrystalline silicon oxide layer 222 is, for example, 12-28nm, 15-25nm or 18-22nm, such as 10nm, 15nm, 20nm, 25nm or 30nm, or the thickness of the N-type doped carbonized microcrystalline silicon layer is, for example, 12-28nm, 15-25nm or 18-22nm, Such as 10nm, 15nm, 20nm, 25nm or 30nm, or the thickness of the N-type doped carbonized microcrystalline silicon oxide layer is eg 12-28nm, 15-25nm or 18-22nm, such as 10nm, 15nm, 20nm, 25nm or 30nm.
  • the preparation method of the above-mentioned silicon/perovskite laminated solar cell comprises the following steps:
  • the P-type silicon wafer 214 with a size of 156.75 mm and a thickness of 180 ⁇ m is subjected to texturing and cleaning treatments.
  • first intrinsic amorphous silicon layer 215 depositing a first intrinsic amorphous silicon layer 215 on the front surface of the P-type silicon wafer 214 , and depositing a second intrinsic amorphous silicon layer 213 on the back surface of the P-type silicon wafer 214 .
  • the preparation 213 of the first intrinsic amorphous silicon layer 215 and the second intrinsic amorphous silicon layer is performed by PECVD.
  • SiH 4 or pure SiH 4 is diluted with H 2 to deposit single-layer or stacked amorphous silicon films, wherein the deposition conditions of the intrinsic amorphous silicon layer include: the flow ratio of H 2 to SiH 4 is (1-15):1, such as (2-14):1, (3-12):1 or (5-10):1; pressure range is 0.3-1mbar, such as 0.4-0.9mbar, 0.5-0.8mbar Or 0.6-0.7mbar; RF power range is 300-1200W, such as 400-1100W, 500-1000W or 600-800W.
  • the first intrinsic amorphous silicon layer 215 and the second intrinsic amorphous silicon layer 213 with a thickness of 3-10 nm.
  • a P-type doped amorphous silicon layer 216 is deposited on the surface of the first intrinsic amorphous silicon layer 215 away from the P-type silicon wafer 214 .
  • the deposition conditions of the P-type doped amorphous silicon layer 216 include: the flow ratio of H 2 , SiH 4 and B 2 H 6 is (5-10):1:(1-10), for example (6-9):1 :(2-8), (7-8):1:(3-7) or (7-8):1:(4-6); pressure range is 0.5-2mbar, such as 0.6-1.9mbar, 0.7- 1.8mbar or 0.8-1.5mbar; RF power range is 1000-3000W, such as 1200-2800W, 1500-2500W or 1800-2200W. To obtain a P-type doped amorphous silicon layer 216 with a thickness of 10-30 nm.
  • N-type doped amorphous silicon layer 212 is deposited on the surface of the second intrinsic amorphous silicon layer 213 away from the P-type silicon wafer 214 .
  • the deposition conditions of the N-type doped amorphous silicon layer 212 include: the flow ratio of H 2 , SiH 4 and PH 3 is (5-10):1:(1-10), for example (6-9):1:( 2-8), (7-8):1:(3-7) or (7-8):1:(4-6); pressure range is 0.5-2mbar, such as 0.6-1.9mbar, 0.7-1.8mbar or 0.8-1.5mbar;, the RF power range is 1000-3000W, such as 1200-2800W, 1500-2500W or 1800-2200W. To obtain an N-type doped amorphous silicon layer 212 with a thickness of 10-30 nm.
  • steps S215 and S216 can be prepared here, or can be prepared after the step S20 is completed, which is not limited in the present disclosure.
  • a seed silicon layer 221 on the upper surface of the silicon bottom cell, and depositing a tunneling layer on the surface of the seed silicon layer 221, wherein the tunneling layer is an N-type doped microcrystalline silicon oxide layer 222, an N-type doped Doped carbonized microcrystalline silicon layer or N-type doped carbonized microcrystalline silicon oxide layer.
  • the tunneling layer is an N-type doped microcrystalline silicon oxide layer 222, an N-type doped Doped carbonized microcrystalline silicon layer or N-type doped carbonized microcrystalline silicon oxide layer.
  • an amorphous silicon layer is deposited on the surface of the P-type doped amorphous silicon layer 216, and a tunneling layer is deposited on the surface of the amorphous silicon layer.
  • the deposition conditions of the amorphous silicon layer are: the gas source SiH
  • the flow rate range is 200-1000sccm, such as 300-900sccm, 400-800sccm or 500-700sccm, such as 200sccm, 400sccm, 500sccm, 600sccm, 800sccm or 1000sccm ;Air pressure range of 0.3-1mbar, such as 0.4-0.9mbar, 0.5-0.8mbar or 0.6-0.7mbar, such as 0.3mbar, 0.4mbar, 0.5mbar, 0.6mbar, 0.7mbar, 0.8mbar, 0.9mbar or 1mbar, RF power
  • the range is 300-800W, such as 400-700W, 450-650W or 500-600W, such as 300W, 400W, 500W, 600W, 700W, 800W, to obtain an amorphous silicon layer with a thickness of 1-3nm.
  • the tunneling layer is an N-type doped microcrystalline silicon oxide layer 222, and its deposition conditions are: the flow ratio of H 2 , SiH 4 , CO 2 , and PH 3 is (200-500):(1 -3):1:(1-3), for example (250-450):(1.2-2.8):1:(1.2-2.8), (280-420):(1.3-2.7):1:(1.3- 2.7) or (320-380):(1.4-2.6):1:(1.4-2.6), such as 0.5mbar, 1.0mbar, 1.5mbar, 1.9mbar; the air pressure range is 0.5-2mbar, such as 0.8-1.8mbar, 1.0 -1.6mbar or 1.2-1.4mbar; RF power range is 1000-3000W, such as 1200-2800W, 1500-2500W or 1800-2200W, such as 1100W, 1300W, 1500W, 1700W, 1900W, 2100W, 2300W, 2500W, 2700W, 2900W ,
  • the tunneling layer is an N-type doped carbonized microcrystalline silicon layer, and its deposition conditions are: the flow ratio of H 2 , SiH 4 , CH 4 , and PH 3 is (200-500):(1- 3):1:(1-3), the air pressure range is 0.5-2mbar, and the RF power range is 1000-3000W.
  • the carbon source is not limited to methane, but can also be ethane or propane.
  • the tunneling layer is an N-type doped carbonized microcrystalline silicon oxide layer, and its deposition conditions are: the flow ratio of H 2 , SiH 4 , CO 2 , CH 4 , and PH 3 is (200-500) :(1-3):1:(1-3):(1-3), for example (250-450):(1.2-2.8):1:(1.2-2.8), (280-420):(1.3 -2.7):1:(1.3-2.7) or (320-380):(1.4-2.6):1:(1.4-2.6); pressure range is 0.5-2mbar, such as 0.7-1.9mbar, 1.0-1.6mbar or 1.2-1.4mbar, such as 0.5mbar, 1.0mbar, 1.5mbar, 1.9mbar; RF power range is 1000-3000W, such as 1200-2800W, 1500-2500W or 1800-2200W, such as 1100W, 1300W, 1500W, 1700W, 1900W, 2100W, 2300W, 2500W, 2700W, 2
  • a hole transport layer 131 , a perovskite layer 132 , an electron transport layer 133 and a transparent conductive oxide layer 134 are sequentially deposited on the surface of the tunneling layer.
  • a Spiro-TTB layer, a Perovskite layer, a LiF layer, a C60 layer, a SnO 2 layer, a TCO layer and a silver electrode are sequentially deposited on the surface of the tunneling layer.
  • the amorphous silicon layer is used as a seed silicon layer, which can induce the growth of a nucleation layer, so as to subsequently grow a large-grained microcrystalline silicon oxide layer, a carbonized microcrystalline silicon layer, or a carbonized microcrystalline silicon oxide layer, and
  • the crystallinity of this layer is high, which can accommodate more doping elements, so that its doping concentration is higher.
  • the crystallinity of the doped microcrystalline oxygen layer, the doped carbonized microcrystalline silicon layer or the doped carbonized microcrystalline silicon oxide layer is lower, and the density of defect states is more, It is convenient for the movement of carriers and can be used as a good tunneling material, so that the tunneling between the silicon bottom cell and the perovskite top cell is easier to improve the open circuit voltage and conversion efficiency of the cell.
  • the P-type doped carbonized microcrystalline silicon layer or the P-type doped carbonized microcrystalline silicon oxide layer when forming the P-type doped In the process of the microcrystalline silicon oxide layer, P-type doped carbonized microcrystalline silicon layer or P-type doped carbonized microcrystalline silicon oxide layer, the nucleation layer can be induced to grow first, and then continue to deposit, which can form large particles The microcrystalline silicon layer, and the P-type doping concentration in it is relatively high, forming a tunneling layer with multiple defect state densities and multiple carrier recombination centers, so that the gap between the N-type silicon bottom cell and the perovskite top cell tunneling is easier.
  • the amorphous silicon layer is used as the seed layer of the N-type doped microcrystalline silicon oxide layer, the N-type doped carbonized microcrystalline silicon layer or the N-type doped carbonized microcrystalline silicon oxide layer, in forming the N-type doped In the process of microcrystalline silicon oxide layer, N-type doped carbonized microcrystalline silicon layer or N-type doped carbonized
  • the microcrystalline silicon layer, and the N-type doping concentration in it is relatively high, forming a tunneling layer with multiple defect state density and multiple carrier recombination centers, so that the connection between the P-type silicon bottom cell and the perovskite top cell Tunneling is easier.
  • a seed silicon layer is first formed on the silicon bottom cell, and during the process of forming the tunneling layer, the growth of a crystalline silicon layer can be induced through the seed silicon layer.
  • the core layer is used to grow a large-grained microcrystalline silicon oxide layer, carbonized microcrystalline silicon layer, or carbonized microcrystalline silicon oxide layer, and the layer has high crystallinity and can accommodate more doping elements to make it doped higher impurity concentration.
  • the crystallinity of the doped microcrystalline oxygen layer, the doped carbonized microcrystalline silicon layer or the doped carbonized microcrystalline silicon oxide layer is lower, and the density of defect states is more, It is convenient for the movement of carriers and can be used as a good tunneling material, so that the tunneling between the silicon bottom cell and the perovskite top cell is easier to improve the open circuit voltage and conversion efficiency of the cell.
  • the method for preparing a silicon/perovskite stacked solar cell includes the following steps:
  • the deposition conditions of the intrinsic amorphous silicon layer include: the flow ratio of H 2 to SiH 4 is 5:1, the air pressure is 0.6 mbar, and the radio frequency power is 800 W to obtain the first intrinsic amorphous silicon layer 115 with a thickness of 8 nm. and the second intrinsic amorphous silicon layer 113 .
  • N-type doped amorphous silicon layer 116 is deposited on the surface of the first intrinsic amorphous silicon layer 115 away from the N-type silicon wafer 114 .
  • the deposition conditions of the N-type doped amorphous silicon layer 116 include: the flow ratio of H 2 , SiH 4 and PH 3 is 8:1:5, the gas pressure range is 1 mbar, and the radio frequency power range is 2000 W to obtain an N-type doped silicon layer with a thickness of 20 nm. Heteromorphic silicon layer 116.
  • the deposition conditions of the P-type doped amorphous silicon layer 112 include: the flow ratio of H 2 , SiH 4 and B 2 H 6 is 8:1:5, the gas pressure range is 1 mbar, and the radio frequency power range is 12000 W, so as to obtain a thickness of 10- 30nm P-type doped amorphous silicon layer 112 .
  • seed crystal silicon layer 121 deposit on the surface of N-type doped amorphous silicon layer 116, seed crystal silicon layer 121 is an amorphous silicon layer, and its deposition condition is: the flow range of gas source SiH 4 is 800 sccm; The air pressure range is 0.7mbar, the radio frequency power range is 500W, and an amorphous silicon layer film with a thickness of 2nm is obtained.
  • a P-type doped microcrystalline silicon oxide layer 122 on the surface of the amorphous silicon layer.
  • the deposition conditions of the P-type doped microcrystalline silicon oxide layer 122 are: H 2 , SiH 4 , CO 2 , B
  • the flow ratio of 2 H 6 is 400:2:1:2, the air pressure range is 1 mbar, and the radio frequency power range is 2000 W, to obtain a P-type doped microcrystalline silicon oxide layer 122 with a thickness of 20 nm.
  • a Spiro-TTB layer On the surface of the P-type doped microcrystalline silicon oxide layer 122, a Spiro-TTB layer, a Perovskite layer, a LiF layer, a C60 layer, a SnO 2 layer, a TCO layer and a silver electrode are sequentially deposited.
  • the preparation method of the silicon/perovskite tandem solar cell provided by the present disclosure includes the following steps:
  • the deposition conditions of the intrinsic amorphous silicon layer include: the flow ratio of H 2 and SiH 4 is 5:1, the air pressure is 0.6 mbar, and the radio frequency power is 800 W, so that the first intrinsic amorphous silicon layer 215 with a thickness of 8 nm is obtained. and the second intrinsic amorphous silicon layer 213 .
  • the deposition conditions of the P-type doped amorphous silicon layer 216 include: the flow ratio of H 2 , SiH 4 and B 2 H 6 is 8:1:5, the gas pressure range is 1 mbar, and the radio frequency power range is 2000 W to obtain a N layer with a thickness of 20 nm. type doped amorphous silicon layer 216 .
  • the deposition conditions of the N-type doped amorphous silicon layer 212 include: the flow ratio of H 2 , SiH 4 and PH 3 is 8:1:5, the gas pressure range is 1 mbar, and the radio frequency power range is 12000 W, so as to obtain a layer with a thickness of 10-30 nm. N-type doped amorphous silicon layer 212 .
  • seed crystal silicon layer 221 is an amorphous silicon layer, and its deposition condition is: the flow range of gas source SiH 4 is 800 sccm; The air pressure range is 0.7mbar, the radio frequency power range is 500W, and an amorphous silicon layer film with a thickness of 2nm is obtained.
  • N-type doped microcrystalline silicon oxide layer 222 on the surface of the seed silicon layer 221.
  • the deposition conditions of the N-type doped microcrystalline silicon oxide layer 222 are: H 2 , SiH 4 , CO 2 ,
  • the flow ratio of PH 3 is 400:2:1:2, the air pressure range is 1 mbar, and the radio frequency power range is 2000 W, to obtain an N-type doped microcrystalline silicon oxide layer 222 with a thickness of 20 nm.
  • a Spiro-TTB layer On the surface of the P-type doped microcrystalline silicon oxide layer 122, a Spiro-TTB layer, a Perovskite layer, a LiF layer, a C60 layer, a SnO 2 layer, a TCO layer and a silver electrode are sequentially deposited.
  • Embodiment 3 is an improvement carried out on the basis of Embodiment 1.
  • the difference between Embodiment 3 and Embodiment 1 is that in step (6), a P-type doped carbonized microcrystalline silicon layer is deposited on the surface of the amorphous silicon layer.
  • the deposition conditions of P-type doped carbonized microcrystalline silicon layer are: the flow ratio of H 2 , SiH 4 , CH 4 , and B 2 H 6 is 400:2:1:2, the air pressure range is 1mbar, and the RF power range is 2000W to obtain a P-type doped carbonized microcrystalline silicon layer with a thickness of 20nm.
  • Embodiment 4 is an improvement carried out on the basis of Embodiment 1.
  • the difference between Embodiment 4 and Embodiment 1 is that in step (6), P-type doped carbonized microcrystalline silicon oxide is deposited on the surface of the amorphous silicon layer. layer, the deposition conditions of P-type doped carbonized microcrystalline silicon oxide layer are: the flow ratio of H 2 , SiH 4 , CO 2 , CH 4 , B 2 H 6 is 400:2:1:2:2, and the pressure range 1mbar, the radio frequency power range is 2000W, and a P-type doped carbonized microcrystalline silicon oxide layer with a thickness of 20nm is obtained.
  • FIG. 3 is a schematic diagram of the layer structure of the silicon/perovskite tandem solar cell provided in Comparative Example 1.
  • FIG. 4 is a schematic diagram of the layer structure of the silicon/perovskite tandem solar cell provided in Comparative Example 2. Please refer to Fig. 4, the difference between Comparative Example 2 and Example 1 is: in Comparative Example 2, step (5) and step (6) in Example 1 are not carried out. And from top to bottom, the layer structure of the silicon bottom cell is: N-type doped amorphous silicon layer 116, silicon oxide layer 311, N-type silicon wafer 114, P-type doped amorphous silicon layer 112, aluminum oxide and nitride Silicon layer 312, and silver electrodes disposed thereon.
  • FIG. 5 is a schematic diagram of the layer structure of the silicon/perovskite tandem solar cell provided in Comparative Example 3.
  • FIG. 5 Please refer to FIG. 5 , the difference between Comparative Example 3 and Example 1 is that in Comparative Example 3, the step (5) in Example 1 is not carried out.
  • FIG. 6 is a schematic diagram of the layer structure of the silicon/perovskite tandem solar cell provided in Comparative Example 4.
  • FIG. 6 Please refer to FIG. 6 , the difference between Comparative Example 4 and Example 1 is that in Comparative Example 4, the step (6) in Example 1 is not carried out.
  • Comparative Example 5 The difference between Comparative Example 5 and Example 2 is that in Comparative Example 5, step (5) and step (6) in Example 2 are not carried out.
  • the lattice arrangement of the P-type doped microcrystalline silicon oxide layer For: partly long-range order, partly disordered arrangement, the PN junction can be formed by the P-type doped microcrystalline silicon oxide layer and the N-type doped amorphous silicon layer below the amorphous silicon layer, and its built-in electric field can promote the void In addition, the PN junction can promote the Voc superposition of the bottom cell and the top cell, thereby increasing the open circuit voltage of the entire laminated cell and improving cell efficiency.
  • the experimental group-1 is the P-type doped microcrystal provided in Example 1
  • the seed crystal silicon layer (arrangement of the amorphous silicon layer) can make the crystallinity of the doped microcrystalline silicon oxide layer on the upper surface higher.
  • Example 1 to Example 4 and Comparative Example 1 to Comparative Example 5 are respectively tested as shown in Table 1; wherein, the detection method is: select BERGER online I-V test system, at 25 ° C
  • the conversion efficiency (Eff), open circuit voltage (Uoc), short circuit current (Isc), fill factor (FF) and other electrical performance parameters of silicon/perovskite tandem solar cells were tested under the conditions of , AM 1.5, and 1 standard sun.
  • Example 1 and Comparative Example 1 and Comparative Example 2 It can be seen from the comparison of Example 1 and Comparative Example 1 and Comparative Example 2 that an amorphous silicon layer and a P-type doped microcrystalline silicon oxide layer are sequentially arranged between the silicon bottom battery and the perovskite battery, which can make the conversion of the battery The efficiency is improved and the open circuit voltage is increased.
  • Comparing Example 1 with Comparative Example 3 and Comparative Example 4 it can be seen that if only a P-type doped microcrystalline silicon oxide layer is set between the silicon bottom cell and the perovskite cell, the conversion efficiency of the cell will not increase significantly. Only the amorphous silicon layer is set between the silicon bottom cell and the perovskite cell, but the conversion efficiency of the cell is reduced, and the amorphous silicon layer and the P-type doped microstructure are sequentially arranged between the silicon bottom cell and the perovskite cell.
  • the crystalline silicon oxide layer has a certain synergistic effect, which can improve the conversion efficiency of the battery and the open circuit voltage.
  • Embodiment 1, embodiment 3 and embodiment 4 can find out, the microcrystalline silicon oxide layer of P-type doping, the carbonized microcrystalline silicon layer of P-type doping and the carbonized microcrystalline silicon oxide layer of P-type doping, and After the amorphous silicon layer is combined, the conversion efficiency of the battery can be improved, and the open circuit voltage can be increased.
  • the disclosure provides a silicon/perovskite stacked solar cell and its preparation method.
  • the disclosure uses the seed silicon layer as an amorphous silicon layer, and the tunneling layer as a doped microcrystalline silicon oxide layer, so that the cell uses silicon
  • the tunneling between the bottom cell and the perovskite top cell is easier to improve the open circuit voltage and conversion efficiency of the cell, which has excellent application performance and broad market prospects.

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Abstract

本公开涉及一种硅/钙钛矿叠层太阳能电池及其制备方法，属于钙钛矿叠层电池技术领域。该硅/钙钛矿叠层太阳能电池包括硅底电池和钙钛矿顶电池，硅底电池的表面和钙钛矿顶电池的底面之间依次设置有种子晶硅层和隧穿层，种子晶硅层靠近硅底电池，隧穿层靠近钙钛矿顶电池。其中，种子晶硅层为非晶硅层，隧穿层为掺杂的微晶硅氧层。该电池使硅底电池和钙钛矿顶电池之间的隧穿更加容易，以提高电池的开路电压和转化效率。

Description

硅/钙钛矿叠层太阳能电池及其制备方法
相关申请的交叉引用
本公开要求于2021年07月29日提交中国专利局的申请号为“CN 202110864717.0”名称为“硅/钙钛矿叠层太阳能电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及钙钛矿叠层电池技术领域，且特别涉及一种硅/钙钛矿叠层太阳能电池及其制备方法。
背景技术
钙钛矿叠层电池属于三代光伏技术，其作为近年来最受关注的新型半导体材料，在光伏、探测、显示、照明等众多领域具备广泛的应用前景，然而现有技术中的钙钛矿叠层电池在制备完成以后，往往存在开路电压低和转化效率低的问题。
发明内容
本公开提供一种硅/钙钛矿叠层太阳能电池，包括硅底电池和钙钛矿顶电池，所述硅底电池的表面和所述钙钛矿顶电池的底面之间依次设置有种子晶硅层和隧穿层，所述种子晶硅层靠近所述硅底电池，所述隧穿层靠近所述钙钛矿顶电池；
其中，所述种子晶硅层为非晶硅层，所述隧穿层为掺杂的微晶硅氧层、掺杂的碳化微晶硅层或掺杂的碳化微晶硅氧层。
在一些实施方式中，所述非晶硅层的厚度为1-3nm；所述隧穿层的厚度为10-30nm。
在一些实施方式中，所述硅底电池包括从上到下依次设置的N型掺杂非晶硅层、第一本征非晶硅层、N型硅片、第二本征非晶硅层和P型掺杂非晶硅层，所述隧穿层为P型掺杂的微晶硅氧层、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层。
在一些实施方式中，所述硅底电池包括从上到下依次设置的P型掺杂非晶硅层、第一本征非晶硅层、P型硅片、第二本征非晶硅层和N型掺杂非晶硅层，所述隧穿层为N型掺杂的微晶硅氧层、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层。
本公开还提供上述硅/钙钛矿叠层太阳能电池的制备方法，包括：
形成所述硅底电池；
在所述硅底电池的上表面沉积所述非晶硅层，在所述非晶硅层的表面沉积所述隧穿层，其中，所述隧穿层为所述掺杂的微晶硅氧层、掺杂的碳化微晶硅层或掺杂的碳化微晶硅氧层；
在所述隧穿层的表面形成所述钙钛矿顶电池。
在一些实施方式中，所述非晶硅层的沉积条件包括：气源SiH 4的流量范围为200-1000sccm；气压范围为0.3-1mbar，射频功率范围为300-800W。
在一些实施方式中，所述隧穿层为P型掺杂的微晶硅氧层，所述隧穿层的沉积条件为：H 2、SiH 4、CO 2、B 2H 6的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W；
或，所述隧穿层为P型掺杂的碳化微晶硅层，所述隧穿层的沉积条件为：H 2、SiH 4、CH 4、B 2H 6的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W；
或，所述隧穿层为P型掺杂的碳化微晶硅氧层，所述隧穿层的沉积条件为：H 2、SiH 4、CO 2、CH 4、B 2H 6的流量比为(200-500):(1-3):1:(1-3):(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。
在一些实施方式中，包括：对N型硅片进行制绒；在所述N型硅片的正面沉积第一本征非晶硅层，在所述硅片的背面沉积第二本征非晶硅层；在所述第一本征非晶硅层的背离所述N型硅片的表面形成N型掺杂非晶硅层，在所述第二本征非晶硅层的背离所述N型硅片的表面形成P型掺杂非晶硅层。
在一些实施方式中，所述隧穿层为N型掺杂的微晶硅氧层，所述隧穿层的沉积条件为：H 2、SiH 4、CO 2、PH 3的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W；
或，所述隧穿层为N型掺杂的碳化微晶硅层，所述隧穿层的沉积条件为：H 2、SiH 4、CH 4、PH 3的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W；
或，所述隧穿层为N型掺杂的碳化微晶硅氧层，所述隧穿层的沉积条件为：H 2、SiH 4、CO 2、CH 4、PH 3的流量比为(200-500):(1-3):1:(1-3):(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。
在一些实施方式中，形成所述硅底电池的方法，包括：对P型硅片进行制绒；在所述P型硅片的正面沉积第一本征非晶硅层，在所述硅片的背面沉积第二本征非晶硅层；在所述第一本征非晶硅层的背离所述P型硅片的表面形成P型掺杂非晶硅层，在所述第二本征非晶硅层的背离所述P型硅片的表面形成N型掺杂非晶硅层。
在一些实施方式中，所述第一本征非晶硅层和第二本征非晶硅层的沉积条件分别包括：H 2与SiH 4的流量比为(1-15):1，气压范围为0.3-1mbar，射频功率范围为300-1200W。
在一些实施方式中，所述P型掺杂非晶硅层216的沉积条件包括：H 2、SiH 4和B 2H 6的流量比为(5-10):1:(1-10)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。
在一些实施方式中，N型掺杂非晶硅层212的沉积条件包括：H 2、SiH 4和PH 3的流量比为(5-10):1:(1-10)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本公开实施例提供的硅/钙钛矿叠层太阳能电池的第一结构示意图；
图2为本公开实施例提供的硅/钙钛矿叠层太阳能电池的第二结构示意图；
图3为对比例1提供的硅/钙钛矿叠层太阳能电池的结构示意图；
图4为对比例2提供的硅/钙钛矿叠层太阳能电池的结构示意图；
图5为对比例3提供的硅/钙钛矿叠层太阳能电池的结构示意图；
图6为对比例4提供的硅/钙钛矿叠层太阳能电池的结构示意图；
图7为本公开实施例1提供的硅/钙钛矿叠层太阳能电池的制备方法的步骤(6)以后的TEM图；
图8为本公开实施例1和实施例2以及对比例4提供的硅/钙钛矿叠层太阳能电池的制备方法制备的掺杂的微晶硅氧层的拉曼光谱测试图。
图标：116，212-N型掺杂非晶硅层；115，215-第一本征非晶硅层；114-N型硅片；113，213-第二本征非晶硅层、112，216-P型掺杂非晶硅层；111，211-ITO导电膜层；134-透明导电氧化物层；133-电子传输层；132-钙钛矿层；131-空穴传输层；121，221-种子晶硅层；122-P型掺杂的微晶硅氧层；214-P型硅片；222-N型掺杂的微晶硅氧层；311-氧化硅层；312-氧化铝和氮化硅层。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面对本公开的技术方案进行清楚、完整地描述。
一般的钙钛矿叠层电池的制备方法为：在N型硅片的背面形成P型掺杂非晶硅层，在N型硅片的正面依次形成二氧化硅层和N型掺杂非晶硅层，然后以N型掺杂非晶硅层作为受光面，在其上方形成钙钛矿电池(钙钛矿电池的空穴传输层与N型掺杂非晶硅层接触)，得到钙钛矿叠层电池。该钙钛矿叠层电池制备完成以后，开路电压和转化效率都不高。
申请人研究发现，现有的钙钛矿叠层电池中，由于N型掺杂非晶硅层的结晶性过高，而空穴传输层的材料为P型无晶态有机材料，堆叠以后，N型掺杂非晶硅层与空穴传输 层的晶格不匹配，从而造成隧穿不易的问题，导致了钙钛矿叠层电池的开路电压和转化效率都不高。
针对现有技术的不足，本公开一些实施方式提供一种硅/钙钛矿叠层太阳能电池及其制备方法，可以提高电池的开路电压和转化效率。
本公开一些实施方式提供两种硅/钙钛矿叠层太阳能电池。
本公开一些实施方式提供一种硅/钙钛矿叠层太阳能电池，该电池的硅底电池为N型硅片上形成的硅电池，其结构示意图请参照图1。
该硅电池包括从上到下依次设置的N型掺杂非晶硅层116、第一本征非晶硅层115、N型硅片114、第二本征非晶硅层113、P型掺杂非晶硅层112、ITO导电膜层111和与ITO导电膜层111形成欧姆接触的银电极。
钙钛矿顶电池包括从上到下依次设置的透明导电氧化物层134、电子传输层133、钙钛矿层132和空穴传输层131。其中，透明导电氧化物层134可以是IZO透明导电薄膜层，且IZO透明导电薄膜层上表面具有与其欧姆接触的银电极。电子传输层133可以是从上到下重叠设置的SnO 2层、C60层和LiF层。空穴传输层131的材料为Spiro-TTB或PTAA。
如果直接在硅底电池上重叠钙钛矿顶电池，则N型掺杂非晶硅层直接与空穴传输层接触，由于N型掺杂非晶硅层的结晶性过高，而空穴传输层的材料为P型无晶态有机材料，二者直接重叠，会出现晶格不匹配隧穿不易的问题，从而导致钙钛矿叠层电池的开路电压和转化效率偏低。
为了解决上述问题，本公开中，在硅底电池的表面和钙钛矿顶电池的底面之间依次设置有种子晶硅层121和隧穿层，种子晶硅层靠近硅底电池，隧穿层靠近钙钛矿顶电池。其中，种子晶硅层121为非晶硅层，隧穿层为P型掺杂的微晶硅氧层122、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层(图1是以隧穿层为P型掺杂的微晶硅氧层122为例进行的说明)。
也就是说，在硅底电池的N型掺杂非晶硅层116上依次设置种子晶硅层121(非晶硅层)、隧穿层(P型掺杂的微晶硅氧层122、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层)、然后在隧穿层上重叠钙钛矿顶电池的空穴传输层131。一方面，种子晶硅层121可以作为种子晶硅层，其可以诱导生长出成核层，以便后续生长出大颗粒的微晶硅氧层、碳化微晶硅层或碳化微晶硅氧层，且该层的结晶度高，可以容纳更多的掺杂元素，以使其掺杂浓度更高。另一方面，相较于N型掺杂的多晶层116，P型掺杂的微晶硅氧层122、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层的结晶性较低，缺陷态密度较多，方便载流子的移动，可以作为很好的隧穿材料，从而使硅底电池和钙钛矿顶电池之间的隧穿更加容易，以提高电池的开路电压和转化效率。可选地，非晶硅层的厚度为1-3nm；P型掺杂的微晶硅氧层122、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层的厚度为10-30nm。厚度很薄的非晶硅层基本不会影响钙钛矿叠层电池的厚度，并且能够很好地形成隧穿层，使电池的开路电压和转化效率更高。
作为示例性地，非晶硅层的厚度为例如1.1-2.9nm、1.2-2.8nm或1.3-2.7nm，诸如1nm、2nm或3nm；P型掺杂的微晶硅氧层122的厚度为例如12-28nm、15-25nm或18-22nm，诸如10nm、15nm、20nm、25nm或30nm，或P型掺杂的碳化微晶硅层的厚度为例如12-28nm、15-25nm或18-22nm，诸如10nm、15nm、20nm、25nm或30nm，或P型掺杂的碳化微晶硅氧层的厚度为例如12-28nm、15-25nm或18-22nm，诸如10nm、15nm、20nm、25nm或30nm。
上述的硅/钙钛矿叠层太阳能电池的制备方法，包括如下步骤：
S110，形成硅底电池。
S111，对N型硅片114进行制绒。可选地，对尺寸为156.75mm，厚度为180μm的N型硅片114进行制绒、清洗处理。
S112，在N型硅片114的正面沉积第一本征非晶硅层115，在N型硅片114的背面沉积第二本征非晶硅层113。可选地，通过PECVD的方式进行第一本征非晶硅层115和第二本征非晶硅层113的制备。
在一些实施方式中，采用H 2稀释SiH 4或纯SiH 4进行沉积单层或叠层非晶硅膜，其中，本征非晶硅层的沉积条件包括：H 2与SiH 4的流量比为(1-15):1，例如(2-14):1、(3-12):1或(5-10):1；气压范围为0.3-1mbar，例如0.4-0.9mbar、0.5-0.8mbar或0.6-0.7mbar；射频功率范围为300-1200W，例如400-1100W、500-1000W或600-800W。以得到厚度为3-10nm的第一本征非晶硅层115和第二本征非晶硅层113。
S113，在第一本征非晶硅层115的背离N型硅片114的表面形成N型掺杂非晶硅层116，且该N型掺杂非晶硅层116为受光面。可选地，在第一本征非晶硅层115的背离N型硅片114的表面沉积N型掺杂非晶硅层116。
N型掺杂非晶硅层116的沉积条件包括：H 2、SiH 4和PH 3的流量比为(5-10):1:(1-10)，例如(6-9):1:(2-8)、(7-8):1:(3-7)或(7-8):1:(4-6)；气压范围为0.5-2mbar，例如0.6-1.9mbar、0.7-1.8mbar或0.8-1.5mbar；射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W。以得到厚度10-30nm的N型掺杂非晶硅层116。
S114，在第二本征非晶硅层113的背离N型硅片114的表面形成P型掺杂非晶硅层112。可选地，在第二本征非晶硅层113的背离N型硅片114的表面沉积P型掺杂非晶硅层112。
P型掺杂非晶硅层112的沉积条件包括：H 2、SiH 4和B 2H 6的流量比为(5-10):1:(1-10)，例如(6-9):1:(2-8)、(7-8):1:(3-7)或(7-8):1:(4-6)；气压范围为0.5-2mbar，例如0.6-1.9mbar、0.7-1.8mbar或0.8-1.5mbar；射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W。以得到厚度10-30nm的P型掺杂非晶硅层112。
S115，使用RPD或者PVD方法在P型掺杂非晶硅层112的背面沉积ITO导电膜层111，厚度80-100nm。
S116，通过丝网印刷形成背面Ag电极，固化使得银栅线与ITO导电膜层111之间形成良好的欧姆接触，HJT底电池制作完成。
其中，上述的步骤S115和S116可以在此处制备完成，也可以在S20步骤完成以后再进行制备，本公开不做限定。
S120，在硅底电池的上表面沉积种子晶硅层121，在种子晶硅层121的表面沉积隧穿层，其中，隧穿层为P型掺杂的微晶硅氧层122、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层。可选地，在N型掺杂非晶硅层116的表面沉积非晶硅层，在非晶硅层的表面沉积隧穿层。
可选地，非晶硅层的沉积条件为：气源SiH 4的流量范围为200-1000sccm，例如300-900sccm、400-800sccm或500-700sccm，诸如200sccm、400sccm、500sccm、600sccm、800sccm或1000sccm；气压范围为0.3-1mbar，例如0.4-0.9mbar、0.5-0.8mbar或0.6-0.7mbar，诸如0.3mbar、0.4mbar、0.5mbar、0.6mbar、0.7mbar、0.8mbar、0.9mbar或1mbar，射频功率范围为300-800W，例如400-700W、450-650W或500-600W，诸如300W、400W、500W、600W、700W、800W。以得到厚度为1-3nm的非晶硅层。
在一些实施方式中，隧穿层为P型掺杂的微晶硅氧层122，其沉积条件为：H 2、SiH 4、CO 2、B 2H 6的流量比为(200-500):(1-3):1:(1-3)，例如(250-450):(1.2-2.8):1:(1.2-2.8)、(280-420):(1.3-2.7):1:(1.3-2.7)或(320-380):(1.4-2.6):1:(1.4-2.6)；气压范围为0.5-2mbar，例如0.8-1.8mbar、1.0-1.6mbar或1.2-1.4mbar，诸如0.5mbar、1.0mbar、1.5mbar、1.9mbar；射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W，诸如1100W、1300W、1500W、1700W、1900W、2100W、2300W、2500W、2700W、2900W。以得到厚度为10-30nm的P型掺杂的微晶硅氧层122。
在一些实施方式中，隧穿层为P型掺杂的碳化微晶硅层，其沉积条件为：H 2、SiH 4、CH 4、B 2H 6的流量比为(200-500):(1-3):1:(1-3)，例如(250-450):(1.2-2.8):1:(1.2-2.8)、(280-420):(1.3-2.7):1:(1.3-2.7)或(320-380):(1.4-2.6):1:(1.4-2.6)；气压范围为0.5-2mbar，例如0.7-1.9mbar、1.0-1.6mbar或1.2-1.4mbar，诸如0.5mbar、1.0mbar、1.5mbar、1.9mbar；射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W，诸如1100W、1300W、1500W、1700W、1900W、2100W、2300W、2500W、2700W、2900W。在其他实施方式中，碳源并不限定为甲烷，还可以是乙烷或丙烷。
在一些实施方式中，隧穿层为P型掺杂的碳化微晶硅氧层，其沉积条件为：H 2、SiH 4、CO 2、CH 4、B 2H 6的流量比为(200-500):(1-3):1:(1-3):(1-3)，例如(250-450):(1.2-2.8):1:(1.2-2.8)、(280-420):(1.3-2.7):1:(1.3-2.7)或(320-380):(1.4-2.6):1:(1.4-2.6)；气压范围为0.5-2mbar，例如0.7-1.9mbar、1.0-1.6mbar或1.2-1.4mbar，诸如0.5mbar、1.0mbar、1.5mbar、1.9mbar；射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W，诸如1100W、1300W、1500W、1700W、1900W、2100W、2300W、2500W、2700W、2900W。在其他实施方式中，碳源并不限定为甲烷，还可以是乙烷或丙烷。
S130，在隧穿层的表面形成钙钛矿顶电池。
可选地，在隧穿层的表面依次沉积空穴传输层131、钙钛矿层132、电子传输层133和透明导电氧化物层134。
例如：在隧穿层的表面依次沉积Spiro-TTB层、Perovskite层、LiF层、C60层、SnO 2层、TCO层和银电极。
本公开一些实施方式还提供了另一种硅/钙钛矿叠层太阳能电池，该电池的硅底电池为P型硅片214上形成的硅电池，其结构示意图请参见图2。
该硅电池包括从上到下依次设置的P型掺杂非晶硅层216、第一本征非晶硅层215、P型硅片214、第二本征非晶硅层213、N型掺杂非晶硅层212、ITO导电膜层211和与ITO导电膜层211形成欧姆接触的银电极。
钙钛矿顶电池的结构与第一种硅/钙钛矿叠层太阳能电池的硅底电池的钙钛矿顶电池的结构相同，此处不再赘述。
如果直接在硅底电池上重叠钙钛矿顶电池，则P型掺杂非晶硅层直接与空穴传输层接触，由于P型掺杂非晶硅层的结晶性过高，而电子传输层的材料为N型无晶态材料，二者直接重叠，会出现晶格不匹配隧穿不易的问题，从而导致钙钛矿叠层电池的开路电压和转化效率偏低。
为了解决上述问题，本公开中，在硅底电池的表面和钙钛矿顶电池的底面之间依次设置有种子晶硅层221和隧穿层，种子晶硅层靠近硅底电池，隧穿层靠近钙钛矿顶电池。其中，种子晶硅层221为非晶硅层，隧穿层为N型掺杂的微晶硅氧层222、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层(图2是以隧穿层为N型掺杂的微晶硅氧层222为例进行的说明)。
也就是说，在硅底电池的P型掺杂非晶硅层216上依次设置种子晶硅层221(非晶硅层)、隧穿层(N型掺杂的微晶硅氧层222、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层)、然后在隧穿层上重叠钙钛矿顶电池的空穴传输层131。一方面，种子晶硅层221可以作为种子晶硅层，其可以诱导生长出成核层，以便后续生长出大颗粒的微晶硅氧层、碳化微晶硅层或碳化微晶硅氧层，且该层的结晶度高，可以容纳更多的掺杂元素，以使其掺杂浓度更高。另一方面，相较于P型掺杂的多晶层216，N型掺杂的微晶硅氧层222、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层的结晶性较低，缺陷态密度较多，方便载流子的移动，可以作为很好的隧穿材料，从而使硅底电池和钙钛矿顶电池之间的隧穿更加容易，以提高电池的开路电压和转化效率。
可选地，非晶硅层的厚度为1-3nm；N型掺杂的微晶硅氧层222、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层的厚度为10-30nm。厚度很薄的非晶硅层基本不会影响钙钛矿叠层电池的厚度，并且能够很好地形成隧穿层，使电池的开路电压和转化效率更高。
作为示例性地，非晶硅层的厚度为例如1.1-2.9nm、1.2-2.8nm或1.3-2.7nm，诸如1nm、2nm或3nm；N型掺杂的微晶硅氧层222的厚度为例如12-28nm、15-25nm或18-22nm，诸如10nm、15nm、20nm、25nm或30nm，或N型掺杂的碳化微晶硅层 的厚度为例如12-28nm、15-25nm或18-22nm，诸如10nm、15nm、20nm、25nm或30nm，或N型掺杂的碳化微晶硅氧层的厚度为例如12-28nm、15-25nm或18-22nm，诸如10nm、15nm、20nm、25nm或30nm。
上述的硅/钙钛矿叠层太阳能电池的制备方法，包括如下步骤：
S210，形成硅底电池。
S211，对P型硅片214进行制绒。可选地，对尺寸为156.75mm，厚度为180μm的P型硅片214进行制绒、清洗处理。
S212，在P型硅片214的正面沉积第一本征非晶硅层215，在P型硅片214的背面沉积第二本征非晶硅层213。可选地，通过PECVD的方式进行第一本征非晶硅层215和第二本征非晶硅层的制备213。
在一些实施方式中，采用H 2稀释SiH 4或纯SiH 4进行沉积单层或叠层非晶硅膜，其中，本征非晶硅层的沉积条件包括：H 2与SiH 4的流量比为(1-15):1，例如(2-14):1、(3-12):1或(5-10):1；气压范围为0.3-1mbar，例如0.4-0.9mbar、0.5-0.8mbar或0.6-0.7mbar；射频功率范围为300-1200W，例如400-1100W、500-1000W或600-800W。以得到厚度为3-10nm的第一本征非晶硅层215和第二本征非晶硅层213。
S213，在第一本征非晶硅层215的背离P型硅片214的表面形成P型掺杂非晶硅层216，且该P型掺杂非晶硅层216为受光面。可选地，在第一本征非晶硅层215的背离P型硅片214的表面沉积P型掺杂非晶硅层216。
P型掺杂非晶硅层216的沉积条件包括：H 2、SiH 4和B 2H 6的流量比为(5-10):1:(1-10)，例如(6-9):1:(2-8)、(7-8):1:(3-7)或(7-8):1:(4-6)；气压范围为0.5-2mbar，例如0.6-1.9mbar、0.7-1.8mbar或0.8-1.5mbar；射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W。以得到厚度10-30nm的P型掺杂非晶硅层216。
S214，在第二本征非晶硅层213的背离P型硅片214的表面形成N型掺杂非晶硅层212。可选地，在第二本征非晶硅层213的背离P型硅片214的表面沉积N型掺杂非晶硅层212。
N型掺杂非晶硅层212的沉积条件包括：H 2、SiH 4和PH 3的流量比为(5-10):1:(1-10)，例如(6-9):1:(2-8)、(7-8):1:(3-7)或(7-8):1:(4-6)；气压范围为0.5-2mbar，例如0.6-1.9mbar、0.7-1.8mbar或0.8-1.5mbar；，射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W。以得到厚度10-30nm的N型掺杂非晶硅层212。
S215，使用RPD或者PVD方法在N型掺杂非晶硅层212的背面沉积ITO导电膜层211，厚度80-100nm。
S216，通过丝网印刷形成背面Ag电极，固化使得银栅线与ITO导电膜层211之间形成良好的欧姆接触，HJT底电池制作完成。
其中，上述的步骤S215和S216可以在此处制备完成，也可以在S20步骤完成以后再进行制备，本公开不做限定。
S220，在硅底电池的上表面沉积种子晶硅层221，在种子晶硅层221的表面沉积隧穿层，其中，隧穿层为N型掺杂的微晶硅氧层222、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层。可选地，在P型掺杂非晶硅层216的表面沉积非晶硅层，在非晶硅层的表面沉积隧穿层。
可选地，非晶硅层的沉积条件为：气源SiH 4的流量范围为200-1000sccm，例如300-900sccm、400-800sccm或500-700sccm，诸如200sccm、400sccm、500sccm、600sccm、800sccm或1000sccm；气压范围为0.3-1mbar，例如0.4-0.9mbar、0.5-0.8mbar或0.6-0.7mbar，诸如0.3mbar、0.4mbar、0.5mbar、0.6mbar、0.7mbar、0.8mbar、0.9mbar或1mbar，射频功率范围为300-800W，例如400-700W、450-650W或500-600W，诸如300W、400W、500W、600W、700W、800W，以得到厚度为1-3nm的非晶硅层。
在一些实施方式中，隧穿层为N型掺杂的微晶硅氧层222，其沉积条件为：H 2、SiH 4、CO 2、PH 3的流量比为(200-500):(1-3):1:(1-3)，例如(250-450):(1.2-2.8):1:(1.2-2.8)、(280-420):(1.3-2.7):1:(1.3-2.7)或(320-380):(1.4-2.6):1:(1.4-2.6)，诸如0.5mbar、1.0mbar、1.5mbar、1.9mbar；气压范围为0.5-2mbar，例如0.8-1.8mbar、1.0-1.6mbar或1.2-1.4mbar；射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W，诸如1100W、1300W、1500W、1700W、1900W、2100W、2300W、2500W、2700W、2900W，以得到厚度为10-30nm的N型掺杂的微晶硅氧层222。
在一些实施方式中，隧穿层为N型掺杂的碳化微晶硅层，其沉积条件为：H 2、SiH 4、CH 4、PH 3的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。在其他实施方式中，碳源并不限定为甲烷，还可以是乙烷或丙烷。
在一些实施方式中，隧穿层为N型掺杂的碳化微晶硅氧层，其沉积条件为：H 2、SiH 4、CO 2、CH 4、PH 3的流量比为(200-500):(1-3):1:(1-3):(1-3)，例如(250-450):(1.2-2.8):1:(1.2-2.8)、(280-420):(1.3-2.7):1:(1.3-2.7)或(320-380):(1.4-2.6):1:(1.4-2.6)；气压范围为0.5-2mbar，例如0.7-1.9mbar、1.0-1.6mbar或1.2-1.4mbar，诸如0.5mbar、1.0mbar、1.5mbar、1.9mbar；射频功率范围为1000-3000W，例如1200-2800W、1500-2500W或1800-2200W，诸如1100W、1300W、1500W、1700W、1900W、2100W、2300W、2500W、2700W、2900W。在其他实施方式中，碳源并不限定为甲烷，还可以是乙烷或丙烷。
S230，在隧穿层的表面形成钙钛矿顶电池。
可选地，在隧穿层的表面依次沉积空穴传输层131、钙钛矿层132、电子传输层133和透明导电氧化物层134。
例如：在隧穿层的表面依次沉积Spiro-TTB层、Perovskite层、LiF层、C60层、SnO 2层、TCO层和银电极。
本申请中，非晶硅层作为种子晶硅层，其可以诱导生长出成核层，以便后续生长出大颗粒的微晶硅氧层、碳化微晶硅层或碳化微晶硅氧层，且该层的结晶度高，可以容纳 更多的掺杂元素，以使其掺杂浓度更高。且，相较于掺杂的多晶层，掺杂的微晶氧层、掺杂的碳化微晶硅层或掺杂的碳化微晶硅氧层的结晶性较低，缺陷态密度较多，方便载流子的移动，可以作为很好的隧穿材料，从而使硅底电池和钙钛矿顶电池之间的隧穿更加容易，以提高电池的开路电压和转化效率。
当非晶硅层作为P型掺杂的微晶硅氧层、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层的种子层时，在形成P型掺杂的微晶硅氧层、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层的过程中，可以先诱导生长出成核层，然后继续沉积，能够形成大颗粒的微晶硅层，并且，其中的P型掺杂浓度较高，形成多缺陷态密度、多载流子复合中心的隧穿层，从而使N型硅底电池和钙钛矿顶电池之间的隧穿更加容易。
当非晶硅层作为N型掺杂的微晶硅氧层、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层的种子层，在形成N型掺杂的微晶硅氧层、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层的过程中，可以先诱导生长出成核层，然后继续沉积，能够形成大颗粒的微晶硅层，并且，其中的N型掺杂浓度较高，形成多缺陷态密度、多载流子复合中心的隧穿层，从而使P型硅底电池和钙钛矿顶电池之间的隧穿更加容易。
同时，在本公开制备硅/钙钛矿叠层太阳能电池的方法中，先在硅底电池上形成种子晶硅层，在形成隧穿层的过程中，可以通过种子晶硅层诱导生长出成核层，以便后续生长出大颗粒的微晶硅氧层、碳化微晶硅层或碳化微晶硅氧层，且该层的结晶度高，可以容纳更多的掺杂元素，以使其掺杂浓度更高。且，相较于掺杂的多晶层，掺杂的微晶氧层、掺杂的碳化微晶硅层或掺杂的碳化微晶硅氧层的结晶性较低，缺陷态密度较多，方便载流子的移动，可以作为很好的隧穿材料，从而使硅底电池和钙钛矿顶电池之间的隧穿更加容易，以提高电池的开路电压和转化效率。
为使本公开实施方式的目的、技术方案和优点更加清楚，下面将对本公开实施例中的技术方案进行清楚、完整地描述。实施例中未注明具体条件者，按照常规条件或制造商建议的条件进行。所用试剂或仪器未注明生产厂商者，均为可以通过市售购买获得的常规产品。
实施例1
请参阅图1，本公开提供的硅/钙钛矿叠层太阳能电池的制备方法，包括如下步骤：
(1)、对尺寸为156.75mm，厚度为180μm的N型硅片114进行制绒、清洗处理。
(2)、在N型硅片114的正面沉积第一本征非晶硅层115，在硅片的背面沉积第二本征非晶硅层113。其中，本征非晶硅层的沉积条件包括：H 2与SiH 4的流量比为5:1，气压为0.6mbar，射频功率为800W，得到厚度为8nm的第一本征非晶硅层115和第二本征非晶硅层113。
(3)、在第一本征非晶硅层115的背离N型硅片114的表面沉积N型掺杂非晶硅层116。N型掺杂非晶硅层116的沉积条件包括：H 2、SiH 4和PH 3的流量比为8:1:5，气压范围为1mbar，射频功率范围为2000W，得到厚度20nm的N型掺杂非晶硅层116。
(4)、在第二本征非晶硅层113的背离N型硅片114的表面沉积P型掺杂非晶硅层112。P型掺杂非晶硅层112的沉积条件包括：H 2、SiH 4和B 2H 6的流量比为8:1:5，气压范围为1mbar，射频功率范围为12000W，以得到厚度10-30nm的P型掺杂非晶硅层112。
(5)、在N型掺杂非晶硅层116的表面沉积种子晶硅层121，种子晶硅层121为非晶硅层，其的沉积条件为：气源SiH 4的流量范围为800sccm；气压范围为0.7mbar，射频功率范围为500W，得到厚度为2nm的非晶硅层薄膜。
(6)、在非晶硅层的表面沉积P型掺杂的微晶硅氧层122，P型掺杂的微晶硅氧层122的沉积条件为：H 2、SiH 4、CO 2、B 2H 6的流量比为400:2:1:2，气压范围为1mbar，射频功率范围为2000W，得到厚度为20nm的P型掺杂的微晶硅氧层122。
(7)、使用PVD法在P型掺杂非晶硅层112的背面沉积ITO导电膜层111，厚度90nm。
(8)、通过丝网印刷形成背面Ag电极，固化使得银栅线与ITO导电膜层111之间形成良好的欧姆接触，HJT底电池制作完成。
(9)、在P型掺杂的微晶硅氧层122的表面依次沉积Spiro-TTB层、Perovskite层、LiF层、C60层、SnO 2层、TCO层和银电极。
实施例2
请参阅图2，本公开提供的硅/钙钛矿叠层太阳能电池的制备方法，包括如下步骤：
(1)、对尺寸为156.75mm，厚度为180μm的P型硅片214进行制绒、清洗处理。
(2)、在P型硅片214的正面沉积第一本征非晶硅层215，在P型硅片214的背面沉积第二本征非晶硅层213。其中，本征非晶硅层的沉积条件包括：H 2与SiH 4的流量比为5:1，气压为0.6mbar，射频功率为800W，得到厚度为8nm的第一本征非晶硅层215和第二本征非晶硅层213。
(3)、在第一本征非晶硅层215的背离P型硅片214的表面沉积P型掺杂非晶硅层216。P型掺杂非晶硅层216的沉积条件包括：H 2、SiH 4和B 2H 6的流量比为8:1:5，气压范围为1mbar，射频功率范围为2000W，得到厚度20nm的N型掺杂非晶硅层216。
(4)、在第二本征非晶硅层213的背离P型硅片214的表面沉积N型掺杂非晶硅层212。N型掺杂非晶硅层212的沉积条件包括：H 2、SiH 4和PH 3的流量比为8:1:5，气压范围为1mbar，射频功率范围为12000W，以得到厚度10-30nm的N型掺杂非晶硅层212。
(5)、在P型掺杂非晶硅层216的表面沉积种子晶硅层221，种子晶硅层221为非晶硅层，其的沉积条件为：气源SiH 4的流量范围为800sccm；气压范围为0.7mbar，射频功率范围为500W，得到厚度为2nm的非晶硅层薄膜。
(6)、在种子晶硅层221的表面沉积N型掺杂的微晶硅氧层222，N型掺杂的微晶硅氧层222的沉积条件为：H 2、SiH 4、CO 2、PH 3的流量比为400:2:1:2，气压范围为1mbar，射频功率范围为2000W，得到厚度为20nm的N型掺杂的微晶硅氧层222。
(7)、使用PVD法在N型掺杂非晶硅层212的背面沉积ITO导电膜层211，厚度90nm。
(8)、通过丝网印刷形成背面Ag电极，固化使得银栅线与ITO导电膜层211之间形成良好的欧姆接触，HJT底电池制作完成。
(9)、在P型掺杂的微晶硅氧层122的表面依次沉积Spiro-TTB层、Perovskite层、LiF层、C60层、SnO 2层、TCO层和银电极。
实施例3
实施例3是在实施例1的基础上进行的改进，实施例3与实施例1的区别在于：步骤(6)中，在非晶硅层的表面沉积P型掺杂的碳化微晶硅层，P型掺杂的碳化微晶硅层的沉积条件为：H 2、SiH 4、CH 4、B 2H 6的流量比为400:2:1:2，气压范围为1mbar，射频功率范围为2000W，得到厚度为20nm的P型掺杂的碳化微晶硅层。
实施例4
实施例4是在实施例1的基础上进行的改进，实施例4与实施例1的区别在于：步骤(6)中，在非晶硅层的表面沉积P型掺杂的碳化微晶硅氧层，P型掺杂的碳化微晶硅氧层的沉积条件为：H 2、SiH 4、CO 2、CH 4、B 2H 6的流量比为400:2:1:2:2，气压范围为1mbar，射频功率范围为2000W，得到厚度为20nm的P型掺杂的碳化微晶硅氧层。
对比例1
图3为对比例1提供的硅/钙钛矿叠层太阳能电池的层结构示意图。请参阅图3，对比例1与实施例1的区别在于：对比例1中，不进行实施例1中的步骤(5)和步骤(6)。
对比例2
图4为对比例2提供的硅/钙钛矿叠层太阳能电池的层结构示意图。请参阅图4，对比例2与实施例1的区别在于：对比例2中，不进行实施例1中的步骤(5)和步骤(6)。且从上到下，硅底电池的层结构为：N型掺杂非晶硅层116、氧化硅层311、N型硅片114、P型掺杂非晶硅层112、氧化铝和氮化硅层312、以及设置其上的银电极。
对比例3
图5为对比例3提供的硅/钙钛矿叠层太阳能电池的层结构示意图。请参阅图5，对比例3与实施例1的区别在于：对比例3中，不进行实施例1中的步骤(5)。
对比例4
图6为对比例4提供的硅/钙钛矿叠层太阳能电池的层结构示意图。请参阅图6，对比例4与实施例1的区别在于：对比例4中，不进行实施例1中的步骤(6)。
对比例5
对比例5与实施例2的区别在于：对比例5中，不进行实施例2中的步骤(5)和步骤(6)。
试验例
实施例1提供的制备方法，完成步骤(6)以后，将其进行TEM测试，得到测试结果如图7，从图7可以看出，P型掺杂的微晶硅氧层的晶格排布为：部分长程有序，部分无序排列，可以通过P型掺杂的微晶硅氧层与非晶硅层下方的N型掺杂非晶硅层形成PN结，其内建电场可以促进空穴隧穿，另外该PN结能够促使底电池和顶电池的Voc叠加，进而提高整个叠层电池的开路电压，提高电池效率。
图8为本公开实施例1和实施例2以及对比例4提供的硅/钙钛矿叠层太阳能电池的制备方法制备的掺杂的微晶硅氧层的拉曼光谱测试图。其中，对比组为对比例4提供的P型掺杂的微晶硅氧层的拉曼光谱测试图(Xc＝8.49％)；实验组-1为实施例1提供的P型掺杂的微晶硅氧层的拉曼光谱测试图(Xc＝29.54％)；实验组-2为实施例2提供的N型掺杂的微晶硅氧层的拉曼光谱测试图(Xc＝28.48％)。从图8可以看出，种子晶硅层(非晶硅层的设置)，可以使其上表面的掺杂的微晶硅氧层的结晶度更高。
分别检测实施例1至实施例4以及对比例1至对比例5提供的硅/钙钛矿叠层太阳能电池的性能如表1；其中，检测方法是：选用BERGER在线I-V测试系统，在25℃、AM 1.5、1个标准太阳的条件下测试硅/钙钛矿叠层太阳能电池的转化效率(Eff)、开路电压(Uoc)、短路电流(Isc)、填充因子(FF)等电性能参数。
表1硅/钙钛矿叠层太阳能电池的性能
Figure PCTCN2022089632-appb-000001
从表1可以看出，本公开提供的硅/钙钛矿叠层太阳能电池，在硅底电池和钙钛矿电池之间依次设置非晶硅层和掺杂微晶硅氧层，可以使电池的转化效率提高，开路电压提高。
实施例1和对比例1以及对比例2对比可以看出，在硅底电池和钙钛矿电池之间依 次设置非晶硅层和P型掺杂的微晶硅氧层，可以使电池的转化效率提高，开路电压提高。
实施例1和对比例3以及对比例4对比可以看出，如果仅仅在硅底电池和钙钛矿电池之间设置P型掺杂的微晶硅氧层，电池的转化效率提高不明显，如果仅仅在硅底电池和钙钛矿电池之间设置非晶硅层，电池的转化效率反而降低，而在硅底电池和钙钛矿电池之间依次设置非晶硅层和P型掺杂的微晶硅氧层，二者具有一定的协同作用，可以使电池的转化效率提高，开路电压提高。
实施例2和对比例5对比可以看出，在硅底电池和钙钛矿电池之间依次设置非晶硅层和N型掺杂的微晶硅氧层，可以使电池的转化效率提高，开路电压提高。
实施例1、实施例3和实施例4可以看出，P型掺杂的微晶硅氧层、P型掺杂的碳化微晶硅层和P型掺杂的碳化微晶硅氧层，与非晶硅层进行配合以后，均可以使电池的转化效率提高，开路电压提高。
以上所描述的实施例是本公开一部分实施例，而不是全部的实施例。本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
工业实用性
本公开提供一种硅/钙钛矿叠层太阳能电池及其制备方法，本公开以种子晶硅层为非晶硅层，隧穿层为掺杂的微晶硅氧层，从而该电池使硅底电池和钙钛矿顶电池之间的隧穿更加容易，以提高电池的开路电压和转化效率，具有优异的应用性能和广阔的市场前景。

Claims (13)

  1. 一种硅/钙钛矿叠层太阳能电池，包括硅底电池和钙钛矿顶电池，其特征在于，所述硅底电池的表面和所述钙钛矿顶电池的底面之间依次设置有种子晶硅层和隧穿层，所述种子晶硅层靠近所述硅底电池，所述隧穿层靠近所述钙钛矿顶电池；
    其中，所述种子晶硅层为非晶硅层，所述隧穿层为掺杂的微晶硅氧层、掺杂的碳化微晶硅层或掺杂的碳化微晶硅氧层。
  2. 根据权利要求1所述的硅/钙钛矿叠层太阳能电池，其特征在于，所述非晶硅层的厚度为1-3nm；所述隧穿层的厚度为10-30nm。
  3. 根据权利要求1或2所述的硅/钙钛矿叠层太阳能电池，其特征在于，所述硅底电池包括从上到下依次设置的N型掺杂非晶硅层、第一本征非晶硅层、N型硅片、第二本征非晶硅层和P型掺杂非晶硅层，所述隧穿层为P型掺杂的微晶硅氧层、P型掺杂的碳化微晶硅层或P型掺杂的碳化微晶硅氧层。
  4. 根据权利要求1或2所述的硅/钙钛矿叠层太阳能电池，其特征在于，所述硅底电池包括从上到下依次设置的P型掺杂非晶硅层、第一本征非晶硅层、P型硅片、第二本征非晶硅层和N型掺杂非晶硅层，所述隧穿层为N型掺杂的微晶硅氧层、N型掺杂的碳化微晶硅层或N型掺杂的碳化微晶硅氧层。
  5. 一种如权利要求1-4任一项所述的硅/钙钛矿叠层太阳能电池的制备方法，其特征在于，包括：
    形成所述硅底电池；
    在所述硅底电池的上表面沉积所述非晶硅层，在所述非晶硅层的表面沉积所述隧穿层，其中，所述隧穿层为所述掺杂的微晶硅氧层、掺杂的碳化微晶硅层或掺杂的碳化微晶硅氧层；
    在所述隧穿层的表面形成所述钙钛矿顶电池。
  6. 根据权利要求5所述的制备方法，其特征在于，所述非晶硅层的沉积条件包括：气源SiH 4的流量范围为200-1000sccm；气压范围为0.3-1mbar，射频功率范围为300-800W。
  7. 根据权利要求5所述的制备方法，其特征在于，所述隧穿层为P型掺杂的微晶硅氧层，所述隧穿层的沉积条件为：H 2、SiH 4、CO 2、B 2H 6的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W；
    或，所述隧穿层为P型掺杂的碳化微晶硅层，所述隧穿层的沉积条件为：H 2、SiH 4、CH 4、B 2H 6的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W；
    或，所述隧穿层为P型掺杂的碳化微晶硅氧层，所述隧穿层的沉积条件为：H 2、SiH 4、CO 2、CH 4、B 2H 6的流量比为(200-500):(1-3):1:(1-3):(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。
  8. 根据权利要求7所述的制备方法，其特征在于，形成所述硅底电池的方法，包括：对N型硅片进行制绒；在所述N型硅片的正面沉积第一本征非晶硅层，在所述硅片的背面沉积第二本征非晶硅层；在所述第一本征非晶硅层的背离所述N型硅片的表面形成N型掺杂非晶硅层，在所述第二本征非晶硅层的背离所述N型硅片的表面形成P型掺杂非晶硅层。
  9. 根据权利要求5所述的制备方法，其特征在于，所述隧穿层为N型掺杂的微晶硅氧层，所述隧穿层的沉积条件为：H 2、SiH 4、CO 2、PH 3的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W；
    或，所述隧穿层为N型掺杂的碳化微晶硅层，所述隧穿层的沉积条件为：H 2、SiH 4、CH 4、PH 3的流量比为(200-500):(1-3):1:(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W；
    或，所述隧穿层为N型掺杂的碳化微晶硅氧层，所述隧穿层的沉积条件为：H 2、SiH 4、CO 2、CH 4、PH 3的流量比为(200-500):(1-3):1:(1-3):(1-3)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。
  10. 根据权利要求9所述的制备方法，其特征在于，形成所述硅底电池的方法，包括：对P型硅片进行制绒；在所述P型硅片的正面沉积第一本征非晶硅层，在所述硅片的背面沉积第二本征非晶硅层；在所述第一本征非晶硅层的背离所述P型硅片的表面形成P型掺杂非晶硅层，在所述第二本征非晶硅层的背离所述P型硅片的表面形成N型掺杂非晶硅层。
  11. 根据权利要求8或10所述的制备方法，其特征在于，所述第一本征非晶硅层和第二本征非晶硅层的沉积条件分别包括：H 2与SiH 4的流量比为(1-15):1，气压范围为0.3-1mbar，射频功率范围为300-1200W。
  12. 根据权利要求8或10所述的制备方法，其特征在于，所述P型掺杂非晶硅层216的沉积条件包括：H 2、SiH 4和B 2H 6的流量比为(5-10):1:(1-10)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。
  13. 根据权利要求8或10所述的制备方法，其特征在于，N型掺杂非晶硅层212的沉积条件包括：H 2、SiH 4和PH 3的流量比为(5-10):1:(1-10)，气压范围为0.5-2mbar，射频功率范围为1000-3000W。
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