WO2023279989A1 - 异质结电池及其制备方法 - Google Patents

异质结电池及其制备方法 Download PDF

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WO2023279989A1
WO2023279989A1 PCT/CN2022/101226 CN2022101226W WO2023279989A1 WO 2023279989 A1 WO2023279989 A1 WO 2023279989A1 CN 2022101226 W CN2022101226 W CN 2022101226W WO 2023279989 A1 WO2023279989 A1 WO 2023279989A1
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layer
intrinsic
sub
intrinsic layer
wide bandgap
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PCT/CN2022/101226
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French (fr)
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徐晓华
辛科
周肃
龚道仁
王文静
李晨
陈梦滢
程尚之
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安徽华晟新能源科技有限公司
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Priority to EP22836743.9A priority Critical patent/EP4354518A1/en
Publication of WO2023279989A1 publication Critical patent/WO2023279989A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/035281—Shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the technical field of solar cell manufacturing, in particular to a heterojunction cell and a preparation method thereof.
  • Heterojunction solar cell is an important solar cell.
  • the heterojunction (HeteroJunction with intrinsic Thin layer, HJT) structure is centered on the N-type monocrystalline silicon substrate, and the two sides of the N-type monocrystalline silicon substrate are respectively arranged P-type amorphous silicon layer and N-type amorphous silicon layer, add a layer of intrinsic amorphous silicon layer between the P-type amorphous silicon layer, N-type amorphous silicon layer and N-type single crystal silicon substrate, take the After the process measures, the passivation characteristics of the substrate silicon wafer are changed, thereby improving the conversion efficiency of the heterojunction cell, making the heterojunction cell a very competitive solar cell technology in the market.
  • the intrinsic amorphous silicon layer itself has parasitic absorption of sunlight, it will affect the conversion efficiency of the heterojunction cell, and the conversion efficiency of the heterojunction cell needs to be further improved.
  • the technical problem to be solved in the present application is to overcome the problem that the conversion efficiency of the heterojunction battery needs to be further improved in the prior art, so as to provide a heterojunction battery and a preparation method thereof.
  • the present application provides a heterojunction battery, including: a semiconductor substrate layer; an intrinsic semiconductor composite layer, the intrinsic semiconductor composite layer is located on at least one side surface of the semiconductor substrate layer, and the intrinsic semiconductor composite layer includes: Bottom intrinsic layer; a wide bandgap intrinsic layer located on the surface of the bottom intrinsic layer facing away from the semiconductor substrate layer, the bandgap of the wide bandgap intrinsic layer is greater than that of the bottom intrinsic layer.
  • the intrinsic semiconductor compound layer is only located on the front side of the semiconductor substrate layer; or, the intrinsic semiconductor compound layer is only located on the back side of the semiconductor substrate layer; or, the intrinsic The semiconductor composite layer is located on both sides of the semiconductor substrate layer.
  • the wide bandgap intrinsic layer includes a first sub-wide bandgap intrinsic layer to an Nth sub-wide bandgap intrinsic layer, where N is an integer greater than or equal to 1.
  • the material of the nth sub-wide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon or carbon-doped nanocrystalline silicon; n is an integer greater than or equal to 1 and less than or equal to N .
  • the bottom intrinsic layer includes: a first sub-bottom intrinsic layer; a second sub-bottom intrinsic layer located on the surface of the first sub-bottom intrinsic layer facing away from the semiconductor substrate layer;
  • the defect state density of the second sub-underlayer intrinsic layer is smaller than the defect state density of the first sub-underlayer intrinsic layer.
  • the ratio of the thickness of the intrinsic layer of the first sub-underlayer to the thickness of the intrinsic layer of the second sub-underlayer is 0.15:1 ⁇ 0.35:1.
  • the thickness of the intrinsic layer of the first sub-underlayer is 0.3nm-0.8nm, and the thickness of the intrinsic layer of the second sub-underlayer is 1nm-2.5nm.
  • the total thickness of the intrinsic semiconductor composite layer located on one side of the semiconductor substrate layer is 2 nm ⁇ 10 nm.
  • N is an integer greater than or equal to 2
  • the kth sub-wide bandgap intrinsic layer is located between the k+1th sub-wide bandgap intrinsic layer and the semiconductor substrate layer
  • k is greater than or equal to 1 and less than or equal to N- Integer of 1.
  • N is equal to 2.
  • the material of the first sub-wide bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon
  • the material of the second sub-wide bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon Silicon
  • the molar ratio of oxygen and silicon in the first sub-wide bandgap intrinsic layer is 1:1 ⁇ 1:5
  • the molar ratio of carbon and silicon in the second sub-wide bandgap intrinsic layer is 1: 1 ⁇ 1:5;
  • the bandgap of the first sub-wide bandgap intrinsic layer is 2.0 eV-9 eV
  • the band gap of the second sub-wide bandgap intrinsic layer is 2.0 eV-9 eV.
  • the material of the first sub-wide bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon
  • the material of the second sub-wide bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped Nanocrystalline silicon
  • the molar ratio of carbon and silicon in the first sub-wide bandgap intrinsic layer is 1:1 to 1:5
  • the molar ratio of oxygen and silicon in the second sub-wide bandgap intrinsic layer is 1:1 ⁇ 1:5;
  • the bandgap of the first sub-wide bandgap intrinsic layer is 2.0 eV-9 eV
  • the band gap of the second sub-wide bandgap intrinsic layer is 2.0 eV-9 eV.
  • the ratio of the thickness of the second sub-wide bandgap intrinsic layer to the thickness of the first sub-wide bandgap intrinsic layer is 0.5:1 ⁇ 1.5:1; the first sub-wide bandgap intrinsic layer
  • the ratio of the thickness of the base layer to the thickness of the underlying intrinsic layer is 0.5:1 ⁇ 1.5:1.
  • the thickness of the second sub-wide bandgap intrinsic layer is 1.5 nm to 4 nm; the thickness of the first sub wide band gap intrinsic layer is 1.5 nm to 4 nm, and the thickness of the underlying intrinsic layer is 1.3 nm. nm ⁇ 3.3nm.
  • the refractive index of the k+1th sub-wide bandgap intrinsic layer in the intrinsic semiconductor compound layer is smaller than that of the first The refractive index of the k-subbandgap intrinsic layer.
  • the valence band difference between the intrinsic semiconductor composite layer and the semiconductor substrate layer is 0.6 eV ⁇ 1.2 eV.
  • N is equal to 1, and the bandgap of the wide bandgap intrinsic layer is 2.0eV ⁇ 9eV.
  • the ratio of the thickness of the wide bandgap intrinsic layer to the thickness of the underlying intrinsic layer is 1:1 ⁇ 3:1.
  • the thickness of the wide bandgap intrinsic layer is 2nm-8nm, and the thickness of the underlying intrinsic layer is 1.3nm-3.3nm.
  • the present application also provides a method for preparing a heterojunction battery, comprising the following steps: providing a semiconductor substrate layer; forming an intrinsic semiconductor compound layer on at least one surface of the semiconductor substrate layer, forming an intrinsic semiconductor compound layer
  • the steps include: forming an underlying intrinsic layer on at least one surface of the semiconductor substrate layer; forming a wide bandgap intrinsic layer on the surface of the underlying intrinsic layer facing away from the semiconductor substrate layer, and the wide bandgap intrinsic layer
  • the bandgap of the intrinsic layer is greater than the bandgap of the underlying intrinsic layer.
  • the intrinsic semiconductor compound layer is only formed on the front side of the semiconductor substrate layer; or, the intrinsic semiconductor compound layer is only formed on the back side of the semiconductor substrate layer; or, on the The intrinsic semiconductor composite layer is formed on both sides of the semiconductor substrate layer.
  • the step of forming the wide bandgap intrinsic layer on the surface of the underlying intrinsic layer facing away from the semiconductor substrate layer includes: forming the intrinsic layer on a side of the underlying intrinsic layer facing away from the semiconductor substrate layer The first sub-wide bandgap intrinsic layer to the Nth sub-wide bandgap intrinsic layer are sequentially formed on the side surface; N is an integer greater than or equal to 1.
  • the material of the nth sub-wide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, carbon-doped nanocrystalline silicon or oxygen-doped nanocrystalline silicon; n is an integer greater than or equal to 1 and less than or equal to N .
  • N is an integer greater than or equal to 2
  • the kth sub-wide bandgap intrinsic layer is located between the k+1th sub-wide bandgap intrinsic layer and the semiconductor substrate layer
  • k is greater than or equal to 1 and less than or equal to N- Integer of 1.
  • the refractive index of the k+1th sub-wide bandgap intrinsic layer in the intrinsic semiconductor compound layer is smaller than that of the first The refractive index of the k-subbandgap intrinsic layer.
  • the valence band difference between the intrinsic semiconductor composite layer and the semiconductor substrate layer is 0.6 eV-7.9 eV.
  • the nth sub-bandgap intrinsic layer is formed by a chemical vapor deposition process.
  • the process parameters for forming the nth sub-wide bandgap intrinsic layer include: the gases used include silane, hydrogen and carbon dioxide , wherein the volume ratio of silane to hydrogen is 1:1 to 1:10, the volume ratio of carbon dioxide to silane is 1:1 to 1:5, the chamber pressure is 0.2mBar to 1mBar, and the deposition temperature is 180°C to 240°C , the source radio frequency power density is 150W/m 2 -600W/m 2 .
  • the process parameters for forming the nth sub-wide bandgap intrinsic layer include: the gases used include silane, hydrogen and carbon dioxide , wherein the volume ratio of silane to hydrogen is 1:20 to 1:80, the volume ratio of carbon dioxide to silane is 1:1 to 1:5, the chamber pressure is 0.5mBar to 5mBar, and the deposition temperature is 180°C to 240°C , the source radio frequency power density is 500W/m 2 -2250W/m 2 .
  • the process parameters for forming the nth sub-wide bandgap intrinsic layer include: the gases used include silane, hydrogen and methane , wherein the volume ratio of silane to hydrogen is 1:1 to 1:10, the volume ratio of methane to silane is 1:1 to 1:5, the chamber pressure is 0.2mBar to 1mBar, and the deposition temperature is 180°C to 240°C , the source radio frequency power density is 150W/m 2 -600W/m 2 .
  • the process parameters for forming the nth sub-wide bandgap intrinsic layer include: the gases used include silane, hydrogen and methane , wherein the volume ratio of silane to hydrogen is 1:20 to 1:80, the volume ratio of methane to silane is 1:1 to 1:5, the chamber pressure is 0.5mBar to 5mBar, and the deposition temperature is 180°C to 240°C , the source radio frequency power density is 500W/m 2 -2250W/m 2 .
  • the step of forming the underlying intrinsic layer includes: forming a first sub-underlying intrinsic layer on at least one side surface of the semiconductor substrate layer; A second sub-underlayer intrinsic layer is formed on one surface of the substrate layer, and the defect state density of the second sub-underlayer intrinsic layer is smaller than that of the first sub-underlayer intrinsic layer.
  • the bandgap of the wide bandgap intrinsic layer is larger than the bandgap of the underlying intrinsic layer, and the bandgap of the wide bandgap intrinsic layer is relatively large.
  • the energy Photons smaller than the bandgap of the wide-bandgap intrinsic layer cannot be parasiticly absorbed, reducing the parasitic absorption of sunlight by the intrinsic semiconductor compound layer, thereby increasing the absorption of sunlight by the semiconductor substrate layer, and the photo-generated current carried by the semiconductor substrate layer
  • the number of electrons increases, which in turn can increase the short-circuit current of the heterojunction battery, and can improve the conversion efficiency of the heterojunction battery.
  • the density of defect states in the intrinsic layer of the first sub-bottom layer is relatively large, which mainly plays a role in preventing the epitaxial growth of the semiconductor substrate layer. There is too much recombination in the intrinsic layer of the sub-bottom; the density of defect states in the intrinsic layer of the second sub-bottom is small and relatively thick, which mainly plays the role of passivating the semiconductor substrate layer, and the photo-generated carriers in the second sub-bottom intrinsic layer There is less recombination in the layer, which can improve the short-circuit current of the heterojunction cell.
  • the second sub-bottom intrinsic layer acts as a transition layer between the first sub-bottom intrinsic layer and the wide-bandgap intrinsic layer, which can improve the wide-bandgap intrinsic layer. The contact performance between the intrinsic layer and the first underlying intrinsic layer.
  • the refractive index of the k+1th sub-wide bandgap intrinsic layer on the front side of the semiconductor substrate layer is smaller than the refractive index of the kth sub-wide bandgap intrinsic layer, so that the intrinsic semiconductor on the front side of the heterojunction cell
  • the refractive index of the composite layer has a gradient effect.
  • the intrinsic semiconductor composite layer on the front of the heterojunction cell has better anti-reflection performance. More sunlight enters the semiconductor substrate layer and is absorbed by the semiconductor substrate layer, which can improve the performance of the heterojunction cell. open circuit voltage.
  • doping oxygen atoms or carbon atoms in the wide bandgap intrinsic layer on the back side of the semiconductor substrate layer can improve the valence band between the intrinsic semiconductor composite layer and the semiconductor substrate layer on the back side of the semiconductor substrate layer Poor, the high valence band difference enhances the accumulation effect of the hole carriers in the photogenerated carriers, makes the open circuit voltage of the heterojunction cell larger, and can improve the direct tunneling of the hole carriers in the semiconductor substrate layer to the semiconductor substrate.
  • the probability of the intrinsic semiconductor compound layer on the back side of the bottom layer can improve the transmission efficiency of hole carriers in the intrinsic semiconductor compound layer on the back side of the semiconductor substrate layer, which will reduce the resistance of the heterojunction cell, and can Improve the conversion efficiency of heterojunction cells.
  • the bandgap of the wide bandgap intrinsic layer is relatively large.
  • photons with energy less than the bandgap of the wide bandgap intrinsic layer cannot be parasitic Absorption, reducing the parasitic absorption of sunlight by the intrinsic semiconductor composite layer, so that the absorption of sunlight by the semiconductor substrate layer increases, and the photogenerated carriers generated by the semiconductor substrate layer increase, which in turn can increase the short-circuit current of the heterojunction cell.
  • the conversion efficiency of the heterojunction cell can be improved.
  • FIG. 1 is a schematic structural diagram of a heterojunction battery provided in Example 1 of the present application.
  • FIG. 2 is a schematic structural diagram of a heterojunction battery provided in Example 2 of the present application.
  • FIG. 3 is a schematic structural diagram of a heterojunction battery provided in Example 3 of the present application.
  • FIG. 4 is a schematic structural diagram of a heterojunction battery provided in Example 4 of the present application.
  • FIG. 5 is a flowchart of a method for manufacturing a heterojunction battery provided by an embodiment of the present application.
  • FIG. 6 is a flow chart of the preparation method of the present application taking the heterojunction battery provided in Example 4 as an example.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it may be mechanically connected, or electrically connected; it may be directly connected, or indirectly connected through an intermediary, or it may be the internal communication of two components, which may be wireless or wired connect. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.
  • the present application provides a heterojunction battery, including: a semiconductor substrate layer; an intrinsic semiconductor composite layer, the intrinsic semiconductor composite layer is located on at least one side surface of the semiconductor substrate layer, and the intrinsic semiconductor composite layer includes: Bottom intrinsic layer; a wide bandgap intrinsic layer located on the surface of the bottom intrinsic layer facing away from the semiconductor substrate layer, the bandgap of the wide bandgap intrinsic layer is greater than that of the bottom intrinsic layer.
  • the bandgap of the wide-bandgap intrinsic layer is relatively large.
  • photons with energy less than the bandgap of the wide-bandgap intrinsic layer cannot be parasiticly absorbed, reducing the parasitic effect of the intrinsic semiconductor composite layer on sunlight.
  • Absorption so that the absorption of sunlight by the semiconductor substrate layer increases, and the photogenerated carriers generated by the semiconductor substrate layer increase, thereby increasing the short-circuit current of the heterojunction cell and improving the conversion efficiency of the heterojunction cell.
  • the intrinsic semiconductor composite layer is only located on the front side of the semiconductor substrate layer. In another embodiment, the intrinsic semiconductor composite layer is only located on the back side of the semiconductor substrate layer. In yet another embodiment, the intrinsic semiconductor composite layer is located on both sides of the semiconductor substrate layer.
  • the semiconductor substrate layer includes an N-type single-crystal silicon substrate, and the N-type single-crystal silicon has a relatively narrow band gap, usually 1.0 eV to 1.2 eV.
  • the wide bandgap intrinsic layer includes a first sub-wide bandgap intrinsic layer to an Nth sub-wide bandgap intrinsic layer, where N is an integer greater than or equal to 1.
  • the material of the nth wide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon or carbon-doped nanocrystalline silicon; n is an integer greater than or equal to 1 and less than or equal to N.
  • FIG. 1 where the arrows in FIG. 1 indicate the direction of sunlight irradiation.
  • the heterojunction cell structure in which the intrinsic semiconductor compound layer 2 is located only on the front side of the semiconductor substrate layer 1 is taken as an example for illustration.
  • the bandgap of the wide bandgap intrinsic layer 22 is 2.0eV ⁇ 9eV, for example, 2.0eV, 2.4eV, 2.8eV, 3.2eV and 9eV.
  • the ratio of the thickness of the wide bandgap intrinsic layer 22 to the thickness of the underlying intrinsic layer 21 is 1:1 ⁇ 3:1, for example, 1:1, 2:1 or 3:1.
  • the thickness of the wide bandgap intrinsic layer 22 is 2 nm to 8 nm, for example, 2 nm, 5 nm, 7 nm or 8 nm, and the thickness of the underlying intrinsic layer 21 is 1.3 nm to 3.3 nm, for example, 1.3 nm, 2nm, 3nm or 3.3nm.
  • the bottom intrinsic layer 21 includes: a first sub-bottom intrinsic layer 211; a second sub-bottom intrinsic layer 212 located on the surface of the first sub-bottom intrinsic layer 211 facing away from the semiconductor substrate layer 1;
  • the defect state density of the second sub-bottom intrinsic layer 212 is smaller than the defect state density of the first sub-bottom intrinsic layer 211, that is, the silylene group (-SiH 2 -) is smaller than the proportion of the silylene group (—SiH 2 —) in the first sub-underlayer intrinsic layer 211 .
  • the defect state density of the first sub-bottom intrinsic layer 211 is relatively large, which mainly plays the role of preventing the epitaxial growth of the semiconductor substrate layer 1.
  • the defect state density of the second sub-underlying intrinsic layer 212 is small and relatively thick, which mainly plays the role of passivating the semiconductor substrate layer 1, and the photogenerated carriers in the second sub-underlying layer
  • the second sub-bottom intrinsic layer 212 serves as a transition layer between the first sub-bottom intrinsic layer 211 and the wide bandgap intrinsic layer 22 , can improve the contact performance between the wide bandgap intrinsic layer 22 and the underlying intrinsic layer 21 .
  • the ratio of the thickness of the first sub-bottom intrinsic layer 211 to the thickness of the second sub-bottom intrinsic layer 212 is 0.15:1 ⁇ 0.35:1, for example, 0.15:1, 0.2: 1, 0.25:1, 0.3:1 or 0.35:1.
  • the thickness of the first sub-bottom intrinsic layer 211 is 0.3nm-0.8nm, for example, 0.3nm, 0.5nm, 0.7nm or 0.8nm, and the defect state of the first sub-bottom intrinsic layer 211
  • the density is relatively high, and the first sub-bottom intrinsic layer 211 mainly plays the role of preventing the epitaxial growth of the semiconductor substrate layer 1. If the first sub-bottom intrinsic layer 211 is too thin, it is difficult to achieve the effect of preventing the epitaxial growth of the semiconductor substrate layer 1. If If the first sub-bottom intrinsic layer 211 is too thick, the recombination of photogenerated carriers in the first sub-bottom intrinsic layer 211 will reduce the conversion efficiency of the heterojunction cell.
  • the second sub-bottom intrinsic layer 212 has a thickness of 1 nm to 2.5 nm, for example, 1 nm, 1.5 nm, 2 nm or 2.5 nm.
  • the second sub-bottom intrinsic layer 212 mainly functions to passivate the semiconductor substrate layer 1 and carry current. The effect of sub-transmission, if the second sub-bottom intrinsic layer 212 is too thin, the passivation effect of the second sub-bottom intrinsic layer 212 on the semiconductor substrate layer 1 will be reduced, if the second sub-bottom intrinsic layer 212 is too thick, the second sub-bottom intrinsic layer 212 will be reduced.
  • the intrinsic layer 212 of the second sub-bottom layer has more parasitic absorption of sunlight, and its own volume resistance is relatively large. The transmission efficiency of carriers in the second sub-bottom intrinsic layer 212 is poor, which will reduce the short circuit of the heterojunction cell. current.
  • the thickness of the first sub-bottom intrinsic layer 211 is 0.5 nm
  • the thickness of the second sub-bottom intrinsic layer 212 is 2 nm
  • the thickness of the wide bandgap intrinsic layer 22 is 5 nm.
  • the intrinsic semiconductor The composite layer 2 has good passivation performance to the semiconductor substrate layer 1, and can reduce the recombination of photogenerated carriers on the surface of the semiconductor substrate layer 1.
  • the volume resistance of the intrinsic semiconductor composite layer 2 is small, and the intrinsic semiconductor composite layer 2 is relatively
  • the parasitic absorption of sunlight is less
  • the second sub-bottom intrinsic layer 212 is used as a transition layer between the first sub-bottom intrinsic layer 211 and the wide bandgap intrinsic layer 22, which can improve the wide bandgap intrinsic layer 22 and the bottom intrinsic layer.
  • the total thickness of the intrinsic semiconductor composite layer 2 located on one side of the semiconductor substrate layer 1 is 2nm ⁇ 10nm, for example, 2nm, 5nm, 7nm, 9nm or 10nm.
  • the thickness of the intrinsic semiconductor composite layer 2 is relatively thin, which has less parasitic absorption of sunlight, can increase the short-circuit current of the heterojunction cell, and can improve the conversion efficiency of the heterojunction cell.
  • the wide bandgap intrinsic layer 22 includes a first sub-wide bandgap intrinsic layer to an Nth sub-wide bandgap intrinsic layer, where N is an integer greater than or equal to 1.
  • the wide bandgap intrinsic layer 22 is a single-layer structure, that is, N is equal to 1.
  • the wide bandgap intrinsic layer 22 is a multilayer structure, N is an integer greater than or equal to 2, and the kth sub-wide-gap intrinsic layer is located between the k+1th sub-wide-gap intrinsic layer and the semiconductor substrate Between bottom layers; k is an integer greater than or equal to 1 and less than or equal to N-1.
  • the material of the nth wide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon or carbon-doped nanocrystalline silicon; n is an integer greater than or equal to 1 and less than or equal to N.
  • N is equal to 2
  • the wide bandgap intrinsic layer 22 includes a first sub wide bandgap intrinsic layer and a second sub wide bandgap intrinsic layer, and the second sub wide bandgap intrinsic layer is located in the first sub wide bandgap intrinsic layer
  • the wide bandgap faces away from the side surface of the semiconductor substrate layer 1 .
  • the material of the first sub-wide bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon
  • the material of the second sub-wide bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped Nanocrystalline silicon
  • the molar ratio of oxygen to silicon in the first sub-wide bandgap intrinsic layer is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4 or 1:5
  • the molar ratio of carbon to silicon in the second sub-wide bandgap intrinsic layer is 1:1 ⁇ 1:5, for example, 1:1, 1:2, 1:3, 1:4 or 1:5.
  • the bandgap of the first sub-wide bandgap intrinsic layer is relatively wide, and the bandgap of the first sub-wide bandgap intrinsic layer is 2.0eV-9eV, for example, 2.0eV , 2.4eV, 2.6eV, 3.2eV or 9eV; due to the doping of carbon atoms in the second sub-wide bandgap intrinsic layer, the bandgap of the second sub-wide bandgap intrinsic layer is wider, and the second sub-wide bandgap intrinsic layer
  • the band gap is 2.0eV ⁇ 9eV, for example, 2.0eV, 2.5eV, 2.8eV, 3.2eV or 9eV.
  • the material of the first sub-wide bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon
  • the material of the second sub-wide bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon
  • the molar ratio of carbon to silicon in the first sub-wide bandgap intrinsic layer is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4 or 1:5
  • the molar ratio of oxygen to silicon in the second sub-wide bandgap intrinsic layer is 1:1 ⁇ 1:5, for example, 1:1, 1:2, 1:3, 1:4 or 1:5.
  • the bandgap of the first sub-wide bandgap intrinsic layer is 2.3eV ⁇ 2.8eV, for example, 2.3eV, 2.5eV, 2.7eV or 2.8eV
  • the bandgap of the second sub-wide bandgap intrinsic layer The band gap is 2.0eV ⁇ 2.6eV, for example, 2.0eV, 2.2eV, 2.6eV, 3.2eV or 9eV.
  • the ratio of the thickness of the second sub-wide bandgap intrinsic layer to the thickness of the first sub-wide bandgap intrinsic layer is 0.5:1 ⁇ 1.5:1, for example, 0.5:1, 0.8:1, 1:1, 1.2:1 or 1.5:1; the ratio of the thickness of the first sub-wide bandgap intrinsic layer to the thickness of the underlying intrinsic layer is 0.5:1 to 1.5:1, such as 0.5:1, 0.8:1, 1 :1, 1.2:1, 1.5:1 or 1.5:1.
  • the thickness of the second sub-wide bandgap intrinsic layer is 1.5 nm to 4 nm, for example, 1.5 nm, 2 nm, 3 nm or 4 nm; the thickness of the first sub wide band gap intrinsic layer is 1.5 nm to 4 nm, for example, 1.5 nm nm, 2 nm, 3 nm or 4 nm; the underlying intrinsic layer has a thickness of 1.3 nm to 3.3 nm, for example, 1.3 nm, 2 nm, 3 nm or 3.3 nm.
  • the refractive index of the k+1th sub-wide bandgap intrinsic layer in the intrinsic semiconductor compound layer 2 is smaller than the kth The refractive index of the sub-wide bandgap intrinsic layer.
  • the refractive index of the second sub-wide bandgap intrinsic layer is smaller than that of the first sub-wide bandgap intrinsic layer, so that the refractive index of the intrinsic semiconductor composite layer 2 on the front side of the heterojunction cell has a gradient effect, and the heterojunction
  • the intrinsic semiconductor composite layer 2 on the front of the battery has better anti-reflection performance, and more sunlight enters the semiconductor substrate layer 1 and is absorbed by the semiconductor substrate layer 1, which can increase the open circuit voltage of the heterojunction battery.
  • the heterojunction cell further includes: a back intrinsic layer 3 located on the surface of the semiconductor substrate layer 1 facing away from the intrinsic semiconductor composite layer 2 .
  • the back intrinsic layer 3 may be a single-layer structure or a multi-layer structure, which is not limited.
  • the heterojunction cell also includes: a first doped layer 4 located on the surface of the intrinsic semiconductor compound layer 2 facing away from the semiconductor substrate layer 1; The first transparent conductive film 6 on one side surface of the semiconductor composite layer 2; the first gate line electrode 8 on the side surface of the first transparent conductive film 6 facing away from the intrinsic semiconductor composite layer 2; the intrinsic layer 3 on the back side facing away from the semiconductor The second doped layer 5 on one side surface of the substrate layer 1; the second transparent conductive film 7 on the side surface of the second doped layer 5 facing away from the intrinsic layer 3 on the back; As for the second gate electrode 9 on one side of the doped layer 5 , it should be noted that the conductivity type of the first doped layer 4 is opposite to that of the second doped layer 5 .
  • this embodiment is described by taking the heterojunction cell structure in which the intrinsic semiconductor compound layer 2 is located only on the back side of the semiconductor substrate layer 1 as an example.
  • the valence band difference between the intrinsic semiconductor composite layer 2 and the semiconductor substrate layer 1 is 0.6eV to 7.9eV, for example 0.6 eV, 1.0eV, 2.1eV, or 7.9eV.
  • Doping oxygen atoms or carbon atoms in the wide bandgap intrinsic layer 22 can improve the valence band difference between the intrinsic semiconductor composite layer 2 on the back side of the semiconductor substrate layer 1 and the semiconductor substrate layer 1, and the high valence band difference is beneficial to The accumulation effect of the hole carriers in the photogenerated carriers is enhanced, so that the open circuit voltage of the heterojunction cell is larger, and the hole carriers in the semiconductor substrate layer 1 can directly tunnel to the back side of the semiconductor substrate layer 1.
  • the probability of the intrinsic semiconductor composite layer 2 can improve the transmission efficiency of hole carriers in the intrinsic semiconductor composite layer 2 on the back side of the semiconductor substrate layer 1, reduce the resistance of the heterojunction battery, and improve the heterogeneity. The conversion efficiency of the junction cell.
  • the wide bandgap intrinsic layer 22 includes a first sub-wide bandgap intrinsic layer to an Nth sub-wide bandgap intrinsic layer, where N is an integer greater than or equal to 1.
  • the wide bandgap intrinsic layer 22 is a single-layer structure, that is, N is equal to 1.
  • the wide bandgap intrinsic layer 22 is a multilayer structure, N is an integer greater than or equal to 2, and the kth sub-wide-gap intrinsic layer is located between the k+1th sub-wide-gap intrinsic layer and the semiconductor substrate Between bottom layers; k is an integer greater than or equal to 1 and less than or equal to N-1.
  • the material of the nth wide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon or carbon-doped nanocrystalline silicon; n is an integer greater than or equal to 1 and less than or equal to N.
  • N is equal to 2
  • the wide bandgap intrinsic layer 22 includes a first sub wide bandgap intrinsic layer and a second sub wide bandgap intrinsic layer, and the second sub wide bandgap intrinsic layer is located in the first sub wide bandgap intrinsic layer
  • the wide bandgap faces away from the side of the semiconductor substrate layer 1 .
  • the heterojunction cell further includes: a front intrinsic layer 3 a located on the surface of the semiconductor substrate layer 1 facing away from the intrinsic semiconductor composite layer 2 .
  • the front intrinsic layer 3a can be a single-layer structure or a multi-layer structure.
  • the heterojunction battery structure in which the intrinsic semiconductor compound layer is located on both sides of the semiconductor substrate layer 1 and the wide bandgap intrinsic layer is a single-layer structure (that is, N is equal to 1) is taken as an example. Be explained.
  • the intrinsic semiconductor composite layer 2 includes a front intrinsic semiconductor composite layer 2A located on the front side of the semiconductor substrate layer 1 and a rear intrinsic semiconductor composite layer 3A located on the back side of the semiconductor substrate layer 1 .
  • the front intrinsic semiconductor composite layer 2A includes: the front bottom intrinsic layer 21A; the front wide bandgap intrinsic layer 22A located on the surface of the front bottom intrinsic layer 21A facing away from the semiconductor substrate layer 1, and the front wide bandgap intrinsic layer 22A.
  • the bandgap of the intrinsic layer 22A is larger than the bandgap of the front bottom intrinsic layer 21A.
  • the back intrinsic semiconductor composite layer 3A comprises: a back bottom intrinsic layer 31A; a back wide bandgap intrinsic layer 32A located on the back side of the back bottom intrinsic layer 31A facing away from the semiconductor substrate layer 1, the back wide bandgap intrinsic layer
  • the bandgap of the intrinsic layer 32A is larger than the bandgap of the bottom intrinsic layer 31A.
  • the bottom intrinsic layer includes a front bottom intrinsic layer 21A located on the front side of the semiconductor substrate layer 1 and a back bottom intrinsic layer 31A located on the back side of the semiconductor substrate layer 1 .
  • the front bottom intrinsic layer 21A includes: a first sub-front bottom intrinsic layer 211A located on the front side of the semiconductor substrate layer 1;
  • the bottom intrinsic layer 31A on the back side comprises: a first sub-back bottom intrinsic layer 311A located on the back side of the semiconductor substrate layer 1;
  • the ratio of the thickness of the first sub-front bottom intrinsic layer 211A to the thickness of the second sub-front bottom intrinsic layer 212A is 0.15:1 ⁇ 0.35:1, for example, 0.15:1, 0.2:1, 0.25:1, 0.3:1 or 0.35:1.
  • the thickness of the first sub-front bottom intrinsic layer 211A is 0.3 nm to 0.8 nm, for example, 0.3 nm, 0.5 nm, 0.7 nm or 0.8 nm
  • the thickness of 212A is 1 nm ⁇ 2.5 nm, for example, 1 nm, 1.5 nm, 2 nm or 2.5 nm.
  • the total thickness of the front intrinsic semiconductor composite layer 2A is 2 nm ⁇ 10 nm, for example, 2 nm, 5 nm, 7 nm, 9 nm or 10 nm.
  • the back intrinsic semiconductor composite layer 3A The total thickness is 5nm ⁇ 10nm, for example, 5nm, 7nm, 9nm or 10nm.
  • the material of the front wide bandgap intrinsic layer 22A includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon or carbon-doped nanocrystalline silicon.
  • the material of the back wide bandgap intrinsic layer 32A includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon or carbon-doped nanocrystalline silicon.
  • the material of the front wide bandgap intrinsic layer 22A includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, and the molar ratio of oxygen and silicon in the front wide bandgap intrinsic layer 22A is 1: 1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4 or 1:5. Because oxygen atoms are doped in the front wide bandgap intrinsic layer 22A, the bandgap of the front wide bandgap intrinsic layer 22A is relatively wide, and the bandgap of the front wide bandgap intrinsic layer 22A is 2.0eV ⁇ 2.6eV, for example, 2.0eV, 2.2 eV, 2.4eV or 2.6eV.
  • the material of the front wide bandgap intrinsic layer 22A includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon.
  • the molar ratio of carbon to silicon in the front wide bandgap intrinsic layer 22A is 1:1 ⁇ 1:5, for example, 1:1, 1:2, 1:3, 1:4 or 1:5. Since carbon atoms are doped in the front wide bandgap intrinsic layer 22A, the bandgap of the front wide bandgap intrinsic layer 22A is relatively wide, and the bandgap of the front wide bandgap intrinsic layer 22A is 2.3eV ⁇ 2.8eV, for example, 2.3eV, 2.5 eV, 2.7eV or 2.8eV.
  • the material of the back wide bandgap intrinsic layer 32A includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, and the molar ratio of carbon to silicon in the back wide bandgap intrinsic layer 32A is 1:1- 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5.
  • the bandgap of the back wide bandgap intrinsic layer 32A is 2.3eV ⁇ 2.8eV, for example, 2.3eV, 2.5eV, 2.7eV or 2.8eV.
  • the material of the back wide bandgap intrinsic layer 32A includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon.
  • the molar ratio of oxygen to silicon in the back wide bandgap intrinsic layer 32A is 1:1 ⁇ 1:5, for example, 1:1, 1:2, 1:3, 1:4 or 1:5.
  • the bandgap of the back wide bandgap intrinsic layer 32A is 2.0eV ⁇ 9eV, for example, 2.0eV, 2.4eV, 2.6eV, 3.2eV or 9eV.
  • the ratio of the thickness of the front wide bandgap intrinsic layer 22A to the thickness of the front bottom intrinsic layer is 1:1 ⁇ 3:1.
  • the thickness of the front wide bandgap intrinsic layer 22A is 2nm-8nm, and the thickness of the front bottom intrinsic layer is 1.3nm-3.3nm.
  • the ratio of the thickness of the back wide bandgap intrinsic layer 32A to the thickness of the back underlying intrinsic layer is 1:1 ⁇ 3:1.
  • the thickness of the back wide bandgap intrinsic layer 32A is 2nm-8nm, and the thickness of the back bottom intrinsic layer is 1.3nm-3.3nm.
  • the first doped layer 4 located on the surface of the front intrinsic semiconductor composite layer 2A facing away from the semiconductor substrate layer 1; the surface of the first doped layer 4 facing away from the semiconductor substrate layer 1
  • the wire electrode 9 it should be noted that the conductivity type of the first doped layer 4 is opposite to that of the second doped layer 5 .
  • the intrinsic semiconductor composite layer is located on both sides of the semiconductor substrate layer 1, the wide bandgap intrinsic layer is a laminated structure, and the wide bandgap intrinsic layer includes a first sub-wide bandgap intrinsic From the intrinsic layer to the Nth sub-wide bandgap intrinsic layer, N is an integer greater than or equal to 2, and the kth sub-wide bandgap intrinsic layer is located between the k+1th sub-wide bandgap intrinsic layer and the semiconductor substrate layer 1; k It is an integer greater than or equal to 1 and less than or equal to N-1.
  • the refractive index of the k+1th sub-wide bandgap intrinsic layer in the intrinsic semiconductor compound layer 2 is smaller than the kth
  • the refractive index of the sub-wide bandgap intrinsic layer makes the refractive index of the intrinsic semiconductor composite layer 2 on the front of the heterojunction cell have a gradient effect, and the intrinsic semiconductor composite layer 2 on the front of the heterojunction cell has better antireflection performance, More sunlight enters the semiconductor substrate layer 1 and is absorbed by the semiconductor substrate layer 1, which can increase the open circuit voltage of the heterojunction cell.
  • the valence band difference between the intrinsic semiconductor composite layer 2 and the semiconductor substrate layer 1 is 0.6 eV ⁇ 7.9 eV.
  • the intrinsic semiconductor composite layer 2 includes a front intrinsic semiconductor composite layer 2A located on the front side of the semiconductor substrate layer 1 and a rear intrinsic semiconductor composite layer 3A located on the back side of the semiconductor substrate layer 1 .
  • the front intrinsic semiconductor composite layer 2A includes: the front bottom intrinsic layer 21A; the front wide bandgap intrinsic layer 22A located on the surface of the front bottom intrinsic layer 21A facing away from the semiconductor substrate layer 1, and the front wide bandgap intrinsic layer 22A.
  • the bandgap of layer 22A is greater than the bandgap of the front bottom intrinsic layer 21A.
  • the front bottom intrinsic layer 21A please refer to the content corresponding to Embodiment 3, which will not be described in detail here.
  • the front wide bandgap intrinsic layer 22A includes a first sub-front wide bandgap intrinsic layer 221A and a second sub-front wide bandgap intrinsic layer located on the side of the first sub-front wide bandgap intrinsic layer 221A facing away from the front underlying intrinsic layer 21A.
  • Layer 222A The front wide bandgap intrinsic layer 22A includes a first sub-front wide bandgap intrinsic layer 221A and a second sub-front wide bandgap intrinsic layer located on the side of the first sub-front wide bandgap intrinsic layer 221A facing away from the front underlying intrinsic layer 21A.
  • the back intrinsic semiconductor composite layer 3A comprises: the back bottom intrinsic layer 31A; the back wide bandgap intrinsic layer 32A located on the back surface of the back bottom intrinsic layer 31A facing away from the semiconductor substrate layer 1, the back wide bandgap intrinsic layer
  • the bandgap of layer 32A is greater than the bandgap of the bottom underlying intrinsic layer 31A.
  • the underlying intrinsic layer 31A on the back please refer to the content corresponding to Embodiment 3, which will not be described in detail here.
  • the back wide-bandgap intrinsic layer 32A includes a first sub-back wide-gap intrinsic layer 321A and a second sub-back wide-gap intrinsic layer located on the side of the first sub-back wide-gap intrinsic layer 321A facing away from the back underlying intrinsic layer 31A. Layer 322A.
  • the material of the first sub-front wide bandgap intrinsic layer 221A includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon
  • the material of the second sub-front wide bandgap intrinsic layer 222A includes carbon-doped amorphous silicon.
  • the molar ratio of oxygen to silicon in the first sub-front wide bandgap intrinsic layer 221A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1 :4 or 1:5
  • the molar ratio of carbon to silicon in the second sub-front wide bandgap intrinsic layer 222A is 1:1 ⁇ 1:5, for example, 1:1, 1:2, 1:3, 1:1 4 or 1:5.
  • the bandgap of the first sub-front wide bandgap intrinsic layer 221A is relatively wide, and the band gap of the first sub-front wide bandgap intrinsic layer 221A is 2.0eV ⁇ 9eV, for example, 2.0eV, 2.4eV, 2.6eV, 3.2eV or 9eV; since carbon atoms are doped in the second sub-front wide bandgap intrinsic layer 222A, the bandgap of the second sub-front wide bandgap intrinsic layer 222A is wider , the bandgap of the second sub-front wide bandgap intrinsic layer 222A is 2.0eV ⁇ 9eV, for example, 2.0eV, 2.5eV, 2.8eV, 3.2eV or 9eV.
  • the material of the first sub-front wide bandgap intrinsic layer 221A includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon
  • the material of the second sub-front wide bandgap intrinsic layer 222A includes oxygen-doped Amorphous silicon or oxygen-doped nanocrystalline silicon
  • the molar ratio of carbon to silicon in the first sub-front wide bandgap intrinsic layer 221A is 1:1 ⁇ 1:5, for example, 1:1, 1:2, 1:3 , 1:4 or 1:5
  • the molar ratio of oxygen to silicon in the second sub-front wide bandgap intrinsic layer 222A is 1:1 ⁇ 1:5, for example, 1:1, 1:2, 1:3, 1 :4 or 1:5.
  • the bandgap of the first sub-front wide bandgap intrinsic layer 221A is 2.0eV ⁇ 9eV, for example, 2.0eV, 2.5eV, 2.8eV, 3.2eV or 9eV
  • the bandgap of the intrinsic layer 222A is 2.0eV ⁇ 9eV, for example, 2.0eV, 2.4eV, 2.6eV, 3.2eV or 9eV.
  • the ratio of the thickness of the second sub-front wide bandgap intrinsic layer 222A to the thickness of the first sub-front wide bandgap intrinsic layer 221A is 0.5:1 ⁇ 1.5:1, for example, 0.5:1, 0.8:1, 1:1, 1.2:1 or 1.5:1; the ratio of the thickness of the first sub-front wide bandgap intrinsic layer 221A to the thickness of the front bottom intrinsic layer 21A is 0.5:1-1.5:1, such as 0.5 :1, 0.8:1, 1:1, 1.2:1, 1.5:1 or 1.5:1.
  • the thickness of the second sub-front wide bandgap intrinsic layer 222A is 1.5 nm to 4 nm, for example, 1.5 nm, 2 nm, 3 nm or 4 nm; the thickness of the first sub front wide band gap intrinsic layer 221A is 1.5 nm to 4 nm. , for example, 1.5 nm, 2 nm, 3 nm or 4 nm; the thickness of the front underlying intrinsic layer 21A is 1.3 nm ⁇ 3.3 nm, for example, 1.3 nm, 2 nm, 3 nm or 3.3 nm.
  • the material, thickness, and bandgap of the first sub-back wide-gap intrinsic layer 321A refer to the first sub-front wide-band-gap intrinsic layer 221A; for the material, thickness, and bandgap of the second sub-back wide-gap intrinsic layer 322A, refer to the second sub
  • the front wide bandgap intrinsic layer 222A will not be described in detail here.
  • the front wide bandgap intrinsic layer 22A is a single-layer structure
  • the second wide bandgap intrinsic layer 32A is a stacked structure
  • the front wide bandgap intrinsic layer 22A is a stacked layer Structure
  • the second wide bandgap intrinsic layer 32A is a single-layer structure.
  • This embodiment provides a method for preparing a heterojunction battery, please refer to FIG. 5, including the following steps:
  • Step S1 providing a semiconductor substrate layer 1 .
  • Step S2 forming an intrinsic semiconductor composite layer 2 on at least one surface of the semiconductor substrate layer 1, the step of forming the intrinsic semiconductor composite layer 2 includes: forming a bottom layer on at least one surface of the semiconductor substrate layer 1 Intrinsic layer; a wide bandgap intrinsic layer is formed on the surface of the bottom intrinsic layer facing away from the semiconductor substrate layer 1, and the bandgap of the wide bandgap intrinsic layer is greater than the band gap of the bottom intrinsic layer 1 Gap.
  • the position of forming the intrinsic semiconductor compound layer 2 includes: forming the intrinsic semiconductor compound layer 2 only on the front side of the semiconductor substrate layer 1; or forming the intrinsic semiconductor compound layer 2 only on the back side of the semiconductor substrate layer 1
  • the intrinsic semiconductor composite layer 2 ; or, the intrinsic semiconductor composite layer 2 is formed on both surfaces of the semiconductor substrate layer 1 .
  • the step of forming the wide bandgap intrinsic layer on the surface of the bottom intrinsic layer facing away from the semiconductor substrate layer 1 includes: forming the bottom intrinsic layer on the surface of the bottom intrinsic layer facing away from the semiconductor substrate layer 1. Forming the first sub-wide bandgap intrinsic layer to the Nth sub-wide bandgap intrinsic layer in sequence; N is an integer greater than or equal to 1.
  • the material of the nth sub-wide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, carbon-doped nanocrystalline silicon or oxygen-doped nanocrystalline silicon; n is an integer greater than or equal to 1 and less than or equal to N .
  • N is an integer greater than or equal to 2
  • the kth sub-wide bandgap intrinsic layer is located between the k+1th sub-wide bandgap intrinsic layer and the semiconductor substrate layer
  • k is greater than or equal to 1 and less than or equal to N- an integer of 1;
  • the refractive index of the k+1th sub-wide bandgap intrinsic layer in the intrinsic semiconductor composite layer 2 is less than The refractive index of the kth sub-wide bandgap intrinsic layer.
  • the valence band difference between the intrinsic semiconductor composite layer 2 and the semiconductor substrate layer 1 is 0.6eV-7.9 eV, such as 0.6eV, 1.0eV, 1.2eV, 2.1eV or 7.9eV.
  • the process parameters for forming the nth sub-wide bandgap intrinsic layer include: the gases used include silane, hydrogen and carbon dioxide, wherein silane
  • the volume ratio of hydrogen to hydrogen is 1:1 ⁇ 1:10, for example, 1:2, 1:4, 1:6, 1:8 or 1:10; the volume ratio of carbon dioxide to silane is 1:1 ⁇ 1:5 , for example, 1:1, 1:2, 1:3, 1:4 or 1:5; chamber pressure is 0.2mBar ⁇ 1mBar, for example, 0.2mBar, 0.4mBar, 0.6mBar, 0.8mBar or 1mBar; deposition temperature 180°C to 240°C, for example, 180°C, 200°C, 220°C or 240°C; source RF power density is 150W/m 2 to 600W/m 2 , for example, 150W/m 2 , 250W/m 2 , 350W/m 2 m 2 , 450W
  • the process parameters for forming the nth sub-wide bandgap intrinsic layer include: the gases used include silane, hydrogen and carbon dioxide, wherein silane
  • the volume ratio of hydrogen to hydrogen is 1:20 to 1:80, for example, 1:20, 1:40, 1:60 or 1:80; the volume ratio of carbon dioxide to silane is 1:1 to 1:5, for example, 1 :1, 1:2, 1:3, 1:4 or 1:5; chamber pressure is 0.5mBar ⁇ 5mBar For example, 0.5mBar, 1mBar, 3mBar, 4mBar or 5mBar; deposition temperature is 180°C-240°C, for example, 180°C, 200°C, 220°C or 240°C; source RF power density is 500W/m 2 -2250W/m 2 , for example, 500W/m 2 , 1000W/m 2 , 1500W/m 2 , 2000W/m 2 or 2250W
  • the process parameters for forming the nth sub-wide bandgap intrinsic layer include: the gases used include silane, hydrogen and methane, wherein silane
  • the volume ratio of hydrogen to hydrogen is 1:1 ⁇ 1:10, for example, 1:2, 1:4, 1:6, 1:8 or 1:10; the volume ratio of methane to silane is 1:1 ⁇ 1:5 , for example, 1:1, 1:2, 1:3, 1:4 or 1:5;
  • the chamber pressure is 0.2mBar ⁇ 1mBar
  • deposition temperature is 180°C ⁇ 240°C, for example, 180°C, 200°C, 220°C or 240°C;
  • source RF power density is 150W/m 2 ⁇ 600W /m 2 , for example, 150W/m 2 , 250W/m 2 , 350W/m 2 , 450W
  • the process parameters for forming the nth sub-wide bandgap intrinsic layer include: the gases used include silane, hydrogen and methane, wherein silane
  • the volume ratio of hydrogen to hydrogen is 1:20 to 1:80, for example, 1:20, 1:40, 1:60 or 1:80; the volume ratio of methane to silane is 1:1 to 1:5, for example, 1 :1, 1:2, 1:3, 1:4 or 1:5; chamber pressure is 0.5mBar ⁇ 5mBar For example, 0.5mBar, 1mBar, 3mBar, 4mBar or 5mBar; deposition temperature is 180°C-240°C, for example, 180°C, 200°C, 220°C or 240°C; source RF power density is 500W/m 2 -2250W/m 2 ,, for example, 500W/m 2 , 1000W/m 2 , 1500W/m 2 , 2000W/m 2 or
  • the step of forming the underlying intrinsic layer includes: forming a first sub-underlying intrinsic layer 211 on at least one side surface of the semiconductor substrate layer 1; A second sub-bottom intrinsic layer 212 is formed on one side of the surface, and the defect state density of the second sub-bottom intrinsic layer 212 is smaller than the defect state density of the first sub-bottom intrinsic layer 211 .
  • the front intrinsic semiconductor composite layer 2A includes the first sub-front wide bandgap intrinsic layer 221A and the second sub-front wide bandgap intrinsic layer 221A.
  • the laminated structure of layer 222A and the laminated structure of the first sub-rear wide bandgap intrinsic layer 321A and the second sub-rear wide bandgap intrinsic layer 322A in the back intrinsic semiconductor composite layer 3A are taken as examples, for heterojunction cells The preparation method is described in detail:
  • Step A1 providing a semiconductor substrate layer.
  • the semiconductor substrate layer includes an N-type single crystal silicon substrate.
  • Step A2 Texturing and cleaning the semiconductor substrate layer 1 .
  • Step A3 On one side of the semiconductor substrate layer 1, a first sub-front underlying intrinsic layer 211A, a second sub-front underlying intrinsic layer 212A, a first sub-front wide bandgap intrinsic layer 221A, The second sub-front wide bandgap intrinsic layer 222A and the first doped layer.
  • Step A4 On the other side of the semiconductor substrate layer 1, the first sub-back bottom intrinsic layer 311A, the second sub-back bottom intrinsic intrinsic layer 312A, and the first sub-back wide bandgap intrinsic layer 321A are sequentially formed by chemical vapor deposition process , the second sub-back wide bandgap intrinsic layer 322A and the second doped layer.
  • first doped layer and the second doped layer after forming the second sub-front wide bandgap intrinsic layer 222A and the second sub-back wide bandgap intrinsic layer 322A. layer.
  • Step A5 Forming a first transparent conductive film 6 on the surface of the first doped layer and forming a second transparent conductive film 7 on the surface of the second doped layer by a physical vapor deposition process.
  • the amorphous silicon structure is a disordered structure, the mobility of electrons and holes is low, and the lateral conductivity is poor, which is not conducive to the collection of photogenerated carriers.
  • the first transparent conductive film 6 and the second transparent conductive film 7 are used to collect Carriers are transported to the electrodes.
  • Step A6 Forming the first gate electrode 8 on the surface of the first transparent conductive film by screen printing process
  • the second gate electrode 9 is formed on the surface of the second transparent conductive film 7 .
  • the first grid line electrode 8 is used to collect the current transmitted by the first transparent conductive film 6
  • the second grid line electrode 9 is used to collect the current transmitted by the second transparent conductive film 7 .
  • Step A7 Curing and light injection annealing are performed on the first grid line electrode 8 and the second grid line electrode 9 .
  • the surface of the heterojunction cell is irradiated with strong light for a certain period of time to improve the conversion efficiency of the heterojunction cell.
  • the bandgap of the wide-bandgap intrinsic layer is relatively large, and when sunlight irradiates the heterojunction battery, photons with energy less than the bandgap of the wide-bandgap intrinsic layer cannot be parasiticly absorbed , reduce the parasitic absorption of sunlight by the intrinsic semiconductor compound layer, so that the absorption of sunlight by the semiconductor substrate layer increases, and the photogenerated carriers generated by the semiconductor substrate layer increase, which in turn can improve the short-circuit current of the heterojunction cell, and can Improve the conversion efficiency of heterojunction cells.

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Abstract

本申请提供一种异质结电池及其制备方法，异质结电池包括：半导体衬底层；本征半导体复合层，所述本征半导体复合层位于所述半导体衬底层的至少一侧表面，所述本征半导体复合层包括：底层本征层；位于所述底层本征层背向所述半导体衬底层一侧表面的宽带隙本征层，所述宽带隙本征层的带隙大于所述底层本征层的带隙。宽带隙本征层的带隙较大，当太阳光照射异质结电池时，能量小于宽带隙本征层的带隙的光子不能被寄生吸收，减小本征半导体复合层对太阳光的寄生吸收，从而使得半导体衬底层对太阳光的吸收增多，半导体衬底层产生的光生载流子增多，进而能提高异质结电池的短路电流，能提高异质结电池的转换效率。

Description

异质结电池及其制备方法
相关申请的交叉引用
本申请要求在2021年7月7日提交中国专利局、申请号为202110767660.2、发明名称为“一种异质结电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用的方式并入本文中。
技术领域
本申请涉及太阳能电池制造技术领域，具体涉及一种异质结电池及其制备方法。
背景技术
太阳能电池是一种清洁能源电池，太阳能电池广泛的应用在生活和生产中。异质结电池是一种重要的太阳能电池，异质结(HeteroJunction with intrinsic Thin layer，简称HJT)结构就是以N型单晶硅衬底为中心，N型单晶硅衬底的两侧分别设置P型非晶硅层和N型非晶硅层，在P型非晶硅层和N型非晶硅层与N型单晶硅衬底之间增加一层本征非晶硅层，采取该工艺措施后，改变了衬底硅片的钝化特性，因而使异质结电池的转换效率提高，使得异质结电池成为非常具有市场竞争力的太阳能电池技术。
但是，由于本征非晶硅层本身对太阳光存在寄生吸收，会影响异质结电池的转换效率，异质结电池的转换效率有待进一步提高。
发明内容
因此，本申请要解决的技术问题在于克服现有技术中异质结电池的转换效率有待进一步提高的问题，从而提供一种异质结电池及其制备方法。
本申请提供一种异质结电池，包括：半导体衬底层；本征半导体复合层，所述本征半导体复合层位于所述半导体衬底层的至少一侧表面，所述本征半导体复合层包括：底层本征层；位于所述底层本征层背向所述半导体衬底层一侧表面的宽带隙本征层，所述宽带隙本征层的带隙大于所述底层本征层的带隙。
可选的，所述本征半导体复合层仅位于所述半导体衬底层的正面一侧；或者，所述本征半导体复合层仅位于所述半导体衬底层的背面一侧；或者，所述本征半导体复合层位于所述半导体衬底层的两侧表面。
可选的，所述宽带隙本征层包括第一子宽带隙本征层至第N子宽带隙本征层，N为大于等于1的整数。
可选的，第n子宽带隙本征层的材料包括掺氧非晶硅、掺碳非晶硅、掺氧纳米晶硅或者掺碳纳米晶硅；n为大于等于1且小于等于N的整数。
可选的，所述底层本征层包括：第一子底层本征层；位于所述第一子底层本征层背向所述半导体衬底层一侧表面的第二子底层本征层；所述第二子底层本征层的缺陷态密 度小于所述第一子底层本征层的缺陷态密度。
可选的，所述第一子底层本征层的厚度与所述第二子底层本征层的厚度的比值为0.15:1～0.35:1。
可选的，所述第一子底层本征层的厚度为0.3nm～0.8nm，所述第二子底层本征层的厚度为1nm～2.5nm。
可选的，位于所述半导体衬底层单侧的所述本征半导体复合层的总厚度为2nm～10nm。
可选的，N为大于等于2的整数，第k子宽带隙本征层位于第k+1子宽带隙本征层和所述半导体衬底层之间；k为大于等于1且小于等于N-1的整数。
可选的，N等于2。
可选的，所述第一子宽带隙本征层的材料包括掺氧非晶硅或掺氧纳米晶硅，第二子宽带隙本征层的材料包括掺碳非晶硅或掺碳纳米晶硅，所述第一子宽带隙本征层中的氧与硅的摩尔比为1:1～1:5，所述第二子宽带隙本征层中的碳与硅的摩尔比为1:1～1:5；
可选的，所述第一子宽带隙本征层的带隙为2.0eV～9eV，第二子宽带隙本征层的带隙为2.0eV～9eV。
可选的，所述第一子宽带隙本征层的材料包括掺碳非晶硅或掺碳纳米晶硅，所述第二子宽带隙本征层的材料包括掺氧非晶硅或掺氧纳米晶硅，所述第一子宽带隙本征层中的碳与硅的摩尔比为1:1～1:5，所述第二子宽带隙本征层中的氧与硅的摩尔比为1:1～1:5；
可选的，所述第一子宽带隙本征层的带隙为2.0eV～9eV，所述第二子宽带隙本征层的带隙为2.0eV～9eV。
可选的，所述第二子宽带隙本征层的厚度与所述第一子宽带隙本征层的厚度的比值为0.5:1～1.5:1；所述第一子宽带隙本征层的厚度与所述底层本征层的厚度的比值为0.5:1～1.5:1。
可选的，所述第二子宽带隙本征层的厚度为1.5nm～4nm；所述第一子宽带隙本征层的厚度为1.5nm～4nm，所述底层本征层的厚度为1.3nm～3.3nm。
可选的，对于位于所述半导体衬底层的正面一侧的本征半导体复合层，所述本征半导体复合层中的所述第k+1子宽带隙本征层的折射率小于所述第k子宽带隙本征层的折射率。
可选的，对于位于所述半导体衬底层的背面一侧的本征半导体复合层，所述本征半导体复合层与所述半导体衬底层之间的价带差为0.6eV～1.2eV。
可选的，N等于1，所述宽带隙本征层的带隙为2.0eV～9eV。
可选的，所述宽带隙本征层的厚度与所述底层本征层的厚度的比值为1:1～3:1。
可选的，所述宽带隙本征层的厚度为2nm～8nm，所述底层本征层的厚度为1.3nm～3.3nm。
本申请还提供一种异质结电池的制备方法，包括如下步骤：提供半导体衬底层；在所述半导体衬底层的至少一侧表面形成本征半导体复合层，形成所述本征半导体复合层的步骤包括：在所述半导体衬底层的至少一侧表面形成底层本征层；在所述底层本征层 背向所述半导体衬底层的一侧表面形成宽带隙本征层，所述宽带隙本征层的带隙大于所述底层本征层的带隙。
可选的，仅在所述半导体衬底层的正面一侧形成所述本征半导体复合层；或者，仅在所述半导体衬底层的背面一侧形成所述本征半导体复合层；或者，在所述半导体衬底层的两侧表面均形成所述本征半导体复合层。
可选的，在所述底层本征层背向所述半导体衬底层的一侧表面形成所述宽带隙本征层的步骤包括：在所述底层本征层背向所述半导体衬底层的一侧表面依次形成第一子宽带隙本征层至第N子宽带隙本征层；N为大于等于1的整数。
可选的，第n子宽带隙本征层的材料包括掺氧非晶硅、掺碳非晶硅、掺碳纳米晶硅或者掺氧纳米晶硅；n为大于等于1且小于等于N的整数。
可选的，N为大于等于2的整数，第k子宽带隙本征层位于第k+1子宽带隙本征层和所述半导体衬底层之间；k为大于等于1且小于等于N-1的整数。
可选的，对于位于所述半导体衬底层的正面一侧的本征半导体复合层，所述本征半导体复合层中的所述第k+1子宽带隙本征层的折射率小于所述第k子宽带隙本征层的折射率。
可选的，对于位于所述半导体衬底层的背面一侧的本征半导体复合层，所述本征半导体复合层与所述半导体衬底层之间的价带差为0.6eV～7.9eV。
可选的，通过化学气相沉积工艺形成所述第n子宽带隙本征层。
可选的，当所述第n子宽带隙本征层的材料包括掺氧非晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和二氧化碳，其中，硅烷与氢气的体积比为1:1～1:10，二氧化碳与硅烷的体积比为1:1～1:5，腔室压强为0.2mBar～1mBar，沉积温度为180℃～240℃，源射频功率密度为150W/m 2～600W/m 2。
可选的，当所述第n子宽带隙本征层的材料包括掺氧纳米晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和二氧化碳，其中，硅烷与氢气的体积比为1:20～1:80，二氧化碳与硅烷的体积比为1:1～1:5，腔室压强为0.5mBar～5mBar，沉积温度为180℃～240℃，源射频功率密度为500W/m 2～2250W/m 2。
可选的，当所述第n子宽带隙本征层的材料包括掺碳非晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和甲烷，其中，硅烷与氢气的体积比为1:1～1:10，甲烷与硅烷的体积比为1:1～1:5，腔室压强为0.2mBar～1mBar，沉积温度为180℃～240℃，源射频功率密度为150W/m 2～600W/m 2。
可选的，当所述第n子宽带隙本征层的材料包括掺碳纳米晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和甲烷，其中，硅烷与氢气的体积比为1:20～1:80，甲烷与硅烷的体积比为1:1～1:5，腔室压强为0.5mBar～5mBar，沉积温度为180℃～240℃，源射频功率密度为500W/m 2～2250W/m 2。
可选的，形成所述底层本征层的步骤包括：在所述半导体衬底层的至少一侧表面形成第一子底层本征层；在所述第一子底层本征层背向所述半导体衬底层的一侧表面形成第二子底层本征层，所述第二子底层本征层的缺陷态密度小于所述第一子底层本征层的 缺陷态密度。
本申请的技术方案具有以下有益效果：
1.本申请提供的异质结电池，宽带隙本征层的带隙大于底层本征层的带隙，宽带隙本征层的带隙较大，当太阳光照射异质结电池时，能量小于宽带隙本征层的带隙的光子不能被寄生吸收，减小本征半导体复合层对太阳光的寄生吸收，从而使得半导体衬底层对太阳光的吸收增多，半导体衬底层产生的光生载流子增多，进而能提高异质结电池的短路电流，能提高异质结电池的转换效率。
2.进一步，第一子底层本征层的缺陷态密度较大，主要起到防止半导体衬底层外延生长的作用，第一子底层本征层的厚度较薄，避免光生载流子在第一子底层本征层中复合过多；第二子底层本征层的缺陷态密度较小且相对较厚，主要起到钝化半导体衬底层的作用，光生载流子在第二子底层本征层中的复合较少，能提高异质结电池的短路电流，同时第二子底层本征层作为第一子底层本征层和宽带隙本征层之间的过渡层，能提高宽带隙本征层和第一底层本征层之间的接触性能。
3.进一步，半导体衬底层的正面一侧的第k+1子宽带隙本征层的折射率小于所述第k子宽带隙本征层的折射率，使得异质结电池正面的本征半导体复合层的折射率具有渐变效果，异质结电池正面的本征半导体复合层具有更好的减反射性能，更多的太阳光进入半导体衬底层而被半导体衬底层吸收，能提高异质结电池的开路电压。
4.进一步，在半导体衬底层的背面一侧的宽带隙本征层中掺入氧原子或者碳原子能够提高半导体衬底层的背面一侧的本征半导体复合层与半导体衬底层之间的价带差，高的价带差对光生载流子中的空穴载流子的累积效应增强，使异质结电池的开路电压更大，能提高半导体衬底层中空穴载流子直接隧穿半导体衬底层的背面一侧的本征半导体复合层的几率，能提高空穴载流子在半导体衬底层的背面一侧的本征半导体复合层内的传输效率，会降低异质结电池的电阻，能提高异质结电池的转换效率。
5.本申请提供的异质结电池的制备方法，宽带隙本征层的带隙较大，当太阳光照射异质结电池时，能量小于宽带隙本征层的带隙的光子不能被寄生吸收，减小本征半导体复合层对太阳光的寄生吸收，从而使得半导体衬底层对太阳光的吸收增多，半导体衬底层产生的光生载流子增多，进而能提高异质结电池的短路电流，能提高异质结电池的转换效率。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例1提供的异质结电池的结构示意图。
图2为本申请实施例2提供的异质结电池的结构示意图。
图3为本申请实施例3提供的异质结电池的结构示意图。
图4为本申请实施例4提供的异质结电池的结构示意图。
图5为本申请一实施例提供的异质结电池的制备方法的流程图。
图6为本申请以实施例4提供的异质结电池为例的制备方法的流程图。
附图标记：
1-半导体衬底层；2-本征半导体复合层；21-底层本征层；211-第一子底层本征层；212-第二子底层本征层；22-宽带隙本征层；2A-正面本征半导体复合层；21A-正面底层本征层；211A-第一子正面底层本征层；212A-第二子正面底层本征层；22A-正面宽带隙本征层；221A-第一子正面宽带隙本征层；222A-第二子正面宽带隙本征层；3-背面本征层；3a-正面本征层；3A-背面本征半导体复合层；31A-背面底层本征层；311A-第一子背面底层本征层；312A-第二子背面底层本征层；32A-背面宽带隙本征层；321A-第一子背面宽带隙本征层；322A-第二子背面宽带隙本征层；4-第一掺杂层；5-第二掺杂层；6-第一透明导电膜；7-第二透明导电膜；8-第一栅线电极；9-第二栅线电极。
具体实施方式
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电学连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
本申请提供一种异质结电池，包括：半导体衬底层；本征半导体复合层，所述本征半导体复合层位于所述半导体衬底层的至少一侧表面，所述本征半导体复合层包括：底层本征层；位于所述底层本征层背向所述半导体衬底层一侧表面的宽带隙本征层，所述宽带隙本征层的带隙大于所述底层本征层的带隙。
宽带隙本征层的带隙较大，当太阳光照射异质结电池时，能量小于宽带隙本征层的带隙的光子不能被寄生吸收，减小本征半导体复合层对太阳光的寄生吸收，从而使得半导体衬底层对太阳光的吸收增多，半导体衬底层产生的光生载流子增多，进而能提高异 质结电池的短路电流，能提高异质结电池的转换效率。
在一个实施例中，所述本征半导体复合层仅位于所述半导体衬底层的正面一侧。在另一个实施例中，所述本征半导体复合层仅位于所述半导体衬底层的背面一侧。在又一个实施例中，所述本征半导体复合层位于所述半导体衬底层的两侧表面。
半导体衬底层包括N型单晶硅衬底，N型单晶硅具有较窄的带隙，带隙通常为1.0eV～1.2eV。
所述宽带隙本征层包括第一子宽带隙本征层至第N子宽带隙本征层，N为大于等于1的整数。
第n子宽带隙本征层的材料包括掺氧非晶硅、掺碳非晶硅、掺氧纳米晶硅或者掺碳纳米晶硅；n为大于等于1且小于等于N的整数。
实施例1
请参考图1，图1中箭头指向表示太阳光的照射方向，本实施例以本征半导体复合层2仅位于所述半导体衬底层1的正面一侧的异质结电池结构为例进行说明。
在此情况下，可选的，所述宽带隙本征层22的带隙为2.0eV～9eV，例如，2.0eV、2.4eV、2.8eV、3.2eV和9eV。可选的，宽带隙本征层22的厚度与所述底层本征层21的厚度的比值为1:1～3:1，例如，1：1、2:1或者3:1。可选的，所述宽带隙本征层22的厚度为2nm～8nm，例如，2nm、5nm、7nm或者8nm，所述底层本征层21的厚度为1.3nm～3.3nm，例如，1.3nm、2nm、3nm或者3.3nm。
所述底层本征层21包括：第一子底层本征层211；位于所述第一子底层本征层211背向所述半导体衬底层1一侧表面的第二子底层本征层212；所述第二子底层本征层212的缺陷态密度小于所述第一子底层本征层211的缺陷态密度，也就是第二子底层本征层212中的亚甲硅烷基(-SiH 2-)的占比小于第一子底层本征层211中的亚甲硅烷基(-SiH 2-)的占比。第一子底层本征层211的缺陷态密度较大，主要起到防止半导体衬底层1外延生长的作用，第一子底层本征层211的厚度较薄，避免光生载流子在第一子底层本征层211中复合过多；第二子底层本征层212的缺陷态密度较小且相对较厚，主要起到钝化半导体衬底层1的作用，光生载流子在第二子底层本征层212中的复合较少，能提高异质结电池的短路电流，同时第二子底层本征层212作为第一子底层本征层211和宽带隙本征层22之间的过渡层，能提高宽带隙本征层22和底层本征层21之间的接触性能。
在本实施例中，所述第一子底层本征层211的厚度与所述第二子底层本征层212的厚度之比为0.15:1～0.35:1，例如，0.15:1、0.2:1、0.25:1、0.3:1或者0.35:1。
在本实施例中，所述第一子底层本征层211的厚度为0.3nm～0.8nm，例如，0.3nm、0.5nm、0.7nm或者0.8nm，第一子底层本征层211的缺陷态密度较大，第一子底层本征层211主要起到防止半导体衬底层1外延生长的作用，如果第一子底层本征层211太薄，难以达到防止半导体衬底层1外延生长的作用，如果第一子底层本征层211太厚，光生载流子在第一子底层本征层211中的复合过多，会降低异质结电池的转换效率。所述第二子底层本征层212的厚度为1nm～2.5nm，例如，1nm、1.5nm、2nm或者2.5nm，第二 子底层本征层212主要起到钝化半导体衬底层1以及载流子传输的作用，如果第二子底层本征层212太薄，会降低第二子底层本征层212对半导体衬底层1的钝化效果，如果第二子底层本征层212太厚，第二子底层本征层212对太阳光的寄生吸收较多，自身的体电阻较大，载流子在第二子底层本征层212中的传输效率较差，会降低异质结电池的短路电流。
可选的，第一子底层本征层211的厚度为0.5nm，第二子底层本征层212的厚度为2nm，宽带隙本征层22的厚度为5nm，在此情况下，本征半导体复合层2对半导体衬底层1具有较好的钝化性能，能够降低半导体衬底层1表面的光生载流子的复合，本征半导体复合层2的体电阻较小，本征半导体复合层2对太阳光的寄生吸收较少，同时第二子底层本征层212作为第一子底层本征层211和宽带隙本征层22之间的过渡层，能提高宽带隙本征层22和底层本征层21之间的接触性能。
位于所述半导体衬底层1单侧的所述本征半导体复合层2的总厚度为2nm～10nm，例如，2nm、5nm、7nm、9nm或者10nm。本征半导体复合层2的厚度较薄，对太阳光的寄生吸收少，能提高异质结电池的短路电流，能提高异质结电池的转换效率。
所述宽带隙本征层22包括第一子宽带隙本征层至第N子宽带隙本征层，N为大于等于1的整数。
在一种情况下，如图1所示，宽带隙本征层22为单层结构，也就是N等于1。
在另一种情况下，宽带隙本征层22为多层结构，N为大于等于2的整数，第k子宽带隙本征层位于第k+1子宽带隙本征层和所述半导体衬底层之间；k为大于等于1且小于等于N-1的整数。
第n子宽带隙本征层的材料包括掺氧非晶硅、掺碳非晶硅、掺氧纳米晶硅或者掺碳纳米晶硅；n为大于等于1且小于等于N的整数。
在一种具体的实施例中，N等于2，宽带隙本征层22包括第一子宽带隙本征层和第二子宽带隙本征层，第二子宽带隙本征层位于第一子宽带隙背向半导体衬底层1的一侧表面。
在一种情况下，所述第一子宽带隙本征层的材料包括掺氧非晶硅或掺氧纳米晶硅，第二子宽带隙本征层的材料包括掺碳非晶硅或掺碳纳米晶硅；第一子宽带隙本征层中的氧与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5，第二子宽带隙本征层中的碳与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5。由于第一子宽带隙本征层中掺有氧原子，第一子宽带隙本征层的带隙较宽，第一子宽带隙本征层的带隙为2.0eV～9eV，例如，2.0eV、2.4eV、2.6eV、3.2eV或9eV；由于第二子宽带隙本征层中掺有碳原子，第二子宽带隙本征层的带隙较宽，第二子宽带隙本征层的带隙为2.0eV～9eV，例如，2.0eV、2.5eV、2.8eV、3.2eV或者9eV。
在另一种情况下，所述第一子宽带隙本征层的材料包括掺碳非晶硅或掺碳纳米晶硅，所述第二子宽带隙本征层的材料包括掺氧非晶硅或掺氧纳米晶硅；第一子宽带隙本征层中的碳与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5，第二子宽带隙本征层中氧与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5。在此情况下，所述 第一子宽带隙本征层的带隙为2.3eV～2.8eV，例如，2.3eV、2.5eV、2.7eV或者2.8eV，所述第二子宽带隙本征层的带隙为2.0eV～2.6eV，例如，2.0eV、2.2eV、2.6eV、3.2eV或者9eV。
所述第二子宽带隙本征层的厚度与所述第一子宽带隙本征层的厚度的比值为0.5:1～1.5:1，例如，0.5:1、0.8:1、1:1、1.2:1或者1.5:1；所述第一子宽带隙本征层的厚度与所述底层本征层的厚度的比值为0.5:1～1.5:1，例如0.5:1、0.8:1、1：1、1.2：1、1.5:1或者1.5:1。
所述第二子宽带隙本征层的厚度为1.5nm～4nm，例如，1.5nm、2nm、3nm或者4nm；所述第一子宽带隙本征层的厚度为1.5nm～4nm，例如，1.5nm、2nm、3nm或者4nm；所述底层本征层的厚度为1.3nm～3.3nm，例如，1.3nm、2nm、3nm或者3.3nm。
对于位于所述半导体衬底层1的正面一侧的本征半导体复合层2，所述本征半导体复合层2中的所述第k+1子宽带隙本征层的折射率小于所述第k子宽带隙本征层的折射率。具体的，第二子宽带隙本征层的折射率小于第一子宽带隙本征层的折射率，使得异质结电池正面的本征半导体复合层2的折射率具有渐变效果，异质结电池正面的本征半导体复合层2具有更好的减反射性能，更多的太阳光进入半导体衬底层1而被半导体衬底层1吸收，能提高异质结电池的开路电压。
请继续参考图1，异质结电池还包括：位于所述半导体衬底层1背向所述本征半导体复合层2一侧表面的背面本征层3。
所述背面本征层3可以是单层结构也可以是多层结构，对此不做限定。
请继续参考图1，异质结电池还包括：位于所述本征半导体复合层2背向半导体衬底层1一侧表面的第一掺杂层4；位于第一掺杂层4背向本征半导体复合层2一侧表面的第一透明导电膜6；位于第一透明导电膜6背向本征半导体复合层2一侧表面的第一栅线电极8；位于背面本征层3背向半导体衬底层1一侧表面的第二掺杂层5；位于第二掺杂层5背向背面本征层3一侧表面的第二透明导电膜7；位于第二透明导电膜7背向第二掺杂层5一侧表面的第二栅线电极9，需要说明的是，第一掺杂层4的导电类型与第二掺杂层5的导电类型相反。
实施例2
请参考图2，本实施例以本征半导体复合层2仅位于所述半导体衬底层1的背面一侧的异质结电池结构为例进行说明。
对于位于所述半导体衬底层1的背面一侧的本征半导体复合层2，所述本征半导体复合层2与所述半导体衬底层1之间的价带差为0.6eV～7.9eV，例如0.6eV、1.0eV、2.1eV或者7.9eV。
在宽带隙本征层22中掺入氧原子或者碳原子能够提高半导体衬底层1的背面一侧的本征半导体复合层2与半导体衬底层1之间的价带差，高的价带差对光生载流子中的空穴载流子的累积效应增强，使异质结电池的开路电压更大，能提高半导体衬底层1中空穴载流子直接隧穿半导体衬底层1的背面一侧的本征半导体复合层2的几率，能提高空 穴载流子在半导体衬底层1的背面一侧的本征半导体复合层2内的传输效率，会降低异质结电池的电阻，能提高异质结电池的转换效率。
所述宽带隙本征层22包括第一子宽带隙本征层至第N子宽带隙本征层，N为大于等于1的整数。
在一种情况下，如图2所示，宽带隙本征层22为单层结构，也就是N等于1。
在另一种情况下，宽带隙本征层22为多层结构，N为大于等于2的整数，第k子宽带隙本征层位于第k+1子宽带隙本征层和所述半导体衬底层之间；k为大于等于1且小于等于N-1的整数。
第n子宽带隙本征层的材料包括掺氧非晶硅、掺碳非晶硅、掺氧纳米晶硅或者掺碳纳米晶硅；n为大于等于1且小于等于N的整数。
在一种具体的实施例中，N等于2，宽带隙本征层22包括第一子宽带隙本征层和第二子宽带隙本征层，第二子宽带隙本征层位于第一子宽带隙背向半导体衬底层1的一侧。
请继续参考图2，异质结电池还包括：位于所述半导体衬底层1背向所述本征半导体复合层2一侧表面的正面本征层3a。
所述正面本征层3a可以是单层结构也可以是多层结构。
本实施例与实施例1相同的结构部分，参照实施例1相关描述，此处不再详述。
实施例3
请参考图3，本实施例以本征半导体复合层位于所述半导体衬底层1的两侧表面、宽带隙本征层为单层结构(也就是N等于1)的异质结电池结构为例进行说明。
本征半导体复合层2包括位于所述半导体衬底层1的正面一侧的正面本征半导体复合层2A以及位于所述半导体衬底层1的背面一侧的背面本征半导体复合层3A。
正面本征半导体复合层2A包括：正面底层本征层21A；位于所述正面底层本征层21A背向所述半导体衬底层1一侧表面的正面宽带隙本征层22A，所述正面宽带隙本征层22A的带隙大于所述正面底层本征层21A的带隙。
背面本征半导体复合层3A包括：背面底层本征层31A；位于所述背面底层本征层31A背向所述半导体衬底层1一侧表面的背面宽带隙本征层32A，所述背面宽带隙本征层32A的带隙大于所述背面底层本征层31A的带隙。
在本实施例中，底层本征层包括位于所述半导体衬底层1的正面一侧的正面底层本征层21A以及位于所述半导体衬底层1的背面一侧的背面底层本征层31A。正面底层本征层21A包括：位于半导体衬底层1的正面一侧的第一子正面底层本征层211A；位于所述第一子正面底层本征层211A背向所述半导体衬底层1一侧表面的第二子正面底层本征层212A，所述第二子正面底层本征层212A的缺陷态密度小于所述第一子正面底层本征层211A的缺陷态密度。背面底层本征层31A包括：位于半导体衬底层1的背面一侧的第一子背面底层本征层311A；位于所述第一子背面底层本征层311A背向所述半导体衬底层1一侧表面的第二子背面底层本征层312A，所述第二子背面底层本征层312A的缺陷态密度小于所述第一子背面底层本征层311A的缺陷态密度。
第一子正面底层本征层211A的厚度与所述第二子正面底层本征层212A的厚度之比为0.15:1～0.35:1，例如，0.15:1、0.2:1、0.25:1、0.3:1或者0.35:1。在本实施例中，所述第一子正面底层本征层211A的厚度为0.3nm～0.8nm，例如，0.3nm、0.5nm、0.7nm或者0.8nm，所述第二子正面底层本征层212A的厚度为1nm～2.5nm，例如，1nm、1.5nm、2nm或者2.5nm。
正面本征半导体复合层2A的总厚度为2nm～10nm，例如，2nm、5nm、7nm、9nm或者10nm。背面本征半导体复合层3A。的总厚度为5nm～10nm，例如，5nm、7nm、9nm或者10nm。
正面宽带隙本征层22A的材料包括掺氧非晶硅、掺碳非晶硅、掺氧纳米晶硅或者掺碳纳米晶硅。背面宽带隙本征层32A的材料包括掺氧非晶硅、掺碳非晶硅、掺氧纳米晶硅或者掺碳纳米晶硅。
在一个具体的实施例中，所述正面宽带隙本征层22A的材料包括掺氧非晶硅或掺氧纳米晶硅，正面宽带隙本征层22A中的氧与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5。由于正面宽带隙本征层22A中掺有氧原子，正面宽带隙本征层22A的带隙较宽，正面宽带隙本征层22A的带隙为2.0eV～2.6eV，例如，2.0eV、2.2eV、2.4eV或者2.6eV。
在另一个具体的实施例中，正面宽带隙本征层22A的材料包括掺碳非晶硅或掺碳纳米晶硅。正面宽带隙本征层22A中的碳与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5。由于正面宽带隙本征层22A中掺有碳原子，正面宽带隙本征层22A的带隙较宽，正面宽带隙本征层22A的带隙为2.3eV～2.8eV，例如，2.3eV、2.5eV、2.7eV或者2.8eV。
在一个具体的实施例中，背面宽带隙本征层32A的材料包括掺碳非晶硅或掺碳纳米晶硅，背面宽带隙本征层32A中的碳与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5。背面宽带隙本征层32A的带隙为2.3eV～2.8eV，例如，2.3eV、2.5eV、2.7eV或者2.8eV。
在另一个具体的实施例中，背面宽带隙本征层32A的材料包括掺氧非晶硅或掺氧纳米晶硅。背面宽带隙本征层32A中氧与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5。所述背面宽带隙本征层32A的带隙为2.0eV～9eV，例如，2.0eV、2.4eV、2.6eV、3.2eV或者9eV。
所述正面宽带隙本征层22A的厚度与所述正面底层本征层的厚度的比值为1:1～3:1。所述正面宽带隙本征层22A的厚度为2nm～8nm，所述正面底层本征层的厚度为1.3nm～3.3nm。
所述背面宽带隙本征层32A的厚度与所述背面底层本征层的厚度的比值为1:1～3:1。所述背面宽带隙本征层32A的厚度为2nm～8nm，所述背面底层本征层的厚度为1.3nm～3.3nm。
本实施例中，还包括：位于正面本征半导体复合层2A背向半导体衬底层1一侧表面的第一掺杂层4；位于第一掺杂层4背向半导体衬底层1一侧表面的第一透明导电膜6； 位于第一透明导电膜6背向半导体衬底层1一侧表面的第一栅线电极8；位于背面本征半导体复合层3A背向半导体衬底层1一侧表面的第二掺杂层5；位于第二掺杂层5背向半导体衬底层1一侧表面的第二透明导电膜7；位于第二透明导电膜7背向半导体衬底层1一侧表面的第二栅线电极9，需要说明的是，第一掺杂层4的导电类型与第二掺杂层5的导电类型相反。
本实施例与实施例1相同的结构部分，参照实施例1相关描述，此处不再详述。
实施例4
本实施例中的异质结电池结构，本征半导体复合层位于所述半导体衬底层1的两侧表面，宽带隙本征层为叠层结构，宽带隙本征层包括第一子宽带隙本征层至第N子宽带隙本征层，N为大于等于2的整数，第k子宽带隙本征层位于第k+1子宽带隙本征层和所述半导体衬底层1之间；k为大于等于1且小于等于N-1的整数。
对于位于所述半导体衬底层1的正面一侧的本征半导体复合层2，所述本征半导体复合层2中的所述第k+1子宽带隙本征层的折射率小于所述第k子宽带隙本征层的折射率，使得异质结电池正面的本征半导体复合层2的折射率具有渐变效果，异质结电池正面的本征半导体复合层2具有更好的减反射性能，更多的太阳光进入半导体衬底层1而被半导体衬底层1吸收，能提高异质结电池的开路电压。
对于位于所述半导体衬底层1的背面一侧的本征半导体复合层2，所述本征半导体复合层2与所述半导体衬底层1之间的价带差为0.6eV～7.9eV。
请参考图4，图4中以N等于2为例进行说明。本征半导体复合层2包括位于所述半导体衬底层1的正面一侧的正面本征半导体复合层2A以及位于所述半导体衬底层1的背面一侧的背面本征半导体复合层3A。
正面本征半导体复合层2A包括：正面底层本征层21A；位于所述正面底层本征层21A背向所述半导体衬底层1一侧表面的正面宽带隙本征层22A，正面宽带隙本征层22A的带隙大于所述正面底层本征层21A的带隙。关于正面底层本征层21A的描述请参照实施例3对应的内容，此处不再详述。
所述正面宽带隙本征层22A包括第一子正面宽带隙本征层221A以及位于第一子正面宽带隙本征层221A背向正面底层本征层21A一侧的第二子正面宽带隙本征层222A。
背面本征半导体复合层3A包括：背面底层本征层31A；位于所述背面底层本征层31A背向所述半导体衬底层1一侧表面的背面宽带隙本征层32A，背面宽带隙本征层32A的带隙大于所述背面底层本征层31A的带隙。关于背面底层本征层31A的描述请参照实施例3对应的内容，此处不再详述。
所述背面宽带隙本征层32A包括第一子背面宽带隙本征层321A以及位于第一子背面宽带隙本征层321A背向背面底层本征层31A一侧的第二子背面宽带隙本征层322A。
在本实施例中，所述第一子正面宽带隙本征层221A的材料包括掺氧非晶硅或掺氧纳米晶硅，第二子正面宽带隙本征层222A的材料包括掺碳非晶硅或掺碳纳米晶硅；第一子正面宽带隙本征层221A中的氧与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或 者1:5，第二子正面宽带隙本征层222A中的碳与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5。由于第一子正面宽带隙本征层221A中掺有氧原子，第一子正面宽带隙本征层221A的带隙较宽，第一子正面宽带隙本征层221A的带隙为2.0eV～9eV，例如，2.0eV、2.4eV、2.6eV、3.2eV或者9eV；由于第二子正面宽带隙本征层222A中掺有碳原子，第二子正面宽带隙本征层222A的带隙较宽，第二子正面宽带隙本征层222A的带隙为2.0eV～9eV，例如，2.0eV、2.5eV、2.8eV、3.2eV或者9eV。
在其他实施例中，所述第一子正面宽带隙本征层221A的材料包括掺碳非晶硅或掺碳纳米晶硅，所述第二子正面宽带隙本征层222A的材料包括掺氧非晶硅或掺氧纳米晶硅；第一子正面宽带隙本征层221A中的碳与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5，第二子正面宽带隙本征层222A中氧与硅的摩尔比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5。在此情况下，所述第一子正面宽带隙本征层221A的带隙为2.0eV～9eV，例如，2.0eV、2.5eV、2.8eV、3.2eV或者9eV，所述第二子正面宽带隙本征层222A的带隙为2.0eV～9eV，例如，2.0eV、2.4eV、2.6eV、3.2eV或者9eV。
所述第二子正面宽带隙本征层222A的厚度与所述第一子正面宽带隙本征层221A的厚度的比值为0.5：1～1.5:1，例如，0.5:1、0.8：1、1:1、1.2:1或者1.5:1；所述第一子正面宽带隙本征层221A的厚度与所述正面底层本征层21A的厚度的比值为0.5:1～1.5：1，例如0.5:1、0.8:1、1：1、1.2:1、1.5:1或者1.5:1。
所述第二子正面宽带隙本征层222A的厚度为1.5nm～4nm，例如，1.5nm、2nm、3nm或者4nm；所述第一子正面宽带隙本征层221A的厚度为1.5nm～4nm，例如，1.5nm、2nm、3nm或者4nm；所述正面底层本征层21A的厚度为1.3nm～3.3nm，例如，1.3nm、2nm、3nm或者3.3nm。
第一子背面宽带隙本征层321A的材料、厚度、带隙参照第一子正面宽带隙本征层221A；第二子背面宽带隙本征层322A的材料、厚度、带隙参照第二子正面宽带隙本征层222A，此处不再详述。
需要说明的是，在其他实施例中，还可以是：正面宽带隙本征层22A为单层结构、第二宽带隙本征层32A为叠层结构或者正面宽带隙本征层22A为叠层结构、第二宽带隙本征层32A为单层结构。
本实施例与实施例3相同的结构部分，参照实施例3相关描述，此处不再详述。
实施例5
本实施例提供一种异质结电池的制备方法，请参考图5，包括如下步骤：
步骤S1：提供半导体衬底层1。
步骤S2：在所述半导体衬底层1的至少一侧表面形成本征半导体复合层2，形成所述本征半导体复合层2的步骤包括：在所述半导体衬底层1的至少一侧表面形成底层本征层；在所述底层本征层背向所述半导体衬底层1的一侧表面形成宽带隙本征层，所述宽带隙本征层的带隙大于所述底层本征层1的带隙。
形成所述本征半导体复合层2的位置包括：仅在所述半导体衬底层1的正面一侧形 成所述本征半导体复合层2；或者，仅在所述半导体衬底层1的背面一侧形成所述本征半导体复合层2；或者，在所述半导体衬底层1的两侧表面均形成所述本征半导体复合层2。
在所述底层本征层背向所述半导体衬底层1的一侧表面形成所述宽带隙本征层的步骤包括：在所述底层本征层背向所述半导体衬底层1的一侧表面依次形成第一子宽带隙本征层至第N子宽带隙本征层；N为大于等于1的整数。
可选的，第n子宽带隙本征层的材料包括掺氧非晶硅、掺碳非晶硅、掺碳纳米晶硅或者掺氧纳米晶硅；n为大于等于1且小于等于N的整数。
可选的，N为大于等于2的整数，第k子宽带隙本征层位于第k+1子宽带隙本征层和所述半导体衬底层之间；k为大于等于1且小于等于N-1的整数；
可选的，对于位于所述半导体衬底层1的正面一侧的本征半导体复合层2，所述本征半导体复合层2中的所述第k+1子宽带隙本征层的折射率小于所述第k子宽带隙本征层的折射率。
可选的，对于位于所述半导体衬底层1的背面一侧的本征半导体复合层2，所述本征半导体复合层2与所述半导体衬底层1之间的价带差为0.6eV～7.9eV，例如0.6eV、1.0eV、1.2eV、2.1eV或者7.9eV。
当所述第n子宽带隙本征层的材料包括掺氧非晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和二氧化碳，其中，硅烷与氢气的体积比为1:1～1:10，例如，1:2、1:4、1:6、1:8或者1:10；二氧化碳与硅烷的体积比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5；腔室压强为0.2mBar～1mBar，例如，0.2mBar、0.4mBar、0.6mBar、0.8mBar或者1mBar；沉积温度为180℃～240℃，例如，180℃、200℃、220℃或者240℃；源射频功率密度为150W/m 2～600W/m 2，例如，150W/m 2、250W/m 2、350W/m 2、450W/m 2、550W/m 2或者600W/m 2。
当所述第n子宽带隙本征层的材料包括掺氧纳米晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和二氧化碳，其中，硅烷与氢气的体积比为1:20～1:80，例如，1:20、1:40、1:60或者1:80；二氧化碳与硅烷的体积比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5；腔室压强为0.5mBar～5mBar
Figure PCTCN2022101226-appb-000001
例如，0.5mBar、1mBar、3mBar、4mBar或者5mBar；沉积温度为180℃～240℃，例如，180℃、200℃、220℃或者240℃；源射频功率密度为500W/m 2～2250W/m 2，例如，500W/m 2、1000W/m 2、1500W/m 2、2000W/m 2或者2250W/m 2。
当所述第n子宽带隙本征层的材料包括掺碳非晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和甲烷，其中，硅烷与氢气的体积比为1:1～1:10，例如，1:2、1:4、1:6、1:8或者1:10；甲烷与硅烷的体积比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5；腔室压强为0.2mBar～1mBar
Figure PCTCN2022101226-appb-000002
例如，0.2mBar、0.4mBar、0.6mBar、0.8mBar或者1mBar；沉积温度为180℃～240℃，例如，180℃、200℃、220℃或者240℃；源射频功率密度为150W/m 2～600W/m 2，例如，150W/m 2、250W/m 2、350W/m 2、450W/m 2、550W/m 2或者600W/m 2。
当所述第n子宽带隙本征层的材料包括掺碳纳米晶硅时，形成所述第n子宽带隙本 征层的工艺参数包括：采用的气体包括硅烷、氢气和甲烷，其中，硅烷与氢气的体积比为1:20～1:80，例如，1:20、1:40、1:60或者1:80；甲烷与硅烷的体积比为1:1～1:5，例如，1:1、1:2、1:3、1:4或者1:5；腔室压强为0.5mBar～5mBar
Figure PCTCN2022101226-appb-000003
例如，0.5mBar、1mBar、3mBar、4mBar或者5mBar；沉积温度为180℃～240℃，例如，180℃、200℃、220℃或者240℃；源射频功率密度为500W/m 2～2250W/m 2，，例如，500W/m 2、1000W/m 2、1500W/m 2、2000W/m 2或者2250W/m 2。
形成底层本征层的步骤包括：在所述半导体衬底层1的至少一侧表面形成第一子底层本征层211；在所述第一子底层本征层211背向所述半导体衬底层1的一侧表面形成第二子底层本征层212，所述第二子底层本征层212的缺陷态密度小于所述第一子底层本征层211的缺陷态密度。
请参考图6，以实施例4提供的异质结电池为例，也就是以正面本征半导体复合层2A中包含了第一子正面宽带隙本征层221A和第二子正面宽带隙本征层222A的叠层结构、背面本征半导体复合层3A中包含了第一子背面宽带隙本征层321A和第二子背面宽带隙本征层322A的叠层结构作为示例，对异质结电池的制备方法做详细的说明：
步骤A1：提供半导体衬底层。
半导体衬底层包括N型单晶硅衬底。
步骤A2：对半导体衬底层1进行制绒和清洗处理。
对半导体衬底层进行制绒以在半导体衬底层1的表面形成陷光结构，减少太阳光的反射，制绒处理之后，对半导体衬底层1进行清洗以去除半导体衬底层1的表面的氧化层和杂质。
步骤A3：在半导体衬底层1的一侧表面通过化学气相沉积工艺依次形成第一子正面底层本征层211A、第二子正面底层本征层212A、第一子正面宽带隙本征层221A、第二子正面宽带隙本征层222A和第一掺杂层。
形成第一子正面宽带隙本征层221A和第二子正面宽带隙本征层222A的工艺参数参照前述描述。
步骤A4：在半导体衬底层1的另一侧表面通过化学气相沉积工艺依次形成第一子背面底层本征层311A、第二子背面底层本征层312A、第一子背面宽带隙本征层321A、第二子背面宽带隙本征层322A和第二掺杂层。
形成第一子背面宽带隙本征层321A和第二子背面宽带隙本征层322A的工艺参数参照前述描述。
需要说明的是，在其他实施例中，也可以是形成第二子正面宽带隙本征层222A和第二子背面宽带隙本征层322A之后，再形成第一掺杂层和第二掺杂层。
步骤A5：通过物理气相沉积工艺在第一掺杂层的表面形成第一透明导电膜6、在第二掺杂层的表面形成第二透明导电膜7。
非晶硅结构呈无序结构，电子与空穴迁徙率较低，且横向导电性较差，不利于光生载流子的收集，第一透明导电膜6和第二透明导电膜7用于收集载流子并向电极传输。
步骤A6：通过丝网印刷工艺在第一透明导电膜的表面形成第一栅线电极8
Figure PCTCN2022101226-appb-000004
在第二 透明导电膜7的表面形成第二栅线电极9。
第一栅线电极8用于收集由第一透明导电膜6传输过来的电流，第二栅线电极9用于收集由第二透明导电膜7传输过来的电流。
步骤A7：对第一栅线电极8和第二栅线电极9进行固化和光注入退火处理。
在一定的温度下，对异质结电池的表面进行一定时间的强光照射，以提高异质结电池的转换效率。
本实施例提供的异质结电池的制备方法，宽带隙本征层的带隙较大，当太阳光照射异质结电池时，能量小于宽带隙本征层的带隙的光子不能被寄生吸收，减小本征半导体复合层对太阳光的寄生吸收，从而使得半导体衬底层对太阳光的吸收增多，半导体衬底层产生的光生载流子增多，进而能提高异质结电池的短路电流，能提高异质结电池的转换效率。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。

Claims (10)

  1. 一种异质结电池，其特征在于，包括：
    半导体衬底层；
    本征半导体复合层，所述本征半导体复合层位于所述半导体衬底层的至少一侧表面，所述本征半导体复合层包括：底层本征层；位于所述底层本征层背向所述半导体衬底层一侧表面的宽带隙本征层，所述宽带隙本征层的带隙大于所述底层本征层的带隙。
  2. 根据权利要求1所述的异质结电池，其特征在于，所述本征半导体复合层仅位于所述半导体衬底层的正面一侧；或者，所述本征半导体复合层仅位于所述半导体衬底层的背面一侧；或者，所述本征半导体复合层位于所述半导体衬底层的两侧表面。
  3. 根据权利要求2所述的异质结电池，其特征在于，所述宽带隙本征层包括第一子宽带隙本征层至第N子宽带隙本征层，N为大于等于1的整数；
    优选的，第n子宽带隙本征层的材料包括掺氧非晶硅、掺碳非晶硅、掺氧纳米晶硅或者掺碳纳米晶硅；n为大于等于1且小于等于N的整数；
    优选的，所述底层本征层包括：第一子底层本征层；位于所述第一子底层本征层背向所述半导体衬底层一侧表面的第二子底层本征层；所述第二子底层本征层的缺陷态密度小于所述第一子底层本征层的缺陷态密度；
    优选的，所述第一子底层本征层的厚度与所述第二子底层本征层的厚度的比值为0.15:1～0.35:1；
    优选的，所述第一子底层本征层的厚度为0.3nm～0.8nm，所述第二子底层本征层的厚度为1nm～2.5nm；
    优选的，位于所述半导体衬底层单侧的所述本征半导体复合层的总厚度为2nm～10nm。
  4. 根据权利要求3所述的异质结电池，其特征在于，N为大于等于2的整数，第k子宽带隙本征层位于第k+1子宽带隙本征层和所述半导体衬底层之间；k为大于等于1且小于等于N-1的整数；
    优选的，N等于2；
    优选的，所述第一子宽带隙本征层的材料包括掺氧非晶硅或掺氧纳米晶硅，第二子宽带隙本征层的材料包括掺碳非晶硅或掺碳纳米晶硅，所述第一子宽带隙本征层中的氧与硅的摩尔比为1:1～1:5，所述第二子宽带隙本征层中的碳与硅的摩尔比为1:1～1:5；优选的，所述第一子宽带隙本征层的带隙为2.0eV～9eV，第二子宽带隙本征层的带隙为2.0eV～9eV；
    优选的，所述第一子宽带隙本征层的材料包括掺碳非晶硅或掺碳纳米晶硅，所述第 二子宽带隙本征层的材料包括掺氧非晶硅或掺氧纳米晶硅，所述第一子宽带隙本征层中的碳与硅的摩尔比为1:1～1:5，所述第二子宽带隙本征层中的氧与硅的摩尔比为1:1～1:5；优选的，所述第一子宽带隙本征层的带隙为2.0eV～9eV
    Figure PCTCN2022101226-appb-100001
    所述第二子宽带隙本征层的带隙为2.0eV～9eV；
    优选的，所述第二子宽带隙本征层的厚度与所述第一子宽带隙本征层的厚度的比值为0.5:1～1.5:1；所述第一子宽带隙本征层的厚度与所述底层本征层的厚度的比值为0.5:1～1.5:1；
    优选的，所述第二子宽带隙本征层的厚度为1.5nm～4nm；所述第一子宽带隙本征层的厚度为1.5nm～4nm，所述底层本征层的厚度为1.3nm～3.3nm；
    优选的，对于位于所述半导体衬底层的正面一侧的本征半导体复合层，所述本征半导体复合层中的所述第k+1子宽带隙本征层的折射率小于所述第k子宽带隙本征层的折射率；
    优选的，对于位于所述半导体衬底层的背面一侧的本征半导体复合层，所述本征半导体复合层与所述半导体衬底层之间的价带差为0.6eV～7.9eV。
  5. 根据权利要求1所述的异质结电池，其特征在于，N等于1，所述宽带隙本征层的带隙为2.0eV～9eV；
    优选的，所述宽带隙本征层的厚度与所述底层本征层的厚度的比值为1:1～3:1；
    优选的，所述宽带隙本征层的厚度为2nm～8nm，所述底层本征层的厚度为1.3nm～3.3nm。
  6. 一种异质结电池的制备方法，其特征在于，包括如下步骤：
    提供半导体衬底层；
    在所述半导体衬底层的至少一侧表面形成本征半导体复合层，形成所述本征半导体复合层的步骤包括：在所述半导体衬底层的至少一侧表面形成底层本征层；在所述底层本征层背向所述半导体衬底层的一侧表面形成宽带隙本征层，所述宽带隙本征层的带隙大于所述底层本征层的带隙。
  7. 根据权利要求6所述的异质结电池的制备方法，其特征在于，仅在所述半导体衬底层的正面一侧形成所述本征半导体复合层；或者，仅在所述半导体衬底层的背面一侧形成所述本征半导体复合层；或者，在所述半导体衬底层的两侧表面均形成所述本征半导体复合层。
  8. 根据权利要求7所述的异质结电池的制备方法，其特征在于，在所述底层本征层背向所述半导体衬底层的一侧表面形成所述宽带隙本征层的步骤包括：在所述底层本征 层背向所述半导体衬底层的一侧表面依次形成第一子宽带隙本征层至第N子宽带隙本征层；N为大于等于1的整数；
    优选的，第n子宽带隙本征层的材料包括掺氧非晶硅、掺碳非晶硅、掺碳纳米晶硅或者掺氧纳米晶硅；n为大于等于1且小于等于N的整数；
    优选的，N为大于等于2的整数，第k子宽带隙本征层位于第k+1子宽带隙本征层和所述半导体衬底层之间；k为大于等于1且小于等于N-1的整数；
    优选的，对于位于所述半导体衬底层的正面一侧的本征半导体复合层，所述本征半导体复合层中的所述第k+1子宽带隙本征层的折射率小于所述第k子宽带隙本征层的折射率；
    优选的，对于位于所述半导体衬底层的背面一侧的本征半导体复合层，所述本征半导体复合层与所述半导体衬底层之间的价带差为0.6eV～7.9eV。
  9. 根据权利要求8所述的异质结电池的制备方法，其特征在于，通过化学气相沉积工艺形成所述第n子宽带隙本征层；
    优选的，当所述第n子宽带隙本征层的材料包括掺氧非晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和二氧化碳，其中，硅烷与氢气的体积比为1:1～1:10，二氧化碳与硅烷的体积比为1:1～1:5，腔室压强为0.2mBar～1mBar，沉积温度为180℃～240℃，源射频功率密度为150W/m 2～600W/m 2；
    优选的，当所述第n子宽带隙本征层的材料包括掺氧纳米晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和二氧化碳，其中，硅烷与氢气的体积比为1:20～1:80，二氧化碳与硅烷的体积比为1:1～1:5，腔室压强为0.5mBar～5mBar，沉积温度为180℃～240℃，源射频功率密度为500W/m 2～2250W/m 2；
    优选的，当所述第n子宽带隙本征层的材料包括掺碳非晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和甲烷，其中，硅烷与氢气的体积比为1:1～1:10，甲烷与硅烷的体积比为1:1～1:5，腔室压强为0.2mBar～1mBar，沉积温度为180℃～240℃，源射频功率密度为150W/m 2～600W/m 2；
    优选的，当所述第n子宽带隙本征层的材料包括掺碳纳米晶硅时，形成所述第n子宽带隙本征层的工艺参数包括：采用的气体包括硅烷、氢气和甲烷，其中，硅烷与氢气的体积比为1:20～1:80，甲烷与硅烷的体积比为1:1～1:5，腔室压强为0.5mBar～5mBar，沉积温度为180℃～240℃，源射频功率密度为500W/m 2～2250W/m 2。
  10. 根据权利要求6所述的异质结电池的制备方法，其特征在于，形成所述底层本征层的步骤包括：在所述半导体衬底层的至少一侧表面形成第一子底层本征层；在所述第一子底层本征层背向所述半导体衬底层的一侧表面形成第二子底层本征层，所述第二子底层本征层的缺陷态密度小于所述第一子底层本征层的缺陷态密度。
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