WO2023005292A1 - 芯片的静电保护电路 - Google Patents

芯片的静电保护电路 Download PDF

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Publication number
WO2023005292A1
WO2023005292A1 PCT/CN2022/088843 CN2022088843W WO2023005292A1 WO 2023005292 A1 WO2023005292 A1 WO 2023005292A1 CN 2022088843 W CN2022088843 W CN 2022088843W WO 2023005292 A1 WO2023005292 A1 WO 2023005292A1
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Prior art keywords
voltage dividing
transistor
terminal
switch
control
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PCT/CN2022/088843
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English (en)
French (fr)
Inventor
朱玲
田凯
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长鑫存储技术有限公司
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Priority to US17/810,900 priority Critical patent/US20230023642A1/en
Publication of WO2023005292A1 publication Critical patent/WO2023005292A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers

Definitions

  • the present disclosure relates to the technical field of integrated circuits, in particular to an electrostatic protection circuit for a chip.
  • Static electricity is everywhere. If there is no electrostatic protection circuit, a chip will be damaged by static electricity introduced for various reasons soon, and it will almost be fatal by one blow.
  • an electrostatic protection circuit is usually provided in the chip, and the electrostatic protection circuit is used to discharge the electrostatic charge in time to prevent the protected circuit from failing or even being burned due to the high voltage brought by the electrostatic charge.
  • An embodiment of the present disclosure provides an electrostatic protection circuit for a chip.
  • the chip includes a power pad and a ground pad.
  • the electrostatic protection circuit includes:
  • a monitoring unit for generating a trigger signal when there is an electrostatic pulse on the power supply pad
  • the discharge transistor is located between the power supply pad and the ground pad, and is used for conducting under the control of the trigger signal to discharge the electrostatic charge to the ground pad;
  • the first controllable voltage dividing unit which is connected to the discharge transistor, is used to switch the working mode under the control of the control signal, wherein the working mode includes the voltage dividing mode, and when the controllable voltage dividing unit works in the voltage dividing mode, it is used for A voltage that carries a portion of the electrostatic charge applied to the bleeder transistor.
  • the electrostatic protection circuit also includes:
  • the second controllable voltage dividing unit is connected with the first controllable voltage dividing unit, and is used to switch the working mode under the control of the control signal, wherein the working mode includes the voltage dividing mode.
  • the discharge transistor when the discharge transistor is a P-type transistor, its source is connected to the power supply pad, and its drain is connected to the first terminal of the first controllable voltage dividing unit;
  • the second end of the first controllable voltage dividing unit is connected to the first end of the second controllable unit, and the second end of the second controllable voltage dividing unit is connected to the ground pad.
  • the discharge transistor when the discharge transistor is an N-type transistor, its source is connected to the ground pad, and its drain is connected to the second end of the first controllable voltage dividing unit;
  • the first end of the first controllable voltage dividing unit is connected to the second end of the second controllable unit, and the first end of the second controllable voltage dividing unit is connected to the power pad.
  • the first controllable voltage dividing unit includes:
  • At least one voltage dividing element which is provided with a first end and a second end, and the first end of the voltage dividing element located at the head end after sequential connection is the first end of the first controllable voltage dividing unit, which is located at the end after sequential connection
  • the second end of the voltage dividing element is the second end of the first controllable voltage dividing unit
  • a control circuit which is connected to the first end of the voltage dividing element at the head end, and is also connected to the second end of the voltage dividing element at the end, for making at least one voltage dividing element from the voltage dividing mode under the control of the control signal Switch to bypass mode, or switch from bypass mode to divider mode.
  • control circuit includes:
  • the first switch is provided with a first end and a second end, the first end of which is connected to the first end of the voltage dividing element at the head end, and the second end is connected to the second end of the voltage dividing element at the end.
  • control circuit includes:
  • the control transistor is provided with a first end, a second end and a control end, the first end of which is connected to the first end of the voltage dividing element at the head end, and the second end is connected to the second end of the voltage dividing element at the end ;
  • the second switch has a first terminal and a second terminal, the first terminal of which is connected to the power supply pad, and the second terminal of which is connected to the control terminal of the control transistor;
  • the third switch has a first terminal and a second terminal, the first terminal is connected to the control terminal of the control transistor, and the second terminal is connected to the ground pad.
  • the first switch to the third switch are one-time programmable memories.
  • the first switch to the third switch are laser fuse devices.
  • control transistor is a P-type transistor
  • the second switch is in a blown state
  • the third switch is in a non-fuse state
  • the first controllable voltage dividing unit is in a bypass mode
  • control transistor is a P-type transistor
  • the second switch is in a non-fusing state
  • the third switch is in a fusing state
  • the first controllable voltage dividing unit is in a voltage dividing mode.
  • control transistor is an N-type transistor
  • the second switch is in a blown state
  • the third switch is in a non-fuse state
  • the first controllable voltage dividing unit is in a voltage dividing mode
  • control transistor is an N-type transistor
  • the second switch is in a non-fusing state
  • the third switch is in a fusing state
  • the first controllable voltage dividing unit is in a bypass mode.
  • the first switch is in a non-fuse state, and the first controllable voltage dividing unit is in a bypass mode
  • the first switch is in a blown state, and the first controllable voltage dividing unit is in a voltage dividing mode.
  • the voltage dividing element includes:
  • a diode, its anode is the first end of the voltage dividing element, and its cathode is the second end of the voltage dividing element.
  • control terminal of the discharge transistor is connected to the monitoring unit.
  • the circuit further includes a driving unit, and the control terminal of the discharge transistor is connected to the monitoring unit through the driving unit.
  • the present disclosure provides an electrostatic protection circuit for a chip, the circuit includes a monitoring unit, a discharge transistor and a first controllable voltage dividing unit, the monitoring unit is used to monitor the electrostatic pulse, and generate a trigger signal when there is an electrostatic pulse on the power supply pad , the discharge transistor is used to discharge the electrostatic charge on the pad of the power supply, the first controllable voltage dividing unit switches the working mode after receiving the control signal, when the first controllable voltage dividing unit works in the voltage dividing mode, it is used for A voltage that carries a portion of the electrostatic charge applied to the bleeder transistor.
  • FIG. 1 is a structural block diagram of an electrostatic protection circuit of a chip provided by an embodiment of the present disclosure
  • FIG. 2 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure
  • FIG. 3 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure.
  • FIG. 4 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure.
  • FIG. 5 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure.
  • FIG. 6 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure.
  • FIG. 7 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure.
  • FIG. 8 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure.
  • FIG. 9 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure.
  • FIG. 10 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by another embodiment of the present disclosure.
  • the present disclosure provides an electrostatic protection circuit for a chip.
  • the technical idea of the present disclosure is to set a plurality of controllable voltage divider units in the electrostatic protection circuit, and make multiple chips at one time, and according to the electrostatic voltage protection level applied to the chip Set the working mode of each controllable voltage divider unit in the chip, and make an electrostatic protection circuit suitable for different electrostatic voltage levels through one tape-out, reducing the cost of chip manufacturing.
  • an embodiment of the present disclosure provides an electrostatic protection circuit for a chip, and the chip is provided with a power pad VDD and a ground pad VSS.
  • the electrostatic protection circuit includes a monitoring unit 101, a discharge transistor 102, and a first controllable voltage dividing unit 103-1.
  • the monitoring unit 101 is connected to the control terminal of the discharge transistor 102, and the discharge transistor 102 is connected to the first controllable voltage dividing unit 103-1 and located between the power pad VDD and the ground pad VSS.
  • the monitoring unit 101 is used to monitor the electrostatic charge on the power supply pad VDD, and generate a trigger signal after the electrostatic charge on the power supply pad VDD.
  • the discharge transistor 102 is configured to be turned on under the control of the trigger signal, so as to discharge the electrostatic charge on the power supply pad VDD to the ground pad VSS.
  • the first controllable voltage dividing unit 103-1 includes a voltage dividing mode and a bypass mode, when the first controllable voltage dividing unit 103-1 works in the voltage dividing mode, it is used to carry part of the electrostatic charge applied to the discharge transistor 102 Voltage.
  • the first controllable voltage dividing unit 103 - 1 works in the bypass mode, the first controllable voltage dividing unit 103 - 1 cannot carry the voltage applied to the discharge transistor 102 by part of the electrostatic charge.
  • the control signal is used to switch the working mode of the first controllable voltage dividing unit 103-1, that is, the control signal can switch the first controllable voltage dividing unit 103-1 from working in the voltage dividing mode to working in the bypass mode. It is also possible to switch the first controllable voltage dividing unit 103-1 from working in the bypass mode to working in the voltage dividing mode.
  • the electrostatic protection circuit further includes a second controllable voltage dividing unit 103-2.
  • the second controllable voltage dividing unit 103-2 is connected with the first controllable voltage dividing unit 103-1, the second controllable voltage dividing unit 103-2 is used to switch the working mode under the control of the control signal, the second controllable voltage dividing unit 103-1
  • the working mode of the controlled voltage dividing unit 103-2 includes a voltage dividing mode and a bypass mode, that is, the control signal can switch the second controllable voltage dividing unit 103-2 from working in the voltage dividing mode to working in the bypass mode. It is also possible to switch the second controllable voltage dividing unit 103-2 from working in the bypass mode to working in the voltage dividing mode.
  • the number of controllable voltage dividing units in the voltage dividing mode in the electrostatic protection circuit can be set, then it can The voltage applied to the bleeder transistor 102 by the electrostatic charge is controlled.
  • the first controllable voltage dividing unit 103-1 and the second controllable voltage dividing unit 103-2 are set to be in the voltage dividing mode, more voltage applied to the bleeder transistor 102 can be divided, thereby preventing The breakdown of the discharge transistor 102 means that the ESD protection circuit is subjected to a higher ESD voltage level.
  • electrostatic protection circuits suitable for different voltage levels can be obtained, thereby reducing chip manufacturing costs.
  • the electrostatic protection circuit may further include a third controllable voltage dividing unit, a fourth controllable voltage dividing unit, ..., the Nth controllable voltage dividing unit, by connecting a plurality of controllable voltage dividing units in sequence After being connected to the drain of the discharge transistor 102, it is connected between the power supply pad VDD and the ground pad VSS, and then the number of controllable voltage division units in the voltage division mode in the electrostatic protection circuit is set through the control signal, so Adapt to a wider range of voltage levels.
  • both the first controllable voltage dividing unit 103 - 1 and the second controllable voltage dividing unit 103 - 2 are provided with a first end and a second end.
  • the discharge transistor 102 is an N-type transistor
  • the source of the discharge transistor 102 is connected to the ground pad VSS
  • the drain of the discharge transistor 102 is connected to the second end of the first controllable voltage dividing unit 103-1
  • the first controllable The first terminal of the voltage dividing unit 103-1 is connected to the second terminal of the second controllable voltage dividing unit 103-2
  • the first terminal of the second controllable voltage dividing unit 103-2 is connected to the power pad VDD. That is, the first controllable voltage dividing unit 103 - 1 and the second controllable voltage dividing unit 103 - 2 adjust the voltage applied to the bleeding transistor 102 between the drain of the bleeding transistor 102 and the power pad VDD.
  • the discharge transistor 102 when the discharge transistor 102 is a P-type transistor, the source of the discharge transistor 102 is connected to the power supply pad VDD, and the drain of the discharge transistor 102 is connected to the first controllable voltage dividing unit 103- 1, the second end of the first controllable voltage dividing unit 103-1 is connected to the first end of the second controllable voltage dividing unit 103-2, and the second end of the second controllable voltage dividing unit 103-2 Connect to the ground pad VSS. That is, the first controllable voltage dividing unit 103 - 1 and the second controllable voltage dividing unit 103 - 2 adjust the voltage applied to the bleeding transistor 102 between the drain of the bleeding transistor 102 and the ground pad VSS.
  • the first controllable voltage dividing unit 103-1 includes at least one voltage dividing element and a control circuit.
  • each voltage dividing element is provided with a first end and a second end, and after they are sequentially connected, the first end of the voltage dividing element located at the head end is the first end of the first controllable voltage dividing unit 103-1, which are sequentially connected to The second end of the voltage dividing element at the end is the second end of the first controllable voltage dividing unit 103-1.
  • the first controllable voltage dividing unit 103-1 includes three voltage dividing elements, marked as the first voltage dividing element, the second voltage dividing element and the third voltage dividing element, the second end of the first voltage dividing element is connected to the Two first ends of the voltage dividing element, the second end of the second voltage dividing element is connected to the first end of the third voltage dividing element, and the first end of the first voltage dividing element at the head end is the first controllable voltage dividing unit 103
  • the first end of -1, the second end of the third voltage dividing element at the end is the second end of the first controllable voltage dividing unit 103-1.
  • control circuit is connected to the first end of the voltage dividing element at the head end, and the control circuit is also connected to the second end of the voltage dividing element at the end, and the control circuit is used to make at least one voltage dividing element from Switch from divider mode to bypass mode, or switch from bypass mode to divider mode.
  • the control circuit is connected in parallel with at least one voltage dividing element connected in sequence. After the control circuit receives the control signal, if the control circuit is switched to the conduction state, at least one voltage dividing element connected in sequence will be bypassed, so as to switch the voltage dividing elements connected in sequence from the voltage dividing mode to the bypass mode. After the control circuit receives the control signal, if the control circuit switches to the cut-off state, at least one voltage dividing element connected in sequence can pass an electrostatic current, so as to switch the voltage dividing elements connected in sequence from the bypass mode to the voltage dividing mode.
  • At least one controllable voltage dividing unit is included in the electrostatic protection circuit, and after a plurality of chips are produced in one tape-out, the number of controllable voltage dividing units in the voltage dividing state in the electrostatic protection circuit can be set, thereby obtaining Adapt to electrostatic protection circuits of different electrostatic voltage levels to reduce chip manufacturing costs.
  • an embodiment of the present disclosure provides an electrostatic protection circuit for a chip.
  • the electrostatic protection circuit includes a monitoring unit 101, a discharge transistor 102, a first controllable voltage dividing unit 103-1 and a second A controllable voltage dividing unit 103-2.
  • the first controllable voltage dividing unit 103-1 and the second controllable voltage dividing unit 103-2 are provided with a first end and a second end, and the first controllable voltage dividing unit 103-1 and the second controllable voltage dividing unit 103-1
  • the unit 103 - 2 is connected in series with the drain of the bleeder transistor 102 .
  • the first controllable voltage dividing unit 103-1 and the second controllable voltage dividing unit 103-2 have the same structure, and the first controllable voltage dividing unit 103-1 is used as an example for description here.
  • the first controllable voltage dividing unit 103-1 includes at least one voltage dividing element and a control circuit. At least one voltage dividing unit is connected in parallel with the control circuit after being connected in sequence.
  • the control circuit includes a first switch K11, the first switch K11 is provided with a first end and a second end, and the first end of the first switch K11 is connected to a voltage dividing element at the first end. The first end of the first switch K11 is connected to the second end of the voltage dividing element at the end.
  • the control signal can switch the state of the first switch K11.
  • the first switch K11 makes the sequentially connected voltage dividing elements in a bypass state, and the electrostatic current flows through the first switch K11.
  • the control signal switches the state of the first switch K11 to the off state, the electrostatic current flows through the sequentially connected voltage dividing elements, and the sequentially connected voltage dividing elements in the first controllable voltage dividing unit 103-1 can be connected with the discharge transistor 102 Divides the voltage caused by electrostatic charges.
  • the voltage dividing element is a diode
  • the anode of the diode is the first end of the voltage dividing element
  • the cathode of the diode is the second end of the voltage dividing element.
  • the voltage of the drain of the bleeder transistor 102 is VDD-0.7*N, where N is the number of diodes, according to the bleeder transistor can withstand The breakdown voltage drop and the voltage VDD caused by the accumulation of electrostatic charges determine the specific value of N.
  • the first switch K11 includes a one-time programmable memory.
  • the one-time programmable memory may be a laser fuse device.
  • the first controllable voltage dividing unit 103-1 when the first switch K11 is in the non-fusing state, the first controllable voltage dividing unit 103-1 is in the bypass mode; The voltage dividing unit 103-1 is controlled to be in the voltage dividing mode.
  • the discharge transistor 102 is an N-type transistor, the source of the discharge transistor 102 is connected to the ground pad VSS, the drain of the discharge transistor 102 is connected to the second end of the first controllable voltage dividing unit 103-1, and A first terminal of a controllable voltage dividing unit 103-1 is connected to a second terminal of a second controllable voltage dividing unit 103-2, and a first terminal of the second controllable voltage dividing unit 103-2 is connected to a power pad VDD.
  • the monitoring unit 101 includes a monitoring capacitor C1 and a monitoring resistor R1, and the monitoring capacitor C1 and the monitoring resistor R1 are both provided with a first terminal and a second terminal.
  • the first terminal of the monitoring capacitor C1 is connected to the power pad VDD
  • the second terminal of the monitoring capacitor C1 is connected to the first terminal of the monitoring resistor R1 and then connected to the control terminal of the discharge transistor 102
  • the second terminal of the monitoring resistor R1 is connected to the grounding pad VSS .
  • the equivalent resistance of the monitoring capacitor C1 decreases, the control terminal of the discharge transistor 102 is pulled up to a high level, and the discharge transistor 102 is turned on.
  • the electrostatic charges are discharged to the ground pad VSS through the second controllable voltage dividing unit 103 - 2 , the first controllable voltage dividing unit 103 - 1 and the discharge transistor 102 .
  • first controllable voltage dividing unit 103 - 1 and/or the second controllable voltage dividing unit 103 - 2 are in the voltage dividing mode, they can bear part of the voltage applied to the discharge transistor 102 by electrostatic charges.
  • the borne voltage is determined according to the voltage dividing capability of the first controllable voltage dividing unit 103-1.
  • the number of voltage-dividing elements in the first controllable voltage-dividing unit 103-1 and the second controllable voltage-dividing unit 103-2 can be set to adjust their voltage-dividing capabilities.
  • the discharge transistor 102 is a P-type transistor, the source of the discharge transistor 102 is connected to the power supply pad VDD, and the drain of the discharge transistor 102 is connected to the first controllable voltage dividing unit 103- 1, the second end of the first controllable voltage dividing unit 103-1 is connected to the first end of the second controllable voltage dividing unit 103-2, and the second end of the second controllable voltage dividing unit 103-2 Connect to the ground pad VSS.
  • the monitoring unit 101 includes a monitoring resistor R1 and a monitoring capacitor C1, both of which are provided with a first terminal and a second terminal.
  • the first terminal of the monitoring resistor R1 is connected to the power pad VDD
  • the second terminal of the monitoring resistor R1 is connected to the first terminal of the monitoring capacitor C1 and then connected to the control terminal of the discharge transistor 102
  • the second terminal of the monitoring capacitor C1 is connected to the grounding pad VSS .
  • the equivalent resistance of the monitoring capacitor C1 decreases, the control terminal of the discharge transistor 102 is pulled down to a low level, and the discharge transistor 102 is turned on.
  • the electrostatic charges are discharged to the ground pad VSS through the discharge transistor 102 , the first controllable voltage dividing unit 103 - 1 and the second controllable voltage dividing unit 103 - 2 .
  • the control circuit includes a control transistor 1031 - 1 , a second switch K12 and a third switch K13 .
  • the control transistor 1031-1 is provided with a first end, a second end and a control end, the first end of the control transistor 1031-1 is connected to the first end of the voltage dividing element located at the head end, and the second end of the control transistor 1031-1 The terminal is connected to the first terminal of the bleeder transistor.
  • the second switch K12 has a first terminal and a second terminal, the first terminal of the second switch K12 is connected to the power pad VDD, and the second terminal of the second switch K12 is connected to the control terminal of the control transistor 1031-1.
  • the third switch K13 also has a first terminal and a second terminal, the first terminal of the third switch K13 is connected to the control terminal of the control transistor 1031-1, and the second terminal of the third switch K13 is connected to the ground pad VSS.
  • Switching the states of the second switch K12 and the third switch K13 through the control signal can switch the control transistor 1031-1 from the on state to the off state, or from the off state to the on state.
  • the control transistor 1031-1 makes the sequentially connected voltage dividing elements in the bypass state, and the electrostatic current flows through the control transistor 1031-1.
  • the control transistor 1031-1 is switched to the cut-off state, the electrostatic current flows through the sequentially connected voltage dividing elements, and the sequentially connected voltage dividing elements in the first controllable voltage dividing unit 103-1 can divide the electrostatic voltage with the discharge transistor 102 pressure.
  • the second switch K12 and the third switch K13 include one-time programmable memories.
  • the one-time programmable memory may be a laser fuse device. The states of the second switch K12 and the third switch K13 can be switched by performing laser fuse processing on the corresponding switches.
  • control signals, switches, etc. are relatively broad concepts.
  • the laser fuse device has two states. When the laser fuse device is not blown, it is equivalent to a switch Closed, when the laser fuse device is blown, it is equivalent to the switch is turned off.
  • the operation of causing the laser fuse device to be blown can be regarded as a control signal to the laser fuse device.
  • the bleeder transistor 102 is an N-type transistor, and the connection relationship between the bleeder transistor 102, the first controllable voltage divider unit 103-1, the second controllable voltage divider unit 103-2, and the monitoring unit 101 is the same as that in FIG. 3 Same, no more details here.
  • the structure and working process of the monitoring unit 101 are also the same as those in FIG. 3 , and will not be repeated here.
  • each controllable voltage dividing unit will be described below by taking the first controllable voltage dividing unit 103-1 as an example.
  • the control transistor 1031-1 is a P-type transistor.
  • the control terminal of the control transistor 1031-1 is connected to the ground pad VSS, and the control transistor 1031-1 is in a conduction state.
  • the electrostatic current flows through the control transistor 1031-1, and the first controllable voltage dividing unit 103-1 is in the bypass mode.
  • the control terminal of the control transistor 1031-1 is connected to the power supply pad VDD, and the control transistor 1031-1 is turned off. state, the current caused by electrostatic charges flows through the control transistor 1031-1, and the first controllable voltage dividing unit 103-1 is in the voltage dividing mode.
  • the bleeding transistor 102 is a P-type transistor, and the connection relationship between the bleeding transistor 102, the first controllable voltage dividing unit 103-1, the second controllable voltage dividing unit 103-2, and the monitoring unit 101 is the same as that in FIG. 4 Same, no more details here.
  • the structure and working process of the monitoring unit 101 are also the same as those in FIG. 4 , and will not be repeated here.
  • each controllable voltage dividing unit is described below using the first controllable voltage dividing unit 103-1.
  • the control transistor 1031-1 is an N-type transistor.
  • the control terminal of the control transistor 1031-1 is connected to the ground pad VSS, and the control transistor 1031-1 is turned off. state, electrostatic current flows through the diode, and the first controllable voltage dividing unit 103-1 is in the voltage dividing mode.
  • the third switch K13 When only the third switch K13 is fusing, so that the second switch K12 is in the non-fusing state, the third switch K13 is in the fusing state, the control terminal of the control transistor 1031-1 is connected to the power supply pad VDD, and the control transistor 1031-1 is in the conduction state. In the on state, the electrostatic current flows through the control transistor 1031-1, and the first controllable voltage dividing unit 103-1 is in the bypass mode.
  • an embodiment of the present disclosure provides an electrostatic protection circuit for a chip, the electrostatic protection circuit includes a monitoring unit 101, a driving unit 104, a discharge transistor 102, a first controllable voltage dividing unit 103- 1 and the second controllable voltage dividing unit 103-2.
  • the monitoring unit 101 is connected to the control terminal of the discharge transistor 102 through the driving unit 104 . 7 and 9, when the discharge transistor 102 is an N-type transistor, the source of the discharge transistor 102 is connected to the ground pad VSS, and the drain of the discharge transistor 102 is connected to the first controllable voltage divider unit 103-1. Two terminals, the first end of the first controllable voltage dividing unit 103-1 is connected to the second end of the second controllable voltage dividing unit 103-2, and the first end of the second controllable voltage dividing unit 103-2 is connected to the power welding Disk VDD.
  • the monitoring unit 101 when the bleeder transistor 102 is an N-type transistor, the monitoring unit 101 includes a monitoring resistor R1 and a monitoring capacitor C1, both of which have a first terminal and a second terminal.
  • the first terminal of the monitoring resistor R1 is connected to the power pad VDD
  • the second terminal of the monitoring resistor R1 is connected to the first terminal of the monitoring capacitor C1 and then connected to the control terminal of the discharge transistor 102
  • the second terminal of the monitoring capacitor C1 is connected.
  • the driving unit 104 includes a first driving transistor P3 and a second driving transistor N3.
  • the first end of the first drive transistor P3 is connected to the power supply pad VDD
  • the first end of the second drive transistor N3 is connected to the second end of the first drive transistor P3 and the control end of the discharge transistor 102
  • the second end of the second drive transistor N3 The second terminal is connected to the ground pad VSS.
  • the first driving transistor P3 is a P-type transistor
  • the second driving transistor N3 is an N-type transistor.
  • the discharge transistor 102 is a P-type transistor, the source of the discharge transistor 102 is connected to the power pad VDD, and the drain of the discharge transistor 102 is connected to the first controllable voltage dividing unit 103-1. terminal, the second terminal of the first controllable voltage dividing unit 103-1 is connected to the first terminal of the second controllable unit, and the second terminal of the second controllable voltage dividing unit 103-2 is connected to the ground pad VSS.
  • the monitoring unit 101 includes a monitoring capacitor C1 and a monitoring resistor R1 , and both the monitoring capacitor C1 and the monitoring resistor R1 are provided with a first terminal and a second terminal.
  • the first terminal of the monitoring capacitor C1 is connected to the power pad VDD
  • the second terminal of the monitoring capacitor C1 is connected to the first terminal of the monitoring resistor R1 and then connected to the control terminal of the discharge transistor 102
  • the second terminal of the monitoring resistor R1 is connected.
  • the structure of the driving unit 104 is the same as that in FIG. 7 and FIG. 9 , and will not be repeated here.
  • the structures of the first controllable voltage dividing unit 103-1 and the second controllable voltage dividing unit 103-2 in Fig. 7 and Fig. 8 are the same as those in Fig. 3 and Fig. 4, and correspondingly, the mode switching mode is also the same, which is not described here repeat.
  • the structures of the first controllable voltage dividing unit 103-1 and the second controllable voltage dividing unit 103-2 in Fig. 9 and Fig. 10 are the same as those in Fig. 5 and Fig. 6, and correspondingly, the mode switching mode is also the same, which is not described here repeat.
  • the turn-on rate of the discharge transistor 102 can be accelerated, thereby increasing the discharge rate of the discharge transistor 102, and further improving the discharge capability of the electrostatic protection circuit.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

一种芯片的静电保护电路，包括：监控单元（101），用于在电源焊盘VDD上有静电脉冲时生成触发信号；泄放晶体管（102），位于电源焊盘VDD和接地焊盘VSS之间，用于在触发信号的控制下导通，以将静电电荷泄放至接地焊盘VSS；第一可控分压单元（103-1），其与泄放晶体管（102）连接，用于在控制信号的控制下切换工作模式；其中，工作模式包括分压模式，当第一可控分压单元（103-1）工作于分压模式时用于承载部分静电电荷施加在泄放晶体管（102）上的电压。通过一次流片制作多个芯片，并通过控制信号设置静电保护电路中处于分压模式的可控分压单元的数量，可以获得适应不同电压等级的静电保护电路，降低制造成本。

Description

芯片的静电保护电路
本申请要求于2021年7月26日提交中国专利局、申请号为202110844712.1、申请名称为“芯片的静电保护电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种芯片的静电保护电路。
背景技术
静电无处不在，假如没有静电保护电路，一块芯片很快会被由于各种各样原因而引入静电所损伤，并且几乎会被一击致命。
因此，芯片中通常设有静电保护电路，静电保护电路用于及时泄放静电电荷，避免被保护电路由于承受静电电荷所带来高压而失效，甚至烧毁。
发明内容
本公开本公开一实施例提供一种芯片的静电保护电路，芯片包括电源焊盘和接地焊盘，静电保护电路包括：
监控单元，用于在电源焊盘上有静电脉冲时生成触发信号；
泄放晶体管，位于电源焊盘和接地焊盘之间，用于在触发信号的控制下导通，以将静电电荷泄放至接地焊盘；
第一可控分压单元，其与泄放晶体管连接，用于在控制信号的控制下切换工作模式，其中，工作模式包括分压模式，当可控分压单元工作于分压模式时用于承载部分静电电荷施加在所述泄放晶体管上的电压。
在一实施例中，静电保护电路还包括：
第二可控分压单元，其与第一可控分压单元连接，用于在控制信号的控制下切换工作模式，其中，工作模式包括分压模式。
在一实施例中，当泄放晶体管为P型晶体管，其源极连接电源焊盘，其漏极连接第一可控分压单元的第一端；
第一可控分压单元的第二端连接第二可控单元的第一端，第二可控分压单元的第二端连接接地焊盘。
在一实施例中，当泄放晶体管为N型晶体管，其源极连接接地焊盘，其漏极连接第一可控分压单元的第二端；
第一可控分压单元的第一端连接第二可控单元的第二端，第二可控分压单元的第 一端连接电源焊盘。
在一实施例中，第一可控分压单元包括：
至少一个分压元件，其设有第一端和第二端，其依次连接后位于首端的分压元件的第一端为第一可控分压单元的第一端，其依次连接后位于末端的分压元件的第二端为第一可控分压单元的第二端；
控制电路，其与位于首端的分压元件的第一端连接，其还与位于末端的分压元件的第二端连接，用于在控制信号的控制下使至少一个分压元件从分压模式切换至旁路模式，或从旁路模式切换至分压模式。
在一实施例中，控制电路包括：
第一开关，其设有第一端和第二端，其第一端与位于首端的分压元件的第一端连接，其第二端与位于末端的分压元件的第二端连接。
在一实施例中，控制电路包括：
控制晶体管，其设有第一端、第二端及控制端，其第一端与位于首端的分压元件的第一端连接，其第二端与位于末端的分压元件的第二端连接；
第二开关，其设有第一端和第二端，其第一端连接电源焊盘，其第二端连接控制晶体管的控制端；
第三开关，其设有第一端和第二端，其第一端连接控制晶体管的控制端，其第二端连接接地焊盘。
在一实施例中，第一开关至第三开关为一次性可编程存储器。
在一实施例中，第一开关至第三开关为激光熔丝器件。
在一实施例中，若控制晶体管为P型晶体管，第二开关处于熔断状态，第三开关处于非熔断状态，第一可控分压单元处于旁路模式；
若控制晶体管为P型晶体管，第二开关处于非熔断状态，第三开关处于熔断状态，第一可控分压单元处于分压模式。
在一实施例中，若控制晶体管为N型晶体管，第二开关处于熔断状态，第三开关处于非熔断状态，第一可控分压单元处于分压模式；
若控制晶体管为N型晶体管，第二开关处于非熔断状态，第三开关处于熔断状态，第一可控分压单元处于旁路模式。
在一实施例中，第一开关处于非熔断状态，第一可控分压单元处于旁路模式；
第一开关处于熔断状态，第一可控分压单元处于分压模式。
在一实施例中，分压元件包括：
二极管，其正极为分压元件的第一端，其负极为分压元件的第二端。
在一实施例中，泄放晶体管的控制端与监控单元连接。
在一实施例中，电路还包括驱动单元，泄放晶体管的控制端通过驱动单元与监控单元连接。
本公开提供一种芯片的静电保护电路，该电路包括监控单元、泄放晶体管以及第一可控分压单元，监控单元用于监控静电脉冲，并在电源焊盘上有静电脉冲时生成触发信号，泄放晶体管用于泄放电源焊盘上的静电电荷，第一可控分压单元在接收到控制信号后切换工作模式，当第一可控分压单元工作于分压模式时，用于承载部分静电电荷施加在所述泄放晶体管上的电压。通过一次流片制作多个芯片，根据芯片所使用的静电电压等级设置芯片内可控分压单元的工作模式，以设置泄放晶体管上承载的静电电荷引起的电压，即可获得适应不同静电电压等级的静电防护电路，减少芯片制造成本。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为本公开一实施例提供的芯片的静电保护电路的结构框图；
图2为本公开另一实施例提供的芯片的静电保护电路的具体电路图；
图3为本公开另一实施例提供的芯片的静电保护电路的具体电路图；
图4为本公开另一实施例提供的芯片的静电保护电路的具体电路图；
图5为本公开另一实施例提供的芯片的静电保护电路的具体电路图；
图6为本公开另一实施例提供的芯片的静电保护电路的具体电路图；
图7为本公开另一实施例提供的芯片的静电保护电路的具体电路图；
图8为本公开另一实施例提供的芯片的静电保护电路的具体电路图；
图9为本公开另一实施例提供的芯片的静电保护电路的具体电路图；
图10为本公开另一实施例提供的芯片的静电保护电路的具体电路图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
本公开提供一种芯片的静电保护电路，本公开的技术构思是：在静电保护电路中设置多个可控分压单元，一次流片制作多个芯片，并根据芯片所应用的静电电压防护等级设置芯片内各个可控分压单元的工作模式，通过一次流片即可制作适应不同静电电压等级的静电防护电路，减少芯片制造成本。
如图1所示，本公开一实施例提供一种芯片的静电保护电路，该芯片设有电源焊盘VDD和接地焊盘VSS。其中，静电保护电路包括监控单元101、泄放晶体管102以及第一可控分压单元103-1。
其中，监控单元101与泄放晶体管102的控制端连接，泄放晶体管102与第一可控分压单元103-1连接之后位于电源焊盘VDD和接地焊盘VSS之间。
监控单元101用于监控电源焊盘VDD上的静电电荷，在电源焊盘VDD上有静电电荷之后生成触发信号。泄放晶体管102用于在触发信号的控制下导通，以实现将电源焊盘VDD上的静电电荷泄放至接地焊盘VSS。
第一可控分压单元103-1包括分压模式和旁路模式，当第一可控分压单元103-1工作于分压模式时用于承载部分静电电荷施加在泄放晶体管102上的电压。当第一可控分压单元103-1工作于旁路模式时，第一可控分压单元103-1无法承载部分静电电荷施加在泄放晶体管102上的电压。
控制信号用于切换第一可控分压单元103-1的工作模式，也就是控制信号可以将第一可控分压单元103-1从工作于分压模式切换到工作于旁路模式。也可以将第一可控分压单元103-1从工作于旁路模式切换到工作于分压模式。
在一实施例中，静电保护电路还包括第二可控分压单元103-2。其中，第二可控分压单元103-2与第一可控分压单元103-1连接，第二可控分压单元103-2用于在控制信号的控制下切换工作模式，第二可控分压单元103-2的工作模式包括分压模式和旁路模式，也就是控制信号可以将第二可控分压单元103-2从工作于分压模式切换到工作于旁路模式。也可以将第二可控分压单元103-2从工作于旁路模式切换到工作于分压模式。
通过控制信号切换第一可控分压单元103-1和第二可控分压单元103-2的工作模式，可以设置静电保护电路中处于分压模式的可控分压单元的数量，则可以控制静电电荷施加在泄放晶体管102上的电压。
例如：设置第一可控分压单元103-1和第二可控分压单元103-2的均处于分压模式，则可以分去更多施加在泄放晶体管102上的电压，从而可以防止泄放晶体管102击穿，也就是该静电保护电路所承受的静电电压等级更高。
通过一次流片制作多个芯片，并通过控制信号设置静电保护电路内处于分压模式的可控分压单元的数量，可以获得适应不同电压等级的静电保护电路，从而降低芯片制造成本。
在一实施例中，静电保护电路还可以包括第三可控分压单元、第四可控分压单元、……、第N可控分压单元，通过让多个可控分压单元依次连接后与泄放晶体管102的漏极连接后，再连接在电源焊盘VDD和接地焊盘VSS之间，再通过控制信号设置静电保护电路内处于分压模式的可控分压单元的数量，所适应的电压等级范围更广泛。
下面以静电保护电路中仅包含两个可控分压单元描述，静电保护电路中包括多个可控分压单元的情况相似，此处不再赘述。
在一实施例中，继续参考图1，第一可控分压单元103-1和第二可控分压单元103-2均设有第一端和第二端。当泄放晶体管102为N型晶体管，泄放晶体管102的源极连接接地焊盘VSS，泄放晶体管102的漏极连接第一可控分压单元103-1的第二端，第一可控分压单元103-1的第一端连接第二可控分压单元103-2的第二端，第二可控分压单元103-2的第一端连接电源焊盘VDD。也就是第一可控分压单元103-1和第二可控分压单元103-2在泄放晶体管102的漏极和电源焊盘VDD之间调节施加在泄放晶体管102上的电压。
在一实施例中，参考图2，当泄放晶体管102为P型晶体管，泄放晶体管102的源极连接电源焊盘VDD，泄放晶体管102的漏极连接第一可控分压单元103-1的第一端，第一可控分压单元103-1的第二端连接第二可控分压单元103-2的第一端，第二可控分压单元103-2的第二端连接接地焊盘VSS。也就是第一可控分压单元103-1和第二可控分压单元103-2在泄放晶体管102的漏极和接地焊盘VSS之间调节施加在泄放晶体管102上的电压。
在一实施例中，第一可控分压单元103-1包括至少一个分压元件和控制电路。其中，每个分压元件设有第一端和第二端，其依次连接后位于首端的分压元件的第一端为第一可控分压单元103-1的第一端，其依次连接后位于末端的分压元件的第二端为第一可控分压单元103-1的第二端。
例如：第一可控分压单元103-1包括三个分压元件，标记为第一分压元件、第二分压元件以及第三分压元件，第一分压元件的第二端连接第二分压元件的第一端，第二分压元件的第二端连接第三分压元件的第一端，位于首端的第一分压元件的第一端 为第一可控分压单元103-1的第一端，位于末端的第三分压元件的第二端为第一可控分压单元103-1的第二端。
其中，控制电路与位于首端的分压元件的第一端连接，控制电路还与位于末端的分压元件的第二端连接，控制电路用于在控制信号的控制下使至少一个分压元件从分压模式切换至旁路模式，或从旁路模式切换至分压模式。
控制电路与依次连接的至少一个分压元件并联。在控制电路接收到控制信号后，若控制电路切换到导通状态，将依次连接的至少一个分压元件旁路，从而实现将依次连接的分压元件从分压模式切换至旁路模式。在控制电路接收到控制信号后，若控制电路切换到截止状态，依次连接的至少一个分压元件可以通过静电电流，从而实现将依次连接的分压元件从旁路模式切换至分压模式。
在上述技术方案中，静电保护电路中包括至少一个可控分压单元，在一次流片制作多个芯片后，可以设置静电保护电路内处于分压状态的可控分压单元的数量，从而获得适应不同静电电压等级的静电防护电路，减少芯片制造成本。
如图3至图6所示，本公开一实施例提供一种芯片的静电保护电路，该静电保护电路包括监控单元101、泄放晶体管102、第一可控分压单元103-1和第二可控分压单元103-2。
其中，第一可控分压单元103-1和第二可控分压单元103-2设有第一端和第二端，第一可控分压单元103-1和第二可控分压单元103-2串联后与泄放晶体管102的漏极连接。
第一可控分压单元103-1和第二可控分压单元103-2的结构相同，此处以第一可控分压单元103-1为例描述。
第一可控分压单元103-1包括至少一个分压元件和控制电路。至少一个分压单元依次连接后与控制电路并联连接。
在一实施例中，参考图3和图4，控制电路包括第一开关K11，第一开关K11设有第一端和第二端，第一开关K11的第一端与位于首端的分压元件的第一端连接，第一开关K11的第二端与位于末端的分压元件的第二端连接。
控制信号可以切换第一开关K11的状态。当控制信号将第一开关K11的状态切换至闭合状态，第一开关K11使得依次连接的分压元件处于旁路状态，静电电流流经第一开关K11。当控制信号将第一开关K11的状态切换至断开状态，静电电流流经依次连接的分压元件，第一可控分压单元103-1中依次连接的分压元件可以与泄放晶体管102对静电电荷引起的电压进行分压。
在一实施例中，分压元件为二极管，二极管的正极为分压元件的第一端，二极管的负极为分压元件的第二端。二极管D11至二极管D1N依次连接后位于首端的二极 管D11的正极作为第一可控分压单元103-1的第一端，位于末端的二极管D1N作为第一可控分压单元103-1的第二端。二极管可以是由PN结构成，也可以由MOS管栅极、漏极短接构成，二极管的具体结构，本公开不做限制。
由于二极管有一定的钳位电压，例如钳位电压为0.7V，因此，泄放晶体管102的漏极的电压为VDD-0.7*N，其中，N为二极管的个数，根据泄放晶体管可以承受的击穿压降和静电电荷累积而引起的电压VDD确定N的具体数值。
在一实施例中，第一开关K11包括一次性可编程存储器。其中，一次性可编程存储器可以为激光熔丝器件。
其中，当第一开关K11处于非熔断状态，第一可控分压单元103-1处于旁路模式，当对第一开关K11进行熔丝处理，使得第一开关K11处于熔断状态，第一可控分压单元103-1处于分压模式。
一次流片制作多个芯片，对静电保护电路内激光熔丝器件进行熔丝处理，可以设置静电保护电路内处于分压模式的可控分压单元的数量，设置静电保护电路所能够承受的静电电荷的等级。
参考图3，泄放晶体管102为N型晶体管，泄放晶体管102的源极连接接地焊盘VSS，泄放晶体管102的漏极与第一可控分压单元103-1的第二端，第一可控分压单元103-1的第一端连接第二可控分压单元103-2的第二端，第二可控分压单元103-2的第一端连接电源焊盘VDD。
监控单元101包括监控电容C1和监控电阻R1，监控电容C1和监控电阻R1均设有第一端和第二端。监控电容C1的第一端连接电源焊盘VDD，监控电容C1的第二端连接监控电阻R1的第一端后连接泄放晶体管102的控制端，监控电阻R1的第二端连接接地焊盘VSS。
在电源焊盘VDD上有静电电荷时，监控电容C1的等效阻值下降，泄放晶体管102的控制端被上拉至高电平，泄放晶体管102导通。静电电荷经过第二可控分压单元103-2、第一可控分压单元103-1以及泄放晶体管102泄放至接地焊盘VSS。
若第一可控分压单元103-1和/或第二可控分压单元103-2处于分压模式，则可以承担部分静电电荷施加在泄放晶体管102上的电压。所承担的电压根据第一可控分压单元103-1的分压能力确定。可以设置第一可控分压单元103-1和第二可控分压单元103-2内分压元件的数量，来调整其分压能力。
参考图4，与图3不同的是，泄放晶体管102为P型晶体管，泄放晶体管102的源极连接电源焊盘VDD，泄放晶体管102的漏极连接第一可控分压单元103-1的第一端，第一可控分压单元103-1的第二端连接第二可控分压单元103-2的第一端，第二可控分压单元103-2的第二端连接接地焊盘VSS。
监控单元101包括监控电阻R1和监控电容C1，监控电阻R1和监控电容C1均设有第一端和第二端。监控电阻R1的第一端连接电源焊盘VDD，监控电阻R1的第二端连接监控电容C1的第一端后连接泄放晶体管102的控制端，监控电容C1的第二端连接接地焊盘VSS。
在电源焊盘VDD上有静电电荷时，监控电容C1的等效阻值下降，泄放晶体管102的控制端被下拉至低电平，泄放晶体管102导通。静电电荷经过泄放晶体管102、第一可控分压单元103-1以及第二可控分压单元103-2泄放至接地焊盘VSS。
在一实施例中，参考图5和图6，控制电路包括控制晶体管1031-1、第二开关K12以及第三开关K13。其中，控制晶体管1031-1设有第一端、第二端及控制端，控制晶体管1031-1的第一端与位于首端的分压元件的第一端连接，控制晶体管1031-1的第二端与泄放晶体管的第一端连接。第二开关K12设有第一端和第二端，第二开关K12的第一端连接电源焊盘VDD，第二开关K12的第二端连接控制晶体管1031-1的控制端。第三开关K13也设有第一端和第二端，第三开关K13的第一端连接控制晶体管1031-1的控制端，第三开关K13的第二端连接接地焊盘VSS。
通过控制信号切换第二开关K12和第三开关K13的状态可以使控制晶体管1031-1从导通状态切换至截止状态，或者从截止状态切换至导通状态。当控制晶体管1031-1切换至导通状态，控制晶体管1031-1使得依次连接的分压元件处于旁路状态，静电电流流经控制晶体管1031-1。当控制晶体管1031-1切换至截止状态，静电电流流经依次连接的分压元件，第一可控分压单元103-1中依次连接的分压元件可以与泄放晶体管102对静电电压进行分压。
在一实施例中，第二开关K12和第三开关K13包括一次性可编程存储器。其中，一次性可编程存储器可以为激光熔丝器件。通过对相应开关进行激光熔丝处理即可切换第二开关K12和第三开关K13的状态。
在一些实施例中，控制信号、开关等是比较宽泛的概念，例如当第二开关K12为激光熔丝器件时，激光熔丝器件有两种状态，激光熔丝器件没有熔断时，相当于开关闭合，激光熔丝器件被熔断时，相当于开关断开。使得激光熔丝器件被熔断的操作可以当作一种对激光熔丝器件的控制信号。
继续参考图5，泄放晶体管102为N型晶体管，泄放晶体管102与第一可控分压单元103-1、第二可控分压单元103-2以及监控单元101的连接关系与图3相同，此处不再赘述。监控单元101的结构和工作过程也与图3相同，此处不再赘述。
下面以第一可控分压单元103-1为例描述各个可控分压单元的模式切换过程。当泄放晶体管102为N型晶体管时，控制晶体管1031-1为P型晶体管。当仅对第二开关K12进行熔断处理，使得第二开关K12处于熔断状态，第三开关K13处于非熔断 状态，控制晶体管1031-1的控制端连接接地焊盘VSS，控制晶体管1031-1处于导通状态，静电电流流经控制晶体管1031-1，第一可控分压单元103-1处于旁路模式。当仅对第三开关K13进行熔断处理，使得第二开关K12处于非熔断状态，第三开关K13处于熔断状态，控制晶体管1031-1的控制端连接电源焊盘VDD，控制晶体管1031-1处于截止状态，静电电荷引起的电流流经控制晶体管1031-1，第一可控分压单元103-1处于分压模式。
继续参考图6，泄放晶体管102为P型晶体管，泄放晶体管102与第一可控分压单元103-1、第二可控分压单元103-2以及监控单元101的连接关系与图4相同，此处不再赘述。监控单元101的结构和工作过程也与图4相同，此处不再赘述。
下面以第一可控分压单元103-1描述各个可控分压单元的模式切换过程。当泄放晶体管102为P型晶体管时，控制晶体管1031-1为N型晶体管。当仅对第二开关K12进行熔断处理，使得第二开关K12处于熔断状态，第三开关K13处于非熔断状态，控制晶体管1031-1的控制端连接接地焊盘VSS，控制晶体管1031-1处于截止状态，静电电流流经二极管，第一可控分压单元103-1处于分压模式。当仅对第三开关K13进行熔断处理，使得第二开关K12处于非熔断状态，第三开关K13处于熔断状态，控制晶体管1031-1的控制端连接电源焊盘VDD，控制晶体管1031-1处于导通状态，静电电流流经控制晶体管1031-1，第一可控分压单元103-1处于旁路模式。
一次流片制作多个芯片，对静电保护电路内激光熔丝器件进行熔丝处理，可以设置静电保护电路内处于分压模式的可控分压单元的数量，设置静电保护电路所能够承受的静电电荷的等级。
如图7至图10所示，本公开一实施例提供一种芯片的静电保护电路，该静电保护电路包括监控单元101、驱动单元104、泄放晶体管102、第一可控分压单元103-1和第二可控分压单元103-2。
监控单元101通过驱动单元104与泄放晶体管102的控制端连接。参考图7和图9，当泄放晶体管102为N型晶体管，泄放晶体管102的源极连接接地焊盘VSS，泄放晶体管102的漏极与第一可控分压单元103-1的第二端，第一可控分压单元103-1的第一端连接第二可控分压单元103-2的第二端，第二可控分压单元103-2的第一端连接电源焊盘VDD。
继续参考图7和图9，当泄放晶体管102为N型晶体管，监控单元101包括监控电阻R1和监控电容C1，监控电阻R1和监控电容C1均设有第一端和第二端。监控电阻R1的第一端连接电源焊盘VDD，监控电阻R1的第二端连接监控电容C1的第一端后连接泄放晶体管102的控制端，监控电容C1的第二端连接。
驱动单元104包括第一驱动晶体管P3和第二驱动晶体管N3。第一驱动晶体管P3 的第一端连接电源焊盘VDD，第二驱动晶体管N3的第一端连接第一驱动晶体管P3的第二端后与泄放晶体管102的控制端，第二驱动晶体管N3的第二端连接接地焊盘VSS。其中，第一驱动晶体管P3为P型管，第二驱动晶体管N3为N型管。
在电源焊盘VDD上有静电电荷时，监控电容C1的阻值下降，第一驱动晶体管P3的控制端被下拉至低电平，第一驱动晶体管P3的漏极被上拉至高电平，泄放晶体管102的控制端被上拉至电平，泄放晶体管102导通。静电电荷经过泄放晶体管102、第一可控分压单元103-1以及第二可控分压单元103-2泄放至接地焊盘VSS。
参考图8和图10，泄放晶体管102为P型晶体管，泄放晶体管102的源极连接电源焊盘VDD，泄放晶体管102的漏极连接第一可控分压单元103-1的第一端，第一可控分压单元103-1的第二端连接第二可控单元的第一端，第二可控分压单元103-2的第二端连接接地焊盘VSS。
继续参考图8和图10，监控单元101包括监控电容C1和监控电阻R1，监控电容C1和监控电阻R1均设有第一端和第二端。监控电容C1的第一端连接电源焊盘VDD，监控电容C1的第二端连接监控电阻R1的第一端后连接泄放晶体管102的控制端，监控电阻R1的第二端连接。
驱动单元104的结构与图7和图9中相同，此处不再赘述。
在电源焊盘VDD上有静电电荷时，监控电容C1的阻值下降，第二驱动晶体管N3的控制端被上拉至高电平，第二驱动晶体管N3的漏极下拉至低电平，泄放晶体管102的控制端被下拉至低电平，泄放晶体管102导通。静电电荷经过第二可控分压单元103-2、第一可控分压单元103-1以及泄放晶体管102泄放至接地焊盘VSS。
图7和图8中第一可控分压单元103-1和第二可控分压单元103-2的结构同图3和图4相同，相应地，模式切换的方式也相同，此处不在赘述。图9和图10中第一可控分压单元103-1和第二可控分压单元103-2的结构同图5和图6相同，相应地，模式切换的方式也相同，此处不在赘述。
在上述技术方案中，通过在静电保护电路中增加驱动单元104，可以加快泄放晶体管102的导通速率，从而提升泄放晶体管102的泄放速率，进而提升静电保护电路的泄放能力。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (15)

  1. 一种芯片的静电保护电路，所述芯片包括电源焊盘和接地焊盘，所述静电保护电路包括：
    监控单元，用于在所述电源焊盘上有静电脉冲时生成触发信号；
    泄放晶体管，位于所述电源焊盘和所述接地焊盘之间，用于在所述触发信号的控制下导通，以将静电电荷泄放至所述接地焊盘；
    第一可控分压单元，其与所述泄放晶体管连接，用于在控制信号的控制下切换工作模式，其中，所述工作模式包括分压模式，当所述第一可控分压单元工作于分压模式时用于承载部分所述静电电荷施加在所述泄放晶体管上的电压。
  2. 根据权利要求1所述的电路，其中，所述静电保护电路还包括：
    第二可控分压单元，其与所述第一可控分压单元连接，用于在控制信号的控制下切换工作模式，其中，所述工作模式包括分压模式。
  3. 根据权利要求2所述的电路，其中，
    当所述泄放晶体管为P型晶体管，其源极连接所述电源焊盘，其漏极连接所述第一可控分压单元的第一端；
    所述第一可控分压单元的第二端连接所述第二可控单元的第一端，第二可控分压单元的第二端连接所述接地焊盘。
  4. 根据权利要求2所述的电路，其中，
    当所述泄放晶体管为N型晶体管，其源极连接所述接地焊盘，其漏极连接所述第一可控分压单元的第二端；
    所述第一可控分压单元的第一端连接所述第二可控单元的第二端，第二可控分压单元的第一端连接所述电源焊盘。
  5. 根据权利要求1至4中任意一项所述的电路，其中，所述第一可控分压单元包括：
    至少一个分压元件，其设有第一端和第二端，其依次连接后位于首端的分压元件的第一端为所述第一可控分压单元的第一端，其依次连接后位于末端的分压元件的第二端为所述第一可控分压单元的第二端；
    控制电路，其与所述位于首端的分压元件的第一端连接，其还与所述位于末端的分压元件的第二端连接，用于在所述控制信号的控制下使所述至少一个分压元件从分压模式切换至旁路模式，或从所述旁路模式切换至所述分压模式。
  6. 根据权利要求5所述的电路，其中，所述控制电路包括：
    第一开关，其设有第一端和第二端，其第一端与所述位于首端的分压元件的第一端连接，其第二端与所述位于末端的分压元件的第二端连接。
  7. 根据权利要求5所述的电路，其中，所述控制电路包括：
    控制晶体管，其设有第一端、第二端及控制端，其第一端与所述位于首端的分压元件的第一端连接，其第二端与所述位于末端的分压元件的第二端连接；
    第二开关，其设有第一端和第二端，其第一端连接所述电源焊盘，其第二端连接所述控制晶体管的控制端；
    第三开关，其设有第一端和第二端，其第一端连接所述控制晶体管的控制端，其第二端连接所述接地焊盘。
  8. 根据权利要求6所述的电路，其中，第一开关至第三开关为一次性可编程存储器。
  9. 根据权利要求8所述的电路，其中，所述第一开关至所述第三开关为激光熔丝器件。
  10. 根据权利要求9所述的电路，其中，
    若所述控制晶体管为P型晶体管，第二开关处于熔断状态，所述第三开关处于非熔断状态，所述第一可控分压单元处于旁路模式；
    若所述控制晶体管为P型晶体管，所述第二开关处于非熔断状态，所述第三开关处于熔断状态，所述第一可控分压单元处于分压模式。
  11. 根据权利要求9所述的电路，其中，
    若所述控制晶体管为N型晶体管，第二开关处于熔断状态，所述第三开关处于非熔断状态，所述第一可控分压单元处于分压模式；
    若所述控制晶体管为N型晶体管，所述第二开关处于非熔断状态，所述第三开关处于熔断状态，所述第一可控分压单元处于旁路模式。
  12. 根据权利要求9所述的电路，其中，
    所述第一开关处于非熔断状态，所述第一可控分压单元处于旁路模式；
    所述第一开关处于熔断状态，所述第一可控分压单元处于分压模式。
  13. 根据权利要求5所述的电路，其中，所述分压元件包括：
    二极管，其正极为所述分压元件的第一端，其负极为所述分压元件的第二端。
  14. 根据权利要求1所述的电路，其中，所述泄放晶体管的控制端与所述监控单元连接。
  15. 根据权利要求1所述的电路，其中，所述电路还包括驱动单元，所述泄放晶体管的控制端通过所述驱动单元与所述监控单元连接。
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