WO2023284360A1 - 芯片的静电保护电路 - Google Patents

芯片的静电保护电路 Download PDF

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Publication number
WO2023284360A1
WO2023284360A1 PCT/CN2022/088845 CN2022088845W WO2023284360A1 WO 2023284360 A1 WO2023284360 A1 WO 2023284360A1 CN 2022088845 W CN2022088845 W CN 2022088845W WO 2023284360 A1 WO2023284360 A1 WO 2023284360A1
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Prior art keywords
control
transistor
electrostatic protection
terminal
switch
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PCT/CN2022/088845
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English (en)
French (fr)
Inventor
朱玲
田凯
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长鑫存储技术有限公司
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Priority to US17/810,682 priority Critical patent/US20230007947A1/en
Publication of WO2023284360A1 publication Critical patent/WO2023284360A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Definitions

  • the present disclosure relates to the technical field of integrated circuits, in particular to an electrostatic protection circuit for a chip.
  • Static electricity is everywhere. If there is no electrostatic protection circuit, a chip will be damaged by static electricity introduced for various reasons soon, and it will almost be fatal by one blow.
  • an electrostatic protection circuit is usually provided in the chip, and the electrostatic protection circuit is used to discharge the electrostatic charge in time to prevent the protected circuit from failing or even being burned due to the high voltage brought by the electrostatic charge.
  • the present disclosure provides an electrostatic protection circuit for a chip.
  • the chip includes a power pad and a ground pad.
  • the electrostatic protection circuit includes:
  • a monitoring unit for generating a trigger signal when there is an electrostatic pulse on the power supply pad
  • a plurality of controllable driving units which are connected to the monitoring unit, are used to switch the working state under the control of the control signal, wherein the working state includes an output state, and the output state refers to generating a driving signal according to the trigger signal;
  • the discharge transistor is connected with a plurality of controllable driving units, and is used for conducting under the drive of the driving signal, so as to discharge the electrostatic charge to the ground pad.
  • each controllable drive unit includes:
  • the main circuit is used to generate a driving signal according to a trigger signal when in an output state
  • the control circuit is connected with the main circuit, and is used to switch the working state of the main circuit according to the control signal; wherein, the working state of the main circuit includes an output state.
  • the main circuit is connected between the power pad and the ground pad;
  • the main circuit is connected with the output terminal of the monitoring unit through the control circuit.
  • the main circuit includes:
  • the first end of the second driving transistor is connected to the second end of the first driving transistor, and the second end is connected to the ground pad.
  • control circuit includes:
  • the first switch its first end is connected to the output end of the monitoring unit, its second end is connected to the control end of the first driving transistor, and is used to switch from the closed state to the open state under the control of the control signal, or from the open state switch to closed state;
  • the second switch has its first terminal connected to the output terminal of the monitoring unit, and its second terminal connected to the control terminal of the second driving transistor, which is used to switch from the closed state to the disconnected state or from the disconnected state under the control of the control signal Switch to closed state.
  • the main circuit is connected to the output end of the monitoring unit
  • the main circuit is connected to the power pad through the first control sub-circuit, and the main circuit is connected to the ground pad through the second control sub-circuit.
  • the main circuit includes:
  • the first drive transistor the control end of which is connected to the output end of the monitoring unit
  • the second driving transistor has its first terminal connected to the second terminal of the first driving transistor, and its control terminal connected to the output terminal of the monitoring unit.
  • control circuit includes:
  • a first control transistor the first end of which is connected to the power supply pad; the second end of which is connected to the first end of the first drive transistor;
  • the third switch has its first end connected to the power supply pad, and its second end connected to the control end of the first control transistor, which is used to switch from the closed state to the open state under the control of the control signal, or from the open state to the open state. closed state;
  • the fourth switch has its first end connected to the control end of the first control transistor, and its second end connected to the ground pad, which is used to switch from the closed state to the open state or from the open state to the open state under the control of the control signal. closed state.
  • control circuit includes:
  • the second control transistor the first end of which is connected to the second end of the second drive transistor, and the second end of which is connected to the ground pad;
  • the fifth switch whose first end is connected to the power supply pad, and whose second end is connected to the control end of the second control transistor, is used to switch from the closed state to the open state, or from the open state to the open state under the control of the control signal. closed state;
  • the sixth switch whose first end is connected to the control end of the second control transistor, and whose second end is connected to the ground pad, is used to switch from the closed state to the open state or from the open state to the open state under the control of the control signal. closed state.
  • the monitoring unit includes:
  • a monitoring resistor the first end of which is connected to the power supply pad
  • the monitoring capacitor the first terminal of which is connected to the second terminal of the monitoring resistor serves as the output terminal of the monitoring unit, and the second terminal of which is connected to the grounding pad.
  • the first driving transistor is a P-type transistor
  • the second driving transistor and the discharge transistor are N-type transistors.
  • the first control transistor is a P-type transistor
  • the second control transistor is an N-type transistor
  • the size of the first control transistor is the same as that of the first driving transistor, and the size of the second control transistor is the same as that of the second driving transistor.
  • the first switch to the sixth switch are one-time programmable memories.
  • the first switch to the sixth switch are laser fuse devices.
  • the disclosure provides an electrostatic protection circuit for a chip, including a monitoring unit, a plurality of controllable driving units, and a discharge transistor.
  • the monitoring unit is used to monitor the electrostatic pulse on the power pad, and generates an electrostatic pulse when there is an electrostatic pulse on the power pad.
  • the trigger signal, the controllable drive unit is used to generate the drive signal according to the trigger signal under the control of the control signal, the discharge transistor is turned on under the control of several drive signals, and the static pulse on the power pad is discharged to the grounding pad in time.
  • FIG. 1 is a specific circuit diagram of an electrostatic protection circuit of a chip provided by an embodiment of the present disclosure
  • Fig. 2 is a structural block diagram of an electrostatic protection circuit of a chip provided in real time by the present disclosure
  • FIG. 3 is a structural block diagram of another chip electrostatic protection circuit provided in real time in the present disclosure.
  • FIG. 4 is a structural block diagram of an electrostatic protection circuit of another chip provided in real time by the present disclosure.
  • FIG. 5 is a specific circuit diagram of an electrostatic protection circuit of a chip provided in real time by the present disclosure
  • FIG. 6 is a specific circuit diagram of an electrostatic protection circuit of a chip provided in real time according to the present disclosure.
  • FIG. 1 is an electrostatic protection circuit of a chip provided by an embodiment of the present disclosure, and the chip includes a power pad VDD and a ground pad VSS.
  • the electrostatic protection circuit includes a monitoring unit 101 , a driving unit 104 and a discharge transistor 103 .
  • the monitoring unit 101 is located between the power pad and the ground pad
  • the driving unit 104 is connected to the monitoring unit 101
  • the driving unit is also connected to the bleeder transistor.
  • the monitoring unit 101 is used to generate a trigger signal when there is an electrostatic pulse on the power supply pad VDD, and the drive unit 104 is used to generate a drive signal according to the trigger signal.
  • the upper electrostatic charge is discharged to the ground pad VSS.
  • the monitoring unit 101 includes a monitoring resistor R1 and a monitoring capacitor C1, the first end of the monitoring resistor R1 is connected to the power pad VDD, the second end of the monitoring capacitor C1 is connected to the ground pad VSS, and the second end of the monitoring resistor R1 The terminal is connected to the first terminal of the monitoring capacitor C1 and then connected to the driving unit 101 .
  • the driving unit 104 includes a first driving transistor P1 and a second driving transistor N1, the first end of the first driving transistor P1 is connected to the power pad VDD, and the second end of the second driving transistor N1 is connected to the ground pad VSS, the second end of the first driving transistor P1 is connected to the first end of the second driving transistor N1 and then connected to the control end of the discharge transistor 103 .
  • the impedance of the monitoring capacitor C1 drops sharply, and the voltage of the first terminal V1 of the monitoring capacitor C1 also drops, so as to control the first drive transistor P1 to be turned on, the second drive transistor N1 to be turned off, and the second drive transistor N1 to be turned off.
  • the voltage of the second terminal Vg of a driving transistor P1 is pulled to a high level, and the discharge transistor N0 is also turned on, and the discharge transistor N0 discharges the electrostatic charge on the power supply pad to the ground pad VSS.
  • the ratio between the size of the first driving transistor P1 and the size of the second driving transistor N1 determines the terminal voltage of the second terminal Vg of the first driving transistor P1, the size of the first driving transistor P1 and the size of the second driving transistor N1
  • the leakage current of the chip during the power-on process is also greater. Therefore, the ratio of the size of the first drive transistor P1 to the size of the second drive transistor N1 has a relatively large impact on the electrostatic protection capability of the chip. Testing will determine the proper ratio.
  • the ESD protection circuit shown in FIG. 1 usually needs to be taped out together with the internal circuit of the chip in order to test the ESD protection level of the chip. If it is found that the electrostatic protection capability of the chip is relatively weak, it is necessary to redesign the size of the first driving transistor P1 and the size of the second driving transistor N1, and then test the electrostatic protection capability of the chip after tape-out.
  • the tape-out cost of the chip is expensive. If the electrostatic protection ability of the chip is weak, it is necessary to redesign the size of the two driving transistors and test again after tape-out, resulting in a complicated test process and high test cost.
  • the present disclosure provides another electrostatic protection circuit for chips, aiming at reducing the test cost of electrostatic protection for chips.
  • the technical concept of the present disclosure is: setting multiple controllable driving units in the electrostatic protection circuit, and setting the number of controllable driving units in the output state in the electrostatic protection circuit through the control signal before the electrostatic protection circuit performs the electrostatic protection capability test, In order to realize the discharge ability of the discharge transistor, so as to realize the electrostatic protection ability of the electrostatic protection circuit, make multiple chips through one tape-out, set the electrostatic protection ability of the electrostatic protection circuit according to the test requirements, and obtain multiple sets of different electrostatic protection capabilities
  • the ESD protection circuit eliminates the need for multiple tape-outs, reduces the cost of ESD protection testing, and simplifies the ESD protection testing process for chips.
  • the disclosure provides an electrostatic protection circuit for a chip.
  • the chip includes a power pad 201 and a ground pad 202 .
  • the electrostatic protection circuit includes a monitoring unit 101 , a plurality of controllable driving units and a discharge transistor 103 .
  • a plurality of controllable driving units are marked as controllable driving unit 101-1, controllable driving unit 101-2, . . . and controllable driving unit 101-N, where N is a positive integer and N>1.
  • the monitoring unit 101 is connected between the power pad 201 and the ground pad 202 , and the monitoring unit 101 is used to generate a trigger signal when there is an electrostatic pulse on the power pad 201 .
  • control signal may be an electrical signal or other signal that is not affected by power-off of the chip, such as a laser signal.
  • the controllable drive unit can output the drive signal according to the trigger signal, the controllable drive unit is in the output state.
  • the controllable drive unit cannot output the drive signal, the controllable drive unit is in a state of stopping output.
  • the control signal can switch the working state of the controllable drive unit, for example, switch the controllable drive unit from an output state to a stop output state.
  • the controllable driving unit does not need the control signal to maintain the working state, so as to ensure that the working state of the controllable driving unit in the chip will be maintained when the chip is in a power-off state during the test. constant.
  • the discharge transistor 103 is connected with each controllable driving unit, and the discharge transistor 103 is used to be turned on under the drive of the drive signal to discharge the electrostatic charge to the ground pad 202.
  • the number of drive signals received by the discharge transistor 103 is The more the number, the faster the turn-on rate of the discharge transistor 103 is, the stronger the discharge capability of the discharge transistor 103 is, and the stronger the electrostatic protection capability of the entire electrostatic protection circuit is.
  • the chips are divided into multiple groups.
  • the working state of the controllable drive unit is switched through the control signal, so that the number of controllable drive units in the output state in each group of chips is different.
  • the conduction rate of the discharge transistor 103 in each group of chips is also different, and the conduction rate will affect the discharge rate of the discharge transistor 103, so that the electrostatic protection capabilities of the electrostatic protection circuits of each group of chips are different, and then use the set
  • the chip is tested, and the electrostatic protection circuit with the best electrostatic protection ability is selected from it, without the need for multiple tape-outs, which can reduce the cost of electrostatic protection testing and simplify the electrostatic protection testing process of the chip.
  • controllable driving unit 102 - 1 is taken as an example to describe the circuit structure in the controllable driving unit.
  • Other controllable units are the same as the controllable driving unit 102 - 1 , and will not be repeated here.
  • the controllable drive unit 102-1 includes a main circuit 1022-1 and a control circuit 1021-1, the main circuit 1022-1 is connected to the monitoring unit 101, the control circuit 1021-1 is connected to the main circuit 1022-1, and the main circuit 1022-1 is in The working state is switched under the control of the control circuit 1021-1.
  • the working state in which the main circuit generates the driving signal according to the trigger signal is called the output state
  • the working state in which the main circuit does not output the driving signal is called the stop output state.
  • the control The signal switches the working state of the control circuit 1021-1, and the switching of the working state of the control circuit 1021-1 makes the main circuit switch from the output state to the output stop state, or switches the main circuit from the output stop state to the output state.
  • the main circuit 1022-1 is connected between the power supply pad 201 and the ground pad 202, and the main circuit 1022-1 is connected to the output terminal of the monitoring unit 101 through the control circuit 1021-1.
  • the control circuit 1021-1 can connect or disconnect the path between the main circuit 1022-1 and the monitoring unit 101.
  • the control signal switches the working state of the control circuit 1021-1 to make the control circuit 1021-1 in the working state of connecting the path between the main circuit 1022-1 and the monitoring unit 101
  • the main circuit 1022-1 is in the output state.
  • the control signal switches the working state of the control circuit 1021-1, so that the control circuit 1021-1 is in the working state of disconnecting the path between the main circuit 1022-1 and the monitoring unit 101, the main circuit 1022-1 is in the output stop state .
  • the working state of the control circuit is set according to the test requirements, so that the path between the main circuit 1022-1 and the monitoring unit 101 is disconnected Or connected to solidify the working state of the controllable drive unit, so as to realize the electrostatic protection capability of the electrostatic protection circuit according to the test requirements.
  • controllable driving unit 102 - 1 the circuit structure in the controllable driving unit is described by taking the controllable driving unit 102 - 1 as an example.
  • Other controllable units are the same as the controllable driving unit 102 - 1 , and will not be repeated here.
  • the controllable drive unit 102-1 includes a main circuit 1022-1 and a control circuit 1021-1, the main circuit 1022-1 is connected to the monitoring unit 101, the control circuit 1021-1 is connected to the main circuit 1022-1, and the control circuit 1021-1 includes The first control subcircuit 1023-1 and the second control subcircuit 1024-1, the main circuit 1022-1 is connected to the power supply pad 201 through the first control subcircuit 1023-1, and the main circuit 1022-1 is connected through the second control subcircuit 1024 - 1 is connected to ground pad 202 .
  • the first control sub-circuit 1023-1 and the second control sub-circuit 1024-1 can connect or disconnect the path between the main circuit 1022-1 and the power pad 201 and the ground pad 202, when the control signal switches the first control
  • the working state of the sub-circuit 1023-1 and the second control sub-circuit 1024-1 makes the first control sub-circuit 1023-1 and the second control sub-circuit 1024-1 in a state where the main circuit 1022-1 and the power pad 201, ground When the path between the pads 202 is in the working state, the main circuit 1022-1 is in the output state.
  • the first control sub-circuit 1023-1 and the second control sub-circuit 1024-1 are in the state where the main circuit 1022-1
  • the main circuit 1022-1 is in the output stop state.
  • an embodiment of the present disclosure provides an electrostatic protection circuit for a chip.
  • the electrostatic protection circuit for the chip includes a monitoring unit 101 , a plurality of controllable driving units, and a discharge transistor N0 .
  • a plurality of controllable driving units are marked as controllable driving unit 102-1, controllable driving unit 102-2, . . . and controllable driving unit 102-N, where N is a positive integer and N>1.
  • Only the driving unit 102-1 and the driving unit 102-2 are shown in the figure, and the circuit structures of other driving units are the same as those of the driving unit 102-1 and the driving unit 102-2, and will not be repeated here.
  • the monitoring unit 101 includes a monitoring capacitor C1 and a monitoring resistor R1, the monitoring capacitor C1 is provided with a first terminal and a second terminal, the monitoring resistor R1 is also provided with a first terminal and a second terminal, and the first terminal of the monitoring resistor R1 is connected to the power supply
  • the pad VDD, the second end of the monitoring capacitor C1 is connected to the grounding pad VSS, the second end of the monitoring resistor R1 and the first end V1 of the monitoring capacitor C1 are connected to each other as the output end of the monitoring unit 101 .
  • controllable driving unit 102-1 The circuit structure and working principle of the controllable driving unit 102-1 will be described below as an example.
  • the controllable driving unit 102-1 includes a main circuit 1022-1 and a control circuit 1021-1, and the main circuit 1022-1 is connected to the output terminal of the monitoring unit 101 through the control circuit 1021-1.
  • the main circuit 1022-1 includes a first driving transistor P11 and a second driving transistor N11, and the first driving transistor P11 and the second driving transistor N11 have a first terminal, a second terminal and a control terminal.
  • the first end of the first drive transistor P11 is connected to the power supply pad VDD
  • the second end of the second drive transistor N11 is connected to the ground pad VSS
  • the second end of the first drive transistor P11 and the first end of the second drive transistor N11 are connected to each other. After being connected, it is connected to the control terminal of the discharge transistor N0, the control terminal of the first drive transistor P11 and the control terminal of the second drive transistor N11 are connected to each other and then connected to the output terminal of the monitoring unit 101 through the control circuit 1021-1.
  • control circuit 1021-1 includes a first switch K11 and a second switch K12. Wherein, both the first switch K11 and the second switch K12 are provided with a first terminal and a second terminal.
  • the first end of the first switch K11 is connected to the output end of the monitoring unit 101, the second end of the first switch K11 is connected to the control end of the first drive transistor P11, and the first switch K11 is used to switch from the closed state under the control of the control signal to the open state, or switch from the open state to the closed state.
  • the first end of the second switch K12 is connected to the output end of the monitoring unit 101, the second end of the second switch K12 is connected to the control end of the second drive transistor N11, and the second switch K12 is used to switch from the closed state under the control of the control signal to the open state, or switch from the open state to the closed state.
  • the first driving transistor P11 and the second driving transistor N11 pull the voltage of the second terminal Vg of the second driving transistor N11 under the control of the trigger signal, so as to control the turn-on or turn-off of the bleeder transistor N0 .
  • the first driving transistor P11 is a P-type transistor
  • the second driving transistor N11 and the discharge transistor N0 are N-type transistors.
  • the size of the bleeding transistor N0 is larger than that of the second driving transistor N11.
  • the size of the first driving transistor in the kth controllable driving unit is twice the size of the first driving transistor in the k-1th controllable driving unit, that is, when the kth controllable driving unit
  • the driving current output by the first driving transistor in the controllable driving unit is 2 k ⁇ i b1
  • the driving current output by the first driving transistor in the k-1th controllable driving unit is 2 k-1 ⁇ i b1 .
  • i b1 is the current reference value.
  • the size of the second drive transistor in the kth controllable drive unit is twice the size of the second drive transistor in the k-1th controllable drive unit, that is, when the kth controllable drive unit
  • the driving current output by the second driving transistor in the controllable driving unit is 2 k ⁇ i b2
  • the driving current output by the second driving transistor in the k-1th controllable driving unit is 2 k-1 ⁇ i b2 .
  • ib2 is the current reference value.
  • the chips are divided into multiple groups, marked as the first group of chips, the second group of chips, the third group of chips, ..., and the Mth group of chips, and the number of chips in each group is Q. This is just an example, and the number of chips in each group may also be different.
  • the number of controllable drive units in the output state in the M group of chips is determined according to the test requirements. Assume that the number of controllable drive units in the output state in the first group of chips, the second group of chips, ... Mth group of chips is l1, l2, ..., lM.
  • the Q-11 controllable drive The first switch and the second switch in the unit send control signals, so that the main circuit in the Q-11 controllable drive units is in the stop output state, thereby setting the controllable drive units in the output state in each chip of the first group of chips
  • the quantity is l1.
  • controllable driving units in other groups of chips are set in the same way, and will not be repeated here.
  • the controllable drive unit in the working state can be controlled according to the size of the drive transistor in each drive unit, thereby adjusting the conduction rate of the bleeder transistor N0, and the number of adjustment levels of the conduction rate is more, which is conducive to selecting a better Static protection circuit.
  • the first switch and the second switch are one-time programmable memory, and the path between the control terminal of the first driving transistor and the first terminal of the monitoring capacitor is controlled by programming the one-time programmable memory. Disconnect, and control the disconnection of the path between the control terminal of the second drive transistor N1 and the first terminal of the monitoring capacitor C1, so that the controllable drive unit is switched from the output state to the stop output state, thereby realizing the electrostatic protection of the electrostatic protection circuit Capability adjustment, and then carry out electrostatic capability test on the chip.
  • electrostatic breakdown is usually in the case of power failure, it is not suitable to use the circuit to generate control signals to control the switch to close or open.
  • the work of the controllable drive unit can be switched by programming the one-time programmable device. state, adjust the electrostatic protection ability of the electrostatic protection circuit, and maintain the working state of the controllable drive unit 102 without making the chip in a charged state, so that it is convenient to obtain chips with different structures of electrostatic protection circuits through test requirements, and then conduct electrostatic on the chip Protection ability test.
  • the first switch and the second switch are laser fuse devices, and the general laser irradiates the laser fuse device in the controllable drive unit, so that the controllable drive unit switches from the output state to the stop output state, and realizes changing the chip The number of controllable drive units in the output state, so as to realize the electrostatic protection capability of the chip according to the test requirements.
  • an embodiment of the present disclosure provides an electrostatic protection circuit for a chip.
  • the electrostatic protection circuit for a chip includes a monitoring unit 101 , a plurality of controllable driving units 102 and a discharge transistor N0 .
  • a plurality of controllable driving units are marked as controllable driving unit 102-1, controllable driving unit 102-2, . . . and controllable driving unit 102-N, where N is a positive integer and N>1.
  • Only the driving unit 102-1 is shown in the figure, and the circuit structure of other driving units is the same as that of the driving unit 102-1, and will not be repeated here.
  • the structure of the monitoring unit 101 is the same as that in FIG. 4 , and will not be repeated here.
  • Each controllable driving unit 102 includes a main circuit 1022-1 and a control circuit 1021-1, and the control circuit 1021-1 further includes a first control sub-circuit 1023-1 and a second control sub-circuit 1024-1.
  • the main circuit 1022-1 is connected to the output terminal of the monitoring unit 101, the main circuit 1022-1 is connected to the power supply pad VDD through the first control sub-circuit 1023-1, and the main circuit 1022-1 is controlled by the first control sub-circuit 1023-1 and power supply pad VDD.
  • the main circuit 1022-1 is connected to the ground pad VSS through the second control sub-circuit 1024-1, and the path between the circuit and the ground pad VSS is controlled by the second control sub-circuit 1024-1.
  • the main circuit 1022-1 includes a first driving transistor P11 and a second driving transistor N11, the control terminal of the first driving transistor P11 is connected to the output terminal of the monitoring unit 101, and the control terminal of the second driving transistor N11 is also connected to The output terminal of the monitoring unit 101.
  • the second end of the first driving transistor P11 is connected to the first end of the second driving transistor N11 and then connected to the control end of the discharge transistor N0.
  • the first control sub-circuit 1023-1 includes a first control transistor P12, a third switch K13, and a fourth switch K14.
  • the first end of the first control transistor P12 is connected to the power pad VDD, and the second end of the first control transistor P12 is connected to
  • the first terminal of the first driving transistor P11 and the control terminal of the first control transistor P12 are connected to the power supply pad VDD through the third switch K13, and the control terminal of the first control transistor P12 is also connected to the ground pad VSS through the fourth switch K14.
  • the second control sub-circuit 1024-1 includes a second control transistor N112, a fifth switch K15 and a sixth switch K16, the first end of the second control transistor N112 is connected to the second end of the second driving transistor N11, and the second control transistor N112
  • the second end of the second drive transistor N11 is connected to the ground pad VSS
  • the control end of the second driving transistor N11 is connected to the power pad VDD through the fifth switch K15
  • the control end of the second driving transistor N11 is also connected to the ground pad VSS through the sixth switch K16.
  • the chips are divided into multiple groups, marked as the first group of chips, the second group of chips, the third group of chips, ..., and the Mth group of chips, and the number of chips in each group is Q.
  • the number of controllable drive units in the output state in the M group of chips is determined according to the test requirements. Assume that the number of controllable drive units in the output state in the first group of chips, the second group of chips, ... Mth group of chips is l1, l2, ..., lM.
  • the initial working state of the third switch and the fourth switch in each controllable drive unit of each chip disconnects the control terminal of the first control transistor from the ground pad and the power pad connected, and the initial working state of the fifth switch and the sixth switch makes the control terminal of the second control transistor disconnected from the ground pad and the power pad, and the fourth switch and the first
  • the five switches send control signals, and send control signals to the third switch and the sixth switch in the l1 controllable drive units, so that the main circuit in the Q-l1 controllable drive units is in the stop output state, so that the l1 controllable drive units
  • the main circuit in the driving unit is in the output state, so that the number of controllable driving units in the output state in the first group of chips is l1.
  • controllable driving units in other groups of chips are set in the same way, and will not be repeated here.
  • the first driving transistor P11 is a P-type transistor
  • the second driving transistor N11 and the discharge transistor N0 are N-type transistors.
  • the first control transistor P12 is a P-type transistor
  • the second control transistor N112 is an N-type transistor.
  • the size of the first control transistor P12 is the same as that of the first driving transistor P11, and the size of the second control transistor N112 is the same as that of the second driving transistor N11.
  • the third switch to the sixth switch are one-time programmable memories.
  • the third switch to the sixth switch are laser fuse devices.
  • the static electricity protection circuit further includes several uncontrollable driving units, and each uncontrollable driving unit includes a third driving transistor P3 and a fourth driving transistor N3.
  • the first end of the third drive transistor P3 is connected to the power supply pad VDD
  • the second end of the fourth drive transistor N3 is connected to the ground pad VSS
  • the second end of the third drive transistor P3 and the first end of the fourth drive transistor N3 are connected to each other. After being connected, it is connected to the control terminal of the discharge transistor N0.
  • the third driving transistor P3 is a P-type transistor
  • the fourth driving transistor N3 is an N-type transistor.
  • At least one driving signal must be generated in the electrostatic protection circuit to control the conduction of the discharge transistor N0.
  • an uncontrollable driving unit in the electrostatic protection circuit to provide the most basic driving signal, the number of switches used in the electrostatic protection circuit can be reduced , thereby simplifying the structure of the electrostatic protection circuit.
  • the present disclosure also provides a test method for the electrostatic protection capability of a chip, the test method comprising the following steps:
  • the chips are divided into several groups, and the controllable drive unit in the output state of each group of chips is determined according to the test requirements number of settings.
  • controllable drive units in the output state in each chip in any two groups of chips is different, and the number of controllable drive units in the output state in each chip in the same group of chips is the same.
  • each group of chips has 10 chips
  • the number of controllable drive units in the output state of the 10 chips in the first group of chips is 1, and the number of controllable drive units in the second group of 10 chips
  • the number of controllable drive units in the output state is 2, and the number of controllable drive units in the output state in the 10 chips in the third group of chips is 3.
  • control signal is used to switch the working state of the controllable driving unit.
  • the one-time programmable device is a laser fuse device
  • laser light is emitted to the corresponding laser fuse device to set the working state of each controllable driving unit in each chip.
  • S304 Perform an electrostatic test on several groups of chips, and determine an optimal number of controllable drive units in an output state according to the test results.
  • the number of controllable drive units in the output state in the chip with the best test results is obtained, and it is taken as the optimal number of controllable drive units in the output state, according to the number of controllable drive units in the output state
  • the optimal number design the electrostatic protection circuit of the chip so that the number of drive units in the electrostatic protection circuit is the optimal number of controllable drive units in the output state.
  • each test performance parameter of the chip can be divided into grades, the grade of each performance parameter of the chip is determined, and the grades of each performance parameter of the chip are weighted and averaged to obtain the performance grade of the chip.
  • the chip with the highest performance level is taken as the chip with the best test result.
  • a plurality of chips are produced through one tape-out, and the working state of the controllable driving unit is set for each group of chips, so as to ensure that the number of controllable driving units in the output state of each group of chips is different, so as to obtain different
  • the chip with electrostatic protection performance and then conduct electrostatic tests on the chip, and obtain the optimal electrostatic protection circuit according to the test results.
  • this solution only needs one-time tape-out. Reduce test cost and simplify test process.

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Abstract

本公开提供一种芯片的静电保护电路，包括监控单元，用于在电源焊盘上有静电脉冲时生成触发信号，多个可控驱动单元，其与监控单元连接，用于在控制信号的控制下切换工作状态，其中，工作状态包括输出状态，输出状态是指根据触发信号生成驱动信号，泄放晶体管，其与多个可控驱动单元连接，用于在驱动信号驱动下导通，以将静电电荷泄放至接地焊盘。本公开提供的芯片的静电保护电路的静电保护能力可调，可以在一次流片时制作多个芯片，并根据测试需求调节静电保护能力后再进行测试，无需通过多次流片调整芯片的静电保护能力，简化测试过程，降低测试成本。

Description

芯片的静电保护电路
本公开要求于2021年7月12日提交中国专利局、申请号为202110783134.5、申请名称为“芯片的静电保护电路”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种芯片的静电保护电路。
背景技术
静电无处不在，假如没有静电保护电路，一块芯片很快会被由于各种各样原因而引入静电所损伤，并且几乎会被一击致命。
因此，芯片中通常设有静电保护电路，静电保护电路用于及时泄放静电电荷，避免被保护电路由于承受静电电荷所带来高压而失效，甚至烧毁。
发明内容
本公开本公开提供一种芯片的静电保护电路，芯片包括电源焊盘和接地焊盘，静电保护电路包括：
监控单元，用于在电源焊盘上有静电脉冲时生成触发信号；
多个可控驱动单元，其与监控单元连接，用于在控制信号的控制下切换工作状态，其中，工作状态包括输出状态，输出状态是指根据触发信号生成驱动信号；
泄放晶体管，其与多个可控驱动单元连接，用于在驱动信号驱动下导通，以将静电电荷泄放至接地焊盘。
在一实施例中，每个可控驱动单元包括：
主电路，用于在处于输出状态时根据触发信号生成驱动信号；
控制电路，其与主电路连接，用于根据控制信号切换主电路的工作状态；其中，主电路的工作状态包括输出状态。
在一实施例中，主电路连接于电源焊盘和接地焊盘之间；
主电路通过控制电路与监控单元的输出端连接。
在一实施例中，主电路包括：
第一驱动晶体管，其第一端连接电源焊盘；
第二驱动晶体管，其第一端与第一驱动晶体管的第二端连接，其第二端连接接地焊盘。
在一实施例中，控制电路包括：
第一开关，其第一端与监控单元的输出端连接，其第二端连接第一驱动晶体管的控制端，用于在控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态；
第二开关，其第一端与监控单元的输出端连接，其第二端连接第二驱动晶体管的控制端，用于在控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态。
在一实施例中，主电路与监控单元的输出端连接；
主电路通过第一控制子电路与电源焊盘连接，主电路通过第二控制子电路与接地焊盘连接。
在一实施例中，主电路包括：
第一驱动晶体管，其控制端连接监控单元的输出端；
第二驱动晶体管，其第一端与第一驱动晶体管的第二端连接，其控制端连接监控单元的输出端。
在一实施例中，控制电路包括：
第一控制晶体管，其第一端连接电源焊盘；其第二端连接第一驱动晶体管的第一端；
第三开关，其第一端与电源焊盘连接，其第二端连接第一控制晶体管的控制端，用于在控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态；
第四开关，其第一端与连接第一控制晶体管的控制端，其第二端连接接地焊盘，用于在控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态。
在一实施例中，控制电路包括：
第二控制晶体管，其第一端连接第二驱动晶体管的第二端，其第二端连接接地焊盘；
第五开关，其第一端与电源焊盘连接，其第二端连接第二控制晶体管的控制端，用于在控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态；
第六开关，其第一端与连接第二控制晶体管的控制端，其第二端连接接地焊盘，用于在控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态。
在一实施例中，监控单元包括：
监控电阻，其第一端连接电源焊盘；
监控电容，其第一端连接监控电阻的第二端后作为监控单元的输出端，其第二端连接接地焊盘。
在一实施例中，第一驱动晶体管为P型晶体管，第二驱动晶体管和泄放晶体管为N型晶体管。
在一实施例中，第一控制晶体管为P型晶体管，第二控制晶体管为N型晶体管。
在一实施例中，第一控制晶体管的尺寸和第一驱动晶体管的尺寸相同，第二控制晶体管的尺寸和第二驱动晶体管的尺寸相同。
在一实施例中，第一开关至第六开关为一次性可编程存储器。
在一实施例中，第一开关至第六开关为激光熔丝器件。
本公开提供一种芯片的静电保护电路，包括监控单元、多个可控驱动单元以及泄放晶体管，监控单元用于监控电源焊盘上的静电脉冲，并在电源焊盘上存在静电脉冲时生成触发信号，可控驱动单元用于在控制信号的控制下根据触发信号生成驱动信号，泄放晶体管在若干个驱动信号的控制下导通，及时将电源焊盘上的静电脉冲泄放至接地焊盘，通过一次流片制作多个芯片，将芯片分成多组，为每组芯片设置不同的可生成驱动信号的可控驱动单元的数量，使得各组芯片的静电防护电路的静电防护能力不同，再使用设置后的芯片进行测试，以确定静电防护能力最优的静电防护电路，无需多次流片，降低静电防护测试的成本，简化芯片的静电防护测试过程。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为本公开一实施例提供的芯片的静电保护电路的具体电路图；
图2为本公开一实时提供的芯片的静电保护电路的结构框图；
图3为本公开另一实时提供的芯片的静电保护电路的结构框图；
图4为本公开另一实时提供的芯片的静电保护电路的结构框图；
图5为本公开一实时提供的芯片的静电保护电路的具体电路图；
图6为本公开一实时提供的芯片的静电保护电路的具体电路图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其 它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
图1为本公开一实施例提供芯片的静电保护电路，芯片包括电源焊盘VDD和接地焊盘VSS。静电保护电路包括监控单元101、驱动单元104以及泄放晶体管103。其中，监控单元101位于电源焊盘和接地焊盘之间，驱动单元104与监控单元101连接，驱动单元还与泄放晶体管连接。
监控单元101用于在电源焊盘VDD上有静电脉冲时生成触发信号，驱动单元104用于根据触发信号生成驱动信号，驱动信号用于控制泄放晶体管103导通，以及时将电源焊盘VDD上静电电荷泄放至接地焊盘VSS。
在一实施例中，监控单元101包括监控电阻R1和监控电容C1，监控电阻R1的第一端连接电源焊盘VDD，监控电容C1的第二端连接接地焊盘VSS，监控电阻R1的第二端与监控电容C1的第一端连接后与驱动单元101连接。
在一实施例中，驱动单元104包括第一驱动晶体管P1和第二驱动晶体管N1，第一驱动晶体管P1的第一端连接电源焊盘VDD，第二驱动晶体管N1的第二端连接接地焊盘VSS，第一驱动晶体管P1的第二端与第二驱动晶体管N1的第一端相互连接后与泄放晶体管103的控制端连接。
在电源焊盘VDD上有静电脉冲时，监控电容C1的阻抗急剧下降，监测电容C1的第一端V1的电压也下降，以控制第一驱动晶体管P1导通，第二驱动晶体管N1截止，第一驱动晶体管P1的第二端Vg的电压被拉至高电平，泄放晶体管N0也导通，由泄放晶体管N0将电源焊盘上的静电电荷泄放至接地焊盘VSS。
其中，第一驱动晶体管P1的尺寸大小和第二驱动晶体管N1的尺寸大小之间的比值决定第一驱动晶体管P1的第二端Vg的端电压，第一驱动晶体管P1的尺寸和第二驱动晶体管N1的尺寸的比值越大，驱动单元的上拉能力越强，泄放晶体管N0的泄放能力越强。然而，芯片在上电过程中的漏电也越大，因此，第一驱动晶体管P1的尺寸大小和第二驱动晶体管N1的尺寸大小的比值对于芯片的静电防护能力有比较大的影响，需要多次测试才能确定合适的比值。
此外，图1所示的静电防护电路通常需要与芯片的内部电路共同流片，才能测试出芯片的静电防护水平。若发现芯片的静电防护能力比较弱，则需要重新设计第一驱动晶体管P1的尺寸大小和第二驱动晶体管N1的尺寸大小，再通过流片后测试芯片的静电防护能力。
然而，芯片的流片成本昂贵，若在测试出芯片的静电防护能力比较弱时，需要重 新设计两个驱动晶体管的尺寸大小，再次流片后测试，导致测试过程复杂，测试成本也比较高。
本公开提供另一种芯片的静电保护电路，旨在降低芯片的静电防护的测试成本。本公开的技术构思是：在静电保护电路中设置多个可控驱动单元，在静电保护电路进行静电防护能力测试之前，通过控制信号设置静电保护电路中处于输出状态的可控驱动单元的数量，以实现设置泄放晶体管的泄放能力，从而实现设置静电保护电路的静电保护能力，通过一次流片制作多个芯片，根据测试需求设置静电防护电路的静电防护能力，获得多组不同静电防护能力的静电保护电路，无需多次流片，降低静电防护测试的成本，简化芯片的静电防护测试过程。
如图2所示，本公开提供一种芯片的静电保护电路，芯片包括电源焊盘201和接地焊盘202，静电保护电路包括监控单元101、多个可控驱动单元以及泄放晶体管103。其中，多个可控驱动单元标记为可控驱动单元101-1、可控驱动单元101-2、……以及可控驱动单元101-N，N为正整数，且N＞1。
监控单元101连接于电源焊盘201和接地焊盘202之间，监控单元101用于在电源焊盘201上有静电脉冲时生成触发信号。可控驱动单元102-1、可控驱动单元101-2、……以及可控驱动单元101-N均与监控单元101连接，各个可控驱动单用于在控制信号切换工作状态。
其中，控制信号可以是不受芯片断电影响的电信号或者其他信号，例如：激光信号。当可控驱动单元能够根据触发信号输出驱动信号时，可控驱动单元处于输出状态。当可控驱动单元无法输出驱动信号时，可控驱动单元处于停止输出状态。
针对任意的可控驱动单元，控制信号可以切换可控驱动单元的工作状态，例如：使可控驱动单元从输出状态切换到停止输出状态。在控制信号改变可控驱动单元的工作状态后，可控驱动单元不需要控制信号维持该工作状态，以保证在测试过程中芯片处于断电状态时芯片中的可控驱动单元的工作状态会保持不变。
泄放晶体管103与各个可控驱动单元连接，泄放晶体管103用于在驱动信号的驱动下导通，以将静电电荷泄放至接地焊盘202，泄放晶体管103接收到的驱动信号的数量越多，泄放晶体管103的导通速率越快，泄放晶体管103的泄放能力越强，整个静电保护电路的静电防护能力越强。
通过一次流片时制作多个芯片，将芯片分成多组，在静电测试前，通过控制信号切换可控驱动单元的工作状态，使每组芯片中处于输出状态的可控驱动单元的数量不同，各组芯片中泄放晶体管103的导通速率也就不同，而导通速率会影响泄放晶体管103的泄放速率，实现各组芯片的静电防护电路的静电防护能力不同，再使用设置后的芯片进行测试，从中选择出静电防护能力最优的静电防护电路，无需多次流片，可 实现降低静电防护测试的成本，简化芯片的静电防护测试过程。
在一实施例中，参考图3，以可控驱动单元102-1为例描述可控驱动单元内的电路结构，其他可控单元与可控驱动单元102-1相同，此处不再赘述。可控驱动单元102-1包括主电路1022-1和控制电路1021-1，主电路1022-1与监控单元101连接，控制电路1021-1与主电路1022-1连接，主电路1022-1在控制电路1021-1的控制下切换工作状态，例如：主电路根据触发信号生成驱动信号的工作状态称为输出状态，主电路不输出驱动信号的工作状态称为停止输出状态，更具体地，控制信号切换控制电路1021-1的工作状态，控制电路1021-1的工作状态切换使主电路从输出状态切换至停止输出状态，或者使主电路从停止输出状态切换至输出状态。
在一实施例中，继续参考图3所示，主电路1022-1连接于电源焊盘201和接地焊盘202之间，主电路1022-1通过控制电路1021-1与监控单元101的输出端连接，控制电路1021-1可以使主电路1022-1和监控单元101之间的路径连通或断开。当控制信号切换控制电路1021-1的工作状态，使控制电路1021-1处于让主电路1022-1和监控单元101之间的路径连通的工作状态时，主电路1022-1处于输出状态。当控制信号切换控制电路1021-1的工作状态，使控制电路1021-1处于让主电路1022-1和监控单元101之间的路径断开的工作状态时，主电路1022-1处于停止输出状态。
通过在主电路1022-1和监控单元101的输出端之间设置控制电路1021-1，根据测试需求设置控制电路的工作状态，以使主电路1022-1与监控单元101之间的路径断开或连通，以固化可控驱动单元的工作状态，从而实现根据测试需求设置静电保护电路的静电保护能力。
在一实施例中，参考图4，以可控驱动单元102-1为例描述可控驱动单元内的电路结构，其他可控单元与可控驱动单元102-1相同，此处不再赘述。可控驱动单元102-1包括主电路1022-1和控制电路1021-1，主电路1022-1与监控单元101连接，控制电路1021-1与主电路1022-1连接，控制电路1021-1包括第一控制子电路1023-1和第二控制子电路1024-1，主电路1022-1通过第一控制子电路1023-1与电源焊盘201连接，主电路1022-1通过第二控制子电路1024-1与接地焊盘202连接。
第一控制子电路1023-1和第二控制子电路1024-1可以使主电路1022-1和电源焊盘201、接地焊盘202之间的路径连通或断开，当控制信号切换第一控制子电路1023-1和第二控制子电路1024-1的工作状态，使第一控制子电路1023-1和第二控制子电路1024-1处于让主电路1022-1和电源焊盘201、接地焊盘202之间的路径连通的工作状态时，主电路1022-1处于输出状态。当控制信号切换第一控制子电路1023-1和第二控制子电路1024-1的工作状态，使第一控制子电路1023-1和第二控制子电路1024-1处于让主电路1022-1和电源焊盘201、接地焊盘202之间的路径断开的工作状态时， 主电路1022-1处于停止输出状态。
通过在主电路1022-1和电源焊盘201之间设置第一控制子电路1023-1，在主电路1022-1和接地焊盘202之间设置第二控制子电路1024-1，根据测试需求设置第一控制子电路1023-1和第二控制子电路1024-1的工作状态，以控制主电路1022-1、电源焊盘201和接地焊盘202之间的路径连通或断开，实现固化可控驱动单元的工作状态，从而实现根据测试需求设置静电保护电路的静电保护能力。
如图5所示，本公开一实施例提供一种芯片的静电保护电路，该芯片的静电保护电路包括监控单元101、多个可控驱动单元以及泄放晶体管N0。其中，多个可控驱动单元标记为可控驱动单元102-1、可控驱动单元102-2、……以及可控驱动单元102-N，N为正整数，且N＞1。图中仅示出驱动单元102-1和驱动单元102-2，其他驱动单元的电路结构同驱动单元102-1和驱动单元102-2相同，此处不再赘述。
其中，监控单元101包括监控电容C1和监控电阻R1，监控电容C1设有第一端和第二端，监控电阻R1也设有第一端和第二端，监控电阻R1的第一端连接电源焊盘VDD，监控电容C1的第二端连接接地焊盘VSS，监控电阻R1的第二端和监控电容C1的第一端V1相互连接后作为监控单元101的输出端。
下面以可控驱动单元102-1为例说明其电路结构和工作原理。
可控驱动单元102-1包括主电路1022-1和控制电路1021-1，主电路1022-1通过控制电路1021-1与监控单元101的输出端连接。
在一实施例中，主电路1022-1包括第一驱动晶体管P11和第二驱动晶体管N11，第一驱动晶体管P11和第二驱动晶体管N11设有第一端、第二端以及控制端。
第一驱动晶体管P11的第一端连接电源焊盘VDD，第二驱动晶体管N11的第二端连接接地焊盘VSS，第一驱动晶体管P11的第二端和第二驱动晶体管N11的第一端相互连接后与泄放晶体管N0的控制端连接，第一驱动晶体管P11的控制端和第二驱动晶体管N11的控制端相互连接后通过控制电路1021-1与监控单元101的输出端连接。
在一实施例中，控制电路1021-1包括第一开关K11和第二开关K12。其中，第一开关K11和第二开关K12均设有第一端和第二端。
第一开关K11的第一端与监控单元101的输出端连接，第一开关K11的第二端连接第一驱动晶体管P11的控制端，第一开关K11用于在控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态。
第二开关K12的第一端与监控单元101的输出端连接，第二开关K12的第二端连接第二驱动晶体管N11的控制端，第二开关K12用于在控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态。
第一驱动晶体管P11和第二驱动晶体管N11在触发信号的控制下拉动第二驱动晶体管N11的第二端Vg的电压，从而实现控制泄放晶体管N0的导通或截止。
在一实施例中，第一驱动晶体管P11为P型晶体管，第二驱动晶体管N11和泄放晶体管N0为N型晶体管。
在一实施例中，泄放晶体管N0的尺寸大于第二驱动晶体管N11的尺寸。
在一实施例中，第k个可控驱动单元中的第一驱动晶体管的尺寸为第k-1个可控驱动单元中的第一驱动晶体管的尺寸的2倍，也就是当第k个可控驱动单元中的第一驱动晶体管输出的驱动电流为2 k×i b1，第k-1个可控驱动单元中的第一驱动晶体管输出的驱动电流为2 k-1×i b1。其中，i b1为电流基准值。
在一实施例中，第k个可控驱动单元中的第二驱动晶体管的尺寸为第k-1个可控驱动单元中的第二驱动晶体管的尺寸的2倍，也就是当第k个可控驱动单元中的第二驱动晶体管输出的驱动电流为2 k×i b2，第k-1个可控驱动单元中的第二驱动晶体管输出的驱动电流为2 k-1×i b2。其中，i b2为电流基准值。
在经过一次流片制造出多个芯片后，将芯片分成多组，标记为第一组芯片、第二组芯片、第三组芯片、……、以及第M组芯片，每组芯片的数量为Q个。此处仅仅是举例说明，各组芯片的数量也可以不同。
根据测试需求确定M组芯片中处于输出状态的可控驱动单元的数量。假设第一组芯片、第二组芯片、……第M组芯片中处于输出状态的可控驱动单元的数量为l1、l2，……，lM。
在测试前，针对第一组芯片，当每个芯片的各可控驱动单元中的第一开关和第二开关的初始工状态使主电路1022处于输出状态时，向Q-l1个可控驱动单元中的第一开关和第二开关发送控制信号，使Q-l1个可控驱动单元中主电路处于停止输出状态，从而设置第一组芯片的各个芯片中处于输出状态的可控驱动单元的数量为l1。当每个芯片的各可控驱动单元中的第一开关和第二开关的初始工状态使主电路1022处于停止输出状态时，向l1个可控驱动单元中的第一开关和第二开关发送控制信号，以使l1个可控驱动单元中主电路处于输出状态，从而设置第一组芯片的各个芯片中处于输出状态的可控驱动单元的数量为l1。
其它组芯片内可控驱动单元的设置方式相同，此处不在赘述。
在设置完各组芯片中处于输出状态的可控驱动单元的数量后，对各组芯片进行静电保护测试，从各组芯片中确定静电保护能力最优的静电保护电路。
在各可控驱动单元中第一驱动晶体管的尺寸不同，且第k个可控驱动单元中的驱动晶体管的尺寸为第k-1个可控驱动单元中对应的驱动晶体管的尺寸的2倍时，可以根据各驱动单元中的驱动晶体管的尺寸控制处于工作状态的可控驱动单元，从而调整 泄放晶体管N0的导通速率，且导通速率的调节档数更多，有利于选择更优的静电保护电路。
在一实施例中，第一开关和第二开关为一次性可编程存储器，通过对一次性可编程存储器进行编程控制，以控制第一驱动晶体管的控制端和监控电容的第一端之间路径断开，以及控制第二驱动晶体管N1的控制端和监控电容C1的第一端之间路径断开，使可控驱动单元从输出状态切换至停止输出状态，从而实现对静电保护电路的静电保护能力的调节，再对芯片进行静电能力测试。
由于静电击穿通常在断电情况下，利用电路生成控制信号以控制开关闭合或断开无法适用于芯片处于断电情况下，通过对一次性可编程器件进行编程控制切换可控驱动单元的工作状态，调整静电保护电路的静电保护能力，无需使芯片处于带电状态即可实现维持可控驱动单元102的工作状态，便于通过测试需求获得具有不同结构的静电保护电路的芯片，再对芯片进行静电保护能力测试。
在一实施例中，第一开关和第二开关为激光熔丝器件，通用激光照射可控驱动单元中的激光熔丝器件，使可控驱动单元从输出状态切换至停止输出状态，实现改变芯片中处于输出状态的可控驱动单元的数量，从而实现根据测试需求设置芯片的静电保护能力。
如图6所示，本公开一实施例提供一种芯片的静电保护电路，该芯片的静电保护电路包括监控单元101、多个可控驱动单元102以及泄放晶体管N0。其中，多个可控驱动单元标记为可控驱动单元102-1、可控驱动单元102-2、……以及可控驱动单元102-N，N为正整数，且N＞1。图中仅示出驱动单元102-1，其他驱动单元的电路结构同驱动单元102-1相同，此处不再赘述。
监控单元101的结构同图4中相同，此处不再赘述。
每个可控驱动单元102包括主电路1022-1和控制电路1021-1，控制电路1021-1又包括第一控制子电路1023-1和第二控制子电路1024-1。主电路1022-1与监控单元101的输出端连接，主电路1022-1通过第一控制子电路1023-1与电源焊盘VDD连接，由第一控制子电路1023-1控制主电路1022-1和电源焊盘VDD之间的路径。主电路1022-1通过第二控制子电路1024-1与接地焊盘VSS连接，由第二控制子电路1024-1控制住电路和接地焊盘VSS之间的路径。
在一实施例中，主电路1022-1包括第一驱动晶体管P11和第二驱动晶体管N11，第一驱动晶体管P11的控制端连接监控单元101的输出端，第二驱动晶体管N11的控制端也连接监控单元101的输出端。第一驱动晶体管P11的第二端与第二驱动晶体管N11的第一端连接后再连接后与泄放晶体管N0的控制端连接。
第一控制子电路1023-1包括第一控制晶体管P12、第三开关K13以及第四开关 K14，第一控制晶体管P12的第一端连接电源焊盘VDD，第一控制晶体管P12的第二端连接第一驱动晶体管P11的第一端，第一控制晶体管P12的控制端通过第三开关K13连接电源焊盘VDD，第一控制晶体管P12的控制端还通过第四开关K14连接接地焊盘VSS。
第二控制子电路1024-1包括第二控制晶体管N112、第五开关K15以及第六开关K16，第二控制晶体管N112的第一端连接第二驱动晶体管N11的第二端，第二控制晶体管N112的第二端连接接地焊盘VSS，第二驱动晶体管N11的控制端通过第五开关K15连接电源焊盘VDD，第二驱动晶体管N11的控制端还通过第六开关K16连接接地焊盘VSS。
在经过一次流片制造出多个芯片后，将芯片分成多组，标记为第一组芯片、第二组芯片、第三组芯片、……、以及第M组芯片，每组芯片的数量为Q个。
根据测试需求确定M组芯片中处于输出状态的可控驱动单元的数量。假设第一组芯片、第二组芯片、……第M组芯片中处于输出状态的可控驱动单元的数量为l1、l2，……，lM。
在测试前，针对第一组芯片，当每个芯片的各可控驱动单元中第三开关和第四开关的初始工状态使第一控制晶体管的控制端与接地焊盘和电源焊盘连接，且第五开关和第六开关的初始工状态使第二控制晶体管的控制端与接地焊盘和电源焊盘连接，向l1个可控驱动单元中的第四开关和第五开关发送控制信号，向Q-l1个可控驱动单元中的第三开关和第六开关发送控制信号，以使Q-l1个可控驱动单元中主电路处于停止输出状态，以使l1个可控驱动单元中主电路处于输出状态，以使第一组芯片中处于输出状态的可控驱动单元的数量为l1。
在测试前，针对第一组芯片，当每个芯片的各可控驱动单元中第三开关和第四开关的初始工状态使第一控制晶体管的控制端与接地焊盘和电源焊盘断开连接，且第五开关和第六开关的初始工状态使第二控制晶体管的控制端与接地焊盘和电源焊盘断开连接，向Q-l1个可控驱动单元中的第四开关和第五开关发送控制信号，向l1个可控驱动单元中的第三开关和第六开关发送控制信号，以使Q-l1个可控驱动单元中主电路处于停止输出状态，以使l1个可控驱动单元中主电路处于输出状态，以使第一组芯片中处于输出状态的可控驱动单元的数量为l1。
其它组芯片内可控驱动单元的设置方式相同，此处不在赘述。
在设置完各组芯片中处于输出状态的可控驱动单元的数量后，对各组芯片进行静电保护测试，以从各组芯片中确定静电保护能力最优的静电保护电路。
在一实施例中，第一驱动晶体管P11为P型晶体管，第二驱动晶体管N11和泄放晶体管N0为N型晶体管。第一控制晶体管P12为P型晶体管，第二控制晶体管N112 为N型晶体管。
在一实施例中，第一控制晶体管P12的尺寸和第一驱动晶体管P11的尺寸相同，第二控制晶体管N112的尺寸和第二驱动晶体管N11的尺寸相同。通过如此设置，可以充分利用控制晶体管和驱动晶体管的通流能力。
在一实施例中，第三开关至第六开关为一次性可编程存储器。
在一实施例中，第三开关至第六开关为激光熔丝器件。
在一实施例中，静电保护电路还包括若干个不可控驱动单元，每个不可控驱动单元包括第三驱动晶体管P3和第四驱动晶体管N3。第三驱动晶体管P3的第一端连接电源焊盘VDD，第四驱动晶体管N3的第二端连接接地焊盘VSS，第三驱动晶体管P3的第二端和第四驱动晶体管N3的第一端相互连接后与泄放晶体管N0的控制端连接。
在一实施例中，第三驱动晶体管P3为P型晶体管，第四驱动晶体管N3为N型晶体管。
静电保护电路中至少要生成一个驱动信号，以控制泄放晶体管N0导通，通过在静电保护电路中设置不可控驱动单元用于提供最基础的驱动信号，可以减少静电保护电路中使用开关的数量，从而简化静电保护电路的结构。
本公开还提供一种芯片的静电保护能力的测试方法，该测试方法包括如下步骤：
S301、获取若干组芯片中的各芯片中的处于输出状态的可控驱动单元的设置数量。
在该步骤中，在一次流片制作包含有上述实施例所描述的静电保护电路的若干芯片后，将若干芯片分成若干组，并根据测试需求确定每组芯片中处于输出状态的可控驱动单元的设置数量。
其中，任意两组芯片中的各芯片中的处于输出状态的可控驱动单元的数量不同，同一组芯片中的各芯片中的处于输出状态的可控驱动单元的数量相同。
例如：在3组芯片中，每组芯片有10个芯片，第一组芯片中的10个芯片中处于输出状态的可控驱动单元的数量均为1个，第二组芯片中的10个芯片中处于输出状态的可控驱动单元的数量均为2个，第三组芯片中的10个芯片中处于输出状态的可控驱动单元的数量均为3个。
S302、根据若干组芯片中的各芯片中的处于输出状态的可控驱动单元的设置数量生成若干组芯片中的各芯片的控制信号。
在该步骤中，控制信号用于切换可控驱动单元的工作状态。
S303、向若干组芯片中的各芯片发送控制信号，以设置各芯片中处于输出状态的可控驱动单元的数量为设置数量。
在该步骤中，当芯片中各可控驱动单元内的开关为一次性可编程器时，向对应的 一次性可编程器发送控制信号，以设置各芯片中各可控驱动单元的工作状态。
在一实施例中，若一次性可编程器为激光熔丝器件时，向对应的激光熔丝器件发射激光，以设置各芯片中各可控驱动单元的工作状态。
S304、对若干组芯片进行静电测试，并根据测试结果确定处于输出状态的可控驱动单元的最优数量。
在该步骤中，获取测试结果最优的芯片内处于输出状态的可控驱动单元的数量，将其作为处于输出状态的可控驱动单元的最优数量，根据处于输出状态的可控驱动单元的最优数量设计芯片的静电保护电路，以使该静电保护电路中驱动单元的数量为处于输出状态的可控驱动单元的最优数量。
在评估测试结果时，可以对芯片的各个测试性能参数划分等级，确定芯片的各性能参数所在等级，并对芯片的各性能参数所在等级进行加权平均，获得芯片的性能等级。将性能等级最高的芯片作为测试结果最优的芯片。
在上述技术方案中，通过一次流片制作出多个芯片，并为各组芯片设置可控驱动单元的工作状态，保证各组芯片处于输出状态的可控驱动单元的数量不同，以获得具有不同静电保护性能的芯片，再对芯片进行静电测试，并根据测试结果获得最优的静电保护电路，相较于采用多次流片更新芯片静电保护能力的方式，本方案采用一次流片即可，降低测试成本，简化测试流程。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (15)

  1. 一种芯片的静电保护电路，所述芯片包括电源焊盘和接地焊盘，所述静电保护电路包括：
    监控单元，用于在所述电源焊盘上有静电脉冲时生成触发信号；
    多个可控驱动单元，其与所述监控单元连接，用于在控制信号的控制下切换工作状态，其中，所述工作状态包括输出状态，所述输出状态是指根据所述触发信号生成驱动信号；
    泄放晶体管，其与所述多个可控驱动单元连接，用于在驱动信号驱动下导通，以将静电电荷泄放至所述接地焊盘。
  2. 根据权利要求1所述的静电保护电路，其中，每个可控驱动单元包括：
    主电路，用于在处于输出状态时根据所述触发信号生成驱动信号；控制电路，其与所述主电路连接，用于根据所述控制信号切换所述主电路的工作状态；其中，所述主电路的工作状态包括输出状态。
  3. 根据权利要求2所述的静电保护电路，其中，
    所述主电路连接于所述电源焊盘和所述接地焊盘之间；
    所述主电路通过所述控制电路与所述监控单元的输出端连接。
  4. 根据权利要求3所述的静电保护电路，其中，所述主电路包括：
    第一驱动晶体管，其第一端连接所述电源焊盘；
    第二驱动晶体管，其第一端与所述第一驱动晶体管的第二端连接，其第二端连接所述接地焊盘。
  5. 根据权利要求4所述的静电保护电路，其中，所述控制电路包括：
    第一开关，其第一端与所述监控单元的输出端连接，其第二端连接所述第一驱动晶体管的控制端，用于在所述控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态；
    第二开关，其第一端与所述监控单元的输出端连接，其第二端连接所述第二驱动晶体管的控制端，用于在所述控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态。
  6. 根据权利要求2所述的静电保护电路，其中，控制电路包括第一控制子电路和第二控制子电路；
    所述主电路与所述监控单元的输出端连接；
    所述主电路通过所述第一控制子电路与所述电源焊盘连接，所述主电路通过所述第二控制子电路与所述接地焊盘连接。
  7. 根据权利要求6所述的静电保护电路，其中，所述主电路包括：
    第一驱动晶体管，其控制端连接监控单元的输出端；
    第二驱动晶体管，其第一端与所述第一驱动晶体管的第二端连接，其控制端连接监控单元的输出端。
  8. 根据权利要求7所述的静电保护电路，其中，所述第一控制子电路包括：
    第一控制晶体管，其第一端连接所述电源焊盘；其第二端连接所述第一驱动晶体管的第一端；
    第三开关，其第一端与所述电源焊盘连接，其第二端连接所述第一控制晶体管的控制端，用于在所述控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态；
    第四开关，其第一端与连接所述第一控制晶体管的控制端，其第二端连接所述接地焊盘，用于在所述控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态。
  9. 根据权利要求8所述的静电保护电路，其中，所述第二控制子电路包括：
    第二控制晶体管，其第一端连接所述第二驱动晶体管的第二端，其第二端连接所述接地焊盘；
    第五开关，其第一端与所述电源焊盘连接，其第二端连接所述第二控制晶体管的控制端，用于在所述控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态；
    第六开关，其第一端与连接所述第二控制晶体管的控制端，其第二端连接所述接地焊盘，用于在所述控制信号控制下从闭合状态切换到断开状态，或从断开状态切换到闭合状态。
  10. 根据权利要求1至9中任意一项所述的静电保护电路，其中，所述监控单元包括：
    监控电阻，其第一端连接所述电源焊盘；
    监控电容，其第一端连接所述监控电阻的第二端后作为所述监控单元的输出端，其第二端连接所述接地焊盘。
  11. 根据权利要求4或7所述的静电保护电路，其中，所述第一驱动晶体管为P型晶体管，所述第二驱动晶体管和所述泄放晶体管为N型晶体管。
  12. 根据权利要求8或9所述的静电保护电路，其中，第一控制晶体管为P型晶体管，第二控制晶体管为N型晶体管。
  13. 根据权利要求12所述的静电保护电路，其中，所述第一控制晶体管的尺寸和第一驱动晶体管的尺寸相同，所述第二控制晶体管的尺寸和第二驱动晶体管的尺寸相同。
  14. 根据权利要求5、8或9所述的静电保护电路，其中，第一开关至第六开关为一次性可编程存储器。
  15. 根据权利要求14所述的静电保护电路，其中，所述第一开关至第六开关为激光熔丝器件。
PCT/CN2022/088845 2021-07-12 2022-04-24 芯片的静电保护电路 WO2023284360A1 (zh)

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CN113097206A (zh) * 2021-04-01 2021-07-09 长鑫存储技术有限公司 静电保护电路及静电保护网络

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US20020191358A1 (en) * 2001-06-18 2002-12-19 Jian-Hsing Lee Electrostatic discharge protection device
US20080123229A1 (en) * 2006-06-30 2008-05-29 Nak Heon Choi Device for discharging static electricity
CN101884103A (zh) * 2007-07-30 2010-11-10 Toumaz科技有限公司 静电放电保护电路
CN103683235A (zh) * 2012-09-24 2014-03-26 上海华虹宏力半导体制造有限公司 静电放电自保护电路
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