WO2023004593A1 - 用于对电路进行仿真的方法、介质、程序产品以及电子设备 - Google Patents

用于对电路进行仿真的方法、介质、程序产品以及电子设备 Download PDF

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WO2023004593A1
WO2023004593A1 PCT/CN2021/108728 CN2021108728W WO2023004593A1 WO 2023004593 A1 WO2023004593 A1 WO 2023004593A1 CN 2021108728 W CN2021108728 W CN 2021108728W WO 2023004593 A1 WO2023004593 A1 WO 2023004593A1
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simulation
reinforcement
rule
rules
rewards
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PCT/CN2021/108728
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English (en)
French (fr)
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李定
冯怡珺
邓文平
胡贻升
方尚侠
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华为技术有限公司
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Priority to PCT/CN2021/108728 priority Critical patent/WO2023004593A1/zh
Publication of WO2023004593A1 publication Critical patent/WO2023004593A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B17/00—Systems involving the use of models or simulators of said systems
    • G05B17/02—Systems involving the use of models or simulators of said systems electric

Definitions

  • Embodiments of the present disclosure relate generally to the field of electronic circuits, and more particularly to methods, media, program products, and electronic devices for simulating circuits.
  • EDA electronic equipment of major electronic design automation
  • SPICE integrated circuit emphasis
  • the embodiments of the present disclosure aim to provide a solution for reducing the time required for circuit simulation.
  • a method for simulating a circuit includes first simulating the circuit using a plurality of rules to determine a plurality of rewards corresponding to a plurality of simulation time periods; determining a target rule based at least on the plurality of rewards; and performing a second simulation of the circuit using the target rule.
  • reinforcement learning to collect and analyze parameters such as the simulation step size and simulation time of the circuit under multiple rules, and give corresponding rewards for multiple rules, it can be determined according to the rewards corresponding to each rule after a period of time target rules.
  • the circuit simulation using the determined target rule can have a relatively ideal simulation step size and a high simulation success rate, so the calculation amount of the electronic device can be greatly reduced and the time required for circuit simulation can be correspondingly reduced.
  • the plurality of simulation periods includes a plurality of initial simulation periods and a plurality of intensive simulation periods subsequent to the plurality of initial simulation periods
  • the plurality of rewards includes a plurality of rewards corresponding to the plurality of initial simulation periods.
  • an initial reward and a plurality of reinforcement rewards corresponding to a plurality of reinforcement simulation time periods and performing a first simulation on the circuit using a plurality of rules to determine a plurality of rewards corresponding to a plurality of simulation time periods comprises: using a plurality of rules to sequentially simulate the circuit performing a simulation to obtain a plurality of initial rewards respectively corresponding to a plurality of initial simulation time periods of the plurality of simulation time periods; selecting one of a plurality of rules to use during the plurality of reinforcement simulation time periods based at least on the plurality of initial rewards or a plurality of rules; and simulating the circuit using the selected one or more rules to determine a plurality of reinforcement rewards corresponding to a plurality of reinforcement simulation time periods.
  • all the rules can be
  • the initial reward represents an iteration time corresponding to the rule determined based at least on the number of iterations and the initial simulation time period.
  • the iteration time is inversely proportional to the number of iterations performed by the electronic device in a unit simulation time period. A lower number of iterations generally means a faster simulation speed for the same simulation time period. Therefore, the speed of simulation using each rule can be measured by this initial reward.
  • selecting from a plurality of rules based at least on a plurality of initial rewards, one or more rules to use during the plurality of intensive simulation time periods includes: selecting from the plurality of rules the largest initial The rule corresponding to the award is used as the rule used during a first intensive simulation period of the plurality of intensive simulation periods. In this way, the best rule that can be determined based on the current information can be preferentially used to simulate the circuit during the first intensive simulation time period, so as to reduce the time required for circuit simulation.
  • selecting one or more rules from the plurality of rules based at least on the plurality of initial rewards for use during the plurality of reinforcement simulation time periods includes: based on the current set of reinforcement rewards corresponding to the current reinforcement simulation time period, Select a rule to be used in the next reinforcement simulation period after the current reinforcement simulation period, and the current reinforcement reward set includes a plurality of current reinforcement rewards derived from a plurality of initial rewards and respectively corresponding to the plurality of rules.
  • the simulation acceleration effects of multiple rules can be continuously evaluated during the reinforcement simulation time period in order to select the most appropriate rule based on the current set of reinforcement rewards.
  • selecting from a plurality of rules a rule to use for the next reinforcement simulation time period after the current reinforcement simulation time period based on the current reinforcement reward set corresponding to the current reinforcement simulation time period includes: selecting from a plurality of rules The rule with the largest reinforcement reward in the current reinforcement reward set is used as the rule for the next reinforcement simulation session.
  • the rate of circuit simulation is optimized by enabling the application of the rule that is predicted to achieve the best simulation acceleration based on historical information in the next hardened simulation time period.
  • the method further includes: updating the current reinforcement reward set using the current reinforcement reward determined according to the current rules and corresponding to the current simulation time period.
  • updating the current reinforcement reward set the evaluation of the simulation acceleration effect of each rule can be updated in real time, so that the most suitable rule for the current simulation situation can be selected in real time.
  • simulating the circuit using the determined one or more rules to determine a plurality of reinforcement rewards corresponding to a plurality of reinforcement simulation time periods includes: using one of the determined one or more rules to The circuit simulates to determine a number of iterations corresponding to an intensive simulation period of the plurality of intensive simulation periods; and based at least on the number of iterations and the one intensive simulation period, determines an intensive reward corresponding to the one intensive simulation period.
  • the simulation speed using each rule can be evaluated using the number of iterations performed in a unit simulation time period.
  • determining a reinforcement reward corresponding to a reinforcement simulation period based at least on the number of iterations and a reinforcement simulation period includes: determining an average iteration time corresponding to a rule based on at least the number of iterations and a reinforcement simulation period; The number of times a rule is used determines a weighted value; and based on the average iteration time and the weighted value, a reinforced reward corresponding to a reinforced simulation time period is determined.
  • determining the target rule based at least on the plurality of rewards includes: in response to the plurality of rewards corresponding to the plurality of consecutive time periods being obtained using the same rule and the aggregate time length of the plurality of consecutive time periods exceeding a time threshold, Identify the same rule as the target rule. In this way, a rule that is continuously used for a longer period of time can be determined as a target rule. Continuous use of the same rule for a longer period of time means that the rule can lead to a faster simulation speed than other rules. Therefore, by determining this rule as a target rule for subsequent simulation of the circuit, the time required for circuit simulation can be reduced.
  • determining the target rule based at least on the plurality of rewards includes responding to the plurality of rewards corresponding to the plurality of consecutive time periods being derived using the same rule and the number of time periods for the plurality of consecutive time periods exceeding the number of time periods Threshold to identify identical rules as target rules.
  • a rule that is continuously used for a long period of time can be determined as a target rule. Continuous use of the same rule for a longer period of time means that the rule can lead to a faster simulation speed than other rules. Therefore, by determining this rule as a target rule for subsequent simulation of the circuit, the time required for circuit simulation can be reduced.
  • the plurality of rules includes: If the number of iterations using a simulation step during a simulation time period exceeds an iteration count threshold using one of the plurality of rules, set a simulation step shortened by the first factor. In this way, it is possible to limit the number of iterations performed using a specific simulation step size, thereby reducing the time required for circuit simulation. In addition, since the selection of the simulation step size will directly affect the efficiency of the circuit simulation, the optimization of the circuit simulation efficiency can be realized by adjusting the simulation step size according to the number of iterations.
  • the plurality of rules further includes: if the truncation error using one simulation step during a simulation time period is not greater than the truncation error threshold using one rule, then using a simulation step with a second Factor scaling, where the second factor is different from the first factor.
  • the truncation error With the help of the truncation error, the accuracy of the result of solving the equation system can be evaluated, so that the accuracy of the circuit simulation can be optimized.
  • the optimization of the circuit simulation efficiency can be achieved by adjusting the simulation step size with different factors according to the truncation error.
  • each rule of the plurality of rules has a first factor and a second factor that is different from another rule of the plurality of rules.
  • each rule of the plurality of rules has a first factor and a second factor that are different from any of the remaining rules of the plurality of rules.
  • the method further includes reading in a netlist input by the user, and the netlist defines the connection relationship of each component in the circuit designed by the user.
  • the netlist defines the connection relationship of each component in the circuit designed by the user.
  • the method also includes establishing a system of equations based on the simulated circuit and Kirchhoff's laws. In this way, a set of equations that can describe the circuit to be simulated can be obtained.
  • the method also includes converting the continuous-time variable to a discrete-time variable using a numerical integration method.
  • the nonlinear differential equations can be discretized in time, so that the difference equations can be used to approximate the nonlinear differential equations that are usually difficult to solve directly.
  • the method also includes solving the system of difference equations using Newton's iterative method.
  • the task of solving a system of difference equations can be adapted to be performed by an electronic device such as a computer.
  • a computer-readable storage medium storing one or more programs.
  • One or more programs are configured for execution by one or more processors.
  • the one or more programs include instructions for performing the method according to the first aspect.
  • reinforcement learning can be used to collect and analyze parameters such as the simulation step size and simulation time of the circuit under multiple rules, and give After a period of time, the target rule can be determined according to the reward corresponding to each rule.
  • the circuit simulation using the determined target rules can have a relatively ideal simulation step size and a high simulation success rate, so it can greatly reduce the calculation amount of electronic equipment and correspondingly reduce the time required for circuit simulation.
  • a computer program product includes one or more programs.
  • One or more programs are configured for execution by one or more processors.
  • the one or more programs include instructions for performing the method according to the first aspect.
  • reinforcement learning can be used to collect and analyze parameters such as the simulation step size and simulation time of the circuit under multiple rules, and corresponding rewards can be given for multiple rules, and after a period of time, according to each
  • the target rule is determined by the reward corresponding to the rule.
  • the circuit simulation using the determined target rule can have a relatively ideal simulation step size and a high simulation success rate, so the calculation amount of the electronic device can be greatly reduced and the time required for circuit simulation can be correspondingly reduced.
  • an electronic device for simulating a circuit comprises: one or more processors; and a memory comprising computer instructions which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of the first aspect.
  • the electronic device uses reinforcement learning to collect and analyze parameters such as the simulation step size and simulation time of the circuit under multiple rules, and gives corresponding rewards for multiple rules. After a period of time, it can Rewards to determine target rules.
  • the circuit simulation using the determined target rule can have a relatively ideal simulation step size and a high simulation success rate, so the calculation amount of the electronic device can be greatly reduced and the time required for circuit simulation can be correspondingly reduced.
  • an electronic device for simulating a circuit includes: a reward determining unit configured to perform a first simulation on the circuit using a plurality of rules to determine a plurality of rewards corresponding to a plurality of simulation time periods; a target rule determining unit configured to determine a target rule based at least on the plurality of rewards ; and a simulation unit, configured to perform a second simulation on the circuit using the target rule.
  • the electronic device uses reinforcement learning to collect and analyze parameters such as the simulation step size and simulation time of the circuit under multiple rules, and gives corresponding rewards for multiple rules. After a period of time, it can Rewards to determine target rules.
  • the circuit simulation using the determined target rule can have a relatively ideal simulation step size and a high simulation success rate, so the calculation amount of the electronic device can be greatly reduced and the time required for circuit simulation can be correspondingly reduced.
  • the plurality of simulation periods includes a plurality of initial simulation periods and a plurality of intensive simulation periods subsequent to the plurality of initial simulation periods
  • the plurality of rewards includes a plurality of rewards corresponding to the plurality of initial simulation periods.
  • the reward determination unit includes: an initial reward obtaining unit configured to use a plurality of rules to sequentially simulate the circuit to obtain a plurality of reinforcement rewards corresponding to the plurality of simulation time periods A plurality of initial rewards respectively corresponding to the initial simulation time periods; a rule selection unit for selecting from a plurality of rules at least based on the plurality of initial rewards, one or more rules used during a plurality of reinforcement simulation time periods; and strengthening
  • a reward determination unit is configured to simulate the circuit using the determined one or more rules to determine a plurality of reinforcement rewards corresponding to a plurality of reinforcement simulation time periods.
  • the rule selection unit is further configured to: select a rule to be used in the next reinforcement simulation time period after the current reinforcement simulation time period from a plurality of rules based on the current reinforcement reward set corresponding to the current reinforcement simulation time period , the current reinforcement reward set includes a plurality of current reinforcement rewards derived from a plurality of initial rewards and respectively corresponding to a plurality of rules.
  • the simulation acceleration effects of multiple rules can be continuously evaluated during the reinforcement simulation time period in order to select the most appropriate rule based on the current set of reinforcement rewards.
  • the rule selection unit is further configured to: select the rule with the largest reinforcement reward in the current reinforcement reward set from the multiple rules as the rule used in the next reinforcement simulation time period.
  • the rate of circuit simulation is optimized by enabling the application of the rule that is predicted to achieve the best simulation acceleration based on historical information in the next hardened simulation time period.
  • the simulation unit is further configured to: in response to multiple rewards corresponding to multiple consecutive time periods obtained using the same rule and the total time length of the multiple consecutive time periods exceeds a time threshold, apply the same rule identified as the target rule.
  • a rule that is continuously used for a longer period of time can be determined as a target rule. Continuous use of the same rule for a longer period of time means that the rule can lead to a faster simulation speed than other rules. Therefore, by determining this rule as a target rule for subsequent simulation of the circuit, the time required for circuit simulation can be reduced.
  • Figure 1 shows a flow chart of the design and manufacture process of an integrated circuit
  • Fig. 2 shows the schematic flowchart of transient simulation process
  • FIG. 3 shows a flowchart of a transient simulation process according to some embodiments of the present disclosure
  • FIG. 4 shows a flowchart of a method for simulating a circuit according to some embodiments of the present disclosure
  • FIG. 5 shows a block diagram of an example apparatus for simulating a circuit according to an embodiment of the disclosure.
  • Fig. 6 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure.
  • the term “comprise” and its variants mean open inclusion, ie “including but not limited to”.
  • the term “or” means “and/or” unless otherwise stated.
  • the term “based on” means “based at least in part on”.
  • the terms “one example embodiment” and “one embodiment” mean “at least one example embodiment.”
  • the term “another embodiment” means “at least one further embodiment”.
  • the circuit simulation based on the target rule can have a relatively ideal simulation step size and a high simulation success rate, so it can greatly reduce the calculation amount of electronic equipment and correspondingly reduce the time required for circuit simulation.
  • the simulation of the circuit usually expects to observe various electrical characteristics of the circuit within a period of time after starting to work through a simulation program.
  • the time required for circuit simulation means the time actually used by running the circuit simulation program to simulate the circuit
  • simulation time means the above-mentioned period of working time of the circuit. For example, a circuit simulation expects to observe how the circuit behaves for a simulation time such as 1 minute, but the actual time required for the circuit simulation may actually take 1 month.
  • FIG. 1 shows a flowchart of a design and manufacture process 100 for an integrated circuit.
  • the design-to-manufacture process 100 begins with specification development 110 .
  • the functional and performance requirements that the integrated circuit needs to meet are determined.
  • circuit design 122 is first performed by means of EDA software.
  • layout planning is performed on the circuit for layout design 124 .
  • mask fabrication 16 may be performed to obtain a mask for forming the designed circuit on the wafer.
  • integrated circuits are formed on the wafer through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing.
  • the wafer is diced to obtain bare chips, and the bare chips are packaged through processes such as bonding, welding, and molding to obtain chips.
  • the resulting chip is tested in a testing 150 stage to ensure that the performance of the finished chip meets the requirements established in specification 110 .
  • the tested chips 160 can be delivered to customers.
  • circuit design 122 In the process of circuit design 122 , transient simulation needs to be performed, so that in the stage of design 120 , it can be verified whether the function and performance of the circuit meet the established specifications.
  • Conventional circuit simulation reads the circuit netlist and standardized device model to perform transient simulation on the circuit within the simulation time period specified by the user.
  • FIG. 2 shows a schematic flowchart of a transient simulation process 200 .
  • an electronic device such as a computer, reads a netlist entered by a user.
  • the netlist defines the connection relationship of each component in the circuit designed by the user.
  • Electronic devices can determine the nodes in the circuit and the components connected to each node by analyzing the netlist.
  • the electronic device can also read in the device model and device parameters to describe the current and voltage characteristics of the device.
  • the transient simulation process 200 shown in FIG. 2 can be executed by electronic devices with computing functions such as personal computers, workstations, servers, and the like. This disclosure is not limited in this regard.
  • the electronic device can utilize Kirchhoff's voltage laws (Kirchhoff's voltage laws, KVL) and/or Kirchhoff's current laws (Kirchhoff's current law) , KCL) establish equations for each node and/or loop, and combine these equations to obtain a system of equations that can describe the circuit to be simulated.
  • the analytical solutions of the relevant circuit parameters can be obtained.
  • circuits often contain nonlinear devices such as diodes, the system of circuit equations is usually a system of nonlinear differential equations.
  • the scale of the circuit is large (that is, the circuit contains a large number of devices), electronic equipment usually cannot directly obtain the analytical solution of the nonlinear differential equation system.
  • conventional electronic devices use numerical calculation methods to solve the nonlinear differential equation system.
  • the electronic device may use the difference equations to approximate the nonlinear differential equations, that is, discretize the nonlinear differential equations in time, thereby transforming continuous time variables into discrete time variables.
  • the length of time period between two adjacent discrete time points is called the simulation step.
  • Commonly used numerical integration methods include backward Euler method, trapezoidal method, Runge-Kutta method, etc.
  • the electronic device may use an iterative method to solve the differential equation system obtained using the numerical integration method.
  • the Newton iterative method is usually used, that is, starting from an initial value, the next point is calculated by calculating the first-order linear matrix (Jacobian matrix) of the current value, and continues until the absolute value of the difference between two adjacent points is less than a certain value.
  • a given allowable error ie, nonlinear convergence judgment.
  • the linear equations involved in each iteration can be solved by means of LU decomposition or Gaussian elimination.
  • the electronic device determines whether the simulation is complete, that is, whether the simulation time reaches the simulation end time.
  • the electronic device performs time-discrete control, ie, adjusts the simulation step size. In order to speed up the simulation, it is expected to choose a larger simulation step size, but the selection of the simulation step size is usually constrained by the following three conditions: the stability requirements of the numerical integration method used; the local truncation error (local truncation error, LTE ) requirements; and to ensure that the nonlinear iteration can converge. On the basis of meeting these conditions, it is expected to choose a larger simulation step size as much as possible to speed up the simulation speed. Then returning to 206, time discretization is performed on the system of nonlinear differential equations using the new selected simulation step size. In response to determining that the simulation has been completed, at 214 the electronic device outputs simulation results.
  • FIG. 3 shows a flowchart of a transient simulation process 300 according to some embodiments of the present disclosure.
  • process 300 may be performed using an electronic device with computing capabilities, such as a personal computer, workstation, server, or the like. This disclosure is not limited in this regard.
  • the electronic device obtains data required for simulation, such as data representing a circuit and simulation parameters.
  • the data representing the circuit includes, but is not limited to, a netlist of the circuit to be simulated, a device model, device parameters, and the like.
  • the simulation parameters are used to control the transient simulation, including but not limited to the total simulation duration T total , the selected numerical integration method, the maximum allowable simulation step size, the iteration convergence error reltol, and the like.
  • some of these data eg, device parameters, iteration convergence errors, etc.
  • Electronic devices can obtain the data needed for simulation in various ways. For example, the data required for the simulation can be loaded into the electronic device by using a storage medium storing data, manual input, wired or wireless transmission, and the like.
  • the electronic device may perform initialization operations.
  • the electronic device may determine an initial state of the circuit, ie determine the state of the circuit at the beginning of the simulation time period.
  • An electronic device can determine the initial state of a circuit by invoking a DC analysis program. Those skilled in the art can also use other methods to determine the initial state of the circuit. The scope of the present disclosure is not limited in this respect.
  • the above simulation control variables and their initial values are only exemplary, and the scope of the present disclosure is not limited thereto. Other methods can be used for initialization, or the above parameters can be set to other values.
  • the electronic device builds a system of equations describing the circuit to be simulated based on the acquired circuit parameters. For example, a system of equations is established as shown at 204 of FIG. 2 .
  • the electronic device uses a numerical integration method such as the backward Euler method to discretize the established circuit equations in time, so as to obtain difference equations.
  • the system of difference equations can then be solved, for example, using an iterative method such as Newton's iterative method.
  • the electronic device may, for example, use the LU decomposition method to solve the system of equations involved in the current iteration step k.
  • the electronic device determines whether the iteration is converged by comparing the absolute value abs of the difference between the solution at the current iteration step k and the solution at the previous iteration step k-1 with a predetermined iteration convergence error reltol. If abs ⁇ reltol, the iteration converges. If abs>reltol, the iteration does not converge.
  • the electronic device compares the current iteration number k with the maximum allowable iteration number k max (also referred to as the iteration number threshold) to decide whether to continue performing iterations for the current simulation step size h n calculate.
  • the maximum allowable number of iterations k max may be predetermined by the user. Alternatively, the maximum allowable number of iterations k max may also adopt a default value.
  • the electronic device increments the current iteration number k by 1. Then, the simulation process 300 returns to 310 to continue performing iterative calculations for the current simulation step h n . In the case of k ⁇ k max , at 318 the electronic device may shorten the simulation step size. Then, at 320, the electronic device may reset the number k of iterations to zero. Then, the simulation process 300 returns to 308, and the electronic device uses the updated simulation step size h n to perform time discretization on the circuit equations again, and uses an iterative method to solve the obtained new difference equations.
  • the electronic device calculates a truncation error.
  • the electronic device can be calculated by substituting the calculated values for the previous several discrete time points based on the error calculation formula corresponding to the selected numerical integration method through the mean difference method or the estimation correction method, which will be described in detail below.
  • the electronic device compares the calculated truncation error to a truncation error threshold to determine whether the current iteration is successful.
  • the truncation error threshold may be predetermined by the user. Alternatively, the truncation error threshold may also adopt a default value.
  • the simulation process 300 proceeds to 318 to shorten the simulation step size and recalculate.
  • the current iteration is successful, that is, the system of equations is successfully solved with the current simulation step size h n .
  • the simulation process 300 proceeds to 326, where the electronic device may calculate the next simulation step h n+1 .
  • the electronic device increments the discrete time point number n by 1 and updates the simulation time T M .
  • the electronic device determines whether the simulation ends by comparing the simulation time TM with a predetermined total duration of the simulation T total . In the case of T M ⁇ T total , the simulation has not ended, and the simulation process 300 proceeds to 320, and the electronic device may reset the number of iterations k to zero. Then, returning to 308, the electronic device uses the next simulation step h n+1 to perform time discretization on the circuit equations again, and uses an iterative method to solve the obtained new difference equations. In the case of T M >T total , the simulation ends. At 332, the electronic device outputs simulation results.
  • the transient simulation process 300 also includes reinforcement learning 350 .
  • reinforcement learning 350 may determine target rules for controlling and adjusting the simulation step size based on relevant data of the simulation process. This will be described in further detail below with reference to FIG. 4 .
  • FIG. 4 shows a flowchart of a method 400 for simulating a circuit according to some embodiments of the present disclosure. It should be understood that the method 400 may also include additional blocks not shown, and/or the blocks shown may be omitted. Method 400 may be performed using an electronic device with computing capabilities, such as a personal computer, workstation, server, or the like.
  • the electronic device performs a first simulation on the circuit using a plurality of rules to determine a plurality of rewards corresponding to a plurality of simulation time periods.
  • Rules are used to control the simulation step size used in solving the equations.
  • rules can be expressed as a function of the current simulation step size.
  • a rule may include a first factor Nf and a second factor Np.
  • the electronic device may shorten the current simulation step size by a first factor Nf. For example, at 318 in FIG.
  • the electronic device divides the current simulation step size h n by the first factor Nf to update the current simulation step size h n .
  • the plurality of rules further include that the electronic device may scale the current simulation step size by a second factor Np if the truncation error of the current simulation step size during a simulation time period is not greater than a truncation error threshold.
  • the second factor Np is different from the first factor Nf.
  • the electronic device first calculates the local truncation error LTE by formula (1) at 322 in FIG. 3 :
  • x n+1 represents the value obtained by solving iteratively, Indicates the predicted value (also known as the ideal value).
  • t n+1 represents the n+1 th discrete time point
  • t n represents the n th discrete time point
  • the electronic device calculates the intermediate variables wRMSNorm and ck based on formulas (3) and (4):
  • relErrTol represents the relative allowable error value
  • absErrTol represents the absolute allowable error value.
  • relErrTol and absErrTol may be predetermined by the user. Alternatively relErrTol and absErrTol may also take default values.
  • the electronics then calculates the truncation error based on equation (5):
  • estOverTol ck ⁇ wRMSNorm (5)
  • the electronic device compares the calculated truncation error estOverTol with the truncation error threshold to determine whether the iteration is successful.
  • the truncation error threshold is 1. It should be understood that the truncation error threshold may also be set to other suitable values.
  • the electronic device determines that the iteration fails, and the electronic device uses the first factor Nf to shorten the simulation step at 318
  • the electronic device determines that the iteration is successful, and the electronic device uses the second factor Np to scale the simulation step size at 326 according to the formula (6):
  • the rules are shown in the form of a combination of the first factor Nf and the second factor Np, the present disclosure is not limited thereto. There may also be other forms of rules to control simulation parameters such as simulation step size, thereby realizing learning under different parameter situations.
  • the first factor Nf and the second factor Np of each rule of the plurality of rules may, for example, be at least partially different from the first factor Nf and the second factor Np of another rule of the plurality of rules.
  • the simulation step size can be adjusted with various scaling factors, and then control strategies of various styles can be set. For example, a conservative strategy (ie, a smaller scaling factor) and an aggressive strategy (ie, a larger scaling factor). In this way, the probability of finding a simulation step size control rule suitable for the current simulation situation is increased. Since the selection of the simulation step size will directly affect the efficiency of circuit simulation, the efficiency of circuit simulation can be optimized by selecting an appropriate control rule for the simulation step size.
  • first factor Nf and the second factor Np of each rule in the plurality of rules may also be different from the first factor Nf and the second factor Np of any other rule in the plurality of rules.
  • the scope of the present disclosure is not limited in this respect.
  • the number of rules can now be denoted as N rule .
  • N rule 5 indicates that the multiple rules include 5 rules in total.
  • 5 rules can be defined as follows:
  • the rule of Np adjusts the simulation step size as shown in 318 or 326 of FIG. 3 , and determines the number of iterations performed during the corresponding simulation time period, for example, accumulating the number of iterations k during the corresponding simulation time period for statistics.
  • reinforcement learning can be used to evaluate each rule and give corresponding rewards. Reinforcement learning can give corresponding rewards based on the statistical data of the initial simulation, and then count the simulation results of the reinforcement stage after rewards are given and continue to give corresponding rewards, and so on, until the maximum reward of reinforcement learning stably corresponds to a certain rule.
  • This rule is the target rule obtained by reinforcement learning.
  • the electronic device can then use the preferred target rules for subsequent simulations to reduce the time required for circuit simulation.
  • the reinforcement learning 350 can be continuously performed in the circuit simulation stage until the circuit simulation ends. This disclosure does not limit this.
  • the plurality of simulation periods includes a plurality of initial simulation periods and a plurality of intensive simulation periods subsequent to the plurality of initial simulation periods
  • the plurality of rewards includes a plurality of rewards corresponding to the plurality of initial simulation periods. initial rewards and multiple reinforcement rewards corresponding to multiple reinforcement simulation time periods.
  • reinforcement learning 350 selects and uses one of the plurality of rules.
  • the electronic device uses the rule to adjust the simulation step size at 318 or 326 in FIG. 3 to obtain an initial reward corresponding to the initial simulation time period.
  • the initial reward corresponding to the initial simulation time period may be represented by the following equation (7):
  • F represents the rule used in the initial simulation time period i
  • P i (F) represents the initial reward of rule F, also known as the iteration time
  • i represents the i-th simulation time period
  • T i represents the initial simulation time period i
  • K i represents the number of iterations performed by the electronic device in the initial simulation time period i.
  • the iteration time is inversely proportional to the number of iterations performed by the electronic device in a unit simulation time period.
  • a lower number of iterations generally means a faster simulation speed for the same simulation time period. Therefore, the speed of simulation using a particular rule can be measured by this iteration time (ie, initial reward).
  • reinforcement learning 350 sequentially selects and uses one of the plurality of rules for circuit simulation, so as to obtain the initial award. In this way, all the rules can be traversed after the simulation starts to obtain a preliminary judgment on the simulation acceleration effect of each rule, so that the most suitable rule can be selected in the subsequent simulation.
  • Reinforcement learning 350 selects one or more rules from the plurality of rules to use during the plurality of reinforcement simulation time periods based at least on the plurality of initial rewards.
  • reinforcement learning 350 may select a rule (eg, rule A) corresponding to the largest initial reward among the plurality of initial rewards for a first reinforcement simulation period among the plurality of reinforcement simulation periods.
  • the electronic device simulates the circuit based on the selected rule A during the first reinforced simulation time period, and obtains the reinforced reward R(A) corresponding to the rule A.
  • the reinforcement reward may be represented by the following equation (8).
  • G represents the rule used in the strengthening phase
  • R(G) represents the strengthening reward of rule G
  • j represents the jth simulation time period (where j>N rule )
  • N j (G) represents the total number of times the rule G is used in the first j-1 simulation time periods
  • log j represents the logarithm of the number j of the current simulation time period.
  • the average iteration time It is inversely proportional to the number of iterations performed by the electronic device in a unit simulation time period, so that the simulation acceleration effect of the rule G obtained in the previously performed simulation can be measured. Then, the weighted value Rules that are selected less often can be compensated to avoid reinforcement learning 350 from neglecting to try these rules. Therefore, the reinforcement reward R(G) enables the reinforcement learning 350 to fully and comprehensively evaluate the simulation acceleration effect of each rule, so as to determine the most suitable rule for the current simulation situation.
  • formula (8) shows a specific implementation manner of strengthening rewards, the scope of the present disclosure is not limited thereto. Different reward methods can be used for different circuits, numerical integration methods used, iteration methods, etc.
  • the electronic device may construct a set of reinforcement rewards.
  • the reinforcement reward set includes a plurality of reinforcement rewards derived from a plurality of initial rewards and respectively corresponding to a plurality of rules. Each element in the reinforcement reward set corresponds to the latest reward corresponding to each rule.
  • reinforcement learning 350 can, for example, use the above formula (8) to calculate the current reinforcement reward, and use the current reinforcement reward determined according to the current rule and corresponding to the current simulation time period to update the reinforcement reward set.
  • rule B is simulated during one reinforcement simulation time period, and the calculated reinforcement reward corresponding to rule B is 5.
  • Reinforcement learning 350 uses 5 to update the original set of reinforcement rewards [Rule A: 1, Rule B: 3, Rule C: 4, Rule D: 6, Rule E: 2].
  • the updated enhanced reward set is [Rule A: 1, Rule B: 5, Rule C: 4, Rule D: 6, Rule E: 2].
  • Reinforcement learning 350 can thus use rule D as the rule to use for the next reinforcement period.
  • the evaluation of the simulation acceleration effect of each rule can be updated in real time, so that the most suitable rule can be selected in real time for the current simulation situation.
  • Reinforcement learning 350 selects a rule from a plurality of rules for use in a next reinforcement simulation time period after the current reinforcement simulation time period based on the current reinforcement reward set corresponding to the current reinforcement simulation time period.
  • reinforcement learning 350 selects from a plurality of rules the rule with the largest reinforcement reward in the current reinforcement reward set as the rule to use in the next reinforcement simulation epoch.
  • the current set of reinforcement rewards is [rule A:1, rule B:5, rule C:4, rule D:6, rule E:2], and the maximum reinforcement reward 6 in this set corresponds to rule D, so reinforcement learning 350 may select rule D as the rule to use for the next reinforcement period.
  • the electronic device simulates the circuit using the rules selected by reinforcement learning 350, and the reinforcement learning 350 determines the value of the selected rules based at least on the reinforced simulation time period and the The reinforcement reward corresponding to the reinforcement simulation time period.
  • the reinforcement learning 350 can calculate the reinforcement reward R(G) corresponding to the used rule G for each reinforcement simulation period by means of the above-described formula (8).
  • Reinforcement learning 350 selects and uses a rule for each simulation time period in the manner described above, updates the reinforcement reward set based on the number of iterations using the rule in the corresponding simulation time period, and selects based on the updated reinforcement reward set And use the rules for the next simulation time period. In this way, reinforcement learning 350 can continuously evaluate the simulation acceleration effect of each rule, so as to more accurately select the most suitable rule for the current simulation situation.
  • the electronic device determines targeting rules based at least on the plurality of rewards.
  • reinforcement learning can be used to determine the target rules used in the subsequent simulation process, so that the subsequent simulation process can be performed with a more appropriate step size, thereby reducing the amount of calculation and shortening the simulation time.
  • the rule is the rule applicable to the simulation of the circuit, that is, the target rule.
  • the same rule is determined as the target rule. For example, if the reinforcement learning selects and uses rule A in 20 consecutive time periods, and the total time length of the 20 continuous time periods exceeds a time threshold of 100 ns, the electronic device may determine the rule A as the target rule. It should be understood that the above numerical values for the time threshold are exemplary only, and the scope of the present disclosure is not limited in this respect.
  • reinforcement learning 350 responds to multiple rewards corresponding to multiple consecutive time periods being derived using the same rule and the number of time periods for the multiple consecutive time periods exceeds a threshold number of time periods, assigning the same
  • the rule is identified as a target rule. For example, if the threshold number of time periods is 30, and the reinforcement learning selects and uses rule B in 31 consecutive time periods, the electronic device may determine rule B as the target rule. It should be understood that the above numerical values for the threshold number of time periods are exemplary only, and the scope of the present disclosure is not limited in this respect.
  • Reinforcement learning 350 keeps selecting and using the same rule for a longer period of time, which means that the reinforcement reward corresponding to the rule is always the largest element in the reinforcement reward set for the longer period of time. That is to say, using this rule can minimize the number of iterations performed by the electronic device in a unit simulation time period. A lower number of iterations generally means a faster simulation, so this same rule achieves the best simulation speedup compared to other rules.
  • the rule with the largest reward may be selected as the target rule after a predetermined simulation time such as 1 ⁇ s.
  • the rule with the best simulation speed-up effect can be determined as the target rule for simulating the circuit in the subsequent simulation time period, so as to maximize the Speed up your simulation.
  • the electronic device performs a second simulation on the circuit using the target rule.
  • reinforcement learning 350 may end the learning process, and select and use the target rule throughout the remaining period of time.
  • the learning process of the reinforcement learning 350 may not be terminated, but the rules selected by the reinforcement learning 350 are used throughout the simulation to simulate the circuit. Accordingly, the scope of the present disclosure is not limited in this regard.
  • the method 400 of the embodiment of the present disclosure can use the reinforcement learning 350 to collect and analyze the simulation parameters of the circuit under multiple rules, and determine the rewards corresponding to the multiple rules to The rule with the highest reward is then selected as the target rule for subsequent simulations.
  • the circuit simulation based on the target rule can have a more appropriate simulation step size and a higher simulation success rate, so it can greatly reduce the calculation amount of electronic equipment and correspondingly reduce the time required for circuit simulation.
  • FIG. 5 shows a block diagram of an example apparatus 500 for simulating a circuit according to an embodiment of the disclosure.
  • the apparatus 500 can be used, for example, to implement electronic equipment.
  • the apparatus 500 may include a reward determining unit 502 configured to perform a first simulation on the circuit using a plurality of rules to determine a plurality of rewards corresponding to a plurality of simulation time periods.
  • the apparatus 500 may further include an objective rule determining unit 504, configured to determine an objective rule based at least on a plurality of rewards.
  • the apparatus 500 may further include a simulation unit 506, configured to perform a second simulation on the circuit using the target rule.
  • the plurality of simulation periods includes a plurality of initial simulation periods and a plurality of intensive simulation periods subsequent to the plurality of initial simulation periods
  • the plurality of rewards includes a plurality of rewards corresponding to the plurality of initial simulation periods.
  • the reward determination unit 502 includes: an initial reward obtaining unit, which is used to use a plurality of rules to sequentially simulate the circuit to obtain a plurality of simulation time periods.
  • the reinforcement reward determining unit is configured to simulate the circuit using the determined one or more rules to determine a plurality of reinforcement rewards corresponding to a plurality of reinforcement simulation time periods.
  • the rule selection unit is further configured to: select a rule to be used in the next reinforcement simulation time period after the current reinforcement simulation time period from a plurality of rules based on the current reinforcement reward set corresponding to the current reinforcement simulation time period , the current reinforcement reward set includes a plurality of current reinforcement rewards derived from a plurality of initial rewards and respectively corresponding to a plurality of rules.
  • the rule selection unit is further configured to: select the rule with the largest reinforcement reward in the current reinforcement reward set from the plurality of rules as the rule used in the next reinforcement simulation time period.
  • the simulation unit 506 is further configured to: in response to multiple rewards corresponding to multiple consecutive time periods are obtained using the same rule and the total time length of the multiple consecutive time periods exceeds the time threshold, apply the same The rule is identified as a target rule.
  • the modules and/or units included in the device 500 may be implemented in various ways, including software, hardware, firmware or any combination thereof.
  • one or more units may be implemented using software and/or firmware, such as machine-executable instructions stored on a storage medium.
  • some or all of the units in apparatus 500 may be at least partially implemented by one or more hardware logic components.
  • Exemplary types of hardware logic components include, by way of example and not limitation, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), System on Chips (SOCs), Complex Programmable Logic Devices (CPLD), and so on.
  • modules and/or units shown in FIG. 5 may be implemented in part or in whole as hardware modules, software modules, firmware modules or any combination thereof.
  • the procedures, methods or processes described above may be implemented by hardware in the storage system or a host corresponding to the storage system or other computing devices independent of the storage system.
  • Fig. 6 shows a schematic block diagram of an example device 600 that may be used to implement embodiments of the present disclosure.
  • the device 600 may be used to implement an electronic device.
  • device 600 includes a central processing unit (CPU) 601 that can be programmed according to computer program instructions stored in read only memory (ROM) 602 or loaded from storage unit 608 into random access memory (RAM) 603. computer program instructions to perform various appropriate actions and processes.
  • ROM read only memory
  • RAM random access memory
  • computer program instructions to perform various appropriate actions and processes.
  • RAM 603 various programs and data necessary for the operation of the device 600 can also be stored.
  • the CPU 601, ROM 602, and RAM 603 are connected to each other through a bus 604.
  • An input/output (I/O) interface 605 is also connected to the bus 604 .
  • I/O input/output
  • the I/O interface 605 includes: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, an optical disk, etc. ; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, and the like.
  • the communication unit 609 allows the device 600 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.
  • the processing unit 601 executes various methods and processes described above, such as the method 400 .
  • method 400 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 608 .
  • part or all of the computer program may be loaded and/or installed on the device 600 via the ROM 602 and/or the communication unit 609.
  • the CPU 601 may be configured to execute the method 400 in any other suitable manner (for example, by means of firmware).
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • ASSP application specific standard product
  • SOC system on a chip
  • CPLD load programmable logic device
  • Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented.
  • the program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing.
  • machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable programmable read only memory
  • CD-ROM compact disk read only memory
  • magnetic storage or any suitable combination of the foregoing.

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Abstract

本公开的实施例提供了用于对电路进行仿真的方法、介质、程序产品以及电子设备。根据本公开的一些实施例的方案使用强化学习来对电路在多个规则下的仿真步长、仿真时间等参数进行收集和分析，并且确定与多个规则对应的奖励，以在一段时间之后选择具有最高奖励的规则作为用于进行后续仿真的目标规则。基于目标规则的电路仿真具有较合适的仿真步长，因此具有较高的仿真成功率。根据本公开的一些实施例的方案可以极大地减小电子设备的计算量并且相应地减少电路仿真所需的时间。

Description

用于对电路进行仿真的方法、介质、程序产品以及电子设备 技术领域
本公开的实施例总体上涉及电子电路领域，并且更具体地涉及用于对电路进行仿真的方法、介质、程序产品以及电子设备。
背景技术
目前，国际上各大电子设计自动化(electronic design automation,EDA)公司的电子设备都是以集成电路为重点的仿真程序(simulation program with integrated circuit emphasis,SPICE)为基础，通过读取电路网表和标准化器件模型，来在用户指定的仿真时间段内对电路进行仿真。
随着微电子技术及先进制造工艺的发展，集成电路(integrated circuit,IC)设计规模越来越庞大，所包含的器件数量也急剧增加。对于电路仿真而言，这会带来待求解的非线性方程组的维数增加，从而导致完成一次迭代计算所需的时间呈超线性增长。常规的电路仿真通常需要较长的时间以实现对于电路的仿真。因此，期望降低电路仿真所需的时间，从而加快集成电路的设计。
发明内容
鉴于上述问题，本公开的实施例旨在提供一种用于减少电路仿真所需时间的方案。
根据本公开的第一方面，提供了一种用于对电路进行仿真的方法。该方法包括使用多个规则对电路进行第一仿真以确定与多个仿真时间段对应的多个奖励；至少基于多个奖励确定目标规则；以及使用目标规则对电路进行第二仿真。通过使用强化学习来对电路在多个规则下的仿真步长、仿真时间等参数进行收集和分析，并且针对多个规则给出相应奖励，可以在一段时间之后根据各个规则所对应的奖励来确定目标规则。使用所确定的目标规则的电路仿真可以具有较为理想的仿真步长并且具有较高的仿真成功率，因此可以极大地减小电子设备的计算量并且相应地减少对于电路仿真所需的时间。
在一些实现方式中，多个仿真时间段包括多个初始仿真时间段和在多个初始仿真时间段之后的多个强化仿真时间段，并且多个奖励包括与多个初始仿真时间段对应的多个初始奖励和与多个强化仿真时间段对应的多个强化奖励，使用多个规则对电路进行第一仿真以确定与多个仿真时间段对应的多个奖励包括：使用多个规则依次对电路进行仿真以获得与多个仿真时间段中的多个初始仿真时间段分别对应的多个初始奖励；至少基于多个初始奖励，从多个规则中选择在多个强化仿真时间段期间使用的一个或多个规则；以及使用所选择的一个或多个规则对电路进行仿真以确定与多个强化仿真时间段对应的多个强化奖励。通过这种方式，可以在仿真开始后就遍历所有规则，以获得对各个规则的仿真加速效果的初步判断，以便于在后续的仿真中能够选择出仿真加速效果最佳的规则。
在一些实现方式中，初始奖励表示至少基于迭代数目和初始仿真时间段确定的与规则对应的迭代时间。迭代时间与电子设备在单位仿真时间段中所执行的迭代的数目成反比。较少的迭代数目通常意味着针对同一仿真时间段的较快的仿真速度。因此，可以通 过该初始奖励来衡量使用各个规则的仿真速度。
在一些实现方式中，至少基于多个初始奖励从多个规则中选择在多个强化仿真时间段期间使用的一个或多个规则包括：从多个规则中选择与多个初始奖励中的最大初始奖励对应的规则作为在多个强化仿真时间段中的第一强化仿真时间段期间使用的规则。通过这种方式，可以优先使用基于当前信息所能够确定的最佳规则来在第一强化仿真时间段期间对电路进行仿真，以减少对于电路仿真所需的时间。
在一些实现方式中，至少基于多个初始奖励从多个规则中选择在多个强化仿真时间段使用的一个或多个规则包括：基于与当前强化仿真时间段对应的当前强化奖励集合，从多个规则中选择在当前强化仿真时间段之后的下一强化仿真时间段使用的规则，当前强化奖励集合包括源自于多个初始奖励的、与多个规则分别对应的多个当前强化奖励。借助于当前强化奖励集合，可以在强化仿真时间段期间持续地评价多个规则的仿真加速效果，以便基于当前强化奖励集合来选择最合适的规则。
在一些实现方式中，基于与当前强化仿真时间段对应的当前强化奖励集合从多个规则中选择在当前强化仿真时间段之后的下一强化仿真时间段使用的规则包括：从多个规则中选择具有在当前强化奖励集合中的最大强化奖励的规则作为在下一强化仿真时间段使用的规则。通过选择具有最大强化奖励的规则，使得能够在下一强化仿真时间段中应用基于历史信息预测能够实现最佳仿真加速效果的规则，从而优化电路仿真的速率。
在一些实现方式中，该方法还包括：使用根据当前规则确定的与当前仿真时间段对应的当前强化奖励来更新当前强化奖励集合。通过更新当前强化奖励集合，可以实时更新对各个规则的仿真加速效果的评价，以便能够实时地选择出最适于当前仿真情形的规则。
在一些实现方式中，使用所确定的一个或多个规则对电路进行仿真以确定与多个强化仿真时间段对应的多个强化奖励包括：使用所确定的一个或多个规则中的一个规则对电路进行仿真以确定与多个强化仿真时间段中的一个强化仿真时间段对应的迭代数目；以及至少基于迭代数目和一个强化仿真时间段，确定与一个强化仿真时间段对应的强化奖励。通过在强化奖励中考虑迭代数目和强化仿真时间段，可以利用单位仿真时间段中所执行的迭代数目来评价使用各个规则的仿真速度。
在一些实现方式中，至少基于迭代数目和一个强化仿真时间段确定与一个强化仿真时间段对应的强化奖励包括：至少基于迭代数目和一个强化仿真时间段确定与一个规则对应的平均迭代时间；基于一个规则被使用的次数确定加权值；以及基于平均迭代时间和加权值确定与一个强化仿真时间段对应的强化奖励。通过在强化奖励中考虑平均迭代时间以及取决于一个规则被使用的次数的加权值，可以充分且全面地评估各个规则的仿真加速效果，以确定最适于当前仿真情形的规则。
在一些实现方式中，至少基于多个奖励确定目标规则包括：响应于与多个连续时间段对应的多个奖励是使用相同的规则得到的并且多个连续时间段的总时间长度超过时间阈值，将相同的规则确定为目标规则。通过这种方式，可以将在较长时间段中被持续使用的规则确定为目标规则。同一规则在较长时间段中被持续使用意味着该规则与其它规则相比可以带来较快的仿真速度。因此，通过将该规则确定为用于对电路进行后续仿真的目标规则，可以减少对于电路仿真所需的时间。
在一些实现方式中，至少基于多个奖励确定目标规则包括：响应于与多个连续时间 段对应的多个奖励是使用相同的规则得到的并且多个连续时间段的时间段数目超过时间段数目阈值，将相同的规则确定为目标规则。通过这种方式，可以将在较长时间段中被持续使用的规则确定为目标规则。同一规则在较长时间段中被持续使用意味着该规则与其它规则相比可以带来较快的仿真速度。因此，通过将该规则确定为用于对电路进行后续仿真的目标规则，可以减少对于电路仿真所需的时间。
在一些实现方式中，多个规则包括：如果在使用多个规则中的一个规则的情形下，在一个仿真时间段期间使用一个仿真步长的迭代次数超过迭代次数阈值，则将一个仿真步长以第一因子缩短。通过这种方式，可以限制使用特定仿真步长执行迭代计算的次数，从而可以减少对于电路仿真所需的时间。此外，由于仿真步长的选择会直接影响电路仿真的效率，因此通过根据迭代次数来调整仿真步长，可以实现对电路仿真效率的优化。
在一些实现方式中，多个规则还包括：如果在使用一个规则的情形下，在一个仿真时间段期间使用一个仿真步长的截断误差不大于截断误差阈值，则将一个仿真步长以第二因子缩放，其中第二因子不同于第一因子。借助于截断误差，可以对求解方程组的结果的准确度进行评价，从而可以优化电路仿真的准确度。此外，由于仿真步长的选择会直接影响电路仿真的效率，因此通过根据截断误以不同的因子差来调整仿真步长，可以实现对电路仿真效率的优化。
在一些实现方式中，多个规则中的每个规则所具有的第一因子和第二因子不同于多个规则中的另一规则所具有的第一因子和第二因子。通过设置具有不同的第一因子和第二因子的多个规则，使得能够以多种缩放系数来对仿真步长进行调整，进而可以设置各种风格的控制策略。
在一些实现方式中，多个规则中的每个规则所具有的第一因子和第二因子不同于多个规则中的其余任一规则所具有的第一因子和第二因子。通过设置具有完全不同的第一因子和第二因子的多个规则，可以提高找到适于当前仿真情形的仿真步长控制规则的可能性。
在一些实现方式中，该方法还包括读入由用户输入的网表，该网表定义了由用户所设计的电路中的各个元器件的连接关系。通过读入网表，可以解析得到电路中的节点、以及每个节点处所连接的元器件，从而可以描述待仿真电路。
在一些实现方式中，该方法还包括基于仿真电路和基尔霍夫定律来建立方程组。通过这种方式，可以得到能够描述待仿真电路的方程组。
在一些实现方式中，该方法还包括利用数值积分方法来将连续时间变量转化为离散时间变量。通过这种方式，可以将非线性的微分方程组在时间上离散化，从而使得能够利用差分方程组来近似通常难以直接求解的非线性微分方程组。
在一些实现方式中，该方法还包括使用牛顿迭代法来求解差分方程组。通过使用迭代方法，可以使得求解差分方程组的任务适于由诸如计算机之类的电子设备执行。
根据本公开的第二方面，提供了一种计算机可读存储介质，存储一个或多个程序。一个或多个程序被配置为一个或多个处理器执行。一个或多个程序包括用于执行根据第一方面的方法的指令。通过读取并执行计算机可读存储介质中的一个或多个程序，可以使用强化学习来对电路在多个规则下的仿真步长、仿真时间等参数进行收集和分析，并且针对多个规则给出相应奖励，可以在一段时间之后根据各个规则所对应的奖励来确定目标规则。使用所确定的目标规则的电路仿真可以具有较为理想的仿真步长并且具有较 高的仿真成功率，因此可以极大地减小电子设备的计算量并且相应地减少对于电路仿真所需的时间。
根据本公开的第三方面，提供了一种计算机程序产品。计算机程序产品包括一个或多个程序。一个或多个程序被配置为一个或多个处理器执行。一个或多个程序包括用于执行根据第一方面的方法的指令。通过执行该计算机程序产品，可以使用强化学习来对电路在多个规则下的仿真步长、仿真时间等参数进行收集和分析，并且针对多个规则给出相应奖励，可以在一段时间之后根据各个规则所对应的奖励来确定目标规则。使用所确定的目标规则的电路仿真可以具有较为理想的仿真步长并且具有较高的仿真成功率，因此可以极大地减小电子设备的计算量并且相应地减少对于电路仿真所需的时间。
根据本公开的第四方面，提供了一种用于对电路进行仿真的电子设备。该电子设备包括：一个或多个处理器；以及包括计算机指令的存储器，计算机指令在由电子设备的一个或多个处理器执行时使得电子设备执行第一方面的方法。该电子设备通过使用强化学习来对电路在多个规则下的仿真步长、仿真时间等参数进行收集和分析，并且针对多个规则给出相应奖励，可以在一段时间之后根据各个规则所对应的奖励来确定目标规则。使用所确定的目标规则的电路仿真可以具有较为理想的仿真步长并且具有较高的仿真成功率，因此可以极大地减小电子设备的计算量并且相应地减少对于电路仿真所需的时间。
根据本公开的第五方面，提供了一种用于对电路进行仿真的电子设备。该电子设备包括：奖励确定单元，用于使用多个规则对电路进行第一仿真以确定与多个仿真时间段对应的多个奖励；目标规则确定单元，用于至少基于多个奖励确定目标规则；以及仿真单元，用于使用目标规则对电路进行第二仿真。该电子设备通过使用强化学习来对电路在多个规则下的仿真步长、仿真时间等参数进行收集和分析，并且针对多个规则给出相应奖励，可以在一段时间之后根据各个规则所对应的奖励来确定目标规则。使用所确定的目标规则的电路仿真可以具有较为理想的仿真步长并且具有较高的仿真成功率，因此可以极大地减小电子设备的计算量并且相应地减少对于电路仿真所需的时间。
在一些实现方式中，多个仿真时间段包括多个初始仿真时间段和在多个初始仿真时间段之后的多个强化仿真时间段，并且多个奖励包括与多个初始仿真时间段对应的多个初始奖励和与多个强化仿真时间段对应的多个强化奖励，奖励确定单元包括：初始奖励获得单元，用于使用多个规则依次对电路进行仿真以获得与多个仿真时间段中的多个初始仿真时间段分别对应的多个初始奖励；规则选择单元，用于至少基于多个初始奖励，从多个规则中选择在多个强化仿真时间段期间使用的一个或多个规则；以及强化奖励确定单元，用于使用所确定的一个或多个规则对电路进行仿真以确定与多个强化仿真时间段对应的多个强化奖励。通过使用多个规则依次对电路进行仿真以获得与多个仿真时间段中的多个初始仿真时间段分别对应的多个初始奖励，可以在仿真开始后就遍历所有规则，以获得对各个规则的仿真加速效果的初步判断，以便于在后续的仿真中能够选择出仿真加速效果最佳的规则。
在一些实现方式中，规则选择单元进一步用于：基于与当前强化仿真时间段对应的当前强化奖励集合，从多个规则中选择在当前强化仿真时间段之后的下一强化仿真时间段使用的规则，当前强化奖励集合包括源自于多个初始奖励的、与多个规则分别对应的多个当前强化奖励。借助于当前强化奖励集合，可以在强化仿真时间段期间持续地评价多个规则的仿真加速效果，以便基于当前强化奖励集合来选择最合适的规则。
在一些实现方式中，规则选择单元进一步用于：从多个规则中选择具有在当前强化奖励集合中的最大强化奖励的规则作为在下一强化仿真时间段使用的规则。通过选择具有最大强化奖励的规则，使得能够在下一强化仿真时间段中应用基于历史信息预测能够实现最佳仿真加速效果的规则，从而优化电路仿真的速率。
在一些实现方式中，仿真单元进一步用于：响应于与多个连续时间段对应的多个奖励是使用相同的规则得到的并且多个连续时间段的总时间长度超过时间阈值，将相同的规则确定为目标规则。通过这种方式，可以将在较长时间段中被持续使用的规则确定为目标规则。同一规则在较长时间段中被持续使用意味着该规则与其它规则相比可以带来较快的仿真速度。因此，通过将该规则确定为用于对电路进行后续仿真的目标规则，可以减少对于电路仿真所需的时间。
提供发明内容部分是为了简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开内容的关键特征或主要特征，也无意限制本公开内容的范围。
附图说明
通过参考附图阅读下文的详细描述，本公开的实施例的上述以及其它目的、特征和优点将变得易于理解。在附图中，以示例而非限制性的方式示出了本公开的若干实施例。
图1示出了集成电路的设计制造过程的流程图；
图2示出了瞬态仿真过程的示意性流程图；
图3示出了根据本公开的一些实施例的瞬态仿真过程的流程图；
图4示出了根据本公开的一些实施例的用于对电路进行仿真的方法的流程图；
图5示出了根据本公开实施例的用于对电路进行仿真的示例装置的框图；以及
图6示出了可以用于实施本公开的实施例的示例设备的示意性框图。
具体实施方式
下面将参照附图更详细地描述本公开的优选实施例。虽然附图中显示了本公开的优选实施例，然而应该理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了使本公开更加透彻和完整，并且能够将本公开的范围完整地传达给本领域的技术人员。
在本文中使用的术语“包括”及其变形表示开放性包括，即“包括但不限于”。除非特别申明，术语“或”表示“和/或”。术语“基于”表示“至少部分地基于”。术语“一个示例实施例”和“一个实施例”表示“至少一个示例实施例”。术语“另一实施例”表示“至少一个另外的实施例”。术语“上”、“下”、“前”、“后”等指示放置或者位置关系的词汇均基于附图所示的方位或者位置关系，仅为了便于描述本公开的原理，而不是指示或者暗示所指的元件必须具有特定的方位、以特定的方位构造或操作，因此不能理解为对本公开的限制。
如上所述，随着集成电路的规模日益增加，常规的EDA通常消耗较长的时间以实现电路仿真。导致EDA仿真消耗时间较长的原因众多，其中一个重要的原因是表示电路的常微分方程组在被转换为差分方程之后并且在使用非线性迭代以求解差分方程的过程中，步长的动态选择并不理想。当使用不合适的较大步长进行迭代时，往往导致迭代不能收 敛或是不能满足局部截断误差的要求。这需要重新选择步长，并再次求解差分方程。另一方面，当仿真步长较小时，迭代次数也极大地增加。这极大地增加了电路仿真所需的时间。
在本公开的一些实施例中，通过使用强化学习来对电路在多个规则下的仿真步长、仿真时间等参数进行收集和分析，并且针对多个规则给出相应奖励，可以在一段时间之后选择具有最高奖励的规则作为目标规则。基于目标规则的电路仿真可以具有较为理想的仿真步长并且具有较高的仿真成功率，因此可以极大地减小电子设备的计算量并且相应地减少对于电路仿真所需的时间。电路的仿真通常期望通过仿真程序来观察电路在开始工作之后的一段时间内的各种电学特性。在本文中，“电路仿真所需的时间”表示运行电路仿真程序对电路进行仿真实际使用的时间，而“仿真时间”则表示电路的上述一段工作时间。例如，对电路仿真期望观察电路在诸如1分钟之类的仿真时间内的工作状态，但实际上该电路仿真所需的时间实际上可能需要1个月。
图1示出了集成电路的设计制造过程100的流程图。设计制造过程100开始于规格制定110。在规格制定110的阶段中，确定集成电路需要达到的功能和性能方面的要求。然后，在集成电路设计120的阶段中，首先借助于EDA软件来进行电路设计122。在确定电路之后，对电路进行布局规划以进行版图设计124。在得到电路版图之后，可以执行光罩制作16以得到用于将所设计的电路形成在晶圆上的光罩。随后，在制造130的阶段中，通过光刻、刻蚀、离子注入、薄膜沉积、抛光等工艺在晶圆上形成集成电路。在封装140的阶段中，对晶圆进行切割得到裸片，并通过黏贴、焊接、模封等工艺对裸片进行封装得到芯片。所得到的芯片在测试150的阶段中被测试，以确保成品芯片的性能满足规格制定110中所确定的要求。最终，测试合格的芯片160可以被交付客户。
在电路设计122的过程中，需要进行瞬态仿真，以便在设计120的阶段中就能够验证电路的功能和性能是否满足所制定的规格的要求。常规的电路仿真通过读取电路网表和标准化器件模型，来在用户指定的仿真时间段内对电路进行瞬态仿真。
图2示出了瞬态仿真过程200的示意性流程图。在202，诸如计算机之类的电子设备读入由用户输入的网表。网表定义了由用户所设计的电路中的各个元器件的连接关系。电子设备可以通过解析网表来确定电路中的节点、以及每个节点处所连接的元器件。此外，电子设备还可以读入器件模型以及器件参数，以用于描述器件的电流电压特性。可以理解，图2所示的瞬态仿真过程200可以由诸如个人计算机、工作站、服务器等具有计算功能的电子设备执行。本公开对此不进行限制。
在204，电子设备可以基于从网表中解析得到的器件连接关系以及器件模型和参数，利用基尔霍夫电压定律(Kirchhoff's voltage laws,KVL)和/或基尔霍夫电流定律(Kirchhoff's current law,KCL)针对各个节点和/或回路建立方程，并且通过将这些方程联立得到能够描述待仿真电路的方程组。通过求解该方程组便可以得到相关电路参数的解析解。由于电路中常常包含诸如二极管的非线性器件，因此电路方程组通常是非线性微分方程组。当电路规模较大(即，电路包含较多数目的器件)时，电子设备通常无法直接求取该非线性微分方程组的解析解。对此，常规的电子设备使用数值计算方法来求解该非线性微分方程组。
在206，电子设备可以利用差分方程组来逼近该非线性微分方程组，即，将非线性微分方程组在时间上离散化，从而将连续时间变量转化为离散时间变量。两个相邻的离 散时间点之间的时间段长度被称为仿真步长。常用的数值积分方法有后向欧拉法、梯形法、龙格库塔法等。
在208，电子设备可以使用迭代方法来求解利用数值积分方法得到的差分方程组。通常使用牛顿迭代法，即，从一个初始值开始通过计算当前值的一阶线性矩阵(雅可比矩阵)推算出下一个点，并一直持续直到相邻两个点之间差的绝对值小于某个给定的允许误差(即，非线性收敛判断)。每次迭代中涉及的线性方程组可以借助于LU分解或高斯消元等方法进行求解。
在210，电子设备确定仿真是否完成，即，仿真时间是否达到仿真结束时间。在212，电子设备执行时间离散控制，即，调整仿真步长。为了加快仿真，期望选择较大的仿真步长，但是对于仿真步长的选择通常受到以下三个条件的约束：所使用的数值积分方法的稳定性的要求；局部截断误差(local truncation error,LTE)的要求；以及保证非线性迭代能够收敛。在满足这些条件基础上，期望尽量选择较大的仿真步长，以加快仿真速度。然后返回206，使用所选择的新仿真步长来对非线性微分方程组进行时间离散化。响应于确定仿真已经完成，在214，电子设备输出仿真结果。
图3示出了根据本公开的一些实施例的瞬态仿真过程300的流程图。在一个实施例中，可以使用诸如个人计算机、工作站、服务器等之类的具有计算功能的电子设备执行过程300。本公开对此不进行限制。
在302，电子设备获取仿真所需的数据，例如表示电路的数据和仿真参数。在一个实施例中，表示电路的数据包括但不限于待仿真电路的网表、器件模型、器件参数等。仿真参数用于控制瞬态仿真，包括但不限于仿真总时长T total、所选择的数值积分方法、最大允许仿真步长、迭代收敛误差reltol等。在一些实施例中，这些数据中的部分数据(例如，器件参数、迭代收敛误差等)可以由用户输入。备选地，该部分参数也可以采用默认值。电子设备可以通过各种方式获得仿真所需的数据。例如，可以通过使用存储有数据的存储介质、人工输入、有线或无线传输等方式将仿真所需的数据加载至电子设备中。
在304，电子设备可以执行初始化操作。电子设备可以确定电路的初始状态，即，确定电路在仿真时间段的开始时刻的状态。电子设备可以通过调用直流分析程序来确定电路的初始状态。本领域技术人员也可以使用其它方式来确定电路的初始状态。本公开的范围在此方面不受限制。
在一些实施例中，电子设备还对仿真控制变量执行初始化，例如设置仿真时间T M＝t 0，其中t 0是仿真时间段的开始时刻；设置仿真步长h＝h 0，其中h 0是初始仿真步长，其既可以由用户预先输入，也可以采用默认值；设置离散时间点数n＝1；以及设置迭代次数k＝0。上述仿真控制变量以及其初始值仅是示例性的，本公开的范围对此不进行限制。可以使用其它方式进行初始化，或是将上述参数设置为其它值。
在306，电子设备基于所获取的电路参数来建立描述待仿真电路的方程组。例如，如图2的204所示地建立方程组。在308，电子设备基于当前仿真时间T M以及当前仿真步长h n，使用诸如后向欧拉法之类的数值积分方法来将所建立的电路方程组在时间上离散化，从而得到待求解的差分方程组。然后，可以例如使用诸如牛顿迭代法之类的迭代方法来求解该差分方程组。
在310，电子设备例如可以使用LU分解法来求解当前迭代步k中涉及的方程组。在312，电子设备通过将当前迭代步k的解与前一迭代步k-1的解之差的绝对值abs与预定 的迭代收敛误差reltol相比较，来确定迭代是否收敛。如果abs≤reltol，则迭代收敛。如果abs>reltol，则迭代不收敛。
在确定迭代不收敛的情况下，在314，电子设备将当前迭代次数k与最大允许迭代次数k max(也称为迭代次数阈值)进行比较，以决定是否针对当前仿真步长h n继续执行迭代计算。在一个实施例中，最大允许迭代次数k max可以由用户预先确定。备选地，该最大允许迭代次数k max也可以采用默认值。
在k<k max的情况下，在316，电子设备将当前迭代次数k递增1。然后，仿真过程300返回到310，以继续针对当前仿真步长h n执行迭代计算。在k≥k max的情况下，在318，电子设备可以缩短仿真步长。然后，在320，电子设备可以将迭代次数k清零。然后，仿真过程300返回到308，电子设备利用更新后的仿真步长h n来重新对电路方程组执行时间离散化，并且利用迭代方法来求解所得到的新的差分方程组。
在322，电子设备计算截断误差。例如，电子设备可以通过均差法或者预估校正法基于与所选择的数值积分方法对应的误差计算公式代入针对前几个离散时间点计算值计算得到，这将在下文详细描述。在324，电子设备将计算得到的截断误差与截断误差阈值进行比较，以确定当前迭代是否成功。截断误差阈值可以由用户预先确定。备选地，截断误差阈值也可以采用默认值。
在截断误差大于截断误差阈值的情况下，当前迭代失败，仿真过程300前进到318，以缩短仿真步长并重新进行计算。在截断误差小于或等于截断误差阈值的情况下，当前迭代成功，即，利用当前仿真步长h n成功求解了方程组。仿真过程300前进到326，电子设备可以计算下一仿真步长h n+1。
在328，电子设备将离散时间点数n递增1，并且更新仿真时间T M。在330，电子设备通过将仿真时间T M与预定的仿真总时长T total进行比较，来确定仿真是否结束。在T M≤T total的情况下，仿真尚未结束，仿真过程300前进到320，电子设备可以将迭代次数k清零。然后，返回到308，电子设备利用下一仿真步长h n+1来重新对电路方程组执行时间离散化，并且利用迭代方法来求解所得到的新的差分方程组。在T M>T total的情况下，仿真结束。在332，电子设备输出仿真结果。
在根据本公开的一些实施例中，瞬态仿真过程300还包括强化学习350。在一个实施例中，强化学习350可以基于仿真过程的相关数据来确定用于控制调整仿真步长的目标规则。这将在下文中结合图4进一步详细描述。
图4示出了根据本公开的一些实施例的用于对电路进行仿真的方法400的流程图。应当理解的是，方法400还可以包括未示出的附加框，和/或可以省略所示出的框。可以使用诸如个人计算机、工作站、服务器等之类的具有计算功能的电子设备执行方法400。
在402，电子设备使用多个规则对电路进行第一仿真以确定与多个仿真时间段对应的多个奖励。规则用于控制求解方程过程中使用的仿真步长。例如，规则可以表示为当前仿真步长的函数。在一个实施例中，规则可以包括第一因子Nf和第二因子Np。在一个仿真时间段期间当前仿真步长的迭代次数超过迭代次数阈值的情况下，电子设备可以将当前仿真步长以第一因子Nf缩短。例如，电子设备在图3的318将当前仿真步长h n除以第一因子Nf来更新当前仿真步长h n。多个规则还包括在一个仿真时间段期间当前仿真步长的截断误差不大于截断误差阈值的情况下，电子设备可以将当前仿真步长以第二因子Np缩放。在一个实施例中，第二因子Np不同于第一因子Nf。
在一些实施例中，电子设备在图3的322首先通过式子(1)计算局部截断误差LTE：
Figure PCTCN2021108728-appb-000001
其中，x n+1表示通过迭代方法求解得到的值，
Figure PCTCN2021108728-appb-000002
表示预测值(也称为理想值)。
Figure PCTCN2021108728-appb-000003
可以例如通过式子(2)基于之前通过迭代方法求解得到的值的x n、x n-1预估得到：
Figure PCTCN2021108728-appb-000004
其中t n+1表示第n+1离散时间点，并且t n表示第n离散时间点。
然后，电子设备基于式子(3)和(4)计算中间变量wRMSNorm和ck：
Figure PCTCN2021108728-appb-000005
Figure PCTCN2021108728-appb-000006
其中，relErrTol表示相对允许误差值，absErrTol表示绝对允许误差值。relErrTol和absErrTol可以由用户预先确定。备选地relErrTol和absErrTol也可以采用默认值。
然后，电子设备基于式子(5)计算截断误差：
estOverTol＝ck×wRMSNorm    (5)
在图3的324，电子设备将所计算得到的截断误差estOverTol与截断误差阈值比较，以确定迭代是否成功。在一个实施例中，截断误差阈值为1。应当理解的是，截断误差阈值还可以被设置为其它合适的值。
如果estOverTol>1，则电子设备确定迭代失败，电子设备在318利用第一因子Nf缩短仿真步长
如果estOverTol≤1，则电子设备确定迭代成功，电子设备在326根据式子(6)利用第二因子Np对仿真步长进行缩放：
h n+1＝h n×Np×r    (6)
其中，
Figure PCTCN2021108728-appb-000007
示例性地，虽然以第一因子Nf和第二因子Np的组合的形式示出规则，但是本公开不限于此。还可以有其它形式的规则以实现对于诸如仿真步长之类的仿真参数进行控制，由此实现在不同参数情形下的学习。多个规则中的每个规则所具有的第一因子Nf和第二因子Np例如可以至少部分地不同于多个规则中的另一规则所具有的第一因子Nf和第二因子Np。通过设置具有不同的第一因子Nf和第二因子Np的多个规则，使得能够以多种缩放系数来对仿真步长进行调整，进而可以设置各种风格的控制策略。例如，偏保守的策略(即，缩放系数较小)和偏激进的策略(即，缩放系数较大)。通过这种方式，提高了找到适于当前仿真情形的仿真步长控制规则的可能性。由于仿真步长的选择会直接 影响电路仿真的效率，因此通过选择合适的仿真步长控制规则，可以实现对电路仿真效率的优化。
可以理解，多个规则中的每个规则所具有的第一因子Nf和第二因子Np还可以不同于多个规则中的其余任一规则所具有的第一因子Nf和第二因子Np。本公开的范围在此方面不受限制。在可以将规则的数目表示为N rule。例如，N rule＝5表示多个规则一共包括5个规则。在一个实施例中，5个规则可以如下限定：
规则A：Np＝1.2，Nf＝16；
规则B：Np＝1.5，Nf＝10；
规则C：Np＝2，Nf＝8；
规则D：Np＝4，Nf＝4；
规则E：Np＝8，Nf＝2。
应当理解，以上规则的数目以及第一因子Nf和第二因子Np的数值仅是示例性的，而非对本公开的范围进行限制。其它规则数目、Np的其它数值以及Nf的其它数值是可能的。
在一个仿真时间段期间，强化学习350选择并使用一个固定的规则(例如，规则A：Np＝1.2，Nf＝16)，电子设备在该仿真时间段期间利用包含第一因子Nf和第二因子Np的该规则如图3的318或326所示地来对仿真步长进行调整，并且确定在相应的仿真时间段期间所执行的迭代数目，例如对相应仿真时间段期间的迭代次数k进行累加以进行统计。
为了评价各个规则在仿真过程中的效果，可以使用强化学习来对各个规则进行评价并且给予相应奖励。强化学习可以基于初始仿真的统计数据给予相应奖励，并且继而统计给予奖励后的强化阶段的仿真结果并且继续给予相应奖励，以此类推，直至强化学习的最大奖励稳定地对应于某个规则。该规则即为强化学习得到的目标规则。在一个实施例中，电子设备继而可以使用该优选的目标规则进行后续仿真，以减少电路仿真所需的时间。在另一实施例中，强化学习350可以在电路仿真阶段持续执行，直至电路仿真结束。本公开对此不加限制。
在一些实施例中，多个仿真时间段包括多个初始仿真时间段和在多个初始仿真时间段之后的多个强化仿真时间段，并且多个奖励包括与多个初始仿真时间段对应的多个初始奖励和与多个强化仿真时间段对应的多个强化奖励。
在多个初始仿真时间段中的一个初始仿真时间段期间，强化学习350选择并使用多个规则中的一个规则。电子设备利用该规则在图3的318或326对仿真步长进行调整，以获得与该初始仿真时间段对应的初始奖励。在一些实施例中，与初始仿真时间段对应的初始奖励可以由下面的式子(7)表示：
Figure PCTCN2021108728-appb-000008
其中，F表示在初始仿真时间段i中使用的规则，P i(F)表示规则F的初始奖励，也称为迭代时间，i表示第i个仿真时间段，T i表示初始仿真时间段i的时间长度，K i表示电子设备在初始仿真时间段i中所执行的迭代的数目。
可以看到，迭代时间与电子设备在单位仿真时间段中所执行的迭代的数目成反比。 迭代时间越大，即初始奖励越大，电子设备在单位仿真时间段中所执行的迭代数目越少。较少的迭代数目通常意味着针对同一仿真时间段的较快的仿真速度。因此，可以通过该迭代时间(即，初始奖励)来衡量使用特定规则的仿真速度。
应当理解的是，其它初始奖励是可能的，本公开对此不加限制。例如，还可以使用单位时间内成功迭代的次数占总迭代次数的比例。
在一个实施例中，在多个初始仿真时间段期间，强化学习350依次选择并使用多个规则中的一个规则以用于电路仿真，以便获得每个规则的与初始仿真时间段分别对应的初始奖励。通过这种方式，可以在仿真开始后就遍历所有规则，以获得对各个规则的仿真加速效果的初步判断，以便于在后续的仿真中能够选择出最合适的规则。
强化学习350至少基于多个初始奖励从多个规则中选择在多个强化仿真时间段期间使用的一个或多个规则。在一些实施例中，强化学习350可以选择与多个初始奖励中最大的初始奖励对应的规则(例如，规则A)，以用于多个强化仿真时间段中的第一强化仿真时间段。电子设备基于所选择的规则A来在该第一强化仿真时间段期间对电路进行仿真，并获得与该规则A对应的强化奖励R(A)。
在一些实施例中，强化奖励可以由下面的式子(8)表示。
Figure PCTCN2021108728-appb-000009
其中，G表示在强化阶段使用的规则，R(G)表示规则G的强化奖励，j表示第j个仿真时间段(其中j>N rule)，
Figure PCTCN2021108728-appb-000010
表示在前j-1个仿真时间段中使用规则G的所有仿真时间段的平均迭代时间，即前j-1个仿真时间段中使用G规则时每个迭代步骤所花费的时间。N j(G)表示前j-1个仿真时间段中使用规则G的总次数，log j表示当前仿真时间段数目j的对数。
在一些实施例中，在式子(8)中，平均迭代时间
Figure PCTCN2021108728-appb-000011
与电子设备在单位仿真时间段中所执行的迭代数目成反比，从而可以衡量规则G的在先前所执行的仿真中获得的仿真加速效果。然后，加权值
Figure PCTCN2021108728-appb-000012
可以对被选择的次数较少的规则进行补偿，以避免强化学习350忽略尝试这些规则。因此，强化奖励R(G)使得强化学习350能够充分且全面地评估各个规则的仿真加速效果，以确定最适于当前仿真情形的规则。
应当理解的是，虽然以式子(8)示出了一种强化奖励的具体实现方式，但是本公开的范围不限于此。可以针对不同的电路、所使用的数值积分方法、迭代方法等使用不同的奖励方式。
在一些实施例中，电子设备可以构建强化奖励集合。强化奖励集合包括源自于多个初始奖励的、与多个规则分别对应的多个强化奖励。强化奖励集合中的每个元素对应于与每个规则对应的最新的奖励。在强化学习的过程中，强化学习350例如可以使用上面的式子(8)计算当前的强化奖励，并且使用根据当前规则确定的与当前仿真时间段对应的当前强化奖励来更新强化奖励集合。例如，在一个强化仿真时间段期间使用规则B进行仿真，并且所计算出的对应于规则B的强化奖励为5。强化学习350使用5来更新原来的强化奖励集合[规则A:1,规则B:3,规则C:4,规则D:6，规则E:2]。更新后的强化奖励集合为[规则A:1,规则B:5,规则C:4,规则D:6，规则E:2]。强化学习350因此可以使用规则D作为下一强化时间段所使用的规则。通过这种方式，可以实时更新对各个规则的仿真加速效果的评价，以便能够实时地选择出最适于当前仿真情形的规则。
强化学习350基于与当前强化仿真时间段对应的当前强化奖励集合，从多个规则中选择在当前强化仿真时间段之后的下一强化仿真时间段使用的规则。在一些实施例中，强化学习350从多个规则中选择具有在当前强化奖励集合中的最大强化奖励的规则作为在下一强化仿真时间段使用的规则。例如，当前强化奖励集合为[规则A:1,规则B:5,规则C:4,规则D:6，规则E:2]，该集合中的最大强化奖励6对应于规则D，因此强化学习350可以选择规则D作为下一强化时间段所使用的规则。通过选择具有最大强化奖励的规则，使得能够在下一强化仿真时间段中应用基于历史信息预测能够实现最佳仿真加速效果的规则。
在强化仿真时间段中，电子设备使用强化学习350所选择的规则对电路进行仿真，强化学习350至少基于强化仿真时间段以及在该强化仿真时间段期间的迭代数目，来确定所选择的规则的与该强化仿真时间段对应的强化奖励。例如，强化学习350可以借助于上文描述的式子(8)来针对每个强化仿真时间段计算与所使用的规则G相对应的强化奖励R(G)。
强化学习350通过上文所描述的方式，针对每个仿真时间段选择并使用一个规则，基于使用该规则在相应仿真时间段的迭代数目来更新强化奖励集合，并基于更新后的强化奖励集合选择并使用用于下一仿真时间段的规则。通过这种方式，强化学习350可以持续地对各个规则的仿真加速效果进行评估，以便能够更为准确地选择出最适于当前仿真情形的规则。
在404，电子设备至少基于多个奖励确定目标规则。如上所述，强化学习可以用于确定在后续仿真过程中使用的目标规则，以使得后续的仿真过程以较为合适的步长进行，从而减少计算量并且缩短仿真时间。通过强化学习，在一段仿真时间之后，电子设备会稳定地选择某个规则。该规则即为针对该电路的仿真所适用的规则，也即目标规则。
在一些实施例中，如果与多个连续时间段对应的多个奖励是使用相同的规则得到的并且该多个连续时间段的总时间长度超过时间阈值，将该相同的规则确定为目标规则。例如，如果强化学习在20个连续时间段内都选择并使用规则A，并且这20个连续时间段的总时间长度超过时间阈值100ns，则电子设备可以将该规则A确定为目标规则。应当理解，时间阈值的以上数值仅是示例性的，本公开的范围在此方面不受限制。
在一些实施例中，强化学习350响应于与多个连续时间段对应的多个奖励是使用相同的规则得到的并且该多个连续时间段的时间段数目超过时间段数目阈值，将该相同的规则确定为目标规则。例如，如果时间段数目阈值为30，并且强化学习在31个连续时间段内都选择并使用规则B，则电子设备可以将该规则B确定为目标规则。应当理解，时间段数目阈值的以上数值仅是示例性的，本公开的范围在此方面不受限制。
强化学习350在较长的时间段中保持选择并使用同一规则，这意味着该规则所对应的强化奖励在该较长的时间段中始终是强化奖励集合中最大的元素。也就是说，使用该规则能够使得电子设备在单位仿真时间段中所执行的迭代数目最少。较少的迭代数目通常意味着较快的仿真速度，因此与其它规则相比，该同一规则能够实现最佳的仿真加速效果。
应当理解的是，其它用于确定目标规则的策略也是可能的，本公开的范围在此方面不受限制。例如，可以在诸如1μs的预定仿真时间之后，选择具有最大奖励的规则作为目标规则。
因此，通过这种方式，可以将具有最佳的仿真加速效果的规则确定为目标规则，以用于在随后的仿真时间段中对电路进行仿真，从而在随后的仿真时间段中在最大程度上加快仿真速度。
在406，电子设备使用目标规则对电路进行第二仿真。在一些实施例中，在确定目标规则之后，强化学习350可以结束学习过程，在剩余的时间段中始终选择并使用该目标规则。通过使用具有最佳的仿真加速效果的目标规则对电路进行仿真，可以加快电子设备执行后续仿真的速度，从而降低执行整个仿真所需要的时间。
在另一些实施例中，还可以不结束强化学习350的学习过程，而是在整个仿真中始终使用由强化学习350所选择的规则来对电路进行仿真。因此，本公开的范围在此方面不受限制。
通过以上描述可以看到，本公开的实施例的方法400可以使用强化学习350来对电路在多个规则下的仿真参数进行收集和分析，并且确定与多个规则对应的奖励，以在一段时间之后选择具有最高奖励的规则作为用于进行后续仿真的目标规则。基于目标规则的电路仿真可以具有较合适的仿真步长并且具有较高的仿真成功率，因此可以极大地减小电子设备的计算量并且相应地减少电路仿真所需的时间。
图5示出了根据本公开实施例的用于对电路进行仿真的示例装置500的框图。该装置500例如可以用于实现电子设备。如图5所示，装置500可以包括奖励确定单元502，用于使用多个规则对电路进行第一仿真以确定与多个仿真时间段对应的多个奖励。装置500还可以包括目标规则确定单元504，用于至少基于多个奖励确定目标规则。此外，装置500还可以包括仿真单元506，用于使用目标规则对电路进行第二仿真。
在一些实施例中，多个仿真时间段包括多个初始仿真时间段和在多个初始仿真时间段之后的多个强化仿真时间段，并且多个奖励包括与多个初始仿真时间段对应的多个初始奖励和与多个强化仿真时间段对应的多个强化奖励，奖励确定单元502包括：初始奖励获得单元，用于使用多个规则依次对电路进行仿真以获得与多个仿真时间段中的多个初始仿真时间段分别对应的多个初始奖励；规则选择单元，用于至少基于多个初始奖励，从多个规则中选择在多个强化仿真时间段期间使用的一个或多个规则；以及强化奖励确定单元，用于使用所确定的一个或多个规则对电路进行仿真以确定与多个强化仿真时间段对应的多个强化奖励。
在一些实施例中，规则选择单元进一步用于：基于与当前强化仿真时间段对应的当前强化奖励集合，从多个规则中选择在当前强化仿真时间段之后的下一强化仿真时间段使用的规则，当前强化奖励集合包括源自于多个初始奖励的、与多个规则分别对应的多个当前强化奖励。
在一些实施例中，规则选择单元进一步用于：从多个规则中选择具有在当前强化奖励集合中的最大强化奖励的规则作为在下一强化仿真时间段使用的规则。
在一些实施例中，仿真单元506进一步用于：响应于与多个连续时间段对应的多个奖励是使用相同的规则得到的并且多个连续时间段的总时间长度超过时间阈值，将相同的规则确定为目标规则。
装置500中所包括的模块和/或单元可以利用各种方式来实现，包括软件、硬件、固件或其任意组合。在一些实施例中，一个或多个单元可以使用软件和/或固件来实现，例如存储在存储介质上的机器可执行指令。除了机器可执行指令之外或者作为替代，装置 500中的部分或者全部单元可以至少部分地由一个或多个硬件逻辑组件来实现。作为示例而非限制，可以使用的示范类型的硬件逻辑组件包括现场可编程门阵列(FPGA)、专用集成电路(ASIC)、专用标准品(ASSP)、片上系统(SOC)、复杂可编程逻辑器件(CPLD)，等等。
图5中所示的这些模块和/或单元可以部分或者全部地实现为硬件模块、软件模块、固件模块或者其任意组合。特别地，在某些实施例中，上文描述的流程、方法或过程可以由存储系统或与存储系统对应的主机或独立于存储系统的其它计算设备中的硬件来实现。
图6示出了可以用于实施本公开的实施例的示例设备600的示意性框图。设备600可以用于实现电子设备。如图6所示，设备600包括中央处理单元(CPU)601，其可以根据存储在只读存储器(ROM)602中的计算机程序指令或者从存储单元608加载到随机访问存储器(RAM)603中的计算机程序指令，来执行各种适当的动作和处理。在RAM 603中，还可存储设备600操作所需的各种程序和数据。CPU 601、ROM 602以及RAM 603通过总线604彼此相连。输入/输出(I/O)接口605也连接至总线604。
设备600中的多个部件连接至I/O接口605，包括：输入单元606，例如键盘、鼠标等；输出单元607，例如各种类型的显示器、扬声器等；存储单元608，例如磁盘、光盘等；以及通信单元609，例如网卡、调制解调器、无线通信收发机等。通信单元609允许设备600通过诸如因特网的计算机网络和/或各种电信网络与其它设备交换信息/数据。
处理单元601执行上文所描述的各个方法和处理，例如方法400。例如，在一些实施例中，方法400可被实现为计算机软件程序，其被有形地包含于机器可读介质，例如存储单元608。在一些实施例中，计算机程序的部分或者全部可以经由ROM 602和/或通信单元609而被载入和/或安装到设备600上。当计算机程序加载到RAM 603并由CPU 601执行时，可以执行上文描述的方法400的一个或多个步骤。备选地，在其它实施例中，CPU 601可以通过其它任何适当的方式(例如，借助于固件)而被配置为执行方法400。
本文中以上描述的功能可以至少部分地由一个或多个硬件逻辑部件来执行。例如，非限制性地，可以使用的示范类型的硬件逻辑部件包括：场可编程门阵列(FPGA)、专用集成电路(ASIC)、专用标准产品(ASSP)、芯片上系统的系统(SOC)、负载可编程逻辑设备(CPLD)等等。
用于实施本公开的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其它可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦 除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
此外，虽然采用特定次序描绘了各操作，但是这应当理解为要求这样操作以所示出的特定次序或以顺序次序执行，或者要求所有图示的操作应被执行以取得期望的结果。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实现中。相反地，在单个实现的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实现中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (20)

  1. 一种用于对电路进行仿真的方法，包括：
    使用多个规则对所述电路进行第一仿真以确定与多个仿真时间段对应的多个奖励；
    至少基于所述多个奖励确定目标规则；以及
    使用所述目标规则对所述电路进行第二仿真。
  2. 根据权利要求1所述的方法，其中所述多个仿真时间段包括多个初始仿真时间段和在所述多个初始仿真时间段之后的多个强化仿真时间段，并且所述多个奖励包括与所述多个初始仿真时间段对应的多个初始奖励和与所述多个强化仿真时间段对应的多个强化奖励，使用所述多个规则对所述电路进行所述第一仿真以确定与所述多个仿真时间段对应的多个奖励包括：
    使用所述多个规则依次对所述电路进行仿真以获得与所述多个仿真时间段中的多个初始仿真时间段分别对应的所述多个初始奖励；
    至少基于所述多个初始奖励，从所述多个规则中选择在所述多个强化仿真时间段期间使用的一个或多个规则；以及
    使用所选择的一个或多个规则对所述电路进行仿真以确定与所述多个强化仿真时间段对应的多个强化奖励。
  3. 根据权利要求2所述的方法，其中至少基于所述多个初始奖励从所述多个规则中选择在所述多个强化仿真时间段期间使用的一个或多个规则包括：
    从所述多个规则中选择与所述多个初始奖励中的最大初始奖励对应的规则作为在所述多个强化仿真时间段中的第一强化仿真时间段期间使用的规则。
  4. 根据权利要求2所述的方法，其中至少基于所述多个初始奖励从所述多个规则中选择在所述多个强化仿真时间段使用的一个或多个规则包括：
    基于与当前强化仿真时间段对应的当前强化奖励集合，从所述多个规则中选择在所述当前强化仿真时间段之后的下一强化仿真时间段使用的规则，所述当前强化奖励集合包括源自于所述多个初始奖励的、与所述多个规则分别对应的多个当前强化奖励。
  5. 根据权利要求4所述的方法，其中基于与当前强化仿真时间段对应的当前强化奖励集合从所述多个规则中选择在所述当前强化仿真时间段之后的下一强化仿真时间段使用的规则包括：
    从所述多个规则中选择具有在所述当前强化奖励集合中的最大强化奖励的规则作为在所述下一强化仿真时间段使用的规则。
  6. 根据权利要求4或5所述的方法，还包括：
    使用根据当前规则确定的与当前仿真时间段对应的当前强化奖励来更新所述当前强化奖励集合。
  7. 根据权利要求2所述的方法，其中使用所确定的一个或多个规则对所述电路进行仿真以确定与所述多个强化仿真时间段对应的多个强化奖励包括：
    使用所确定的一个或多个规则中的一个规则对所述电路进行仿真以确定与所述多个强化仿真时间段中的一个强化仿真时间段对应的迭代数目；以及
    至少基于所述迭代数目和所述一个强化仿真时间段，确定与所述一个强化仿真时间段对应的强化奖励。
  8. 根据权利要求7所述的方法，其中至少基于所述迭代数目和所述一个强化仿真时间段确定与所述一个强化仿真时间段对应的强化奖励包括：
    至少基于所述迭代数目和所述一个强化仿真时间段确定与所述一个规则对应的平均迭代时间；
    基于所述一个规则被使用的次数确定加权值；以及
    基于所述平均迭代时间和所述加权值确定与所述一个强化仿真时间段对应的强化奖励。
  9. 根据权利要求1-8中任一项所述的方法，其中至少基于所述多个奖励确定目标规则包括：
    响应于与多个连续时间段对应的多个奖励是使用相同的规则得到的并且所述多个连续时间段的总时间长度超过时间阈值，将所述相同的规则确定为所述目标规则。
  10. 根据权利要求1-8中任一项所述的方法，其中至少基于所述多个奖励确定目标规则包括：
    响应于与多个连续时间段对应的多个奖励是使用相同的规则得到的并且所述多个连续时间段的时间段数目超过时间段数目阈值，将所述相同的规则确定为所述目标规则。
  11. 根据权利要求1-10中任一项所述的方法，其中所述多个规则包括：
    如果在使用所述多个规则中的一个规则的情形下，在一个仿真时间段期间使用一个仿真步长的迭代次数超过迭代次数阈值，则将所述一个仿真步长以第一因子缩短；以及
    如果在使用所述一个规则的情形下，在所述一个仿真时间段期间使用所述一个仿真步长的截断误差不大于截断误差阈值，则将所述一个仿真步长以第二因子缩放，所述第二因子不同于所述第一因子。
  12. 根据权利要求11所述的方法，其中所述多个规则中的每个规则所具有的第一因子和第二因子不同于所述多个规则中的另一规则所具有的第一因子和第二因子。
  13. 一种计算机可读存储介质，存储多个程序，所述多个程序被配置为由一个或多个处理器执行，所述多个程序包括用于执行权利要求1-12中任一项所述的方法的指令。
  14. 一种计算机程序产品，所述计算机程序产品包括多个程序，所述多个程序被配置为由一个或多个处理器执行，所述多个程序包括用于执行权利要求1-12中任一项所述的方法的指令。
  15. 一种电子设备，包括：
    一个或多个处理器；
    包括计算机指令的存储器，所述计算机指令在由所述电子设备的所述一个或多个处理器执行时使得所述电子设备执行权利要求1-12中任一项所述的方法。
  16. 一种电子设备，包括：
    奖励确定单元，用于使用多个规则对电路进行第一仿真以确定与多个仿真时间段对应的多个奖励；
    目标规则确定单元，用于至少基于所述多个奖励确定目标规则；以及
    仿真单元，用于使用所述目标规则对所述电路进行第二仿真。
  17. 根据权利要求16所述的电子设备，其中所述多个仿真时间段包括多个初始仿真时间段和在所述多个初始仿真时间段之后的多个强化仿真时间段，并且所述多个奖励包括与所述多个初始仿真时间段对应的多个初始奖励和与所述多个强化仿真时间段对应的多个强化奖励，所述奖励确定单元包括：
    初始奖励获得单元，用于使用所述多个规则依次对所述电路进行仿真以获得与所述多个仿真时间段中的多个初始仿真时间段分别对应的所述多个初始奖励；
    规则选择单元，用于至少基于所述多个初始奖励，从所述多个规则中选择在所述多个强化仿真时间段期间使用的一个或多个规则；以及
    强化奖励确定单元，用于使用所确定的一个或多个规则对所述电路进行仿真以确定与所述多个强化仿真时间段对应的多个强化奖励。
  18. 根据权利要求17所述的电子设备，其中所述规则选择单元进一步用于：
    基于与当前强化仿真时间段对应的当前强化奖励集合，从所述多个规则中选择在所述当前强化仿真时间段之后的下一强化仿真时间段使用的规则，所述当前强化奖励集合包括源自于所述多个初始奖励的、与所述多个规则分别对应的多个当前强化奖励。
  19. 根据权利要求18所述的电子设备，其中所述规则选择单元进一步用于：
    从所述多个规则中选择具有在所述当前强化奖励集合中的最大强化奖励的规则作为在所述下一强化仿真时间段使用的规则。
  20. 根据权利要求16-19中任一项所述的电子设备，其中所述仿真单元进一步用于：
    响应于与多个连续时间段对应的多个奖励是使用相同的规则得到的并且所述多个连续时间段的总时间长度超过时间阈值，将所述相同的规则确定为所述目标规则。
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CN110187647A (zh) * 2018-02-23 2019-08-30 北京京东尚科信息技术有限公司 模型训练方法及系统
CN112215363A (zh) * 2019-07-12 2021-01-12 罗伯特·博世有限公司 用于为机器人创建策略的方法、设备和计算机程序
CN113158608A (zh) * 2021-02-26 2021-07-23 北京大学 确定模拟电路参数的处理方法、装置、设备及存储介质

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