WO2022267115A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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Publication number
WO2022267115A1
WO2022267115A1 PCT/CN2021/106810 CN2021106810W WO2022267115A1 WO 2022267115 A1 WO2022267115 A1 WO 2022267115A1 CN 2021106810 W CN2021106810 W CN 2021106810W WO 2022267115 A1 WO2022267115 A1 WO 2022267115A1
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Prior art keywords
layer
opening
sub
connection part
array substrate
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Ceased
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PCT/CN2021/106810
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English (en)
French (fr)
Inventor
王若男
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/427,612 priority Critical patent/US12114546B2/en
Publication of WO2022267115A1 publication Critical patent/WO2022267115A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80517—Multilayers, e.g. transparent multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the display field, and in particular to an array substrate and a display panel.
  • the planarization layer of the array substrate contains sulfur element.
  • One side of the planarization layer is usually the anode layer.
  • the material of the anode layer usually contains silver element.
  • Sulfur (S) in the planarization layer easily diffuses to the anode layer to form black silver (Ag) sulfide.
  • the purpose of the present application is to provide an array substrate and a display panel, so as to solve the problem that dark spots of pixels are prone to appear in the display panel in the prior art.
  • the application provides an array substrate, including:
  • planarization layer is disposed on one side of the substrate, and the planarization layer includes a first opening;
  • connection layer comprising a connection part, the connection part is arranged in the first opening and extends to the surface of the planarization layer;
  • An anode layer, the anode layer is disposed on a side of the connecting portion away from the planarization layer.
  • connection part includes a first sub-connection part and a second sub-connection part, there is a gap between the first sub-connection part and the second sub-connection part, and the first sub-connection part Covering the first opening, the second sub-connection part is arranged on the surface of the planarization layer, the anode layer covers the first sub-connection part, the second sub-connection part and the The planarization layer at the location, the first sub-connection part and the second sub-connection part are connected through the anode layer.
  • the array substrate further includes a first metal layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a second metal layer, and a passivation layer that are sequentially stacked.
  • the second metal layer includes a source, a drain, and a first binding part, the source is connected to the connection part, and the first binding part is connected to the first metal layer connect.
  • the planarization layer further includes a second opening
  • the connection layer further includes a second binding portion
  • the second binding portion is disposed in the second opening
  • the first binding portion is disposed in the second opening.
  • the second binding part is connected with the first binding part.
  • the array substrate further includes a pixel definition layer, the pixel definition layer includes a first opening and a second opening, the first opening exposes the anode layer, the second opening is connected to the A second opening is provided correspondingly, and the second opening exposes the second binding portion.
  • the second metal layer further includes a first pole plate, and the first pole plate is connected to the first metal layer.
  • the material of the connecting layer includes one or more of molybdenum, titanium, molybdenum/titanium, titanium alloy and indium tin oxide.
  • the anode layer includes a first sublayer, a second sublayer and a third sublayer, the material of the first sublayer is indium tin oxide or indium zinc oxide, and the material of the second sublayer is The material is silver or silver alloy, and the material of the third sublayer is indium tin oxide or indium zinc oxide.
  • connection portion between the anode layer and the planarization layer has a thickness of 30 nm to 300 nm.
  • the present application also provides a display panel, the display panel includes an array substrate, and the array substrate includes:
  • planarization layer is disposed on one side of the substrate, and the planarization layer includes a first opening;
  • connection layer comprising a connection part, the connection part is arranged in the first opening and extends to the surface of the planarization layer;
  • An anode layer, the anode layer is disposed on a side of the connecting portion away from the planarization layer.
  • connection part includes a first sub-connection part and a second sub-connection part, there is a gap between the first sub-connection part and the second sub-connection part, and the first sub-connection part Covering the first opening, the second sub-connection part is arranged on the surface of the planarization layer, the anode layer covers the first sub-connection part, the second sub-connection part and the The planarization layer at the location, the first sub-connection part and the second sub-connection part are connected through the anode layer.
  • the array substrate further includes a first metal layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a second metal layer, and a passivation layer that are sequentially stacked.
  • the second metal layer includes a source, a drain, and a first binding part, the source is connected to the connection part, and the first binding part is connected to the first metal layer connect.
  • the planarization layer further includes a second opening
  • the connection layer further includes a second binding portion
  • the second binding portion is disposed in the second opening
  • the first binding portion is disposed in the second opening.
  • the second binding part is connected with the first binding part.
  • the array substrate further includes a pixel definition layer, the pixel definition layer includes a first opening and a second opening, the first opening exposes the anode layer, the second opening is connected to the A second opening is provided correspondingly, and the second opening exposes the second binding portion.
  • the second metal layer further includes a first pole plate, and the first pole plate is connected to the first metal layer.
  • the material of the connecting layer includes one or more of molybdenum, titanium, molybdenum/titanium, titanium alloy and indium tin oxide.
  • the anode layer includes a first sublayer, a second sublayer and a third sublayer, the material of the first sublayer is indium tin oxide or indium zinc oxide, and the material of the second sublayer is The material is silver or silver alloy, and the material of the third sublayer is indium tin oxide or indium zinc oxide.
  • connection portion between the anode layer and the planarization layer has a thickness of 30 nm to 300 nm.
  • the present application provides an array substrate and a display panel.
  • the array substrate includes a substrate, a planarization layer, a connection layer and an anode layer.
  • the planarization layer is disposed on one side of the substrate.
  • the planarization layer includes first openings.
  • the connection layer includes a connection part.
  • the connecting portion is disposed in the first opening and extends to the surface of the planarization layer.
  • the anode layer is disposed on a side of the connecting portion away from the planarization layer.
  • the array substrate provided by this application can prevent the sulfur element in the planarization layer from diffusing into the anode layer by providing a connection between the planarization layer and the anode layer, avoiding the formation of silver sulfide in the anode layer, thereby improving the performance of the display panel.
  • the occurrence of the problem of dark pixels is beneficial to improve the display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • Fig. 2 is a cross-sectional view along line AA' of the first embodiment of the array substrate provided by the present application.
  • Fig. 3 is a cross-sectional view along line AA' of the second embodiment of the array substrate provided by the present application.
  • Fig. 4 is a cross-sectional view along line AA' of the third embodiment of the array substrate provided by the present application.
  • FIG. 5 is a flowchart of a method for preparing an array substrate provided in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • serial numbers such as [first], [second], [third] and [fourth] mentioned in this application do not represent any order, quantity or importance, but are only used to distinguish different part.
  • the directional terms such as [upper], [lower], [left] and [right] mentioned in this application are only directions referring to the attached drawings. Therefore, the used serial numbers, directional terms and positional relational terms are used to illustrate and understand the present application, but not to limit the present application.
  • structurally similar units are denoted by the same reference numerals.
  • the present application provides an array substrate, and the present application will be described in detail below with reference to specific embodiments.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • Fig. 2 is a cross-sectional view along line AA' of the first embodiment of the array substrate provided by the present application.
  • the array substrate 100 includes a substrate 101 , a planarization layer 102 , a connection layer 103 and an anode layer 104 .
  • the planarization layer 102 is disposed on one side of the substrate 101 .
  • the planarization layer 102 includes a first opening 1021 .
  • the connection layer 103 includes a connection part 1031 .
  • the connecting portion 1031 is disposed in the first opening 1021 and extends to the surface of the planarization layer 102 .
  • the anode layer 104 is disposed on a side of the connecting portion 1031 away from the planarization layer 102 .
  • the substrate 101 may be a glass substrate or a flexible substrate.
  • the planarization layer 102 may be formed of one or more organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.
  • the thickness of the planarization layer 102 is 100 nm to 500 nm. Specifically, the thickness of the planarization layer 102 may be 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers or 500 nanometers.
  • the connection layer 103 may be formed of one or more of molybdenum (Mo), titanium (Ti), molybdenum (Mo)/titanium (Ti), an alloy of titanium (Ti), and indium tin oxide (ITO).
  • Silver (Ag) and silver alloy (APC) can react with sulfur (S) to form black silver (Ag) sulfide. If black silver (Ag) sulfide is formed on the anode layer, it is easy to cause a short circuit between the cathode and the anode, resulting in dark spots of pixels on the display panel.
  • the array substrate 100 provided in this application can prevent the sulfur (S) element in the planarization layer 102 from diffusing
  • the alloy (APC) reacts to form black silver (Ag) sulfide, so as to avoid the short circuit between the cathode and the anode, resulting in dark pixels on the display panel, which is conducive to improving the display effect of the display panel.
  • connection portion 1031 between the anode layer 104 and the planarization layer 102 has a thickness of 30 nm to 300 nm.
  • the thickness of the connecting portion 1031 located between the anode layer 104 and the planarization layer 102 may be 30 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm.
  • the present application sets the thickness of the connecting portion 1031 between the anode layer 104 and the planarization layer 102 to be 30 nm to 300 nm.
  • FIG. 3 is a cross-sectional view along line AA' of the second embodiment of the array substrate provided by the present application.
  • the anode layer 104 includes a first sublayer 1041 , a second sublayer 1042 and a third sublayer 1043 .
  • the material of the first sub-layer 1041 may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the material of the second sub-layer 1042 may be silver (Ag) or an alloy of silver (APC). Among them, APC is an alloy formed of silver (Ag), palladium (Pd), and copper (Cu).
  • the material of the third sublayer 1043 may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the anode layer 104 is set as a laminated structure including the first sublayer 1041, the second sublayer 1042 and the third sublayer 1043, and the electrode material is silver (Ag) or silver alloy (APC).
  • the second sublayer is arranged in the middle of the stack, which can further prevent the sulfur (S) element in the planarization layer 102 from diffusing into the anode layer 104 to react with silver (Ag) or silver alloy (APC) to form black silver (Ag).
  • S sulfur
  • Ag silver alloy
  • sulfide so as to avoid the short circuit between the cathode and the anode, resulting in dark pixels on the display panel, which is conducive to improving the display effect of the display panel.
  • the array substrate 100 may further include a first metal layer 105, a buffer layer 106, a semiconductor layer 107, a gate insulating layer 108, a gate layer 109, an interlayer dielectric layer 110, a second metal layer 111 and passivation layer 112 .
  • the first metal layer 105 is disposed on one side of the substrate 101 .
  • the first metal layer 105 may be formed of stacked metal Cu/Ti or Cu/Mo/Ti. By disposing Mo between Cu and Ti, the adhesion between Cu and Ti can be improved.
  • the thickness of the first metal layer 105 is 50 nm to 200 nm. Specifically, the thickness of the first metal layer 105 may be 50 nanometers, 100 nanometers, 150 nanometers or 200 nanometers.
  • the first metal layer 105 includes a light shielding portion 1051 , a first metal portion 1052 and a second metal portion 1053 .
  • the buffer layer 106 is disposed on a side of the first metal layer 105 away from the substrate 101 .
  • the buffer layer 106 may be formed of one or more of silicon oxide (SiO x ), silicon nitride (SiN x ) or aluminum oxide (AlO x ).
  • the buffer layer 106 has a thickness of 100 nm to 500 nm. Specifically, the buffer layer 106 may have a thickness of 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.
  • the semiconductor layer 107 is disposed on a side of the buffer layer 106 away from the first metal layer 105 .
  • the semiconductor layer 107 may be formed of one or more of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO).
  • the thickness of the semiconductor layer 107 is 10 nm to 100 nm. Specifically, the thickness of the semiconductor layer 107 may be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.
  • the semiconductor layer 107 includes an active portion 1071 and a semiconductor portion 1072 .
  • the active portion 1071 includes a channel region and a non-channel region.
  • the gate insulating layer 108 is disposed on a side of the active portion 1071 away from the buffer layer 106 .
  • the orthographic projection of the gate insulating layer 108 on the substrate 101 falls within the range of the orthographic projection of the active portion 1071 on the substrate 101 .
  • the gate insulating layer 108 may be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), or a stack of silicon oxide (SiO x )/silicon nitride (SiN x ).
  • the gate insulating layer 108 has a thickness of 50 nm to 200 nm. Specifically, the thickness of the gate insulating layer 108 may be 50 nanometers, 100 nanometers, 150 nanometers or 200 nanometers.
  • the gate layer 109 is disposed on a side of the gate insulating layer 108 away from the semiconductor layer 107 .
  • the orthographic projection of the gate layer 109 on the substrate 101 falls within the range of the orthographic projection of the gate insulating layer 108 on the substrate 101 .
  • the gate layer 109 may be formed of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the gate layer 109 has a thickness of 200 nm to 800 nm. Specifically, the thickness of the gate layer 109 may be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm or 800 nm.
  • the interlayer dielectric layer 110 covers the buffer layer 106 , the semiconductor layer 107 , the gate insulating layer 108 and the gate layer 109 .
  • the interlayer dielectric layer 110 may be formed of silicon oxide (SiO x ), silicon nitride (SiN x ) or a stack of silicon oxide (SiO x )/silicon nitride (SiN x ).
  • the thickness of the interlayer dielectric layer 110 is 200 nm to 1000 nm. Specifically, the thickness of the interlayer dielectric layer 110 may be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm.
  • the second metal layer 111 is disposed on a side of the interlayer dielectric layer 110 away from the buffer layer 106 .
  • the second metal layer 111 may be formed of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the thickness of the second metal layer 111 is 200 nm to 800 nm. Specifically, the thickness of the second metal layer 111 may be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm or 800 nm.
  • the passivation layer 112 covers the second metal layer 111 .
  • the passivation layer 112 may be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), or a stack of silicon oxide (SiO x )/silicon nitride (SiN x ).
  • the passivation layer 112 has a thickness of 100 nm to 500 nm. Specifically, the thickness of the passivation layer 112 may be 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.
  • the second metal layer 111 includes a source 1111 , a drain 1112 and a first binding part 1113 .
  • the source 1111 is connected to the connection part 1031 .
  • the first binding portion 1113 is connected to the first metal layer 105 .
  • the source electrode 1111 is connected to the non-channel region of the active portion 1071 and the light shielding portion 1051 .
  • the drain 1112 is connected to the non-channel region of the active portion 1071 .
  • the first binding part 1113 is connected to the first metal part 1052 .
  • the second metal layer 111 also includes a first plate 1114 .
  • the first pole plate 1114 is connected to the first metal layer 105 .
  • the first pole plate 1114 is connected to the second metal part 1053 .
  • the preparation process of the array substrate 100 can be simplified and the cost of preparing the array substrate 100 can be saved.
  • the first pole plate 1114 is connected to the second metal part 1053 as a pole plate of the capacitor.
  • the semiconductor part 1072 is used as the other plate of the capacitor after being conductive.
  • the buffer layer 106 and the interlayer dielectric layer 110 serve as the insulating dielectric layer of the capacitor.
  • the planarization layer 102 further includes a second opening 1022 .
  • the connection layer 103 also includes a second binding part 1032 .
  • the second binding portion 1032 is disposed in the second opening 1022 .
  • the second binding part 1032 is connected with the first binding part 1113 .
  • the second binding part 1032 is connected to the first binding part 1113 .
  • the first binding part 1113 is connected to the first metal part 1052 , so as to realize the transmission of electrical signals from the external power source to the array substrate 100 .
  • the array substrate 100 further includes a pixel definition layer 113 .
  • the pixel definition layer 113 includes a first opening 1131 and a second opening 1132 .
  • the first opening 1131 exposes the anode layer 104 .
  • the second opening 1132 is disposed corresponding to the second opening 1022 .
  • the second opening 1132 exposes the second binding portion 1032 .
  • the pixel definition layer 113 may be formed of a high light-shielding material. For example, materials with light transmittance less than 15%.
  • a first opening 1131 exposing the anode layer 104 is formed in the pixel definition layer 113 , and a light-emitting unit can be subsequently prepared in the first opening 1131 .
  • the second opening 1132 exposing the second binding portion 1032 is formed in the pixel definition layer 113 , which can be subsequently used for external circuits to transmit electrical signals to the array substrate 100 .
  • FIG. 4 is a cross-sectional view along the line AA' of the third embodiment of the array substrate provided by the present application.
  • connection part 1031 includes a first sub-connection part 1031a and a second sub-connection part 1031b. There is a gap 1033 between the first sub-connection part 1031a and the second sub-connection part 1031b.
  • the first sub-connecting portion 1031 a covers the first opening 1021 .
  • the second sub-connection part 1031b is disposed on the surface of the planarization layer 102 .
  • the anode layer 104 covers the first sub-connection portion 1031 a , the second sub-connection portion 1031 b and the planarization layer 102 located at the gap 1033 .
  • the first sub-connection part 1031 a and the second sub-connection part 1031 b are connected through the anode layer 104 .
  • the thickness of the second sub-connecting portion 1031b is 30 nm to 300 nm.
  • the thickness of the second sub-connecting portion 1031b may be 30 nanometers, 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers or 300 nanometers.
  • the array substrate 100 provided in the present application is provided with a connection part 1031 between the planarization layer 102 and the anode layer 104 .
  • the connection part 1031 includes a first sub-connection part 1031a and a second sub-connection part 1031b. There is a gap 1033 between the first sub-connection part 1031a and the second sub-connection part 1031b.
  • the first sub-connecting portion 1031 a covers the first opening 1021 .
  • the second sub-connection part 1031b is disposed on the surface of the planarization layer 102 .
  • the anode layer 104 covers the first sub-connection portion 1031 a , the second sub-connection portion 1031 b and the planarization layer 102 located at the gap 1033 .
  • the first sub-connection part 1031a and the second sub-connection part 1031b are connected through the anode layer 104, which can prevent the sulfur (S) element in the planarization layer 102 from diffusing into the anode layer 104 with silver (Ag) or silver alloy (APC)
  • the reaction forms black silver (Ag) sulfide, thereby avoiding the short circuit between the cathode and the anode, resulting in dark spots of pixels on the display panel, which is beneficial to improving the display effect of the display panel.
  • the gap 1033 between the first sub-connection part 1031a and the second sub-connection part 1031b the contact area between the anode layer 104 and the connection layer 103 can be increased to improve the stability of signal transmission.
  • FIG. 5 is a flowchart of a method for preparing an array substrate provided in an embodiment of the present application.
  • the present application provides a method for preparing an array substrate, including:
  • Step B10 forming a first metal layer on one side of the substrate, and patterning the first metal layer to form a light shielding portion, a first metal portion, and a second metal portion.
  • the substrate may be a glass substrate or a flexible substrate.
  • the first metal layer may be formed of stacked metals Cu/Ti or Cu/Mo/Ti. By disposing Mo between Cu and Ti, the adhesion between Cu and Ti can be improved.
  • the thickness of the first metal layer is 50 nm to 200 nm. Specifically, the thickness of the first metal layer may be 50 nanometers, 100 nanometers, 150 nanometers or 200 nanometers.
  • Step B20 forming a buffer layer covering the first metal layer.
  • the buffer layer may be formed of one or more of silicon oxide (SiO x ), silicon nitride (SiN x ) and aluminum oxide (AlO x ).
  • the buffer layer has a thickness of 100 nm to 500 nm. Specifically, the thickness of the buffer layer may be 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.
  • Step B30 sequentially forming a semiconductor layer, a gate insulating layer, a gate layer and an interlayer dielectric layer on the side of the buffer layer away from the first metal layer.
  • the semiconductor layer may be formed of one or more of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), or indium gallium zinc tin oxide (IGZTO).
  • the thickness of the semiconductor layer is 10 nm to 100 nm. Specifically, the thickness of the semiconductor layer may be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.
  • the gate insulating layer may be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), or a stack of silicon oxide (SiO x )/silicon nitride (SiN x ).
  • the gate insulating layer has a thickness of 50 nm to 200 nm. Specifically, the thickness of the gate insulating layer may be 50 nanometers, 100 nanometers, 150 nanometers or 200 nanometers.
  • the gate layer may be formed of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the gate layer has a thickness of 200 nm to 800 nm. Specifically, the thickness of the gate layer may be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm or 800 nm.
  • the interlayer dielectric layer may be formed of silicon oxide (SiO x ), silicon nitride (SiN x ) or a stack of silicon oxide (SiO x )/silicon nitride (SiN x ).
  • the thickness of the interlayer dielectric layer is 200 nm to 1000 nm. Specifically, the thickness of the interlayer dielectric layer may be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm.
  • the interlayer dielectric layer may also include: forming a gate on the gate metal pattern; and then patterning the gate insulating layer by using the gate pattern for self-alignment.
  • the gate insulating layer exists only under the film layer with the gate pattern, and the gate insulating layer is etched away in other places.
  • the gate insulating layer is etched away in other places.
  • it may also include: plasma treatment on the semiconductor layer.
  • the resistance is significantly reduced after the plasma treatment, and an N+ conductor layer is formed. Because the semiconductor layer under the gate insulating layer has not undergone plasma treatment, it continues to maintain semiconductor characteristics.
  • the plasma treatment of the semiconductor layer may further include: patterning the semiconductor layer to form the active part and the semiconductor part.
  • a part of the active part after the plasma treatment can be used as a non-channel region of the thin film transistor.
  • a part of the active part that has not undergone plasma treatment can be used as a channel region of the thin film transistor.
  • the semiconductor part can be used as a plate of the capacitor.
  • Step B40 forming a second metal layer on the side of the interlayer dielectric layer away from the gate layer, and patterning the second metal layer to form a source, a drain, a first bonding portion and a first plate.
  • the source electrode and the non-channel region of the active part are connected to the light shielding layer.
  • the drain is connected to the non-channel region of the active portion.
  • the first binding part is connected with the first metal part.
  • the first pole plate is connected to the second metal part.
  • the second metal layer may be formed of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the thickness of the second metal layer is 200 nm to 800 nm. Specifically, the thickness of the second metal layer may be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm or 800 nm.
  • the second metal layer is patterned to form a source electrode, a drain electrode, a first binding part and a first electrode plate.
  • Step B50 Form a planarization layer covering the second metal layer, pattern the planarization layer to form a first opening and a second opening, the first opening exposes the source electrode, and the second opening exposes the first bond department.
  • the planarization layer may be formed of one or more organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.
  • the thickness of the planarization layer is 100 nm to 500 nm. Specifically, the thickness of the planarization layer may be 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.
  • Step B60 forming a connection layer on the surface of the planarization layer, the first opening and the second opening, patterning the connection layer to form a connection part and a second binding part, the connection part is located on the surface of the planarization layer and the first opening In the opening, the second binding part is located in the second opening.
  • connection layer is connected to the source.
  • the second binding part is connected to the first binding part.
  • the connection layer may be formed of one or more of molybdenum (Mo), titanium (Ti), molybdenum (Mo)/titanium (Ti), titanium (Ti) alloy and indium tin oxide (ITO).
  • the connection layer on the surface of the planarization layer has a thickness of 30 nanometers to 300 nanometers. Specifically, the thickness of the connection layer located on the surface of the planarization layer may be 30 nanometers, 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers or 300 nanometers.
  • Step B70 Form an anode layer and a pixel definition layer sequentially on the side of the connection portion away from the planarization layer, pattern the pixel definition layer to form a first opening and a second opening, the first opening exposes the anode layer, and the second opening exposes the second binding part.
  • the anode layer includes a first sublayer, a second sublayer and a third sublayer.
  • the material of the first sublayer may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the material of the second sub-layer may be silver (Ag) or an alloy of silver (APC). Among them, APC is an alloy formed of silver (Ag), palladium (Pd), and copper (Cu).
  • the material of the third sublayer may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the pixel definition layer may be formed of high light-shielding material. For example, materials with light transmittance less than 15%.
  • Silver (Ag) and silver alloy (APC) can react with sulfur (S) to form black silver (Ag) sulfide. If black silver (Ag) sulfide is formed on the anode layer, it is easy to cause a short circuit between the cathode and the anode, resulting in dark spots of pixels on the display panel.
  • the array substrate provided in this application can prevent the sulfur (S) element in the planarization layer from diffusing into the anode layer 104 and silver (Ag) or silver alloy (APC) by providing a connection between the planarization layer and the anode layer
  • the reaction forms black silver (Ag) sulfide, thereby avoiding the short circuit between the cathode and the anode, resulting in dark spots of pixels on the display panel, which is conducive to improving the display effect of the display panel.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 1000 provided in this application includes the array substrate 100 as described in any previous embodiment.
  • the display panel provided by the present application includes an array substrate.
  • the array substrate provided by this application can prevent the sulfur (S) element in the planarization layer from diffusing into the anode layer with silver (Ag) or silver alloy (APC ) reaction to form black silver (Ag) sulfide, thereby avoiding the short circuit between the cathode and the anode, resulting in dark pixels on the display panel, which is conducive to improving the display effect of the display panel.

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Abstract

本申请提供一种阵列基板和显示面板。阵列基板包括基板、平坦化层、连接层以及阳极层。所述平坦化层设置在所述基板的一侧，所述平坦化层包括第一开孔。所述连接层包括连接部，所述连接部设置在所述第一开孔内并延伸至所述平坦化层的表面。所述阳极层设置在所述连接部远离所述平坦化层的一侧。本申请提供的阵列基板通过在平坦化层与阳极层之间设置连接部，可以避免显示面板出现像素暗点。

Description

阵列基板和显示面板 技术领域
本申请涉及显示领域，尤其涉及一种阵列基板和显示面板。
 背景技术
目前阵列基板的平坦化层中含有硫元素。平坦化层的一侧通常为阳极层。阳极层的材料通常含有银元素。平坦化层中的硫元素（S）容易扩散至阳极层形成黑色的银（Ag）的硫化物。当上述阵列基板用于显示面板时，容易造成显示面板出现像素暗点的问题。因此，需要提出一种解决方案，以避免显示面板出现像素暗点。
 技术问题
本申请的目的在于提供一种阵列基板和显示面板，以解决现有技术中显示面板容易出现像素暗点的问题。
 技术解决方案
本申请提供一种阵列基板，包括：
基板；
平坦化层，所述平坦化层设置在所述基板的一侧，所述平坦化层包括第一开孔；
连接层，所述连接层包括连接部，所述连接部设置在所述第一开孔内并延伸至所述平坦化层的表面；
阳极层，所述阳极层设置在所述连接部远离所述平坦化层的一侧。
在一些实施例中，所述连接部包括第一子连接部和第二子连接部，所述第一子连接部和所述第二子连接部之间具有间隙，所述第一子连接部覆盖所述第一开孔，所述第二子连接部设置在所述平坦化层的表面，所述阳极层覆盖所述第一子连接部、所述第二子连接部以及位于所述间隙处的所述平坦化层，所述第一子连接部和所述第二子连接部通过所述阳极层连接。
在一些实施例中，所述阵列基板还包括依次层叠设置的第一金属层、缓冲层、半导体层、栅极绝缘层、栅极层、层间介质层、第二金属层以及钝化层。
在一些实施例中，所述第二金属层包括源极、漏极和第一绑定部，所述源极与所述连接部连接，所述第一绑定部与所述第一金属层连接。
在一些实施例中，所述平坦化层还包括第二开孔，所述连接层还包括第二绑定部，所述第二绑定部设置在所述第二开孔内，所述第二绑定部与所述第一绑定部连接。
在一些实施例中，所述阵列基板还包括像素定义层，所述像素定义层包括第一开口和第二开口，所述第一开口暴露出所述阳极层，所述第二开口与所述第二开孔对应设置，所述第二开口暴露出所述第二绑定部。
在一些实施例中，所述第二金属层还包括第一极板，所述第一极板与所述第一金属层连接。
在一些实施例中，所述连接层的材料包括钼、钛、钼/钛、钛的合金和氧化铟锡中的一种或多种。
在一些实施例中，所述阳极层包括第一子层、第二子层和第三子层，所述第一子层的材料为氧化铟锡或氧化铟锌，所述第二子层的材料为银或者银的合金，所述第三子层的材料为氧化铟锡或氧化铟锌。
在一些实施例中，位于所述阳极层与所述平坦化层之间的所述连接部的厚度为30纳米至300纳米。
本申请还提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
基板；
平坦化层，所述平坦化层设置在所述基板的一侧，所述平坦化层包括第一开孔；
连接层，所述连接层包括连接部，所述连接部设置在所述第一开孔内并延伸至所述平坦化层的表面；
阳极层，所述阳极层设置在所述连接部远离所述平坦化层的一侧。
在一些实施例中，所述连接部包括第一子连接部和第二子连接部，所述第一子连接部和所述第二子连接部之间具有间隙，所述第一子连接部覆盖所述第一开孔，所述第二子连接部设置在所述平坦化层的表面，所述阳极层覆盖所述第一子连接部、所述第二子连接部以及位于所述间隙处的所述平坦化层，所述第一子连接部和所述第二子连接部通过所述阳极层连接。
在一些实施例中，所述阵列基板还包括依次层叠设置的第一金属层、缓冲层、半导体层、栅极绝缘层、栅极层、层间介质层、第二金属层以及钝化层。
在一些实施例中，所述第二金属层包括源极、漏极和第一绑定部，所述源极与所述连接部连接，所述第一绑定部与所述第一金属层连接。
在一些实施例中，所述平坦化层还包括第二开孔，所述连接层还包括第二绑定部，所述第二绑定部设置在所述第二开孔内，所述第二绑定部与所述第一绑定部连接。
在一些实施例中，所述阵列基板还包括像素定义层，所述像素定义层包括第一开口和第二开口，所述第一开口暴露出所述阳极层，所述第二开口与所述第二开孔对应设置，所述第二开口暴露出所述第二绑定部。
在一些实施例中，所述第二金属层还包括第一极板，所述第一极板与所述第一金属层连接。
在一些实施例中，所述连接层的材料包括钼、钛、钼/钛、钛的合金和氧化铟锡中的一种或多种。
在一些实施例中，所述阳极层包括第一子层、第二子层和第三子层，所述第一子层的材料为氧化铟锡或氧化铟锌，所述第二子层的材料为银或者银的合金，所述第三子层的材料为氧化铟锡或氧化铟锌。
在一些实施例中，位于所述阳极层与所述平坦化层之间的所述连接部的厚度为30纳米至300纳米。
 有益效果
本申请提供一种阵列基板和显示面板。阵列基板包括基板、平坦化层、连接层以及阳极层。所述平坦化层设置在所述基板的一侧。所述平坦化层包括第一开孔。所述连接层包括连接部。所述连接部设置在所述第一开孔内并延伸至所述平坦化层的表面。所述阳极层设置在所述连接部远离所述平坦化层的一侧。本申请提供的阵列基板通过在平坦化层与阳极层之间设置连接部，可以阻挡平坦化层中的硫元素扩散至阳极层中，避免阳极层中形成银的硫化物，进而改善显示面板中出现像素暗点的问题，有利于提高显示面板的显示效果。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的结构示意图。
图2为本申请提供的阵列基板的第一种实施例沿AA’线的剖面图。
图3为本申请提供的阵列基板的第二种实施例沿AA’线的剖面图。
图4为本申请提供的阵列基板的第三种实施例沿AA’线的剖面图。
图5为本申请实施例提供的阵列基板的制备方法流程图。
图6为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明的是，本申请所提到的[第一]、[第二]、[第三]和[第四]等序号用语并不代表任何顺序、数量或者重要性，只是用于区分不同的部分。本申请所提到的[上]、[下]、[左]和[右]等方向用语仅是参考附加图式的方向。因此，使用的序号用语、方向用语和位置关系用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是以相同标号表示。
本申请提供一种阵列基板，下面将结合具体实施例对本申请进行详细说明。
请参阅图1-2，图1为本申请实施例提供的阵列基板的结构示意图。图2为本申请提供的阵列基板的第一种实施例沿AA’线的剖面图。
阵列基板100包括基板101、平坦化层102、连接层103以及阳极层104。平坦化层102设置在基板101的一侧。平坦化层102包括第一开孔1021。连接层103包括连接部1031。连接部1031设置在第一开孔1021内并延伸至平坦化层102的表面。阳极层104设置在连接部1031远离平坦化层102的一侧。
其中，基板101可以为玻璃基板或柔性基板。平坦化层102可以由丙烯酸树脂、环氧树脂、酚醛树脂、聚酰胺树脂或聚酰亚胺树脂等有机材料中的一种或多种形成。平坦化层102的厚度为100纳米至500纳米。具体的，平坦化层102的厚度可以为100纳米、200纳米、300纳米、400纳米或500纳米。连接层103可以由钼（Mo）、钛（Ti）、钼（Mo）/钛（Ti）、钛（Ti）的合金和氧化铟锡（ITO）中的一种或多种形成。
银（Ag）和银的合金（APC）可以与硫（S）反应形成黑色的银（Ag）的硫化物。如果阳极层上有黑色的银（Ag）的硫化物生成，容易造成阴极和阳极短路，导致显示面板出现像素暗点。本申请提供的阵列基板100通过在平坦化层102与阳极层104之间设置连接部1031，可以阻挡平坦化层102中的硫（S）元素扩散至阳极层104中与银（Ag）或银的合金（APC）反应形成黑色的银（Ag）的硫化物，从而避免因阴极和阳极短路，导致显示面板出现像素暗点，有利于提高显示面板的显示效果。
在一些实施例中，位于阳极层104与平坦化层102之间的连接部1031的厚度为30纳米至300纳米。具体的，位于阳极层104与平坦化层102之间的连接部1031的厚度可以为30纳米、50纳米、100纳米、150纳米、200纳米、250纳米或300纳米。
当位于阳极层104与平坦化层102之间的连接部1031的厚度过薄时，不能有效阻挡平坦化层102中的硫元素扩散至阳极层104中。当位于阳极层104与平坦化层102之间的连接部1031的厚度过厚时，不利于制备轻薄化的显示面板。因此，本申请设置位于阳极层104与平坦化层102之间的连接部1031的厚度为30纳米至300纳米。
请参阅图3，图3为本申请提供的阵列基板的第二种实施例沿AA’线的剖面图。
在一些实施例中，阳极层104包括第一子层1041、第二子层1042和第三子层1043。其中，第一子层1041的材料可以是氧化铟锡（ITO）或氧化铟锌（IZO）。第二子层1042的材料可以是银（Ag）或者银的合金（APC）。其中，APC是由银（Ag）、钯（Pd）和铜（Cu）形成的合金。第三子层1043的材料可以是氧化铟锡（ITO）或氧化铟锌（IZO）。
本申请通过将阳极层104设置为包括第一子层1041、第二子层1042和第三子层1043的叠层结构，并将电极材料为银（Ag）或者银的合金（APC）的第二子层设置在叠层的中间，可以进一步阻挡平坦化层102中的硫（S）元素扩散至阳极层104中与银（Ag）或银的合金（APC）反应形成黑色的银（Ag）的硫化物，从而避免因阴极和阳极短路，导致显示面板出现像素暗点，有利于提高显示面板的显示效果。
在一些实施例中，阵列基板100还可以包括依次层叠设置的第一金属层105、缓冲层106、半导体层107、栅极绝缘层108、栅极层109、层间介质层110、第二金属层111以及钝化层112。
第一金属层105设置在基板101的一侧。第一金属层105可以由叠层金属Cu/Ti或Cu/Mo/Ti形成。通过将Mo设置在Cu与Ti之间，可以提高Cu与Ti的贴合性。第一金属层105的厚度为50纳米至200纳米。具体的，第一金属层105的厚度可以为50纳米、100纳米、150纳米或200纳米。第一金属层105包括遮光部1051、第一金属部1052和第二金属部1053。
缓冲层106设置在第一金属层105远离基板101的一侧。缓冲层106可以由氧化硅（SiO X）、氮化硅（SiN X）或氧化铝（AlO X）一种或多种形成。缓冲层106的厚度为100纳米至500纳米。具体的，缓冲层106的厚度可以为100纳米、200纳米、300纳米、400纳米或500纳米。
半导体层107设置在缓冲层106远离所述第一金属层105的一侧。半导体层107可以由氧化铟镓锌（IGZO）、氧化铟锌锡（IZTO）或氧化铟镓锌锡（IGZTO）中的一种或多种形成。半导体层107的厚度为10纳米至100纳米。具体的，半导体层107的厚度可以为10纳米、20纳米、30纳米、40纳米、50纳米、60纳米、70纳米、80纳米、90纳米或100纳米。半导体层107包括有源部1071和半导体部1072。有源部1071包括沟道区和非沟道区。
栅极绝缘层108设置在有源部1071远离所述缓冲层106的一侧。栅极绝缘层108在基板101上的正投影落入到有源部1071在基板101上的正投影的范围内。栅极绝缘层108可以由氧化硅（SiO X）、氮化硅（SiN X）或氧化硅（SiO X）/氮化硅（SiN X）的叠层形成。栅极绝缘层108的厚度为50纳米至200纳米。具体的，栅极绝缘层108的厚度可以为50纳米、100纳米、150纳米或200纳米。
栅极层109设置在栅极绝缘层108远离所述半导体层107的一侧。栅极层109在基板101上的正投影落入到栅极绝缘层108在基板101上的正投影的范围内。栅极层109可以由钼（Mo）、钛（Ti）、铝（Al）或铜（Cu）的一种或多种形成。栅极层109的厚度为200纳米至800纳米。具体的，栅极层109的厚度可以为200纳米、300纳米、400纳米、500纳米、600纳米、700纳米或800纳米。
层间介质层110覆盖缓冲层106、半导体层107、栅极绝缘层108和栅极层109。层间介质层110可以由氧化硅（SiO X）、氮化硅（SiN X）或氧化硅（SiO X）/氮化硅（SiN X）的叠层形成。层间介质层110的厚度为200纳米至1000纳米。具体的，层间介质层110的厚度可以为200纳米、300纳米、400纳米、500纳米、600纳米、700纳米、800纳米、900纳米或1000纳米。
其中，第二金属层111设置在层间介质层110远离缓冲层106的一侧。第二金属层111可以由钼（Mo）、钛（Ti）、铝（Al）或铜（Cu）的一种或多种形成。第二金属层111的厚度为200纳米至800纳米。具体的，第二金属层111的厚度可以为200纳米、300纳米、400纳米、500纳米、600纳米、700纳米或800纳米。
其中，钝化层112覆盖第二金属层111。钝化层112可以由氧化硅（SiO X）、氮化硅（SiN X）或氧化硅（SiO X）/氮化硅（SiN X）的叠层形成。钝化层112的厚度为100纳米至500纳米。具体的，钝化层112的厚度可以为100纳米、200纳米、300纳米、400纳米或500纳米。
在一些实施例中，第二金属层111包括源极1111、漏极1112和第一绑定部1113。源极1111与连接部1031连接。第一绑定部1113与第一金属层105连接。具体的，源极1111和有源部1071的非沟道区和遮光部1051连接。漏极1112和有源部1071的非沟道区连接。第一绑定部1113与第一金属部1052连接。第二金属层111还包括第一极板1114。第一极板1114与第一金属层105连接。具体的，第一极板1114与第二金属部1053连接。
本申请通过在一道制程中形成源极1111、漏极1112、第一绑定部1113和第一极板1114，可以简化阵列基板100的制备过程，节约制备阵列基板100的成本。
本申请将第一极板1114与第二金属部1053连接，作为电容的一个极板。半导体部1072导体化后作为电容的另一个极板。缓冲层106和层间介质层110作为电容的绝缘介质层。
在一些实施例中，平坦化层102还包括第二开孔1022。连接层103还包括第二绑定部1032。第二绑定部1032设置在第二开孔1022内。第二绑定部1032与第一绑定部1113连接。
本申请通过将第二绑定部1032与第一绑定部1113连接。第一绑定部1113与第一金属部1052连接，从而实现外接电源对阵列基板100传输电信号。
在一些实施例中，阵列基板100还包括像素定义层113。像素定义层113包括第一开口1131和第二开口1132。第一开口1131暴露出阳极层104。第二开口1132与第二开孔1022对应设置。第二开口1132暴露出第二绑定部1032。其中，像素定义层113可以由高遮光的材料形成。比如光透过率小于15%的材料。
本申请通过在像素定义层113中形成暴露出阳极层104的第一开口1131，后续可以在第一开口内1131制备发光单元。本申请通过在像素定义层113中形成暴露出第二绑定部1032的第二开口1132，后续可以用于外接电路对阵列基板100传输电信号。
请参阅图4，图4为本申请提供的阵列基板的第三种实施例沿AA’线的剖面图。
第三种实施例提供的阵列基板100与第一种实施例提供的阵列基板100不同的是，连接部1031包括第一子连接部1031a和第二子连接部1031b。第一子连接部1031a和第二子连接部1031b之间具有间隙1033。第一子连接部1031a覆盖第一开孔1021。第二子连接部1031b设置在平坦化层102的表面。阳极层104覆盖第一子连接部1031a、第二子连接部1031b以及位于间隙1033处的平坦化层102。第一子连接部1031a和第二子连接部1031b通过阳极层104连接。其中，第二子连接部1031b的厚度为30纳米至300纳米。具体的，第二子连接部1031b的厚度可以为30纳米、50纳米、100纳米、150纳米、200纳米、250纳米或300纳米。
银（Ag）和银的合金（APC）可以与硫（S）反应形成黑色的银（Ag）的硫化物。如果阳极层上有黑色的银（Ag）的硫化物生成，容易造成阴极和阳极短路，导致显示面板出现像素暗点。本申请提供的阵列基板100通过在平坦化层102与阳极层104之间设置连接部1031。连接部1031包括第一子连接部1031a和第二子连接部1031b。第一子连接部1031a和第二子连接部1031b之间具有间隙1033。第一子连接部1031a覆盖第一开孔1021。第二子连接部1031b设置在平坦化层102的表面。阳极层104覆盖第一子连接部1031a、第二子连接部1031b以及位于间隙1033处的平坦化层102。第一子连接部1031a和第二子连接部1031b通过阳极层104连接，可以阻挡平坦化层102中的硫（S）元素扩散至阳极层104中与银（Ag）或银的合金（APC）反应形成黑色的银（Ag）的硫化物，从而避免因阴极和阳极短路，导致显示面板出现像素暗点，有利于提高显示面板的显示效果。此外，本申请通过在第一子连接部1031a和第二子连接部1031b之间设置间隙1033，还可以增大阳极层104与连接层103的接触面积，提高信号传输的稳定性。
第三种实施例提供的阵列基板100的其他部件与第一种实施例提供的阵列基板100相同，这里不再赘述。
请参阅图5，图5为本申请实施例提供的阵列基板的制备方法流程图。
本申请提供一种阵列基板的制备方法，包括：
步骤B10：在基板一侧形成第一金属层，对第一金属层图案化形成遮光部、第一金属部和第二金属部。
其中，基板可以为玻璃基板或柔性基板。第一金属层可以由叠层金属Cu/Ti或Cu/Mo/Ti形成。通过将Mo设置在Cu与Ti之间，可以提高Cu与Ti的贴合性。第一金属层的厚度为50纳米至200纳米。具体的，第一金属层的厚度可以为50纳米、100纳米、150纳米或200纳米。
步骤B20：形成覆盖第一金属层的缓冲层。
其中，缓冲层可以由氧化硅（SiO X）、氮化硅（SiN X）和氧化铝（AlO X）一种或多种形成。缓冲层的厚度为100纳米至500纳米。具体的，缓冲层的厚度可以为100纳米、200纳米、300纳米、400纳米或500纳米。
步骤B30：在缓冲层远离第一金属层的一侧依次形成半导体层、栅极绝缘层、栅极层和层间介质层。
半导体层可以由氧化铟镓锌（IGZO）、氧化铟锌锡（IZTO）或氧化铟镓锌锡（IGZTO）中的一种或多种形成。半导体层的厚度为10纳米至100纳米。具体的，半导体层的厚度可以为10纳米、20纳米、30纳米、40纳米、50纳米、60纳米、70纳米、80纳米、90纳米或100纳米。
栅极绝缘层可以由氧化硅（SiO X）、氮化硅（SiN X）或氧化硅（SiO X）/氮化硅（SiN X）的叠层形成。栅极绝缘层的厚度为50纳米至200纳米。具体的，栅极绝缘层的厚度可以为50纳米、100纳米、150纳米或200纳米。
栅极层可以由钼（Mo）、钛（Ti）、铝（Al）或铜（Cu）的一种或多种形成。栅极层的厚度为200纳米至800纳米。具体的，栅极层的厚度可以为200纳米、300纳米、400纳米、500纳米、600纳米、700纳米或800纳米。
层间介质层可以由氧化硅（SiO X）、氮化硅（SiN X）或氧化硅（SiO X）/氮化硅（SiN X）的叠层形成。层间介质层的厚度为200纳米至1000纳米。具体的，层间介质层的厚度可以为200纳米、300纳米、400纳米、500纳米、600纳米、700纳米、800纳米、900纳米或1000纳米。
其中，在形成层间介质层之前，还可以包括：对栅极金属图形案形成栅极；再利用栅极图形为自对准，对栅极绝缘层图案化。
具体的，只在有栅极图形的膜层下方，才有栅极绝缘层存在，其余地方栅极绝缘层均被蚀刻掉。其中，在对栅极金属图形案形成栅极；再利用栅极图形为自对准，对栅极绝缘层图案化之后，还可以包括：对半导体层等离子化处理。
具体的，对于上方没有栅极绝缘层和栅极金属保护的半导体层，等离子化处理后电阻明显降低，形成N+导体层。因栅极绝缘层下方的半导体层没有经过等离子化处理，继续保持半导体特性。
其中，在对半导体层等离子化处理之后，还可以包括：对半导体层图案化处理，形成有源部和半导体部。经过等离子化处理后的一部分有源部，可以作为薄膜晶体管的非沟道区。没有经过等离子化处理后的一部分有源部，可以作为薄膜晶体管的沟道区。半导体部在等离子化处理后，可以作为电容的一个极板。
步骤B40：在层间介质层远离栅极层的一侧形成第二金属层，对第二金属层图案化形成源极、漏极、第一绑定部和第一极板。
具体的，源极和有源部的非沟道区和遮光层连接。漏极和有源部的非沟道区连接。第一绑定部和第一金属部连接。第一极板和第二金属部连接。第二金属层可以由钼（Mo）、钛（Ti）、铝（Al）或铜（Cu）的一种或多种形成。第二金属层的厚度为200纳米至800纳米。具体的，第二金属层的厚度可以为200纳米、300纳米、400纳米、500纳米、600纳米、700纳米或800纳米。对第二金属层图案化形成源极、漏极、第一绑定部和第一极板。
步骤B50：形成覆盖第二金属层的平坦化层，对平坦化层图案化形成第一开孔和第二开孔，第一开孔暴露出源极，第二开孔暴露出第一绑定部。
其中，平坦化层可以由丙烯酸树脂、环氧树脂、酚醛树脂、聚酰胺树脂或聚酰亚胺树脂等有机材料中的一种或多种形成。平坦化层的厚度为100纳米至500纳米。具体的，平坦化层的厚度可以为100纳米、200纳米、300纳米、400纳米或500纳米。
步骤B60：在平坦化层的表面、第一开孔和第二开孔内形成连接层，对连接层图案化形成连接部和第二绑定部，连接部位于平坦化层的表面和第一开孔内，第二绑定部位于第二开孔内。
具体的，连接部和源极连接。第二绑定部和第一绑定部连接。其中，连接层可以由钼（Mo）、钛（Ti）、钼（Mo）/钛（Ti）、钛（Ti）合金和氧化铟锡（ITO）中的一种或多种形成。位于平坦化层表面的连接层的厚度为30纳米至300纳米。具体的，位于平坦化层表面的连接层的厚度可以为30纳米、50纳米、100纳米、150纳米、200纳米、250纳米或300纳米。
步骤B70：在连接部远离平坦化层的一侧形成依次阳极层和像素定义层，对像素定义层图案化形成第一开口和第二开口，第一开口暴露出阳极层，第二开口暴露出第二绑定部。
其中，阳极层包括第一子层、第二子层和第三子层。其中，第一子层的材料可以是氧化铟锡（ITO）或氧化铟锌（IZO）。第二子层的材料可以是银（Ag）或者银的合金（APC）。其中，APC是由银（Ag）、钯（Pd）和铜（Cu）形成的合金。第三子层的材料可以是氧化铟锡（ITO）或氧化铟锌（IZO）。像素定义层可以由高遮光的材料形成。比如光透过率小于15%的材料。
银（Ag）和银的合金（APC）可以与硫（S）反应形成黑色的银（Ag）的硫化物。如果阳极层上有黑色的银（Ag）的硫化物生成，容易造成阴极和阳极短路，导致显示面板出现像素暗点。本申请提供的阵列基板通过在平坦化层与阳极层之间设置连接部，可以阻挡平坦化层中的硫（S）元素扩散至阳极层104中与银（Ag）或银的合金（APC）反应形成黑色的银（Ag）的硫化物，从而避免因阴极和阳极短路，导致显示面板出现像素暗点，有利于提高显示面板的显示效果。
请参阅图6，图6为本申请实施例提供的显示面板的结构示意图。
本申请提供的显示面板1000包括如前任一实施例所述的阵列基板100。
本申请提供的显示面板包括阵列基板。其中，本申请提供的阵列基板通过在平坦化层与阳极层之间设置连接部，可以阻挡平坦化层中的硫（S）元素扩散至阳极层中与银（Ag）或银的合金（APC）反应形成黑色的银（Ag）的硫化物，从而避免因阴极和阳极短路，导致显示面板出现像素暗点，有利于提高显示面板的显示效果。
综上所述，虽然本申请实施例的详细介绍如上，但上述实施例并非用以限制本申请，本领域的普通技术人员应当理解：其依然可以对前述实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其中，包括：
    基板；
    平坦化层，所述平坦化层设置在所述基板的一侧，所述平坦化层包括第一开孔；
    连接层，所述连接层包括连接部，所述连接部设置在所述第一开孔内并延伸至所述平坦化层的表面；
    阳极层，所述阳极层设置在所述连接部远离所述平坦化层的一侧。
  2. 根据权利要求1所述的阵列基板，其中，所述连接部包括第一子连接部和第二子连接部，所述第一子连接部和所述第二子连接部之间具有间隙，所述第一子连接部覆盖所述第一开孔，所述第二子连接部设置在所述平坦化层的表面，所述阳极层覆盖所述第一子连接部、所述第二子连接部以及位于所述间隙处的所述平坦化层，所述第一子连接部和所述第二子连接部通过所述阳极层连接。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括依次层叠设置的第一金属层、缓冲层、半导体层、栅极绝缘层、栅极层、层间介质层、第二金属层以及钝化层。
  4. 根据权利要求3所述的阵列基板，其中，所述第二金属层包括源极、漏极和第一绑定部，所述源极与所述连接部连接，所述第一绑定部与所述第一金属层连接。
  5. 根据权利要求4所述的阵列基板，其中，所述平坦化层还包括第二开孔，所述连接层还包括第二绑定部，所述第二绑定部设置在所述第二开孔内，所述第二绑定部与所述第一绑定部连接。
  6. 根据权利要求5所述的阵列基板，其中，所述阵列基板还包括像素定义层，所述像素定义层包括第一开口和第二开口，所述第一开口暴露出所述阳极层，所述第二开口与所述第二开孔对应设置，所述第二开口暴露出所述第二绑定部。
  7. 根据权利要求3所述的阵列基板，其中，所述第二金属层还包括第一极板，所述第一极板与所述第一金属层连接。
  8. 根据权利要求1所述的阵列基板，其中，所述连接层的材料包括钼、钛、钼/钛、钛的合金和氧化铟锡中的一种或多种。
  9. 根据权利要求1所述的阵列基板，其中，所述阳极层包括第一子层、第二子层和第三子层，所述第一子层的材料为氧化铟锡或氧化铟锌，所述第二子层的材料为银或者银的合金，所述第三子层的材料为氧化铟锡或氧化铟锌。
  10. 根据权利要求1所述的阵列基板，其中，位于所述阳极层与所述平坦化层之间的所述连接部的厚度为30纳米至300纳米。
  11. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括：
    基板；
    平坦化层，所述平坦化层设置在所述基板的一侧，所述平坦化层包括第一开孔；
    连接层，所述连接层包括连接部，所述连接部设置在所述第一开孔内并延伸至所述平坦化层的表面；
    阳极层，所述阳极层设置在所述连接部远离所述平坦化层的一侧。
  12. 根据权利要求11所述的显示面板，其中，所述连接部包括第一子连接部和第二子连接部，所述第一子连接部和所述第二子连接部之间具有间隙，所述第一子连接部覆盖所述第一开孔，所述第二子连接部设置在所述平坦化层的表面，所述阳极层覆盖所述第一子连接部、所述第二子连接部以及位于所述间隙处的所述平坦化层，所述第一子连接部和所述第二子连接部通过所述阳极层连接。
  13. 根据权利要求11所述的显示面板，其中，所述阵列基板还包括依次层叠设置的第一金属层、缓冲层、半导体层、栅极绝缘层、栅极层、层间介质层、第二金属层以及钝化层。
  14. 根据权利要求13所述的显示面板，其中，所述第二金属层包括源极、漏极和第一绑定部，所述源极与所述连接部连接，所述第一绑定部与所述第一金属层连接。
  15. 根据权利要求14所述的显示面板，其中，所述平坦化层还包括第二开孔，所述连接层还包括第二绑定部，所述第二绑定部设置在所述第二开孔内，所述第二绑定部与所述第一绑定部连接。
  16. 根据权利要求15所述的显示面板，其中，所述阵列基板还包括像素定义层，所述像素定义层包括第一开口和第二开口，所述第一开口暴露出所述阳极层，所述第二开口与所述第二开孔对应设置，所述第二开口暴露出所述第二绑定部。
  17. 根据权利要求13所述的显示面板，其中，所述第二金属层还包括第一极板，所述第一极板与所述第一金属层连接。
  18. 根据权利要求11所述的显示面板，其中，所述连接层的材料包括钼、钛、钼/钛、钛的合金和氧化铟锡中的一种或多种。
  19. 根据权利要求11所述的显示面板，其中，所述阳极层包括第一子层、第二子层和第三子层，所述第一子层的材料为氧化铟锡或氧化铟锌，所述第二子层的材料为银或者银的合金，所述第三子层的材料为氧化铟锡或氧化铟锌。
  20. 根据权利要求11所述的显示面板，其中，位于所述阳极层与所述平坦化层之间的所述连接部的厚度为30纳米至300纳米。
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