WO2022267054A1 - 显示基板、显示面板和显示装置 - Google Patents

显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2022267054A1
WO2022267054A1 PCT/CN2021/102536 CN2021102536W WO2022267054A1 WO 2022267054 A1 WO2022267054 A1 WO 2022267054A1 CN 2021102536 W CN2021102536 W CN 2021102536W WO 2022267054 A1 WO2022267054 A1 WO 2022267054A1
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WIPO (PCT)
Prior art keywords
pixel
sub
layer
substrate
along
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PCT/CN2021/102536
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English (en)
French (fr)
Inventor
韩影
徐攀
李伟
张宜驰
周影
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京东方科技集团股份有限公司
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Priority to CN202180001641.7A priority Critical patent/CN115868259A/zh
Priority to EP21946546.5A priority patent/EP4199098A4/en
Priority to PCT/CN2021/102536 priority patent/WO2022267054A1/zh
Publication of WO2022267054A1 publication Critical patent/WO2022267054A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines

Definitions

  • Embodiments of the present disclosure belong to the field of display technology, and specifically relate to a display substrate, a display panel, and a display device.
  • OLED Organic Light-Emitting Diode
  • organic electro-laser display panels organic light-emitting semiconductor display panels
  • color gamut is an important indicator for evaluating OLED display panels, high color gamut display will bring users
  • a better visual experience is an indicator that is currently being pursued in the development of new products.
  • Embodiments of the present disclosure provide a display substrate, a display panel, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base;
  • a plurality of pixel circuits are arranged on the substrate;
  • a plurality of pixels arranged in an array and located on the side of the pixel circuit away from the substrate;
  • the pixel includes a first sub-pixel, a second sub-pixel and a third sub-pixel; the orthographic projections of the first sub-pixel, the second sub-pixel and the third sub-pixel on the base have no overlap; the first sub-pixel, the second sub-pixel The third sub-pixel is electrically connected to the pixel circuit in one-to-one correspondence;
  • a first distance is set between the first sub-pixel and the second sub-pixel along the first direction, and a first via hole is set in the first distance;
  • a second pitch is set along the first direction between the first sub-pixel and the third sub-pixel, and a first via hole is set in the second pitch;
  • a third distance is set between the second sub-pixel and the third sub-pixel along the first direction.
  • the pixel circuit includes a driving tube and an insulating layer; the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively include an anode; the driving tube, the insulating layer, and the anode are sequentially arranged away from the substrate;
  • the pixel circuit also includes an auxiliary electrode
  • the auxiliary electrode includes a first conductive layer, the first conductive layer and the anode are located on the same film layer, and the orthographic projection of the first conductive layer on the substrate and the orthographic projection of the anode on the substrate do not overlap each other;
  • the auxiliary electrode also includes a second conductive layer, the second conductive layer is located on the same film layer as the first pole and the second pole of the drive tube, and the orthographic projection of the second conductive layer on the substrate is the same as that of the first pole and the second pole of the drive tube.
  • the orthographic projections of the two poles on the substrate do not overlap each other.
  • the second sub-pixel and the third sub-pixel are located on the same side of the first sub-pixel; and the second sub-pixel and the third sub-pixel are arranged along the second direction;
  • the first spacing is equal to the second spacing
  • the third distance is smaller than the first distance.
  • the first sub-pixel and the third sub-pixel are arranged along the first direction;
  • the first direction is perpendicular to the second direction.
  • the size of the first sub-pixel along the second direction is equal to the sum of the sizes of the second sub-pixel, the third sub-pixel and the space between them along the second direction;
  • a size of the first sub-pixel along the first direction is smaller than a size of any one of the second sub-pixel and the third sub-pixel along the first direction.
  • the orthographic projection of the first conductive layer on the substrate is located in a space between at least part of adjacent pixels along the first direction.
  • the size of the first conductive layer along the second direction is equal to the sum of the sizes of two adjacent pixels along the second direction and the space between them;
  • the size of the first conductive layer along the first direction is smaller than the size of the first sub-pixel along the first direction.
  • the first spacing is equal to the second spacing
  • the third pitch is equal to the sum of the first pitch, the second pitch and the width of the first sub-pixel along the first direction.
  • the second sub-pixel, the first sub-pixel and the third sub-pixel are sequentially arranged along the first direction.
  • the size of the first conductive layer along the first direction is larger than the sum of the sizes of the first sub-pixel and the second sub-pixel along the first direction; or, the size of the first conductive layer along the first direction is larger than the first the sum of the dimensions of the sub-pixel and the third sub-pixel along the first direction;
  • the size of the first conductive layer along the second direction is smaller than the size of the first sub-pixel along the second direction.
  • the first pitch is smaller than the second pitch
  • the second pitch is equal to the sum of the first pitch, the width of the second sub-pixel along the first direction and the third pitch.
  • the second sub-pixel, the third sub-pixel and the first sub-pixel are sequentially arranged along the first direction.
  • the size of the first sub-pixel along the second direction is smaller than the size of any one of the second sub-pixel and the third sub-pixel along the second direction;
  • the size of the first sub-pixel along the first direction is smaller than the size of any one of the second sub-pixel and the third sub-pixel along the first direction;
  • the first direction is perpendicular to the second direction.
  • the orthographic projection of the first conductive layer on the substrate is located in the space between at least some adjacent pixels along the second direction.
  • the size of the first conductive layer along the first direction is smaller than the first pitch or the second pitch
  • the size of the first conductive layer along the second direction is smaller than the size of the first sub-pixel along the second direction.
  • any two adjacent rows of pixels arranged along the second direction are mirror-symmetrical;
  • any two adjacent columns of pixels arranged along the first direction are mirror-symmetrical.
  • each row of pixels is arranged along the second direction;
  • the second sub-pixels in each row of pixels are arranged along the second direction;
  • the third sub-pixels in each row of pixels are arranged along the second direction;
  • the first sub-pixels in each row of pixels are arranged along the second direction.
  • each row of pixels is arranged along the second direction;
  • the first sub-pixel is a blue sub-pixel; the second sub-pixel is a red sub-pixel; the third sub-pixel is a green sub-pixel;
  • the first sub-pixel is a blue sub-pixel; the second sub-pixel is a green sub-pixel; and the third sub-pixel is a red sub-pixel.
  • the first via hole is opened in the insulating layer, and is used to respectively connect the anodes of the first sub-pixel, the second sub-pixel and the third sub-pixel to the first electrodes of the driving transistors in the respective pixel circuits.
  • a second via hole is further opened in the insulating layer for connecting the first conductive layer to the second conductive layer;
  • the orthographic projection of the second via hole on the substrate is located between two adjacent pixels along the second direction.
  • the pitch ranges of the first pitch and the second pitch are 7-25 ⁇ m, respectively.
  • the orthographic projections of the first via hole and the second via hole in the first direction do not overlap.
  • the orthographic projections of the first via hole and the second via hole in the first direction are at least partially overlapped.
  • a pixel defining layer located on a side of the insulating layer away from the substrate;
  • the first sub-pixel, the second sub-pixel and the third sub-pixel are respectively located in the area defined by the pixel defining layer;
  • the first sub-pixel, the second sub-pixel and the third sub-pixel also include a light-emitting functional layer and a cathode respectively; the light-emitting functional layer and the cathode are arranged away from the anode in turn; and the orthographic projection of the light-emitting functional layer and the cathode on the substrate is the same as that of the anode on the substrate
  • the orthographic projections of are at least partially overlapping;
  • the pixel defining layer is formed with an opening in the area corresponding to the first conductive layer; the luminescent functional layer and the cathode also extend into the opening, and the part inside the opening and the part outside the opening of the luminescent functional layer and the cathode are mutually disconnected at the edge of the opening. open;
  • the part of the cathode outside the opening covers the disconnected edge of the light-emitting functional layer at the edge of the opening, and the part of the cathode outside the opening also extends to contact with at least part of the edge surface of the first conductive layer.
  • the first conductive layer includes a first sublayer, a second sublayer, and a third sublayer stacked in sequence along a direction away from the substrate;
  • the cross-sectional shape of the first conductive layer perpendicular to the base includes an "I" shape or an inverted trapezoid;
  • the part of the cathode lying outside the opening is in contact with at least the edge end faces of the second sublayer and the third sublayer.
  • the aperture ratio ratio of the second sub-pixel, the third sub-pixel and the first sub-pixel ranges from 2:2:1 to 3:2:1.
  • the shape of the orthographic projection of the second sub-pixel, the third sub-pixel and the first sub-pixel on the substrate includes a rectangle.
  • the first sub-pixel, the second sub-pixel and the third sub-pixel respectively further include a color conversion layer, which is located on the side of the cathode away from the light-emitting functional layer;
  • the luminescent functional layer emits blue light
  • the color conversion layer is used for color conversion of blue light.
  • the color conversion layer includes a first color conversion unit, a second color conversion unit and a first transmissive unit;
  • the orthographic projection of the first color conversion unit on the substrate covers the orthographic projection of the second sub-pixel on the substrate;
  • the orthographic projection of the second color conversion unit on the substrate covers the orthographic projection of the third sub-pixel on the substrate;
  • the orthographic projection of the first transmission unit on the substrate covers the orthographic projection of the first sub-pixel on the substrate.
  • it further includes a retaining wall and a first black matrix, which are located on the side of the pixel defining layer away from the substrate, and the first black matrix and the retaining wall are arranged away from the pixel defining layer in turn;
  • the orthographic projection of the retaining wall and the first black matrix on the substrate at least partially overlaps with the orthographic projection of the pixel defining layer on the substrate.
  • the first sub-pixel, the second sub-pixel and the third sub-pixel respectively further include a color-resist layer, located on a side of the color conversion layer away from the substrate;
  • the color resistance layer includes a first color resistance, a second color resistance and a third color resistance
  • the orthographic projection of the first color resist on the substrate falls within the orthographic projection of the first color conversion unit on the substrate;
  • the orthographic projection of the second color resist on the substrate falls within the orthographic projection of the second color conversion unit on the substrate;
  • the orthographic projection of the third color resist on the substrate falls within the orthographic projection of the first transmission unit on the substrate.
  • it also includes a second black matrix, located on the side of the retaining wall away from the base;
  • the orthographic projection of the second black matrix on the substrate falls within the orthographic projection of the first black matrix on the substrate.
  • the orthographic projection areas of the plurality of pixel circuits on the substrate are equal.
  • the orthographic projections of the first sub-pixel, the second sub-pixel and the third sub-pixel on the substrate and the orthographic projections of the pixel circuits electrically connected thereto on the substrate are at least partially non-overlapping.
  • a first encapsulation layer, a second encapsulation layer and an anti-reflection layer are also included;
  • the first encapsulation layer is located on the side of the cathode facing away from the substrate and on the side of the color conversion layer close to the cathode;
  • the second encapsulation layer is located on the side of the color conversion layer away from the substrate and the side of the color resistance layer close to the color conversion layer;
  • the antireflection layer is located on the side of the color resist layer away from the substrate.
  • an embodiment of the present disclosure further provides a display panel, including the above-mentioned display substrate.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of the arrangement of pixels in an OLED display panel in the disclosed technology
  • Fig. 2a is a schematic diagram of optical crosstalk caused by a blue sub-pixel to its surrounding red and green sub-pixels in the disclosed technology.
  • Fig. 2b is a schematic diagram of optical crosstalk caused by red and green sub-pixels to their surrounding blue sub-pixels in the disclosed technology.
  • Fig. 2c is a schematic diagram of optical crosstalk between red sub-pixels and green sub-pixels in the disclosed technology.
  • FIG. 3 is a schematic diagram of pixel arrangement in a display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of the structure along line AA in FIG. 3 .
  • FIG. 5 is a schematic diagram of the distance between the first sub-pixel and the second sub-pixel before improvement.
  • FIG. 6 is a schematic diagram of the distance between the first sub-pixel and the second sub-pixel after improvement.
  • FIG. 7 is a structural cross-sectional view along line BB in FIG. 3 .
  • FIG. 8 is a schematic diagram of an arrangement of first vias and second vias in an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of another arrangement of first vias and second vias in an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of another arrangement of pixels in a display substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of another arrangement of pixels in a display substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of another arrangement of pixels in a display substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of another arrangement of pixels in a display substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of another arrangement of pixels in a display substrate according to an embodiment of the present disclosure.
  • Fig. 15a is a pattern of one of the plates used to form the capacitance in the pixel circuit on the substrate among the plurality of pixel circuits, and some conductive layer patterns connecting the patterns of the via holes and the patterns of the signal traces.
  • Fig. 15b is a pattern of the active layer of the transistor located on the side of the conductive layer pattern in Fig. 15a away from the substrate in a plurality of pixel circuits.
  • Fig. 15c is a pattern of via holes in the insulating layer on the side of the active layer pattern away from the substrate in a plurality of pixel circuits.
  • Fig. 15d is a diagram of the transistor source-drain electrode layer, the second conductive layer and other conductive structures located on the side of the insulating layer away from the base in multiple pixel circuits.
  • Fig. 15e is a top view of a plurality of pixel circuits after the film layers in Fig. 15a, Fig. 15b, Fig. 15c and Fig. 15d are sequentially stacked.
  • Fig. 16a is a diagram showing the anode, the first conductive layer and the via holes opened in the insulating layer on the substrate on the side of the source and drain electrode layers of the transistor away from the substrate.
  • Fig. 16b is a diagram showing openings formed in the pixel defining layer on the substrate side where the anode is away from the base.
  • FIG. 16c is a diagram showing the barrier wall and the first black matrix on the substrate on the side of the pixel defining layer facing away from the base.
  • Figure 16d is a diagram showing a color conversion layer on a substrate located in a region separated by a barrier wall.
  • Fig. 16e is a top view of the display substrate after the film layers in Figs. 15a-15d and Figs. 16a-16d are sequentially stacked.
  • Fig. 17a is a pattern of one of the plates used to form the capacitance in the pixel circuit on the substrate among the plurality of pixel circuits, and some conductive layer patterns connecting the patterns of the via holes and the patterns of the signal traces.
  • Fig. 17b is a pattern of the active layer of the transistor located on the side of the conductive layer pattern in Fig. 15a away from the substrate in a plurality of pixel circuits.
  • Fig. 17c is a diagram of via holes in the insulating layer on the side of the active layer pattern away from the substrate in a plurality of pixel circuits.
  • Fig. 17d is a diagram of the transistor source-drain electrode layer, the second conductive layer and other conductive structures located on the side of the insulating layer away from the base in multiple pixel circuits.
  • Fig. 18a is a diagram showing the anode, the first conductive layer and the via hole opened in the insulating layer on the substrate on the side of the transistor source and drain electrode layer pattern away from the base.
  • Fig. 18b is a diagram showing an opening formed in the pixel defining layer on the substrate side where the anode is away from the base.
  • FIG. 18c is a diagram showing the barrier wall and the first black matrix on the substrate on the side of the pixel defining layer facing away from the base.
  • Fig. 18d is a diagram showing a color conversion layer on a substrate in a region separated by a barrier wall.
  • Fig. 18e is a top view of the display substrate after the film layers in Figs. 17a-17d and Figs. 18a-18d are sequentially stacked.
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Accordingly, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions and are not intended to be limiting.
  • an OLED display panel that is, a QD-OLED display panel
  • QD quantum dots
  • OLED as a light-emitting element
  • a large-size QD-OLED display panel includes a plurality of pixels 2 arranged in an array, and each pixel may include red sub-pixels 151 , green sub-pixels 152 and blue sub-pixels 153 arranged adjacently.
  • the pixel 2 includes vertically arranged light emitting elements and a color conversion layer, wherein the light emitting elements can emit blue light, and the color conversion layer includes a first color conversion unit, a second color conversion unit and a first transmission unit.
  • the blue light emitted by the light-emitting element can be converted into red light and emitted through the first color conversion unit; the blue light emitted by the light-emitting element can be converted into green light and emitted through the second color conversion unit;
  • the first transmission unit can include scattering particles, The blue light emitted by the light-emitting element passes through the first transmission unit, and can still be emitted as blue light through the action of the scattering particles.
  • the blue sub-pixel 153 will cause crosstalk to adjacent sub-pixels that emit light of other colors due to the thicker cell, causing light crosstalk between adjacent sub-pixels, resulting in light leakage, and ultimately resulting in poor display color gamut of the OLED display panel.
  • the optical crosstalk between adjacent sub-pixels is referred to FIG. 2a, FIG. 2b and FIG. to the distance between the pixel circuit substrate of the OLED display panel), under a certain box thickness, the blue light emitted by the light-emitting element in the blue sub-pixel will irradiate the quantum dot color conversion unit of the adjacent red sub-pixel and green sub-pixel above, the first color conversion unit is excited to emit red light, and the second color conversion unit emits green light, resulting in optical crosstalk, referring to Figure 2a; in this case, part of the blue light emitted by the light emitting element of the blue sub-pixel passes through the first transmission Units are converted, so there will be effects of crosstalk light conversion efficiency.
  • the blue light emitted by the light-emitting element in the red sub-pixel and the blue light emitted by the light-emitting element in the green sub-pixel will also irradiate the first transmission unit of the blue sub-pixel, and the light scattered by the first transmission unit will cause optical crosstalk. , but in this case there is no influence of crosstalk light conversion efficiency, refer to Figure 2b.
  • the blue light emitted by the light-emitting element in the red sub-pixel and the blue light emitted by the light-emitting element in the green sub-pixel will also irradiate the quantum dot conversion layer of each other, causing optical crosstalk, as shown in FIG. 2c.
  • embodiments of the present disclosure provide the following technical solutions.
  • an embodiment of the present disclosure provides a display substrate, including: a substrate 1; a plurality of pixel circuits disposed on the substrate 1; a plurality of pixels 2 arranged in an array, and located on the side of the pixel circuit away from the substrate 1; the pixel 2 includes a first sub-pixel 21, a second sub-pixel 220 and a third sub-pixel 221; the first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221 are in The orthographic projection on the substrate 1 has no overlap; the first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221 are electrically connected to the pixel circuit in one-to-one correspondence; the edge between the first sub-pixel 21 and the second sub-pixel 220 A first pitch is set along the first direction Y, and a first via hole 41 is set in the first pitch; a second pitch is set between the first sub-pixel 21 and the third sub-pixel 221 along the first direction Y
  • the pixel circuit includes a driving tube 3 and an insulating layer 4; the first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221 respectively include an anode 201; the driving tube 3, The insulating layer 4 and the anode 201 are disposed away from the substrate 1 in turn.
  • the first via hole 41 is opened in the insulating layer 4 for connecting the anodes 201 of the first sub-pixel 21 , the second sub-pixel 220 and the third sub-pixel 221 to the first electrodes of the drive transistor 3 in the respective pixel circuits.
  • the first pitch and the second pitch can be respectively increased from about 10 ⁇ m in the disclosed technology to 15-25 ⁇ m; Greatly improve or avoid the light crosstalk between the first sub-pixel 21 and the second sub-pixel 220 and the third sub-pixel 221, thereby greatly improving or avoiding the first sub-pixel 21 and the second sub-pixel 220 and the third sub-pixel 221 The light leakage phenomenon between them is conducive to improving the color gamut of the display substrate, and finally improving the display effect of the display substrate.
  • the distance between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 is equal to that between the adjacent first sub-pixel 21 and the second sub-pixel 220 or the third
  • the distance between the adjacent edges of the sub-pixels 221, such as the distance between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 is along the first direction Y, the anode of the first sub-pixel 21 and the The orthographic projection overlapping area b1 of the pixel defining layer between the adjacent first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221, the anode of the pixel defining layer and the adjacent first sub-pixel 21 and the second sub-pixel
  • the arrangement position of the pixel circuit is kept unchanged, and by changing the arrangement position of the sub-pixels, the first process at least partially located in the area where the sub-pixels are located in the disclosed technology
  • the hole 41 is completely located in the first pitch area between the first sub-pixel 21 and the second sub-pixel 220 and in the second pitch area between the first sub-pixel 21 and the third sub-pixel 221, compared to the sub-pixel in the disclosed technology
  • the arrangement method can increase the first distance between the first sub-pixel 21 and the second sub-pixel 220 and the second distance between the first sub-pixel 21 and the third sub-pixel 221, thereby greatly improving or avoiding Light crosstalk between the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 can greatly improve or avoid light leakage between the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 phenomenon, it is beneficial to improve the color gamut of the display substrate, and ultimately improve the display effect of the display substrate
  • the pixel circuit further includes an auxiliary electrode 6;
  • the auxiliary electrode 6 includes a first conductive layer 61, the first conductive layer 61 is located on the same film layer as the anode 201, and the second The orthographic projection of a conductive layer 61 on the substrate 1 does not overlap with the orthographic projection of the anode 201 on the substrate 1; 31 and the second pole 32 are located on the same film layer, and the orthographic projection of the second conductive layer 62 on the substrate 1 does not overlap with the orthographic projection of the first pole 31 and the second pole 32 of the drive tube 3 on the substrate 1 .
  • a second via hole 42 is also opened in the insulating layer 4 for connecting the first conductive layer 61 to the second conductive layer 62; the orthographic projection of the second via hole 42 on the substrate 1 is located along the Between two adjacent pixels 2 in the two directions X.
  • the orthographic projection of the second via hole 42 on the substrate 1 be located between two adjacent pixels 2 along the second direction X, compared with the disclosed technology where the second via hole 42 is at least partially located in the area where the sub-pixel is located
  • the arrangement of the sub-pixels can further increase the first pitch and the second pitch, thereby greatly improving or avoiding the light crosstalk between the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221, and further
  • the light leakage phenomenon between the first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221 can be greatly improved or avoided, which is beneficial to improving the color gamut of the display substrate, and finally improving the display effect of the display substrate.
  • the orthographic projections of the first via hole 41 and the second via hole 42 in the first direction Y have no overlap.
  • the distance between the adjacent first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 can not only increase the size p of the first via hole 41 along the first direction Y, but also increase the distance of the second via hole 41. 42 the size n along the first direction Y, so that the distance between the adjacent first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 is further increased, thereby greatly improving or avoiding the first sub-pixel 21 crosstalk with light between the second sub-pixel 220 and the third sub-pixel 221 .
  • the orthographic projections of the first via hole 41 and the second via hole 42 in the first direction Y are at least partially overlapped. Wherein, if the orthographic projections of the first via hole 41 and the second via hole 42 in the first direction Y partially overlap, the distance between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221 will be increased.
  • the orthographic projections of the first via hole 41 and the second via hole 42 in the first direction Y completely overlap, and the size of the orthographic projection of the first via hole 41 in the first direction Y is larger than that of the second via hole 42 in the
  • the size of the orthographic projection in the first direction Y will also increase the distance between the first sub-pixel 21 and the second sub-pixel 220 or the third sub-pixel 221, so that the adjacent first sub-pixel 21 and the second sub-pixel 220 Or the distance between the third sub-pixels 221 is further increased, thereby greatly improving or avoiding the light crosstalk between the first sub-pixel 21 , the second sub-pixel 220 and the third sub-pixel 221 .
  • the pitch ranges of the first pitch and the second pitch are 7-25 ⁇ m, respectively.
  • the distribution positions of the first via hole 41 and the second via hole 42 ensure that It will affect the aperture ratio of the sub-pixel and the resolution of the display substrate, that is, the resolution of the display substrate and the aperture ratio of the sub-pixel will not change due to changes in the distribution positions of the first via holes 41 and the second via holes 42 .
  • the display substrate further includes a pixel defining layer 5 located on the side of the insulating layer 4 away from the substrate 1 ; the first sub-pixel 21 , the second sub-pixel 220 and the third sub-pixel 221 Respectively located in the area defined by the pixel defining layer 5; the first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221 also include a light-emitting functional layer 202 and a cathode 203 respectively; the light-emitting functional layer 202 and the cathode 203 are in turn away from the anode 201 set; and the orthographic projection of the light-emitting functional layer 202 and the cathode 203 on the substrate 1 overlaps at least partially the orthographic projection of the anode 201 on the substrate 1, and the overlapped part constitutes a light-emitting element; the pixel defining layer 5 corresponds to the first conductive layer 61 An opening is formed in the region; the lumin
  • the cathode 203 is in contact with the first conductive layer 61 at the edge of the opening of the pixel defining layer 5, thereby realizing the connection between the two; and the first conductive layer 61 is also connected to the second conductive layer 62 through the second via hole 42 In this way, the interconnection between the cathode 203 and the first conductive layer 61 and the second conductive layer 62 is realized, that is, the interconnection between the cathode 203 and the auxiliary electrode 6 is realized.
  • the cathode 203 is usually thinner and has a higher resistance.
  • the auxiliary electrode 6 can increase the cross-sectional area of the cathode 203, thereby reducing the resistance of the cathode 203. Furthermore, the voltage drop on the cathode 203 is reduced and the voltage of the entire cathode 203 is more consistent, so that the display uniformity and display brightness of the display substrate can be improved, and the display effect of the display substrate can be improved.
  • the first conductive layer 61 includes a first sublayer 611, a second sublayer 612, and a third sublayer 613 stacked in sequence along the direction away from the substrate 1; the vertical direction of the first conductive layer 61
  • the cross-sectional shape of the substrate 1 includes an "I" shape or an inverted trapezoid; the part of the cathode 203 outside the opening is at least in contact with the edge surfaces of the second sub-layer 612 and the third sub-layer 613 .
  • the cross-sectional shape of the first conductive layer 61 is an "I" shape, referring to FIG.
  • Width if the cross-sectional shape of the first conductive layer 61 is an inverted trapezoid, the width of the third sublayer 613 in cross section is greater than the width of second sublayer 612 in cross section, and the width of second sublayer 612 in cross section is greater than that of the second sublayer 612 in cross section.
  • the cross-sectional width of any sublayer refers to the dimension of the sublayer perpendicular to the direction away from the substrate 1 .
  • the cross-sectional shape of the first conductive layer 61 is caused by the traditional manufacturing process, and will not be repeated here, as long as the cathode 203 can be in good contact with the edge end surface of the first conductive layer 61 .
  • the anode 201 and the first conductive layer 61 have the same sub-layer stack structure, that is, the anode 201 is also formed by stacking three sub-layers, which can reduce the resistance of the anode 201 and improve the display effect.
  • the first sublayer 611 and the third sublayer 613 can be made of materials such as indium tin oxide
  • the second sublayer 612 can be made of materials such as aluminum.
  • the materials of the three sub-layers of the anode 201 are respectively the same as those of the three sub-layers of the first conductive layer 61 , so that they can be manufactured through one patterning process, which simplifies the manufacturing process.
  • the anode 201 is opaque and can reflect the light irradiated on it, so as to realize a top-emission OLED display substrate.
  • the anode 201 can also transmit light.
  • a reflective layer can be provided on the side of the anode 201 close to the substrate 1 to reflect light irradiated thereon, thereby realizing a top-emission OLED display substrate.
  • the top emission OLED display substrate can achieve a larger display aperture ratio.
  • the second sub-pixel 220 and the third sub-pixel 221 are located on the same side of the first sub-pixel 21; and the second sub-pixel 220 and the third The sub-pixels 221 are arranged along the second direction X; the first pitch is equal to the second pitch; the third pitch is smaller than the first pitch.
  • the first sub-pixels 21 and the third sub-pixels 221 are arranged along a first direction Y; the first direction Y is perpendicular to the second direction X.
  • the size of the first sub-pixel 21 along the second direction X is equal to the second sub-pixel 220, the third sub-pixel 221 and the distance between them along the second direction X.
  • the sum of the sizes; the size of the first sub-pixel 21 along the first direction Y is smaller than the size of any one of the second sub-pixel 220 and the third sub-pixel 221 along the first direction Y.
  • the sub-pixel aperture design it is necessary to comprehensively consider the luminous efficiency and lifetime of the sub-pixel to achieve a balance between the two. Since the first sub-pixel 21 accounts for a relatively small proportion in the color mixing, and the first sub-pixel 21 does not involve the problem of excitation conversion of the quantum dot color conversion layer, its relative luminous efficiency is relatively high, the sub-pixel current is small, and the service life is long; while the second sub-pixel 21 The sub-pixel 220 and the third sub-pixel 221 are excited by the quantum dot color conversion layer to convert blue light into red light and green light, respectively, and need to be excited and converted by the quantum dot color conversion layer to emit light of the corresponding color, so their relative luminous efficiency is relatively high. Low, the sub-pixel current is larger and the lifetime is shorter.
  • the sub-pixel aperture ratio ratio and its lifetime ratio can be calculated by the following formula.
  • a is the acceleration factor, which is a fixed value
  • LTpixel is the sub-pixel lifetime
  • LTltc is the measurable lifetime of the OLED light-emitting element (including anode, light-emitting functional layer and cathode)
  • Jpixel is the sub-pixel current density
  • Jltc is a given The current density of the OLED light-emitting element
  • Ipixel is the sub-pixel current
  • S is the sub-pixel opening area
  • AR is the sub-pixel opening ratio.
  • the life of the sub-pixel depends on its aperture ratio AR.
  • the minimum aperture required for the first sub-pixel can be calculated by the above formula .
  • the current efficiencies of the second sub-pixel 220, the third sub-pixel 221 and the first sub-pixel 21 are respectively 2.3 cd/A, 5.8 cd/A and 1.7 cd/A, the white point or
  • the second sub-pixel can be calculated according to the above formulas (1) and (2). 220.
  • the aperture ratio ratio between the third sub-pixel 221 and the first sub-pixel 21 is 2.75:2.4:1, that is, the aperture required by the first sub-pixel 21 is the smallest; the actual aperture ratio can be determined according to the white point target of the pixel 2 to which the sub-pixel belongs and the actual The color point achieved by the process and the efficiency data are adjusted.
  • the orthographic projection of the first conductive layer 61 on the substrate 1 is located in the space between at least part of adjacent pixels 2 along the first direction Y.
  • the size of the first conductive layer 61 along the second direction X is equal to the sum of the sizes of two adjacent pixels 2 along the second direction X and the space between them;
  • the size of a conductive layer 61 along the first direction Y is smaller than the size of the first sub-pixel 21 along the first direction Y.
  • the size of the orthographic projection area of the first conductive layer 61 on the substrate 1 affects the resistance of the cathode on the one hand, and affects the aperture ratio of the sub-pixel and the resolution of the display substrate on the other hand.
  • the first conductive layer 61 The distribution ensures that the aperture ratio of the sub-pixels and the resolution of the display substrate will not be affected, that is, the resolution of the display substrate and the aperture ratio of the sub-pixels will not change because the first conductive layer 61 occupies a part of the area.
  • the sub-pixels can also be arranged as shown in FIG. 10 and FIG. 11 .
  • the arrangement of the sub-pixels in FIG. 10 and FIG. 11 is similar to the arrangement of the sub-pixels in FIG. 3 .
  • the first pitch is equal to the second pitch; the third pitch is equal to the sum of the first pitch, the second pitch and the width of the first sub-pixel 21 along the first direction Y.
  • the sub-pixels may also be arranged as follows: referring to FIG. 12 and FIG. 14 , the second sub-pixel 220 , the first sub-pixel 21 and the third sub-pixel 221 are arranged in sequence along the first direction Y.
  • the dimension of the first conductive layer along the first direction Y is greater than the sum of the dimensions of the first subpixel 21 and the second subpixel 220 along the first direction Y; or, the dimension of the first conductive layer along the first direction Y
  • the size of the first direction Y is greater than the sum of the sizes of the first sub-pixel 21 and the third sub-pixel 221 along the first direction Y; the size of the first conductive layer along the second direction X is smaller than the size of the first sub-pixel 21 along the second direction X size of.
  • the first pitch is smaller than the second pitch; the second pitch is equal to the sum of the first pitch, the width of the second sub-pixel 220 along the first direction Y, and the third pitch.
  • the second sub-pixel 220 , the third sub-pixel 221 and the first sub-pixel 21 are sequentially arranged along the first direction Y.
  • the size of the first sub-pixel 21 along the second direction X is smaller than that of any one of the second sub-pixel 220 and the third sub-pixel 221 along the second direction X.
  • the size of the second direction X; the size of the first sub-pixel 21 along the first direction Y is smaller than the size of any one of the second sub-pixel 220 and the third sub-pixel 221 along the first direction Y; the first direction Y and the second direction X vertical.
  • the orthographic projection of the first conductive layer on the substrate is located in the space between at least part of adjacent pixels 2 along the second direction X.
  • the size of the first conductive layer along the first direction Y is smaller than the first pitch or the second pitch; the size of the first conductive layer along the second direction X is smaller than the first pitch.
  • the size of the sub-pixel 21 along the second direction X is smaller than the first pitch.
  • any two adjacent rows of pixels 2 arranged along the second direction X are mirror-symmetrical.
  • any two adjacent columns of pixels 2 arranged along the first direction Y are mirror-symmetrical.
  • each row of pixels 2 is arranged along the second direction X; the second sub-pixels 220 in each row of pixels 2 are arranged along the second direction X; The third sub-pixels 221 in each row of pixels 2 are arranged along the second direction X; the first sub-pixels 21 in each row of pixels 2 are arranged along the second direction X.
  • the printing or coating process can be made easier, Easier to implement.
  • the first sub-pixel 21 is a blue sub-pixel; the second sub-pixel 220 is a red sub-pixel; and the third sub-pixel 221 is a green sub-pixel. In some embodiments, the first sub-pixel 21 is a blue sub-pixel; the second sub-pixel 220 is a green sub-pixel; and the third sub-pixel 221 is a red sub-pixel.
  • the aperture ratio ratios of the second sub-pixel 220 , the third sub-pixel 221 and the first sub-pixel 21 are The range is 2:2:1 to 3:2:1.
  • the aperture ratio ratio of the second sub-pixel 220, the third sub-pixel 221 and the first sub-pixel 21 is 2.75:2.4:1.
  • the ratio of the aperture ratio can realize the lifetime ratio of the second sub-pixel 220, the third sub-pixel 221 and the first sub-pixel 21 to be 1:1:1.5, so that it can It is ensured that the aperture ratio and lifespan of the sub-pixels are balanced, thereby improving the display effect of the display substrate while ensuring the longest display life of the display substrate.
  • the second sub-pixel 220, the third sub-pixel 221 and the first sub-pixel 21 are on the substrate 1
  • the orthographic shapes of include rectangles. In this way, when the first transmission unit corresponding to the first sub-pixel 21 and the color conversion unit corresponding to the second sub-pixel 220 and the third sub-pixel 221 are prepared through the subsequent printing or coating process, the printing or coating process can be made easier, Easier to implement.
  • the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 further include a color conversion layer 7, which is located on the side of the cathode 203 away from the light-emitting functional layer 202; the light-emitting functional layer 202 emits blue light; the color conversion layer 7 is used for color conversion of blue light.
  • the color conversion layer 7 includes a first color conversion unit 71, a second color conversion unit 72, and a first transmission unit 73; the front projection of the first color conversion unit 71 on the substrate 1 covers the first color conversion unit 71.
  • the orthographic projection of the first sub-pixel 21 on the substrate 1 is covered.
  • the first color conversion unit 71 converts the blue light emitted by the light-emitting functional layer 202 in its corresponding sub-pixel into red light by exciting the quantum dots therein;
  • the blue light emitted by the light-emitting functional layer 202 is converted into green light;
  • the first transmission unit 73 further scatters the blue light emitted by the light-emitting functional layer 202 in the corresponding sub-pixel through the scattering particles therein.
  • the display substrate further includes a retaining wall 8 and a first black matrix 9, located on the side of the pixel defining layer 5 away from the substrate 1, and the first black matrix 9 and the retaining wall 8 are sequentially separated from the pixels to define
  • the layer 5 is arranged; the orthographic projection of the barrier wall 8 and the first black matrix 9 on the substrate 1 overlaps at least partially the orthographic projection of the pixel defining layer 5 on the substrate 1 .
  • the function of the barrier wall 8 is to separate the color conversion layer 7 corresponding to sub-pixels of different colors, so that crosstalk occurs between light rays of adjacent sub-pixels when the color conversion layer 7 performs color conversion.
  • the function of the first black matrix 9 is also to block the light emitted by adjacent sub-pixels from irradiating the corresponding color conversion layer 7 , so as to avoid crosstalk between the light from adjacent sub-pixels when the color conversion layer 7 performs color conversion.
  • the first sub-pixel 21, the second sub-pixel 220, and the third sub-pixel 221 further include a color-resist layer 10, which is located on the side of the color conversion layer 7 away from the substrate 1; the color-resist layer 10 includes a first color resistance 101, a second color resistance 102 and a third color resistance 103; the orthographic projection of the first color resistance 101 on the substrate 1 falls within the orthographic projection of the first color conversion unit 71 on the substrate 1; The orthographic projection of the second color resist 102 on the substrate 1 falls within the orthographic projection of the second color conversion unit 72 on the substrate 1; the orthographic projection of the third color resist 103 on the substrate 1 falls within the orthographic projection of the first transmission unit 73 on the substrate 1 In the orthographic projection on .
  • the color of the first color resistance 101 is the same as the color converted by the first color conversion unit 71; the color of the second color resistance 102 is the same as the color converted by the second color conversion unit 72; the color of the third color resistance 103 is the same as that of the first color resistance
  • the luminous color of the light-emitting functional layers of the sub-pixels 21 is the same; the color-resist layer 10 can filter the unconverted light color after being converted by the color conversion layer 7, thereby further improving the purity of the color displayed by each sub-pixel, thereby improving the display effect.
  • the light emitting principle of each sub-pixel is as follows: a battery or a power supply applies a voltage to the anode 201 and the cathode 203 of the sub-pixel; current flows from the cathode 203 to the anode 201, And through the light-emitting functional layer 202; the light-emitting functional layer 202 includes an organic molecule emission layer and an organic molecule conduction layer; the cathode 203 outputs electrons to the organic molecule emission layer in the light-emitting function layer 202; the anode 201 absorbs organic molecules from the light-emitting function layer 202 The electrons from the conductive layer (here can be regarded as the anode outputs holes to the conductive layer, and the two effects are equal); at the junction of the emissive layer and the conductive layer, the electrons will combine with the holes; when the electrons encounter the holes, they will The hole is filled (it will fall).
  • the light-emitting functional layer 202 of each sub-pixel emits blue light.
  • the light-emitting functional layer 202 is laid with an organic blue light-emitting material, and the size of the anode pattern of each sub-pixel determines the size of each sub-pixel.
  • the size of the opening area after the blue light passes through the color conversion layer 7 in the pixel, it is converted into other colors, such as red, green, and blue; the color conversion layer 7 uses quantum dot materials, and quantum dots are semiconductor nanocrystals, which can produce pure Monochromatic red light, green light and blue light; thus the color display of the display substrate can be realized. Setting the color resist layer 10 on the side of the color conversion layer 7 away from the substrate 1 can further improve the purity of the color displayed by each sub-pixel and improve the display effect.
  • the display substrate further includes a second black matrix 11 located on the side of the retaining wall 8 away from the base 1; the orthographic projection of the second black matrix 11 on the base 1 falls into the first black matrix 9 In the orthographic projection on base 1.
  • the second black matrix 11 separates the color-resist layers 10 of different colors on the one hand, and on the other hand, it can prevent the light emitted by adjacent sub-pixels from passing through their corresponding color conversion layers 7 and then irradiating the color-resist layers corresponding to each other.
  • the orthographic projection of the second black matrix 11 on the substrate 1 falls within the orthographic projection of the first black matrix 9 on the substrate 1, which can better prevent phase
  • the light crosstalk between adjacent sub-pixels improves the display effect.
  • Figure 15a is a pattern of a conductive layer on the substrate in multiple pixel circuits, the pattern of the conductive layer includes a pattern of one of the plates used to form the capacitance in the pixel circuit and some patterns of connecting via holes and patterns of signal traces .
  • Fig. 15b is a pattern of the active layer of the transistor located on the side of the conductive layer pattern in Fig. 15a away from the substrate in a plurality of pixel circuits.
  • Figure 15c is a pattern of via holes in the insulating layer (such as gate insulating layer, intermediate dielectric layer, etc.) located on the side of the active layer pattern away from the substrate in multiple pixel circuits.
  • Fig. 15d is a diagram of the transistor source-drain electrode layer, the second conductive layer and other conductive structures located on the side of the insulating layer away from the base in multiple pixel circuits.
  • Fig. 15e is a top view of a plurality of pixel circuits after the film layers in Fig. 15a, Fig. 15b, Fig. 15c and Fig. 15d are sequentially stacked. In this embodiment, no changes are made to the design and arrangement of the pixel circuits.
  • FIG. 16a shows the anode, the first conductive layer, and the anode located on the side of the source and drain electrode layer of the transistor away from the substrate on the display substrate, and the insulating layer (such as a passivation layer, a flat layer, etc.) ) Graphics of the vias.
  • Fig. 16b is a diagram showing an opening formed in the pixel defining layer on the side where the anode is away from the base on the substrate, and the orthographic projection of the sub-pixel and the first conductive layer on the base is located in the opening.
  • FIG. 16c is a diagram showing the barrier wall and the first black matrix on the substrate on the side of the pixel defining layer facing away from the base.
  • Figure 16d is a diagram showing a color conversion layer on a substrate located in a region separated by a barrier wall.
  • Fig. 16e is a top view of the display substrate after the film layers in Figs. 15a-15d and Figs. 16a-16d are sequentially stacked.
  • the arrangement of the sub-pixels is changed so that the orthographic projections of the first via holes 41 and the second via holes 42 on the substrate are located at the orthographic projections of the first sub-pixels 21 and the second sub-pixels 22 on the substrate.
  • 15a-15d and 16a-16d are patterns of various film layers on the display substrate corresponding to the arrangement of sub-pixels in FIG. 3 .
  • the orthographic projections of the first subpixel, the second subpixel, and the third subpixel on the substrate and the orthographic projections of the pixel circuit electrically connected thereto on the substrate do not overlap at least partially.
  • the orthographic projection of the circuit on the substrate is not one-to-one correspondence, and the overlapping areas of the two are not regular and consistent, that is, the two are randomly corresponding.
  • the first pass The hole 41 and the second via hole 42 are located in the area between the first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221, thereby increasing the distance between the first sub-pixel 21 and the second sub-pixel 220 and the third sub-pixel.
  • the spacing between the pixels 221 can improve or avoid light crosstalk between the two; on the other hand, the space can be used more effectively and rationally, so that the change of the arrangement of the sub-pixels will not reduce the opening of the sub-pixels rate, and will not reduce the display resolution of the display substrate.
  • FIG. 17a-FIG. 17d and FIG. 18a-FIG. 18d are patterns of various film layers on the display substrate corresponding to the arrangement of sub-pixels in FIG. 12 .
  • Fig. 17a is a pattern of a conductive layer located on the substrate in a plurality of pixel circuits, the pattern of the conductive layer includes a pattern of one of the plates used to form the capacitor in the pixel circuit and some patterns of connecting via holes and signal traces graphics.
  • Fig. 17b is a pattern of the active layer of the transistor located on the side of the conductive layer pattern in Fig. 15a away from the substrate in a plurality of pixel circuits.
  • Fig. 17a is a pattern of a conductive layer located on the substrate in a plurality of pixel circuits, the pattern of the conductive layer includes a pattern of one of the plates used to form the capacitor in the pixel circuit and some patterns of connecting via holes and signal traces graphics.
  • Fig. 17b is a pattern of the active layer of
  • FIG. 17c is a pattern of via holes in the insulating layer (such as gate insulating layer, intermediate dielectric layer, etc.) located on the side of the active layer pattern away from the substrate in multiple pixel circuits.
  • Fig. 17d is a diagram of the transistor source-drain electrode layer, the second conductive layer and other conductive structures located on the side of the insulating layer away from the base in multiple pixel circuits.
  • FIG. 18a shows the anode on the substrate, the first conductive layer and the insulating layer (such as a passivation layer, a flat layer, etc. ) Graphics of the vias.
  • Fig. 18b is a diagram showing an opening formed in the pixel defining layer on the side of the substrate where the anode is away from the base, and the orthographic projection of the sub-pixel and the first conductive layer on the base is located in the opening.
  • FIG. 18c is a diagram showing the barrier wall and the first black matrix on the substrate on the side of the pixel defining layer facing away from the base.
  • FIG. 18d is a diagram showing a color conversion layer on a substrate in a region separated by a barrier wall.
  • Fig. 18e is a top view of the display substrate after the film layers in Figs. 17a-17d and Figs. 18a-18d are sequentially stacked.
  • the arrangement of the sub-pixels is changed so that the orthographic projections of the first via hole 41 and the second via hole 42 on the substrate are located in the first sub-pixel 21, the second sub-pixel 220 and the third sub-pixel 221 on the substrate, so as to improve or avoid light crosstalk between adjacent first sub-pixels 21 and second sub-pixels 220 and third sub-pixels 221 .
  • the display substrate further includes a first encapsulation layer 12, a second encapsulation layer 13, and an anti-reflection layer 14;
  • the first encapsulation layer 12 is located on the side of the cathode 203 away from the substrate 1 and the color conversion layer 7 on the side close to the cathode 203;
  • the second encapsulation layer 13 is located on the side of the color conversion layer 7 away from the substrate 1 and on the side of the color resistance layer 10 close to the color conversion layer 7;
  • the antireflection layer 14 is located on the side of the color resistance layer 10 away from side of base 1.
  • the first encapsulation layer 12 can form an encapsulation for the light-emitting functional layer 202 and the cathode 203 of the sub-pixel to prevent external water vapor and oxygen from entering the light-emitting functional layer 202 to prevent damage to it.
  • the second encapsulation layer 13 can form an encapsulation for the color conversion layer 7, thereby forming protection for the color conversion layer 7, and simultaneously forming multiple protections for the light-emitting functional layer 202 and the cathode 203 of the sub-pixel.
  • the anti-reflection layer 14 can be a polarizer, which can prevent the reflection of external light irradiated on the display surface of the display substrate, so as to ensure that the display substrate can display normally.
  • the first encapsulation layer 12 may adopt a laminated arrangement of an inorganic film layer, an organic film layer and an inorganic film layer.
  • the second encapsulation layer 13 may use an inorganic film layer.
  • the embodiments of the present disclosure further provide a display panel, including the display substrate in the above embodiments.
  • the embodiments of the present disclosure further provide a display device, including the display panel in the above embodiments.
  • the display device may be any product or component with a display function, such as an OLED panel, an OLED TV, a monitor, a mobile phone, or a navigator.

Abstract

一种显示基板，包括：基底（1）;多个像素电路，设置于基底（1）±;多个像素（2）,呈阵列排布，且位于像素电路背离基底（1）的一侧；像素（2）包括第一子像素（21）、第二子像素（220）和第三子像素（221）；第一子像素（21）、第二子像素（220）和第三子像素（221）在基底（1）上的正投影无交叠；第一子像素（21）、第二子像素（220）和第三子像素（221）与像素电路一一对应电连接；第一子像素（21）和第二子像素（220）之间沿着第一方向（Y）设置第一间距，在第一间距中设置第一过孔（41）；第一子像素（21）和第三子像素（221）之间沿着第一方向（Y）设置第二间距，在第二间距中设置第一过孔（41）；第二子像素（220）和第三子像素（221）之间沿着第一方向（Y）设置第三间距。

Description

显示基板、显示面板和显示装置 技术领域
本公开实施例属于显示技术领域，具体涉及一种显示基板、显示面板和显示装置。
背景技术
目前，OLED(Organic Light-Emitting Diode)显示面板，又称为有机电激光显示面板、有机发光半导体显示面板，色域是评价OLED显示面板的一个重要指标，高色域显示会给使用者带来更好视觉体验，是目前新产品研发中重点追求的一个指标。
发明内容
本公开实施例提供一种显示基板、显示面板和显示装置。
第一方面，本公开实施例提供一种显示基板，包括：基底；
多个像素电路，设置于基底上；
多个像素，呈阵列排布，且位于像素电路背离基底的一侧；
像素包括第一子像素、第二子像素和第三子像素；第一子像素、第二子像素和第三子像素在基底上的正投影无交叠；第一子像素、第二子像素和第三子像素与像素电路一一对应电连接；
第一子像素和第二子像素之间沿着第一方向设置第一间距，在第一间距中设置第一过孔；
第一子像素和第三子像素之间沿着第一方向设置第二间距，在第二间距中设置第一过孔；
第二子像素和第三子像素之间沿着第一方向设置第三间距。
在一些实施例中，像素电路包括驱动管和绝缘层；第一子像素、第二子像素和第三子像素分别包括阳极；驱动管、绝缘层和阳极依次远离基底设置；
像素电路还包括辅助电极；
辅助电极包括第一导电层，第一导电层与阳极位于同一膜层上，且第一导电层在基底上的正投影与阳极在基底上的正投影互不交叠；
辅助电极还包括第二导电层，第二导电层与驱动管的第一极和第二极位于同一膜层上，且第二导电层在基底上的正投影与驱动管的第一极和第二极在基底上的正投影互不交叠。
在一些实施例中，像素中，第二子像素和第三子像素位于第一子像素的同一侧；且第二子像素和第三子像素沿第二方向排布；
第一间距等于第二间距；
第三间距小于第一间距。
在一些实施例中，第一子像素与第三子像素沿第一方向排布；
第一方向与第二方向垂直。
在一些实施例中，像素中，第一子像素沿第二方向的尺寸等于沿第二方向第二子像素、第三子像素以及二者之间的间隔的尺寸之和；
第一子像素沿第一方向的尺寸小于第二子像素和第三子像素中任意一者沿第一方向的尺寸。
在一些实施例中，第一导电层在基底上的正投影位于沿第一方向至少部分相邻的像素之间的间隔区。
在一些实施例中，第一导电层沿第二方向的尺寸等于沿第二方向相邻两个像素以及二者之间的间隔的尺寸之和；
第一导电层沿第一方向的尺寸小于第一子像素沿第一方向的尺寸。
在一些实施例中，第一间距等于第二间距；
第三间距等于第一间距、第二间距和第一子像素沿第一方向的宽度之和。
在一些实施例中，第二子像素、第一子像素和第三子像素沿第一方向依次排布。
在一些实施例中，第一导电层沿第一方向的尺寸大于第一子像素与第二子像素沿第一方向的尺寸之和；或者，第一导电层沿第一方向的尺寸大于第一子像素与第三子像素沿第一方向的尺寸之和；
第一导电层沿第二方向的尺寸小于第一子像素沿第二方向的尺寸。
在一些实施例中，第一间距小于第二间距；
第二间距等于第一间距、第二子像素沿第一方向的宽度和第三间距之和。
在一些实施例中，像素中，第二子像素、第三子像素和第一子像素沿第一方向依次排布。
在一些实施例中，像素中，第一子像素沿第二方向的尺寸小于第二子像素和第三子像素中任意一者沿第二方向的尺寸；
第一子像素沿第一方向的尺寸小于第二子像素和第三子像素中任意一者沿第一方向的尺寸；
第一方向与第二方向垂直。
在一些实施例中，第一导电层在基底上的正投影位于沿第二方向至少部分相邻像素之间的间隔区。
在一些实施例中，第一导电层沿第一方向的尺寸小于第一间距或第二间距；
第一导电层沿第二方向的尺寸小于第一子像素沿第二方向的尺寸。
在一些实施例中，沿第二方向排布的任意相邻两行像素镜像对称；
或者，沿第一方向排布的任意相邻两列像素镜像对称。
在一些实施例中，像素阵列中，各行像素沿第二方向排布；
各行像素中的第二子像素沿第二方向排布；
各行像素中的第三子像素沿第二方向排布；
各行像素中的第一子像素沿第二方向排布。
在一些实施例中，像素阵列中，各行像素沿第二方向排布；
第2n+1行与第2n+2行像素的第一子像素沿第二方向排布；其中，n为整数，n＝0,1,2…。
在一些实施例中，第一子像素为蓝色子像素；第二子像素为红色子像素；第三子像素为绿色子像素；
或者，第一子像素为蓝色子像素；第二子像素为绿色子像素；第三子像素为红色子像素。
在一些实施例中，第一过孔开设在绝缘层中，用于将第一子像素、第二子像素和第三子像素的阳极分别连接至各自像素电路中驱动管的第一极。
在一些实施例中，绝缘层中还开设有第二过孔，用于将第一导电层连接至第二导电层；
第二过孔在基底上的正投影位于沿第二方向相邻的两个像素之间。
在一些实施例中，像素中，第一间距和第二间距的间距范围分别为7-25μm。
在一些实施例中，第一过孔和第二过孔在第一方向上的正投影无交叠。
在一些实施例中，第一过孔和第二过孔在第一方向上的正投影至少部分交叠。
在一些实施例中，还包括像素界定层，位于绝缘层背离基底的一侧；
第一子像素、第二子像素和第三子像素分别位于像素界定层所界定的区域；
第一子像素、第二子像素和第三子像素分别还包括发光功能层和阴极；发光功能层和阴极依次远离阳极设置；且发光功能层和阴极在基底上的正投影与阳极在基底上的正投影至少部分交叠；
像素界定层在对应第一导电层的区域形成有开口；发光功能层和阴极还延伸至开口中，且发光功能层和阴极的位于开口以内的部分与位于开口以外的部分在开口边缘处相互断开；
阴极的位于开口以外的部分包覆发光功能层在开口边缘处的断开边缘，且阴极的位于开口以外的部分还延伸至与第一导电层的至少部分边缘端面相接触。
在一些实施例中，第一导电层包括沿远离基底方向依次叠置的第一子层、第二子层和第三子层；
第一导电层的垂直于基底的截面形状包括“工”字型或倒梯形；
阴极的位于开口以外的部分至少与第二子层和第三子层的边缘端面相接触。
在一些实施例中，像素中，第二子像素、第三子像素和第一子像素的开口率比例范围为2：2：1至3：2：1。
在一些实施例中，像素中，第二子像素、第三子像素和第一子像素在基底上的正投影形状包括矩形。
在一些实施例中，第一子像素、第二子像素和第三子像素分别还包括颜色转换层，位于阴极背离发光功能层的一侧；
发光功能层发蓝光；
颜色转换层用于对蓝光进行颜色转换。
在一些实施例中，颜色转换层包括第一色转换单元、第二色转换单元和第一透射单元；
第一色转换单元在基底上的正投影覆盖第二子像素在基底上的正投影；
第二色转换单元在基底上的正投影覆盖第三子像素在基底上的正投影；
第一透射单元在基底上的正投影覆盖第一子像素在基底上的正投影。
在一些实施例中，还包括挡墙和第一黑矩阵，位于像素界定层背离基底的一侧，且第一黑矩阵和挡墙依次远离像素界定层设置；
挡墙和第一黑矩阵在基底上的正投影与像素界定层在基底上的正投影 至少部分交叠。
在一些实施例中，第一子像素、第二子像素和第三子像素分别还包括色阻层，位于颜色转换层背离基底的一侧；
色阻层包括第一色阻、第二色阻和第三色阻；
第一色阻在基底上的正投影落入第一色转换单元在基底上的正投影内；
第二色阻在基底上的正投影落入第二色转换单元在基底上的正投影内；
第三色阻在基底上的正投影落入第一透射单元在基底上的正投影内。
在一些实施例中，还包括第二黑矩阵，位于挡墙背离基底的一侧；
第二黑矩阵在基底上的正投影落入第一黑矩阵在基底上的正投影内。
在一些实施例中，多个像素电路在基底上的正投影面积相等。
在一些实施例中，第一子像素、第二子像素和第三子像素在基底上的正投影和与其电连接的像素电路在基底上的正投影至少部分不交叠。
在一些实施例中，还包括第一封装层、第二封装层和防反射层；
第一封装层位于阴极的背离基底的一侧和颜色转换层的靠近阴极的一侧；
第二封装层位于颜色转换层背离基底的一侧和色阻层的靠近颜色转换层的一侧；
防反射层位于色阻层背离基底的一侧。
第二方面，本公开实施例还提供一种显示面板，包括上述显示基板。
第三方面，本公开实施例还提供一种显示装置，包括上述显示面板。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域 技术人员将变得更加显而易见，在附图中：
图1为公开技术中OLED显示面板中像素的排布示意图；
图2a为公开技术中蓝色子像素对其周围红色、绿色子像素造成光串扰的示意图。
图2b为公开技术中红色、绿色子像素对其周围蓝色子像素造成光串扰的示意图。
图2c为公开技术中红色子像素与绿色子像素相互之间光串扰的示意图。
图3为本公开实施例显示基板中的一种像素排布示意图。
图4为沿图3中AA剖切线的结构剖视图。
图5为改进之前第一子像素与第二子像素之间的间距示意图。
图6为改进之后第一子像素与第二子像素之间的间距示意图。
图7为沿图3中BB剖切线的结构剖视图。
图8为本公开实施例中第一过孔和第二过孔的一种排布示意图。
图9为本公开实施例中第一过孔和第二过孔的另一种排布示意图。
图10为本公开实施例显示基板中的另一种像素排布示意图。
图11为本公开实施例显示基板中的又一种像素排布示意图。
图12为本公开实施例显示基板中的又一种像素排布示意图。
图13为本公开实施例显示基板中的又一种像素排布示意图。
图14为本公开实施例显示基板中的又一种像素排布示意图。
图15a为多个像素电路中位于基底上的一个用于形成像素电路中的电容的其中一个极板的图形以及一些连接过孔的图形和信号走线的图形的导电层图形。
图15b为多个像素电路中位于图15a中导电层图形背离基底侧的晶体管有源层的图形。
图15c为多个像素电路中位于有源层图形背离基底侧的绝缘层中的过 孔的图形。
图15d为多个像素电路中位于绝缘层背离基底侧的晶体管源漏电极层、第二导电层以及其他导电结构的图形。
图15e为图15a、图15b、图15c和图15d中各膜层依次叠加之后的多个像素电路的俯视图形。
图16a为显示基板上位于晶体管源漏电极层图形背离基底侧的阳极、第一导电层以及开设在绝缘层中的过孔的图形。
图16b为显示基板上位于阳极背离基底侧的像素界定层中形成的开口的图形。
图16c为显示基板上位于像素界定层背离基底侧的挡墙和第一黑矩阵的图形。
图16d为显示基板上位于挡墙所隔开区域内的颜色转换层的图形。
图16e为图15a-图15d以及图16a-图16d中的各膜层依次叠加之后的显示基板的俯视图形。
图17a为多个像素电路中位于基底上的一个用于形成像素电路中的电容的其中一个极板的图形以及一些连接过孔的图形和信号走线的图形的导电层图形。
图17b为多个像素电路中位于图15a中导电层图形背离基底侧的晶体管有源层的图形。
图17c为多个像素电路中位于有源层图形背离基底侧的绝缘层中的过孔的图形。
图17d为多个像素电路中位于绝缘层背离基底侧的晶体管源漏电极层、第二导电层以及其他导电结构的图形。
图18a为显示基板上位于晶体管源漏电极层图形背离基底侧的阳极、第一导电层以及开设在绝缘层中的过孔的图形。
图18b为显示基板上位于阳极背离基底侧的像素界定层中形成的开口 的图形。
图18c为显示基板上位于像素界定层背离基底侧的挡墙和第一黑矩阵的图形。
图18d为显示基板上位于挡墙所隔开区域内的颜色转换层的图形。
图18e为图17a-图17d以及图18a-图18d中的各膜层依次叠加之后的显示基板的俯视图形。
具体实施方式
为使本领域技术人员更好地理解本公开实施例的技术方案，下面结合附图和具体实施方式对本公开实施例提供的显示基板、显示面板和显示装置作进一步详细描述。
在下文中将参考附图更充分地描述本公开实施例，但是所示的实施例可以以不同形式来体现，且不应当被解释为限于本公开阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了区的具体形状，但并不是旨在限制性的。
公开技术中，采用量子点(quantum dot,QD)作为色转换层、OLED作为发光元件的OLED显示面板(即QD-OLED显示面板)可实现高色域显示，同时视角色偏较好。参照图1，大尺寸QD-OLED显示面板中，包含阵列排布的多个像素2，每个像素可包含相邻排布的红色子像素151、绿色子像素152和蓝色子像素153。像素2包含垂直设置的发光元件和色转换层，其中，发光元件可发射蓝光，色转换层包含第一色转换单元、第二色转换单元和第一透射单元。具体的，发光元件所发蓝光经过第一色转换单元，可转换为红光出射；发光元件所发蓝光经过第二色转换单元，可转换为绿光出射；第一透射单元可包含散射粒子，发光元件所发蓝光经过第一透射单元，可 经散射粒子作用，仍以蓝光出射。但蓝色子像素153会由于盒厚较厚串扰到相邻发其他颜色光的子像素，引起相邻子像素之间的光串扰，造成漏光，最终导致OLED显示面板显示色域较差。
具体地，相邻子像素之间的光串扰参照图2a、图2b和图2c，由于OLED显示面板盒厚较厚(盒厚为对子像素进行封装的封装层的靠近发光层的一侧表面到OLED显示面板的像素电路基板之间的距离)，在一定的盒厚下，蓝色子像素中的发光元件发出的蓝光会照射到相邻红色子像素和绿色子像素的量子点色转换单元上，激发第一色转换单元发出红光，第二色转换单元发出绿光，造成光串扰，参照图2a；此种情况下，由于蓝色子像素的发光元件发出的蓝光一部分经过第一透射单元进行转换，所以会存在串扰光线转化效率的影响。同时，红色子像素中的发光元件发出的蓝光和绿色子像素中的发光元件发出的蓝光同样会照射到蓝色子像素的第一透射单元上，经第一透射单元散射后的出光造成光串扰，但此种情况下无串扰光线转化效率的影响，参照图2b。另外，红色子像素中的发光元件发出的蓝光和绿色子像素中的发光元件发出的蓝光同样会照射到彼此的量子点转换层上，造成光串扰，参照图2c。
实测中发现，红色子像素和绿色子像素之间的光串扰影响相对较小，蓝色子像素与其他颜色子像素之间的光串扰影响最为严重，容易导致较为严重的子像素间漏光现象，不利于提升OLED显示面板的色域，以致会比较严重的影响OLED显示面板的显示效果。
针对QD-OLED显示面板中蓝色子像素与其他颜色子像素之间较严重的光串扰问题，本公开实施例提供如下技术方案。
第一方面，参照图3，图10-图14，本公开实施例提供一种显示基板，包括：基底1；多个像素电路，设置于基底1上；多个像素2，呈阵列排布，且位于像素电路背离基底1的一侧；像素2包括第一子像素21、第二子像 素220和第三子像素221；第一子像素21、第二子像素220和第三子像素221在基底1上的正投影无交叠；第一子像素21、第二子像素220和第三子像素221与像素电路一一对应电连接；第一子像素21和第二子像素220之间沿着第一方向Y设置第一间距，在第一间距中设置第一过孔41；第一子像素21和第三子像素221之间沿着第一方向Y设置第二间距，在第二间距中设置第一过孔41；第二子像素220和第三子像素221之间沿着第一方向Y设置第三间距。
在一些实施例中，参照图3和图4，像素电路包括驱动管3和绝缘层4；第一子像素21、第二子像素220和第三子像素221分别包括阳极201；驱动管3、绝缘层4和阳极201依次远离基底1设置。第一过孔41开设在绝缘层4中，用于将第一子像素21、第二子像素220和第三子像素221的阳极201分别连接至各自像素电路中驱动管3的第一极。
在一些实施例中，通过使第一过孔41位于第一间距和第二间距中，能使第第一间距和第二间距分别由公开技术中的10μm左右增大至15～25μm；从而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的光线串扰，进而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的漏光现象，有利于提升显示基板的色域，最终提升显示基板的显示效果。其中，参照图5和图2a，改进之前，第一子像素21与第二子像素220或第三子像素221之间的间距为相邻第一子像素21与第二子像素220或第三子像素221的相邻边缘之间的间距，如第一子像素21与第二子像素220或第三子像素221之间的间距为沿第一方向Y，第一子像素21的阳极与位于相邻第一子像素21和第二子像素220或第三子像素221之间的像素界定层的正投影交叠区域尺寸b1、像素界定层的与相邻的第一子像素21阳极和第二子像素220或第三子像素221阳极都不交叠部分的尺寸b2、第二子像素220或第三子像素221的阳极与位于相邻第一子像素21和第二子像素220或第三子像素221之间的像素界定层的正投影交 叠区域尺寸b3的尺寸之和；例如：b1+b2+b3＝3.5+4+3.5＝11μm。参照图6和图4，改进之后，第一子像素21与第二子像素220或第三子像素221之间的间距为沿第一方向Y，相邻第一子像素21与第二子像素220或第三子像素221的相邻边缘之间的间距再加上第一过孔41沿第一方向Y的尺寸p，如第一过孔41为6×6μm的正方形过孔，第一过孔41沿第一方向Y的尺寸p为6μm；则改进之后第一子像素21与第二子像素220或第三子像素221之间的间距为：b1+b2+b3+p＝3.5+4+3.5+6＝17μm。
本实施例中，在显示基板盒厚不变的情况下，保持像素电路的排布位置不变，通过改变子像素的排布位置，使公开技术中至少部分位于子像素所在区域的第一过孔41完全位于第一子像素21与第二子像素220之间的第一间距区域和第一子像素21与第三子像素221之间的第二间距区域，相对于公开技术中子像素的排布方式，能使第一子像素21与第二子像素220之间的第一间距和第一子像素21与第三子像素221之间的第二间距增大，从而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的光线串扰，进而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的漏光现象，有利于提升显示基板的色域，最终提升显示基板的显示效果。
在一些实施例中，参照图3、图4和图7，像素电路还包括辅助电极6；辅助电极6包括第一导电层61，第一导电层61与阳极201位于同一膜层上，且第一导电层61在基底1上的正投影与阳极201在基底1上的正投影互不交叠；辅助电极6还包括第二导电层62，第二导电层62与驱动管3的第一极31和第二极32位于同一膜层上，且第二导电层62在基底1上的正投影与驱动管3的第一极31和第二极32在基底1上的正投影互不交叠。
在一些实施例中，绝缘层4中还开设有第二过孔42，用于将第一导电层61连接至第二导电层62；第二过孔42在基底1上的正投影位于沿第二方向X相邻的两个像素2之间。
其中，通过使第二过孔42在基底1上的正投影位于沿第二方向X相邻的两个像素2之间，相对于公开技术中第二过孔42至少部分位于子像素所在区域的子像素的排布方式，能使第一间距和第二间距进一步增大，从而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的光线串扰，进而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的漏光现象，有利于提升显示基板的色域，最终提升显示基板的显示效果。
在一些实施例中，参照图8，第一过孔41和第二过孔42在第一方向Y上的正投影无交叠。如此，能使相邻第一子像素21与第二子像素220或第三子像素221之间的间距不仅增加第一过孔41沿第一方向Y的尺寸p，而且会增加第二过孔42沿第一方向Y的尺寸n，从而使相邻第一子像素21与第二子像素220或第三子像素221之间的间距进一步增大，进而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的光线串扰。
在一些实施例中，参照图9，第一过孔41和第二过孔42在第一方向Y上的正投影至少部分交叠。其中，如果第一过孔41和第二过孔42在第一方向Y上的正投影部分交叠，则会增加第一子像素21与第二子像素220或第三子像素221之间的间距；如果第一过孔41和第二过孔42在第一方向Y上的正投影完全交叠，且第一过孔41在第一方向Y上的正投影尺寸大于第二过孔42在第一方向Y上的正投影尺寸，也会增加第一子像素21与第二子像素220或第三子像素221之间的间距，从而使相邻第一子像素21与第二子像素220或第三子像素221之间的间距进一步增大，进而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的光线串扰。
在一些实施例中，像素2中，第一间距和第二间距的间距范围分别为7-25μm。通过上述在第一间距和第二间距内设置第一过孔41和第二过孔42的技术方案，能使第一间距和第二间距由未改进子像素排布前的较小间 距增大为改进子像素排布后的较大间距，从而能大大改善或避免第一子像素21与第二子像素220和第三子像素221之间的光线串扰。
本实施例中，通过调整子像素的排布使第一过孔41和第二过孔42位于第一间距和第二间距内，第一过孔41和第二过孔42的分布位置确保不会影响子像素的开口率和显示基板的分辨率，即显示基板的分辨率和子像素的开口率不会因为第一过孔41和第二过孔42的分布位置变化而发生变化。
在一些实施例中，参照图4和图7，显示基板还包括像素界定层5，位于绝缘层4背离基底1的一侧；第一子像素21、第二子像素220和第三子像素221分别位于像素界定层5所界定的区域；第一子像素21、第二子像素220和第三子像素221分别还包括发光功能层202和阴极203；发光功能层202和阴极203依次远离阳极201设置；且发光功能层202和阴极203在基底1上的正投影与阳极201在基底1上的正投影至少部分交叠，交叠部分构成发光元件；像素界定层5在对应第一导电层61的区域形成有开口；发光功能层202和阴极203还延伸至开口中，且发光功能层202和阴极203的位于开口以内的部分与位于开口以外的部分在开口边缘处相互断开；阴极203的位于开口以外的部分包覆发光功能层202在开口边缘处的断开边缘，且阴极203的位于开口以外的部分还延伸至与第一导电层61的至少部分边缘端面相接触。
其中，阴极203在像素界定层5开口边缘处与第一导电层61相接触，从而实现了二者之间的连接；而第一导电层61还通过第二过孔42与第二导电层62连接，如此实现了阴极203与第一导电层61和第二导电层62的互连，即实现了阴极203与辅助电极6的互连。在顶发射型OLED显示基板中，由于对阴极203有透光要求，所以阴极203通常膜层较薄，电阻较大，辅助电极6能够增大阴极203的截面积，从而降低阴极203的电阻，进而使阴极203上的电压降减小且整个阴极203的电压更加趋于一致，从而能 够提升显示基板的显示均一性和显示亮度，有利于提升显示基板的显示效果。
在一些实施例中，参照图7，第一导电层61包括沿远离基底1方向依次叠置的第一子层611、第二子层612和第三子层613；第一导电层61的垂直于基底1的截面形状包括“工”字型或倒梯形；阴极203的位于开口以外的部分至少与第二子层612和第三子层613的边缘端面相接触。其中，如果第一导电层61的截面形状为“工”字型，参照图7，则第一子层611和第三子层613在截面上的宽度分别大于第二子层612在截面上的宽度；如果第一导电层61的截面形状为倒梯形，则第三子层613在截面上的宽度大于第二子层612在截面上的宽度，第二子层612在截面上的宽度大于第一子层611在截面上的宽度。任意一个子层在截面上的宽度均指该子层的垂直于其远离基底1方向的尺寸。第一导电层61的截面形状是传统制备工艺所致，这里不再赘述，只要确保阴极203能够与第一导电层61的边缘端面良好接触即可。
在一些实施例中，阳极201与第一导电层61具有相同的子层叠层结构，即阳极201也由三个子层叠置而成，如此能够降低阳极201电阻，提升显示效果。其中，第一子层611和第三子层613可以采用如氧化铟锡材料，第二子层612可以采用如铝材料。阳极201的三个子层材料分别与第一导电层61的三个子层材料相同，如此可以通过一次构图工艺制备而成，简化制备工艺。阳极201不透光，能够对照射至其上的光线进行反射，从而实现顶发射型OLED显示基板。当然，阳极201也可以透光，此时可以通过在阳极201的靠近基底1的一侧设置反射层以实现对照射至其上光线的反射，从而实现顶发射型OLED显示基板。顶发射型OLED显示基板能够实现较大的显示开口率。
在一些实施例中，参照图3，图10和图11，像素2中，第二子像素220和第三子像素221位于第一子像素21的同一侧；且第二子像素220和第三 子像素221沿第二方向X排布；第一间距等于第二间距；第三间距小于第一间距。
在一些实施例中，参照图3，第一子像素21与第三子像素221沿第一方向Y排布；第一方向Y与第二方向X垂直。
在一些实施例中，参照图3，像素2中，第一子像素21沿第二方向X的尺寸等于沿第二方向X第二子像素220、第三子像素221以及二者之间的间隔的尺寸之和；第一子像素21沿第一方向Y的尺寸小于第二子像素220和第三子像素221中任意一者沿第一方向Y的尺寸。
其中，在子像素开口设计中，需要综合考量子像素的发光效率和寿命，使二者达到平衡。由于第一子像素21在混色中占比较小，且第一子像素21不涉及量子点色转换层激发转化问题，其相对发光效率较高，子像素电流较小，寿命较长；而第二子像素220和第三子像素221为通过量子点色转换层受激发将蓝光分别转换为红光和绿光，需要通过量子点色转换层激发转化发出相应颜色的光，所以其相对发光效率较低，子像素电流较大，寿命较短。通过下述公式可计算子像素开口率比例及其寿命比例。
LTpixel＝LTltc×(Jltc/Jpixel) a…公式(1)
Jpixel＝Ipixel/(S×AR)…公式(2)
其中，a为加速因子，为固定值；LTpixel为子像素寿命；LTltc为可测得的OLED发光元件(包括阳极、发光功能层和阴极)的寿命；Jpixel为子像素电流密度；Jltc为给定的OLED发光元件的电流密度；Ipixel为子像素电流；S为子像素开口面积；AR为子像素开口率。
当子像素的色点效率等数据固定时，子像素的寿命取决于其开口率AR，在采用量子点色转换层的OLED显示基板中，通过上述公式计算可得第一子像素所需开口最小。例如，当第二子像素220、第三子像素221和第一子像素21的电流效率分别为2.3cd/A、5.8cd/A、1.7cd/A时，搭配其所属像素2的白点或色点信息，若第二子像素220、第三子像素221和第一子像素21 的寿命按照1：1：1.5分配，则根据上述公式(1)和(2)计算可得到第二子像素220、第三子像素221和第一子像素21开口率比例为2.75:2.4:1，即第一子像素21所需开口最小；实际开口比例可根据子像素所属像素2的白点目标以及实际工艺达到的色点以及效率数据进行调整。
在一些实施例中，参照图3和图7，第一导电层61在基底1上的正投影位于沿第一方向Y至少部分相邻的像素2之间的间隔区。
在一些实施例中，参照图3和图7，第一导电层61沿第二方向X的尺寸等于沿第二方向X相邻两个像素2以及二者之间的间隔的尺寸之和；第一导电层61沿第一方向Y的尺寸小于第一子像素21沿第一方向Y的尺寸。其中，第一导电层61在基底1上正投影面积的大小一方面影响着阴极的电阻，另一方面影响着子像素的开口率和显示基板的分辨率，本实施例中第一导电层61的分布确保不会影响子像素的开口率和显示基板的分辨率，即显示基板的分辨率和子像素的开口率不会因为第一导电层61占用了部分区域而发生变化。
在一些实施例中，子像素也可以如图10和图11中排布。图10和图11中子像素的排布与图3中子像素的排布类似。
在一些实施例中，参照图12和图14，第一间距等于第二间距；第三间距等于第一间距、第二间距和第一子像素21沿第一方向Y的宽度之和。
在一些实施例中，子像素也可以如此排布：参照图12和图14，第二子像素220、第一子像素21和第三子像素221沿第一方向Y依次排布。
在一些实施例中，参照图12，第一导电层沿第一方向Y的尺寸大于第一子像素21与第二子像素220沿第一方向Y的尺寸之和；或者，第一导电层沿第一方向Y的尺寸大于第一子像素21与第三子像素221沿第一方向Y的尺寸之和；第一导电层沿第二方向X的尺寸小于第一子像素21沿第二方向X的尺寸。
在一些实施例中，参照图13，第一间距小于第二间距；第二间距等于 第一间距、第二子像素220沿第一方向Y的宽度和第三间距之和。
在一些实施例中，像素2中，第二子像素220、第三子像素221和第一子像素21沿第一方向Y依次排布。
在一些实施例中，参照图12、图13和图14，像素2中，第一子像素21沿第二方向X的尺寸小于第二子像素220和第三子像素221中任意一者沿第二方向X的尺寸；第一子像素21沿第一方向Y的尺寸小于第二子像素220和第三子像素221中任意一者沿第一方向Y的尺寸；第一方向Y与第二方向X垂直。
在一些实施例中，第一导电层在基底上的正投影位于沿第二方向X至少部分相邻像素2之间的间隔区。
在一些实施例中，参照图10、图13和图14，第一导电层沿第一方向Y的尺寸小于第一间距或第二间距；第一导电层沿第二方向X的尺寸小于第一子像素21沿第二方向X的尺寸。
在一些实施例中，参照图10，沿第二方向X排布的任意相邻两行像素2镜像对称。参照图13和图14，沿第一方向Y排布的任意相邻两列像素2镜像对称。
在一些实施例中，参照图12、图13和图14，像素2阵列中，各行像素2沿第二方向X排布；各行像素2中的第二子像素220沿第二方向X排布；各行像素2中的第三子像素221沿第二方向X排布；各行像素2中的第一子像素21沿第二方向X排布。如此在后续通过打印或涂布工艺制备对应第一子像素21的第一透射单元和对应第二子像素220和第三子像素221的色转换单元时，能使打印或涂布工艺更加简便，更加容易实现。
在一些实施例中，参照图11和图13，像素2阵列中，各行像素2沿第二方向X排布；第2n+1行与第2n+2行像素2的第一子像素21沿第二方向X排布；其中，n为整数，n＝0,1,2…。如此在后续通过打印或涂布工艺制备对应第一子像素21的散射粒子层时，能使打印或涂布工艺更加简便，更 加容易实现。
在一些实施例中，第一子像素21为蓝色子像素；第二子像素220为红色子像素；第三子像素221为绿色子像素。在一些实施例中，第一子像素21为蓝色子像素；第二子像素220为绿色子像素；第三子像素221为红色子像素。
在一些实施例中，参照图3、图10、图11、图12、图13和图14，像素2中，第二子像素220、第三子像素221和第一子像素21的开口率比例范围为2：2：1至3：2：1。如像素2中，第二子像素220、第三子像素221和第一子像素21的开口率比例为2.75:2.4:1。如此，根据前述子像素开口率及其寿命的计算公式，该开口率比例能够实现第二子像素220、第三子像素221和第一子像素21的寿命比例为1：1：1.5，从而能够确保子像素的开口率和寿命达到平衡，进而在提升显示基板显示效果的同时，还能确保显示基板的显示寿命最长。
在一些实施例中，参照图3，图10、图11、图12、图13和图14，像素2中，第二子像素220、第三子像素221和第一子像素21在基底1上的正投影形状包括矩形。如此在后续通过打印或涂布工艺制备对应第一子像素21的第一透射单元和对应第二子像素220和第三子像素221的色转换单元时，能使打印或涂布工艺更加简便，更加容易实现。
在一些实施例中，参照图4，第一子像素21、第二子像素220和第三子像素221分别还包括颜色转换层7，位于阴极203背离发光功能层202的一侧；发光功能层202发蓝光；颜色转换层7用于对蓝光进行颜色转换。
在一些实施例中，参照图4，颜色转换层7包括第一色转换单元71、第二色转换单元72和第一透射单元73；第一色转换单元71在基底1上的正投影覆盖第二子像素220在基底1上的正投影；第二色转换单元72在基底1上的正投影覆盖第三子像素在基底1上的正投影；第一透射单元73在基底1上的正投影覆盖第一子像素21在基底1上的正投影。第一色转换单 元71通过激发其中的量子点将其对应子像素中的发光功能层202发出的蓝光转换成红光；第二色转换单元72通过激发其中的量子点将其对应子像素中的发光功能层202发出的蓝光转换成绿光；第一透射单元73通过其中的散射粒子使其对应子像素中的发光功能层202发出的蓝光进一步散射。
在一些实施例中，参照图4，显示基板还包括挡墙8和第一黑矩阵9，位于像素界定层5背离基底1的一侧，且第一黑矩阵9和挡墙8依次远离像素界定层5设置；挡墙8和第一黑矩阵9在基底1上的正投影与像素界定层5在基底1上的正投影至少部分交叠。其中，挡墙8的作用是将对应不同颜色子像素的颜色转换层7隔开，以便在颜色转换层7进行颜色转换时相邻子像素的光线之间发生串扰。第一黑矩阵9的作用也是阻挡相邻子像素发出的光线照射到彼此对应的颜色转换层7上，从而避免颜色转换层7进行颜色转换时相邻子像素的光线之间发生串扰。
在一些实施例中，参照图4，第一子像素21、第二子像素220和第三子像素221分别还包括色阻层10，位于颜色转换层7背离基底1的一侧；色阻层10包括第一色阻101、第二色阻102和第三色阻103；第一色阻101在基底1上的正投影落入第一色转换单元71在基底1上的正投影内；第二色阻102在基底1上的正投影落入第二色转换单元72在基底1上的正投影内；第三色阻103在基底1上的正投影落入第一透射单元73在基底1上的正投影内。第一色阻101的颜色与第一色转换单元71所转换出颜色相同；第二色阻102的颜色与第二色转换单元72所转换出颜色相同；第三色阻103的颜色与第一子像素21的发光功能层的发光颜色相同；色阻层10能够对经过颜色转换层7转换后未被转换的光线颜色进行过滤，从而进一步提升各子像素显示颜色的纯度，进而提升显示效果。
在一些实施例中，基于图4中显示基板的结构设置，其中各子像素的发光原理为：电池或电源在子像素的阳极201和阴极203上施加一个电压；电流从阴极203流向阳极201，并经过发光功能层202；发光功能层202包 括有机分子发射层和有机分子传导层；阴极203向发光功能层202中的有机分子发射层输出电子；阳极201吸收从发光功能层202中的有机分子传导层传来的电子(这里可以视为阳极向传导层输出空穴，两者效果相等)；在发射层和传导层的交界处，电子会与空穴结合；电子遇到空穴时，会填充空穴(它会落入缺失电子的原子中的某个能级)；这一过程发生时，电子会以光子的形式释放能量；发光功能层202发光。本实施例中，各子像素的发光功能层202都发出蓝光，本实施例显示基板中，发光功能层202采用有机发蓝光材料整层铺置，各子像素的阳极图形大小决定了各子像素的开口面积大小；蓝光经过像素中的颜色转换层7之后，转换为其他多种颜色，如红、绿、蓝色；颜色转换层7采用量子点材料，量子点是半导体纳米晶体，可以产生纯单色的红光、绿光和蓝光；从而能够实现该显示基板的彩色显示。在颜色转换层7的背离基底1的一侧设置色阻层10，能够进一步提升各子像素显示颜色的纯度，提升显示效果。
在一些实施例中，参照图4，显示基板还包括第二黑矩阵11，位于挡墙8背离基底1的一侧；第二黑矩阵11在基底1上的正投影落入第一黑矩阵9在基底1上的正投影内。其中，第二黑矩阵11一方面将不同颜色的色阻层10隔开，另一方面能够阻挡相邻子像素发出的光线经过其各自对应的颜色转换层7后照射到彼此对应的色阻层10上，从而避免相邻子像素的光线之间发生串扰；第二黑矩阵11在基底1上的正投影落入第一黑矩阵9在基底1上的正投影内，能够更好地防止相邻子像素之间的光线串扰，提升显示效果。
在一些实施例中，参照图15a-图15e，多个像素电路在基底上的正投影面积相等。图15a为多个像素电路中位于基底上的一个导电层图形，该导电层图形包括用于形成像素电路中的电容的其中一个极板的图形以及一些连接过孔的图形和信号走线的图形。图15b为多个像素电路中位于图15a中导电层图形背离基底侧的晶体管有源层的图形。图15c为多个像素电路 中位于有源层图形背离基底侧的绝缘层(如栅绝缘层、中间介电层等)中的过孔的图形。图15d为多个像素电路中位于绝缘层背离基底侧的晶体管源漏电极层、第二导电层以及其他导电结构的图形。图15e为图15a、图15b、图15c和图15d中各膜层依次叠加之后的多个像素电路的俯视图形。本实施例中，对像素电路的设计以及排布未做改变。
在一些实施例中，参照图16a-图16e，图16a为显示基板上位于晶体管源漏电极层图形背离基底侧的阳极、第一导电层以及开设在绝缘层(如钝化层、平坦层等)中的过孔的图形。图16b为显示基板上位于阳极背离基底侧的像素界定层中形成的开口的图形，子像素和第一导电层在基底上的正投影位于开口中。图16c为显示基板上位于像素界定层背离基底侧的挡墙和第一黑矩阵的图形。图16d为显示基板上位于挡墙所隔开区域内的颜色转换层的图形。图16e为图15a-图15d以及图16a-图16d中的各膜层依次叠加之后的显示基板的俯视图形。本实施例中，对子像素的排布进行了改变，使第一过孔41和第二过孔42在基底上的正投影位于第一子像素21和第二子像素22在基底上的正投影之间的区域，从而改善或避免相邻第一子像素21和第二子像素22之间的光线串扰。其中，图15a-图15d以及图16a-图16d为对应图3中子像素排布的显示基板上各膜层图形。
在一些实施例中，参照图16e，第一子像素、所述第二子像素和第三子像素在基底上的正投影和与其电连接的像素电路在基底上的正投影至少部分不交叠。公开技术中，各个子像素和与其电连接的像素电路在基底上的正投影一一对应，且二者相互交叠区域规律且一致；而本实施例中，各个子像素和与其电连接的像素电路在基底上的正投影并不是一一对应，且二者相互交叠区域也不规律和一致，即二者是随机对应的，如此，一方面，通过改变子像素的排布使第一过孔41和第二过孔42位于第一子像素21、第二子像素220和第三子像素221之间的区域，从而增大了第一子像素21与第二子像素220和第三子像素221之间的间距，进而能改善或避免二者 之间的光线串扰；另一方面，可以更加有效且合理地利用空间，使对子像素排布的改变并不会减小子像素的开口率，也不会减小显示基板的显示分辨率。
在一些实施例中，参照图17a-图17d以及图18a-图18d为对应图12中子像素排布的显示基板上各膜层图形。其中，图17a为多个像素电路中位于基底上的一个导电层图形，该导电层图形包括用于形成像素电路中的电容的其中一个极板的图形以及一些连接过孔的图形和信号走线的图形。图17b为多个像素电路中位于图15a中导电层图形背离基底侧的晶体管有源层的图形。图17c为多个像素电路中位于有源层图形背离基底侧的绝缘层(如栅绝缘层、中间介电层等)中的过孔的图形。图17d为多个像素电路中位于绝缘层背离基底侧的晶体管源漏电极层、第二导电层以及其他导电结构的图形。
在一些实施例中，参照图18a-图18e，图18a为显示基板上位于晶体管源漏电极层图形背离基底侧的阳极、第一导电层以及开设在绝缘层(如钝化层、平坦层等)中的过孔的图形。图18b为显示基板上位于阳极背离基底侧的像素界定层中形成的开口的图形，子像素和第一导电层在基底上的正投影位于开口中。图18c为显示基板上位于像素界定层背离基底侧的挡墙和第一黑矩阵的图形。图18d为显示基板上位于挡墙所隔开区域内的颜色转换层的图形。图18e为图17a-图17d以及图18a-图18d中的各膜层依次叠加之后的显示基板的俯视图形。本实施例中，对子像素的排布进行了改变，使第一过孔41和第二过孔42在基底上的正投影位于第一子像素21、第二子像素220和第三子像素221在基底上的正投影之间的区域，从而改善或避免相邻第一子像素21与第二子像素220和第三子像素221之间的光线串扰。
在一些实施例中，参照图4，显示基板还包括第一封装层12、第二封装层13和防反射层14；第一封装层12位于阴极203的背离基底1的一侧 和颜色转换层7的靠近阴极203的一侧；第二封装层13位于颜色转换层7背离基底1的一侧和色阻层10的靠近颜色转换层7的一侧；防反射层14位于色阻层10背离基底1的一侧。其中，第一封装层12能够对子像素的发光功能层202和阴极203形成封装，防止外界水汽和氧气进入发光功能层202，以防止对其造成损坏。第二封装层13能够对颜色转换层7形成封装，从而对颜色转换层7形成保护，同时对子像素的发光功能层202和阴极203形成多重保护。防反射层14可以采用偏光片，能防止照射至显示基板显示面上的外界光线发生反射，从而确保该显示基板能够正常显示。
在一些实施例中，第一封装层12可以采用无机膜层、有机膜层和无机膜层的叠层设置。第二封装层13可以采用无机膜层。
第二方面，本公开实施例还提供一种显示面板，包括上述实施例中的显示基板。
第三方面，本公开实施例还提供一种显示装置，包括上述实施例中的显示面板。
本公开实施例所提供的显示装置可以为OLED面板、OLED电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (38)

  1. 一种显示基板，其特征在于，包括：
    基底；
    多个像素电路，设置于所述基底上；
    多个像素，呈阵列排布，且位于所述像素电路背离所述基底的一侧；
    所述像素包括第一子像素、第二子像素和第三子像素；所述第一子像素、所述第二子像素和所述第三子像素在所述基底上的正投影无交叠；所述第一子像素、所述第二子像素和所述第三子像素与所述像素电路一一对应电连接；
    所述第一子像素和所述第二子像素之间沿着第一方向设置第一间距，在所述第一间距中设置第一过孔；
    所述第一子像素和所述第三子像素之间沿着第一方向设置第二间距，在所述第二间距中设置第一过孔；
    所述第二子像素和所述第三子像素之间沿着第一方向设置第三间距。
  2. 根据权利要求1所述的显示基板，其特征在于，所述像素电路包括驱动管和绝缘层；所述第一子像素、所述第二子像素和所述第三子像素分别包括阳极；所述驱动管、所述绝缘层和所述阳极依次远离所述基底设置；
    所述像素电路还包括辅助电极；
    所述辅助电极包括第一导电层，所述第一导电层与所述阳极位于同一膜层上，且所述第一导电层在所述基底上的正投影与所述阳极在所述基底上的正投影互不交叠；
    所述辅助电极还包括第二导电层，所述第二导电层与所述驱动管的第一极和第二极位于同一膜层上，且所述第二导电层在所述基底上的正投影与所述驱动管的第一极和第二极在所述基底上的正投影互不交叠。
  3. 根据权利要求2所述的显示基板，其特征在于，所述像素中，所述第二子像素和所述第三子像素位于所述第一子像素的同一侧；且所述第二子像素和所述第三子像素沿第二方向排布；
    所述第一间距等于所述第二间距；
    所述第三间距小于所述第一间距。
  4. 根据权利要求3所述的显示基板，其特征在于，所述第一子像素与所述第三子像素沿第一方向排布；
    所述第一方向与所述第二方向垂直。
  5. 根据权利要求4所述的显示基板，其特征在于，所述像素中，所述第一子像素沿第二方向的尺寸等于沿第二方向所述第二子像素、所述第三子像素以及二者之间的间隔的尺寸之和；
    所述第一子像素沿第一方向的尺寸小于所述第二子像素和所述第三子像素中任意一者沿所述第一方向的尺寸。
  6. 根据权利要求5所述的显示基板，其特征在于，所述第一导电层在所述基底上的正投影位于沿所述第一方向至少部分相邻的所述像素之间的间隔区。
  7. 根据权利要求6所述的显示基板，其特征在于，所述第一导电层沿所述第二方向的尺寸等于沿所述第二方向相邻两个所述像素以及二者之间的间隔的尺寸之和；
    所述第一导电层沿所述第一方向的尺寸小于所述第一子像素沿所述第一方向的尺寸。
  8. 根据权利要求2所述的显示基板，其特征在于，所述第一间距等于所述第二间距；
    所述第三间距等于所述第一间距、所述第二间距和所述第一子像素沿第一方向的宽度之和。
  9. 根据权利要求8所述的显示基板，其特征在于，所述像素中，所述第二子像素、所述第一子像素和所述第三子像素沿第一方向依次排布。
  10. 根据权利要求9所述的显示基板，其特征在于，所述第一导电层沿所述第一方向的尺寸大于所述第一子像素与所述第二子像素沿所述第一方向的尺寸之和；或者，所述第一导电层沿所述第一方向的尺寸大于所述第一子像素与所述第三子像素沿所述第一方向的尺寸之和；
    所述第一导电层沿第二方向的尺寸小于所述第一子像素沿所述第二方向的尺寸。
  11. 根据权利要求2所述的显示基板，其特征在于，所述第一间距小于所述第二间距；
    所述第二间距等于所述第一间距、所述第二子像素沿所述第一方向的宽度与所述第三间距之和。
  12. 根据权利要求11所述的显示基板，其特征在于，所述像素中，所述第二子像素、所述第三子像素和所述第一子像素沿所述第一方向依次排布。
  13. 根据权利要求9或12所述的显示基板，其特征在于，所述像素中， 所述第一子像素沿第二方向的尺寸小于所述第二子像素和所述第三子像素中任意一者沿所述第二方向的尺寸；
    所述第一子像素沿所述第一方向的尺寸小于所述第二子像素和所述第三子像素中任意一者沿所述第一方向的尺寸；
    所述第一方向与所述第二方向垂直。
  14. 根据权利要求13所述的显示基板，其特征在于，所述第一导电层在所述基底上的正投影位于沿所述第二方向至少部分相邻所述像素之间的间隔区。
  15. 根据权利要求6、9或12所述的显示基板，其特征在于，所述第一导电层沿所述第一方向的尺寸小于所述第一间距或所述第二间距；
    所述第一导电层沿第二方向的尺寸小于所述第一子像素沿所述第二方向的尺寸。
  16. 根据权利要求4、9或12所述的显示基板，其特征在于，沿第二方向排布的任意相邻两行所述像素镜像对称；
    或者，沿所述第一方向排布的任意相邻两列所述像素镜像对称。
  17. 根据权利要求14所述的显示基板，其特征在于，所述像素阵列中，各行所述像素沿所述第二方向排布；
    各行所述像素中的所述第二子像素沿所述第二方向排布；
    各行所述像素中的所述第三子像素沿所述第二方向排布；
    各行所述像素中的所述第一子像素沿所述第二方向排布。
  18. 根据权利要求4、9或12所述的显示基板，其特征在于，所述像 素阵列中，各行所述像素沿所述第二方向排布；
    第2n+1行与第2n+2行所述像素的所述第一子像素沿所述第二方向排布；其中，n为整数，n＝0,1,2…。
  19. 根据权利要求1所述的显示基板，其特征在于，所述第一子像素为蓝色子像素；所述第二子像素为红色子像素；所述第三子像素为绿色子像素；
    或者，所述第一子像素为蓝色子像素；所述第二子像素为绿色子像素；所述第三子像素为红色子像素。
  20. 根据权利要求2所述的显示基板，其特征在于，所述第一过孔开设在所述绝缘层中，用于将所述第一子像素、所述第二子像素和所述第三子像素的所述阳极分别连接至各自所述像素电路中所述驱动管的第一极。
  21. 根据权利要求20所述的显示基板，其特征在于，所述绝缘层中还开设有第二过孔，用于将所述第一导电层连接至所述第二导电层；
    所述第二过孔在所述基底上的正投影位于沿第二方向相邻的两个所述像素之间。
  22. 根据权利要求21所述的显示基板，其特征在于，所述像素中，所述第一间距和所述第二间距的间距范围分别为7-25μm。
  23. 根据权利要求22所述的显示基板，其特征在于，所述第一过孔和所述第二过孔在第一方向上的正投影无交叠。
  24. 根据权利要求22所述的显示基板，其特征在于，所述第一过孔和 所述第二过孔在第一方向上的正投影至少部分交叠。
  25. 根据权利要求23或24所述的显示基板，其特征在于，还包括像素界定层，位于所述绝缘层背离所述基底的一侧；
    所述第一子像素、所述第二子像素和所述第三子像素分别位于所述像素界定层所界定的区域；
    所述第一子像素、所述第二子像素和所述第三子像素分别还包括发光功能层和阴极；所述发光功能层和所述阴极依次远离所述阳极设置；且所述发光功能层和所述阴极在所述基底上的正投影与所述阳极在所述基底上的正投影至少部分交叠；
    所述像素界定层在对应所述第一导电层的区域形成有开口；所述发光功能层和所述阴极还延伸至所述开口中，且所述发光功能层和所述阴极的位于所述开口以内的部分与位于所述开口以外的部分在所述开口边缘处相互断开；
    所述阴极的位于所述开口以外的部分包覆所述发光功能层在所述开口边缘处的断开边缘，且所述阴极的位于所述开口以外的部分还延伸至与所述第一导电层的至少部分边缘端面相接触。
  26. 根据权利要求25所述的显示基板，其特征在于，所述第一导电层包括沿远离所述基底方向依次叠置的第一子层、第二子层和第三子层；
    所述第一导电层的垂直于所述基底的截面形状包括“工”字型或倒梯形；
    所述阴极的位于所述开口以外的部分至少与所述第二子层和所述第三子层的边缘端面相接触。
  27. 根据权利要求19所述的显示基板，其特征在于，所述像素中，所 述第二子像素、所述第三子像素和所述第一子像素的开口率比例范围为2：2：1至3：2：1。
  28. 根据权利要求27所述的显示基板，其特征在于，所述像素中，所述第二子像素、所述第三子像素和所述第一子像素在所述基底上的正投影形状包括矩形。
  29. 根据权利要求25所述的显示基板，其特征在于，所述第一子像素、所述第二子像素和所述第三子像素分别还包括颜色转换层，位于所述阴极背离所述发光功能层的一侧；
    所述发光功能层发蓝光；
    所述颜色转换层用于对蓝光进行颜色转换。
  30. 根据权利要求29所述的显示基板，其特征在于，所述颜色转换层包括第一色转换单元、第二色转换单元和第一透射单元；
    所述第一色转换单元在所述基底上的正投影覆盖所述第二子像素在所述基底上的正投影；
    所述第二色转换单元在所述基底上的正投影覆盖所述第三子像素在所述基底上的正投影；
    所述第一透射单元在所述基底上的正投影覆盖所述第一子像素在所述基底上的正投影。
  31. 根据权利要求30所述的显示基板，其特征在于，还包括挡墙和第一黑矩阵，位于所述像素界定层背离所述基底的一侧，且所述第一黑矩阵和所述挡墙依次远离所述像素界定层设置；
    所述挡墙和所述第一黑矩阵在所述基底上的正投影与所述像素界定层 在所述基底上的正投影至少部分交叠。
  32. 根据权利要求31所述的显示基板，其特征在于，所述第一子像素、所述第二子像素和所述第三子像素分别还包括色阻层，位于所述颜色转换层背离所述基底的一侧；
    所述色阻层包括第一色阻、第二色阻和第三色阻；
    所述第一色阻在所述基底上的正投影落入所述第一色转换单元在所述基底上的正投影内；
    所述第二色阻在所述基底上的正投影落入所述第二色转换单元在所述基底上的正投影内；
    所述第三色阻在所述基底上的正投影落入所述第一透射单元在所述基底上的正投影内。
  33. 根据权利要求32所述的显示基板，其特征在于，还包括第二黑矩阵，位于所述挡墙背离所述基底的一侧；
    所述第二黑矩阵在所述基底上的正投影落入所述第一黑矩阵在所述基底上的正投影内。
  34. 根据权利要求1所述的显示基板，其特征在于，所述多个像素电路在所述基底上的正投影面积相等。
  35. 根据权利要求34所述的显示基板，其特征在于，所述第一子像素、所述第二子像素和所述第三子像素在所述基底上的正投影和与其电连接的所述像素电路在所述基底上的正投影至少部分不交叠。
  36. 根据权利要求33所述的显示基板，其特征在于，还包括第一封装 层、第二封装层和防反射层；
    所述第一封装层位于所述阴极的背离基底的一侧和颜色转换层的靠近所述阴极的一侧；
    所述第二封装层位于所述颜色转换层背离所述基底的一侧和色阻层的靠近所述颜色转换层的一侧；
    所述防反射层位于所述色阻层背离所述基底的一侧。
  37. 一种显示面板，其特征在于，包括权利要求1-36任意一项所述的显示基板。
  38. 一种显示装置，其特征在于，包括权利要求37所述的显示面板。
PCT/CN2021/102536 2021-06-25 2021-06-25 显示基板、显示面板和显示装置 WO2022267054A1 (zh)

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