WO2022267026A1 - 一种用于ldo的辅助电路、芯片系统及设备 - Google Patents

一种用于ldo的辅助电路、芯片系统及设备 Download PDF

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Publication number
WO2022267026A1
WO2022267026A1 PCT/CN2021/102450 CN2021102450W WO2022267026A1 WO 2022267026 A1 WO2022267026 A1 WO 2022267026A1 CN 2021102450 W CN2021102450 W CN 2021102450W WO 2022267026 A1 WO2022267026 A1 WO 2022267026A1
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circuit
voltage
transistor
output
ldo
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PCT/CN2021/102450
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English (en)
French (fr)
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周浩阳
潘越
布明恩
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华为技术有限公司
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Priority to PCT/CN2021/102450 priority Critical patent/WO2022267026A1/zh
Priority to CN202180097879.4A priority patent/CN117280294A/zh
Publication of WO2022267026A1 publication Critical patent/WO2022267026A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • the present application relates to the field of electronic technology, and in particular to an auxiliary circuit, chip system and equipment for an LDO.
  • LDO Low dropout regulator
  • off-chip LDO refers to the output The capacitance (usually 0.1-10 ⁇ F) is set on the LDO off-chip
  • on-chip LDO refers to the LDO whose output capacitance (usually 0-100pF) is set on-chip.
  • off-chip LDO is widely used in new memory and high-speed digital circuits because of its small output capacitance and easy integration.
  • the transient amplitude of the output voltage will have a large overshoot or undershoot.
  • the compensation circuit includes: a delay chain, a comparator, a NOT gate, a NAND gate and a transistor M0, the input end of the delay chain is coupled to the first input end of the NAND gate and is used for receiving Enable signal EN, the first output end of the delay chain is coupled to the control end of the comparator, the second output end of the delay chain is coupled to the second input end of the NAND gate through the NOT gate, the comparator
  • the two input terminals of the comparator are used to receive the reference voltage Vref and the output voltage Vout of the LDO
  • the output terminal of the comparator is coupled to the third input terminal of the NAND gate
  • the output terminal of the NAND gate is coupled to the gate of the transistor M0
  • the transistor M0 is coupled between the power supply terminal Vdd and the output terminal of the LDO, and the load of the LDO can be turned
  • the compensation process includes: S1.
  • the EN signal changes from a low level to a high level, that is, when the EN signal turns on the load of the LDO, the AND in the compensation circuit
  • the first input terminal and the third input terminal of the NAND gate are high level, and the EN signal still outputs low level after passing through the delay chain, and the second input terminal of the NAND gate is high level, thereby turning on the transistor M0 (that is, the compensation circuit is turned on);
  • the S2.EN signal turns on the comparator through the first output terminal after the first delay of the delay chain, and the comparator compares Vout and Vref; S3a.
  • Vout is greater than Vref, then The comparator outputs a low level to turn off the transistor M0 (that is, the compensation circuit is closed); S3b. If Vout is less than Vref, the EN signal changes the second input terminal of the NAND gate after the second delay of the delay chain is low level to turn off the transistor M0 (that is, the compensation circuit is turned off).
  • the compensation circuit provided above can improve the stabilization speed of the output voltage of the LDO without increasing the area and power consumption.
  • the compensation circuit changes the output terminal of the NAND gate to low by outputting a low level when the comparator detects that Vref is greater than Vout Level, and then turn off the transistor M0 through the low level, so there is a certain delay ⁇ T between the moment when Vout is greater than Vref and the moment when the compensation circuit is turned off, so that when the compensation circuit is turned off, Vout is already much greater than Vref , which in turn causes overcompensation of the Vout of the LDO, and the compensated Vout can only be slowly stabilized to Vref through the feedback adjustment of the LDO.
  • the present application provides an auxiliary circuit, a chip system and a device for an LDO, which are used to improve the stabilization speed of the output voltage of the LDO without increasing the extra area and power consumption.
  • an auxiliary circuit for a low dropout linear regulator LDO including: an LDO, a compensation circuit and a discharge circuit respectively coupled to the LDO; the LDO is used to output a first voltage, the first voltage It can also be referred to as the output voltage of the LDO; the compensation circuit is used to compensate the first voltage when the first voltage undershoots and shut down when the first voltage is detected to be greater than the first reference voltage, the first voltage Occurrence of undershoot may mean that the peak value or valley value of the first voltage V1 output by the LDO is smaller than the set output voltage range; the discharge circuit is used to reduce the first voltage when the first voltage overshoots and When it is detected that the first voltage is lower than the second reference voltage, it is turned off.
  • the first reference voltage can be greater than or equal to the second reference voltage.
  • the overshoot of the first voltage can mean that the peak value or valley value of the first voltage output by the LDO is greater than the setting output voltage range.
  • the compensation circuit when the LDO is powered on or the external load changes, if the first voltage output by the LDO undershoots, the compensation circuit can be used to compensate the first voltage and detect that the first voltage is greater than the first reference
  • the discharge circuit can be used to discharge through the first voltage to reduce the first voltage, and it will be turned off when it detects that the first voltage V1 is less than the second reference voltage Vref, so that
  • This solution does not need to increase the output capacitance of the LDO, and the compensation circuit and the discharge circuit only work during the overshoot and undershoot of the first voltage, which can effectively reduce the The transient amplitude of the first voltage when overshoot and undershoot occurs, and the response speed of the LDO are improved, thereby increasing the stabilization speed of the first voltage.
  • the discharge circuit can also increase the recovery speed after the first voltage compensation by reducing the first voltage.
  • the compensation circuit can also compensate the first voltage to increase the recovery speed of the first voltage after discharge, thereby further improving the first voltage. Stabilize the speed while also improving the accuracy of the first voltage.
  • the compensation circuit is coupled to the discharge circuit; the compensation circuit is further configured to turn on the discharge circuit when it is detected that the first voltage is greater than the first reference voltage.
  • the compensation circuit can also turn on the discharge circuit, which can Open the discharge circuit while closing the compensation circuit, so that the discharge circuit can reduce the overcompensation of the compensation circuit to the first voltage, that is, when there is overcompensation, the first voltage can be reduced by the discharge circuit in time to increase the first voltage
  • the recovery speed after compensation is used to further improve the stabilization speed of the first voltage, and also improve the accuracy of the first voltage.
  • the compensation circuit is coupled to the discharge circuit; the discharge circuit is further configured to turn on the compensation circuit when it is detected that the first voltage is lower than the second reference voltage.
  • the discharge circuit can also turn on the compensation circuit, so that The compensation circuit can be turned on while the discharge circuit is closed, so that the compensation circuit can compensate the over-discharge of the first voltage by the discharge circuit, that is, when there is over-discharge, the first voltage can be compensated by the compensation circuit in time to increase the first voltage discharge
  • the final recovery speed is used to further increase the stabilization speed of the first voltage, and also improve the accuracy of the first voltage.
  • the compensation circuit includes a pull-up circuit and a first detector; the pull-up circuit is configured to compensate the first voltage when the first voltage undershoots; the The first detector is used for closing the pull-up circuit when detecting that the first voltage is greater than the first reference voltage.
  • the pull-up circuit when the LDO is powered on or the external load changes, if the first voltage output by the LDO undershoots, the pull-up circuit can be used to compensate the first voltage, and the first detector When it is detected that the first voltage is greater than the first reference voltage, the pull-up circuit is turned off, so that the transient amplitude of the first voltage when an undershoot occurs can be effectively reduced without excessively increasing additional area and power consumption, and Improve the response speed of LDO.
  • the discharge circuit includes a pull-down circuit and a second detector; the pull-down circuit is configured to reduce the first voltage when the first voltage overshoots; the second The second detector is used to close the pull-down circuit when detecting that the first voltage is lower than the second reference voltage.
  • the pull-down circuit can be used to reduce the first voltage and detect that the first voltage is lower than the first voltage when the second detector detects The second reference voltage is turned off, thereby effectively reducing the transient amplitude of the first voltage when an undershoot occurs and improving the response speed of the LDO without increasing the extra area and power consumption too much.
  • the pull-up circuit includes: a first delay circuit, a first NAND gate, a first transistor, and a second transistor; wherein, the input terminal of the first delay circuit Coupled with the first input end of the first NAND gate and used to receive a clock signal, the output end of the first delay circuit is used to output the first control signal, and the second input end of the first NAND gate is used for Receive the first comparison signal, one pole of the first transistor is coupled to the power supply terminal, the other pole of the first transistor is coupled to one pole of the second transistor, the other pole of the second transistor is coupled to the pull-up circuit Between the output terminals, the control terminal of the first transistor is coupled to the output terminal of the first NAND gate, and the control terminal of the second transistor is used to receive a bias voltage; the first detector includes: a first comparator; Wherein, the control terminal of the first comparator is used to receive the first control signal, the two input terminals of the first comparator are used to receive the first voltage and the first reference voltage respectively
  • a simple and effective pull-down circuit and a second comparator are provided, through which the first voltage output by the LDO can be overshot to reduce the first voltage, and It is turned off when it is detected that the first voltage is lower than the first reference voltage, so as to effectively reduce the transient amplitude when the first voltage overshoots, and improve the response speed of the LDO, thereby increasing the stabilization speed of the first voltage.
  • the pull-up circuit further includes a second delay circuit and a first NOT gate, the input end of the second delay circuit is coupled to the output end of the first delay circuit , the output terminal of the second delay circuit is coupled to the third input terminal of the first NAND gate through the first NOT gate.
  • the pull-down circuit includes: a third delay circuit, a second NAND gate, a second NOT gate, a third NOT gate, and a third transistor; wherein, the third delay
  • the input terminal of the timing circuit is used to receive the clock signal
  • the output terminal of the third delay circuit is coupled to the first input terminal of the second NAND gate
  • the second input terminal of the second NAND gate is used to receive the first input terminal of the second NAND gate.
  • the second detector includes: Two comparators; wherein, the control terminal of the second comparator is used to receive the second control signal, and the two input terminals of the second comparator are respectively used to receive the first voltage and the second reference voltage, and the second The output terminal of the comparator is used to output the second comparison signal.
  • a simple and effective pull-down circuit and a second comparator are provided, through which the first voltage output by the LDO can be overshot to reduce the first voltage, and It is turned off when it is detected that the first voltage is lower than the second reference voltage, so as to effectively reduce the transient amplitude when the first voltage overshoots, and improve the response speed of the LDO, thereby increasing the stabilization speed of the first voltage.
  • the first switch signal is a signal generated by an output terminal of the first NAND gate.
  • the discharge circuit is turned on while the compensation circuit is turned off, so that when there is overcompensation, the first voltage can be reduced by the discharge circuit to improve the recovery speed after the first voltage compensation, so as to further improve the first voltage.
  • the stabilization speed of the voltage also improves the accuracy of the first voltage.
  • the third input terminal of the second NAND gate is used to receive the first control signal. In the foregoing possible implementation manner, it can be ensured that the pull-down circuit and the second detector are turned off after discharging the first voltage, thereby reducing power consumption of the pull-down circuit and the second detector.
  • the pull-down circuit includes: a fourth delay circuit, a third NAND gate, a fourth NOT gate, and a fourth transistor; wherein, the input terminal of the fourth delay circuit Coupled with the first input end of the third NAND gate and used to receive the clock signal, the output end of the fourth delay circuit is used to output the third control signal, and the second input end of the third NAND gate is used for receiving the third comparison signal, the output terminal of the third NAND gate is coupled to the control terminal of the fourth transistor through the fourth NOT gate, and the fourth transistor is coupled between the input terminal of the pull-down circuit and the ground terminal; the The second detector includes: a third comparator; wherein, the control terminal of the third comparator is used to receive the third control signal, and the two input terminals of the third comparator are respectively used to receive the first voltage and the first voltage.
  • the output terminal of the third comparator is used to output the third comparison signal.
  • a simple and effective pull-up circuit and a first comparator are provided, through the pull-up circuit and the first comparator, the first voltage output by the LDO can be undershooted to compensate for the first voltage, And it is turned off when it is detected that the first voltage is greater than the second reference voltage, so as to effectively reduce the transient amplitude when the first voltage undershoots, and improve the response speed of the LDO, thereby increasing the stabilization speed of the first voltage.
  • the pull-down circuit further includes a fifth delay circuit and a fifth NOT gate, the input end of the fifth delay circuit is coupled to the output end of the fourth delay circuit, The output terminal of the fifth delay circuit is coupled with the third input terminal of the third NAND gate through the fifth NOT gate.
  • the pull-up circuit includes: a sixth delay circuit, a fourth NAND gate, a sixth NOT gate, a fifth transistor, and a sixth transistor; wherein, the sixth delay circuit
  • the input terminal of the timing circuit is used to receive the clock signal
  • the output terminal of the sixth delay circuit is coupled to the first input terminal of the fourth NAND gate
  • the second input terminal of the fourth NAND gate is used to receive the first input terminal of the fourth NAND gate.
  • the output terminal of the fourth NAND gate is coupled to the input terminal of the sixth NAND gate, the output terminal of the sixth NAND gate is used to output the fourth control signal, and one pole of the fifth transistor is connected to the power supply terminal coupling, the other pole of the fifth transistor is coupled to one pole of the sixth transistor, between the other pole of the sixth transistor and the output terminal of the pull-up circuit, the control terminal of the fifth transistor is used to receive the first Four comparison signals, the control terminal of the sixth transistor is used to receive the bias voltage;
  • the first detector includes: a fourth comparator; wherein, the control terminal of the fourth comparator is used to receive the fourth control signal, the The two input terminals of the fourth comparator are respectively used to receive the first voltage and the first reference voltage, and the output terminal of the fourth comparator is used to output the fourth comparison signal.
  • a simple and effective pull-down circuit and a second comparator are provided, through which the first voltage output by the LDO can be overshot to reduce the first voltage, and It is turned off when it is detected that the first voltage is lower than the first reference voltage, so as to effectively reduce the transient amplitude when the first voltage overshoots, and improve the response speed of the LDO, thereby increasing the stabilization speed of the first voltage.
  • the second switch signal is a signal generated by an output terminal of the third NAND gate.
  • the discharge circuit is turned on while the compensation circuit is turned off, so that when there is overcompensation, the first voltage can be reduced by the discharge circuit to improve the recovery speed after the first voltage compensation, so as to further improve the first voltage.
  • the stabilization speed of the voltage also improves the accuracy of the first voltage.
  • the third input terminal of the fourth NAND gate is used to receive the third control signal. In the foregoing possible implementation manner, it can be ensured that the pull-up circuit and the first detector are turned off after compensating for the undershooted first voltage, thereby reducing power consumption of the pull-up circuit and the first detector.
  • a chip system in a second aspect, includes a load, and an auxiliary circuit for a low-dropout linear regulator LDO according to any one of claims 1-14; wherein the auxiliary circuit includes LDO, and a compensation circuit and a discharge circuit coupled with the LDO, the LDO is used to supply power to the load, and the compensation circuit and the discharge circuit are used to increase the stabilization speed of the first voltage output by the LDO.
  • an electronic device in a third aspect, includes a load and a circuit board, and the circuit board includes the LDO for a low-dropout linear regulator provided in the first aspect or any possible implementation of the first aspect.
  • An auxiliary circuit wherein, the auxiliary circuit includes an LDO, and a compensation circuit and a discharge circuit coupled to the LDO, the LDO is used to supply power to the load, and the compensation circuit and the discharge circuit are used to increase the first output voltage of the LDO stable speed.
  • the chip system and electronic equipment provided above all include the auxiliary circuit for the low dropout linear regulator LDO provided above, therefore, the beneficial effects that it can achieve can refer to the above provided for The beneficial effect in the auxiliary circuit of the low dropout linear regulator LDO will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a compensation circuit applied to an LDO provided in the prior art
  • Fig. 2 is the working flow diagram of a kind of compensation circuit that prior art provides
  • FIG. 3 is a schematic circuit diagram of an LDO provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of adjusting the output voltage Vout provided by the embodiment of the present application.
  • FIG. 5 is a relationship diagram between an output voltage and a stable speed of Vout provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an auxiliary circuit for an LDO provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another auxiliary circuit for an LDO provided in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another auxiliary circuit for LDO provided by the embodiment of the present application.
  • FIG. 9 is a timing diagram of different signals used in an auxiliary circuit of an LDO provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of fluctuations when the first voltage V1 undershoots according to the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another auxiliary circuit for LDO provided by the embodiment of the present application.
  • FIG. 12 is a timing diagram of different signals in an auxiliary circuit for an LDO provided by an embodiment of the present application.
  • circuits or other components may be described or referred to as “operating" to perform one or more tasks.
  • "for” is used to imply structure by indicating that a circuit/component includes structure (eg, circuitry) that performs one or more tasks during operation. Accordingly, even when the specified circuit/component is not currently operational (eg, not turned on), the circuit/component may be said to be used to perform the task.
  • a circuit/component used with the phrase “for” includes hardware, such as a circuit to perform an operation, and the like.
  • At least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.
  • words such as "first" and "second” do not limit the quantity and order.
  • the transistors involved in the embodiments of the present application may be metal oxide semiconductor (metal oxide semiconductor, MOS) field effect transistors (may be referred to as MOS transistors for short).
  • MOS metal oxide semiconductor
  • the control terminal of the transistor may refer to the gate of the transistor; in a possible embodiment, one pole of the transistor may refer to the source, and the other pole may refer to the drain; in another possibility In the embodiment, one terminal of the transistor may be referred to as the drain, and the other terminal may be referred to as the source.
  • the low dropout regulator can usually be divided into off-chip (off-chip) LDO and on-chip (on-chip) LDO.
  • the off-chip LDO is Refers to the LDO whose output capacitor (usually 0.1-10 ⁇ F) is set off-chip
  • the on-chip LDO refers to the LDO whose output capacitor (usually 0-100pF) is set on-chip.
  • on-chip LDO has the characteristics of small output capacitance and easy integration, so it is widely used in various subsystems or systems that require high stability of the output voltage of LDO, such as new memories and high-speed digital circuits. .
  • the new memory may include magnetic random access memory (MRAM), phase change memory (phase change memory, PCM) and resistance random access memory (resistance random access memory, RRAM), etc.
  • the high-speed digital circuit may include Chip system (system of chip, SoC) and digital phase-locked loop (phase loop lock, PLL), etc.
  • FIG. 3 is a schematic circuit diagram of an LDO provided by an embodiment of the present application.
  • the LDO may include: an error amplifier (error amplifier, EA), a transistor M0, a feedback circuit, and an output capacitor C.
  • the feedback circuit includes a first resistor R1 and a first resistor R1. Two resistors R2.
  • the output terminal of the error amplifier EA is coupled to the control terminal of the transistor M0 (ie, the gate of the PMOS).
  • One terminal of the transistor M0 (for example, the source of the PMOS) is coupled to the power terminal (Vdd).
  • the other pole of the transistor M0 (for example, the drain of the PMOS) is used as the output terminal of the LDO, and is coupled with the input terminal of the feedback circuit at the same time.
  • the output terminal of the feedback circuit is coupled to the positive input terminal of the error amplifier EA, the negative input terminal of the error amplifier EA is used to receive the reference voltage Vref, and the output capacitor C is coupled between the output terminal of the LDO and the ground terminal GND.
  • the output voltage Vout of the LDO will have an overshoot or undershoot phenomenon.
  • the feedback circuit controls Vout through the first resistor R1 and the second resistor R2 Sampling is performed, and the sampled feedback voltage Vfb is transmitted to the positive-phase input terminal of the error amplifier EA; the error amplifier EA compares and amplifies the feedback voltage Vfb and the Vref received by the negative-phase input terminal, and the amplified voltage is used as the transistor M0
  • the gate voltage Vg of the gate voltage Vg dynamically adjusts Vout by changing the conduction current Ip flowing through the transistor M0, so as to realize the regulated output of the LDO.
  • Vfb decreases, and the decrease of Vfb will cause Vg to decrease.
  • Vg decreases, the current Ip increases, thereby increasing Vout;
  • Vfb increases, and the increase of Vfb will cause Vg to increase.
  • the current Ip decreases, thereby reducing Vout.
  • the transient amplitude when the output voltage Vout of the LDO appears to overshoot or undershoot mainly depends on the size of the output capacitor C, as shown in Figure 5, when the output capacitor C is a large capacitor (for example, the capacitance value is 0.1-10 ⁇ F ) when the transient amplitude of Vout changes small, when the output capacitor C is a small capacitor (for example, the capacitance value is 0 to 100pF), the transient amplitude of Vout changes greatly, that is, when the load changes with a small output capacitor C Will cause Vout to stabilize at a slower rate.
  • the response speed of the LDO will also affect the stabilization speed of Vout. When the response speed is faster, the stabilization speed of Vout will also increase.
  • the embodiment of the present application provides an auxiliary circuit for LDO, which is used to ensure that when the LDO is powered on or the external load changes, its output voltage can quickly recover after a small overshoot or undershoot Stabilization, that is, increasing the stabilization speed of the output voltage of the LDO without increasing additional area and power consumption.
  • FIG. 6 is a schematic structural diagram of an auxiliary circuit for an LDO provided by an embodiment of the present application.
  • the auxiliary circuit includes: LDO1, a compensation circuit 2 and a discharge circuit 3 coupled to LDO1.
  • the LDO1 is used to output a first voltage V1.
  • the first voltage V1 may refer to a voltage used by the LDO1 to supply power to various devices, subsystems or systems using the LDO1.
  • the first voltage V1 may also be referred to as an output voltage of the LDO1.
  • LDO1 is the LDO shown in FIG. 3
  • the first voltage V1 is the output voltage Vout shown in FIG. 3 .
  • the first voltage V1 may be the voltage used by LDO1 to supply power to the new memory.
  • the compensation circuit 2 is configured to compensate the first voltage V1 when the first voltage V1 undershoots, and shut down when it is detected that the first voltage V1 is greater than the first reference voltage.
  • the undershoot of the first voltage V1 may mean that the peak value or the valley value of the first voltage V1 output by the LDO1 is smaller than the set output voltage range.
  • the discharge circuit 3 is configured to reduce the first voltage V1 when the first voltage V1 overshoots and shut down when it is detected that the first voltage V1 is lower than the second reference voltage.
  • the overshoot of the first voltage V1 may mean that the peak value or the valley value of the first voltage V1 output by the LDO1 is greater than the set output voltage range.
  • the first reference voltage may be greater than or equal to the second reference voltage, and the following description will be made by taking the first reference voltage equal to the second reference voltage and denoted as Vref as an example.
  • the compensation circuit 2 can be used to compensate the first voltage V1 and detect that when the first voltage V1 is greater than the reference
  • the discharge circuit 3 can be used to discharge through the first voltage to reduce the first voltage V1, and turn off when it is detected that the first voltage V1 is lower than the reference voltage Vref .
  • the compensation circuit 2 and the discharge circuit 3 only work during the overshoot and undershoot of the first voltage V1, so that the additional area and power consumption can not be increased too much
  • the transient amplitude of the first voltage V1 when overshooting and undershooting occurs is effectively reduced, and the response speed of the LDO1 is improved, thereby increasing the stabilization speed of the first voltage V1.
  • the discharge circuit 3 can also reduce the first voltage V1 to increase the first voltage V1 after compensation.
  • the compensation circuit 2 can also compensate the first voltage V1 to increase the first voltage V1 after discharge recovery speed, thereby further improving the stabilization speed of the first voltage V1, and also improving the accuracy of the first voltage V1.
  • the compensation circuit 2 and the discharge circuit 3 may be coupled.
  • the compensation circuit 2 can also be used to turn on the discharge circuit 3 ; and/or, the discharge circuit 3 can also be used to turn on the compensation circuit 2 .
  • the compensation circuit 2 is also used to: when it is detected that the first voltage V1 is greater than the reference voltage Vref, turn on the discharge circuit 3; and/or, the discharge circuit 3 is also used to: when the first voltage V1 is detected to be lower than the reference voltage Vref When the voltage Vref is reached, the compensation circuit 2 is turned on.
  • the compensation circuit 2 may also Turn on the discharge circuit 3, so that the discharge circuit 3 can be turned on while the compensation circuit 2 is closed, so that the discharge circuit 3 can reduce the overcompensation of the compensation circuit 2 to the first voltage V1, that is, it can pass through in time when there is overcompensation.
  • the discharge circuit 3 reduces the first voltage V1 to increase the recovery speed of the first voltage V1 after compensation, so as to further increase the stabilization speed of the first voltage V1 and also improve the accuracy of the first voltage V1.
  • the discharge circuit 3 when the first voltage V1 output by the LDO1 overshoots, and the discharge circuit 3 detects that the first voltage V1 is lower than the reference voltage Vref during the process of reducing the first voltage V1, the discharge circuit 3
  • the compensation circuit 2 can also be turned on, so that the compensation circuit 2 can be turned on while the discharge circuit 3 is turned off, so that the compensation circuit 2 can compensate the over-discharge of the discharge circuit 3 to the first voltage V1, that is, when there is an over-discharge, it can be timely
  • the compensation circuit 2 compensates the first voltage V1 to increase the recovery speed of the first voltage V1 after discharge, so as to further increase the stabilization speed of the first voltage V1 and also improve the accuracy of the first voltage V1.
  • the compensation circuit 2 may include a pull-up circuit 21 and a first detector 22
  • the discharge circuit 3 may include: a pull-down circuit 31 and a second detector 32 .
  • the pull-up circuit 21 can be used to compensate the first voltage V1 when the first voltage V1 undershoots; the first detector 22 can be used to turn off the pull-up circuit when it detects that the first voltage V1 is greater than the reference voltage Vref. Pull circuit 21 to turn off compensation circuit 2 .
  • the pull-down circuit 31 can be used to reduce the first voltage V1 when the first voltage V1 overshoots; the second detector 32 can be used to turn off the pull-down when the first voltage V1 is detected to be lower than the reference voltage Vref circuit 31 to close the discharge circuit 3.
  • the pull-up circuit 21 in the compensation circuit 2 can be used to turn on the pull-down circuit in the discharge circuit 3.
  • the discharge circuit 3 when the discharge circuit 3 is also used to turn on the compensation circuit 2, specifically, it can be realized by turning on the pull-up circuit 21 in the compensation circuit 2 by the pull-down circuit 31 in the discharge circuit 3 .
  • auxiliary circuit for LDO The specific structure of the auxiliary circuit for LDO provided above is described below, that is, the pull-up circuit 21, the first detector 22, the pull-down circuit 31 and the second detection circuit in the auxiliary circuit for LDO The structure of the device 32 is described.
  • Fig. 8 is a schematic structural diagram of an auxiliary circuit for an LDO provided by an embodiment of the present application.
  • the auxiliary circuit can be used to compensate the first voltage V1 when the first voltage V1 undershoots, and the first voltage V1 appears after compensation. When overshooting, the first voltage V1 is reduced.
  • the pull-up circuit 21 may include: a first delay circuit 211 , a first NAND gate 212 , a first transistor M1 and a second transistor M2 .
  • the input end of the first delay circuit 211 is coupled with the first input end of the first NAND gate 212 and is used to receive the clock signal CLK (the clock signal CLK can be the clock signal for the load operation of LDO1), the first delay circuit
  • the output terminal of 211 is used to output the first control signal SC1
  • the second input terminal of the first NAND gate 212 is used to receive the first comparison signal SM1
  • one pole of the first transistor M1 is coupled to the power supply terminal Vdd
  • the other pole of the second transistor M2 is coupled to one pole of the second transistor M2, and the other pole of the second transistor M2 is coupled to the output terminal of the pull-up circuit 21, and the output terminal of the pull-up circuit 21 is used to couple with the output terminal of the LDO1.
  • the control terminal of the transistor M1 and the output terminal of the first NAND gate 212 are coupled to the first node P1, and the control terminal of the second transistor M2 is used to receive a bias voltage VB, which is lower than the power supply terminal Vdd and the second transistor M2.
  • the difference between the turn-on voltage Vth of M2 (that is, VB ⁇ Vdd-Vth), the turn-on voltage Vth can be a voltage between 0.4V and 0.7V.
  • the first detector 22 may include a first comparator CMP1, the control terminal of the first comparator CMP1 is used to receive the first control signal SC1, and the two input terminals of the first comparator CMP1 are respectively used to receive the first voltage V1 and the The reference voltage Vref, the output terminal of the first comparator CMP1 is used to output the first comparison signal SM1.
  • the pull-up circuit 21 may also include a second delay circuit 213 and a first NAND gate 214, the first NAND gate 212 also includes a third input terminal, and the input terminal of the second delay circuit 213 is connected to the first delay circuit 214.
  • the output terminal of the time delay circuit 211 is coupled, and the output terminal of the second delay circuit 213 is coupled with the third input terminal of the first NAND gate 212 through the first NOT gate 214 .
  • the pull-up circuit 21 and the first detector 22 can be used to compensate the first voltage V1, and the specific process may include: when the first voltage V1 undershoots, the clock signal CLK is high level, that is, the first input terminal of the first NAND gate 212 receives a high level, and at this time the second input terminal of the first NAND gate 212 is a preset high level, so that the output of the first NAND gate 212 terminal outputs low level, that is, the signal of the first node P1 is low level; when the signal of the first node P1 is low level, the first transistor M1 and the second transistor M2 are turned on, because the first transistor M1 and the power supply Terminal Vdd is coupled, so that the first voltage V1 is pulled high, that is, compensation for the first voltage V1 is realized; when the high level of the clock signal CLK is delayed by the first delay circuit 211, the first comparator CMP1 The controller receives a high level, that is, the first control signal SC
  • the pull-up circuit 21 also includes a second delay circuit 213 and a first NAND gate 214
  • the first NAND gate 212 also includes a third input terminal
  • the pull-up circuit 21 is not closed during the above process, the After the high level of the clock signal CLK is delayed by the first delay circuit 211 and the second delay circuit 213 in sequence, the first NOT gate 214 receives the high level and outputs a low level, so that the first NAND gate
  • the third input terminal of 212 receives a low level, so that the output terminal of the first NAND gate 212 outputs a high level, that is, the signal of the first node P1 is high level, and then the first transistor M1 and the second transistor M2 are off, so that the pull-up circuit 21 is turned off.
  • the pull-down circuit 31 may include: a third delay circuit 311, a second NAND gate 312, a second NOT gate 313, a third NOT gate 314 and a third delay circuit 311. Three transistors M3.
  • the input terminal of the third delay circuit 311 is used to receive the clock signal CLK
  • the output terminal of the third delay circuit 311 is coupled with the first input terminal of the second NAND gate 312
  • the second input terminal of the second NAND gate 312 terminal is used to receive the first switch signal SW1
  • the output terminal of the second NAND gate 312 is coupled to the input terminal of the second NOT gate 313
  • the output terminal of the second NOT gate 313 is used to output the second control signal SC2
  • the third NAND gate 313 is used to output the second control signal SC2.
  • the input terminal of the gate 314 is used to receive the second comparison signal SM2, the output terminal of the third NOT gate 314 and the control terminal of the third transistor M3 are coupled to the second node P2, and the third transistor M3 is coupled to the input terminal of the pull-down circuit 31 and Between the ground terminals, the input terminal of the pull-down circuit 31 is used to couple with the output terminal of LDO1.
  • the second detector 32 may include a second comparator CMP2, the control terminal of the second comparator CMP2 is used to receive the second control signal SC2, and the two input terminals of the second comparator CMP2 are respectively used to receive the first voltage V1 and the The reference voltage Vref, the output terminal of the second comparator CMP2 is used to output the second comparison signal SM2.
  • the first switch signal SW1 may be a signal generated by the output terminal of the first NAND gate 212 , that is, the first switch signal SW1 may be a signal of the first node P1 .
  • the second NAND gate 312 further includes a third input terminal, and the third input terminal of the second NAND gate 312 is used for receiving the first control signal SC1.
  • the pull-down circuit 31 and the second detector 32 can be used to reduce the first voltage V1, and the specific process may include: the clock signal CLK is still high after passing through the third delay circuit 311 Level, the first input terminal of the second NAND gate 312 receives a high level, when the first switch signal SW1 is high level, the second input terminal of the second NAND gate 312 receives a high level, so that the first The output terminal of two NAND gates 312 outputs a low level; the second NOT gate 313 receives the low level and outputs a high level, that is, the controller of the second comparator CMP2 receives a high level, so that the second comparator CMP2 is turned on; when the second comparator CMP2 detects that the first voltage V1 is greater than the reference voltage Vref (that is, detects that the first voltage V1 has an overshoot after compensation), it outputs a low level; the low level is passed through the third NOT gate After 314, it is
  • the third transistor M3 Since the third transistor M3 is coupled to the ground terminal GND, Therefore, the first voltage V1 is pulled down, that is, the first voltage V1 is reduced, so as to improve the recovery speed when the first voltage V1 is compensated and the overshoot occurs; when the clock signal CLK is delayed by the third delay circuit 311, it is When the level is low, the first input terminal of the second NAND gate 312 receives a low level, so that the output terminal of the second NAND gate 312 outputs a high level. According to the above-mentioned similar logic, it can be known that the third transistor M3 is off, that is, the pull-down circuit 31 is turned off.
  • the third input terminal of the second NAND gate 312 can receive the first control signal SC1, and the first control signal SC1 is the clock signal CLK passed through the second input terminal.
  • a signal behind the delay circuit 211 if the clock signal CLK is low level (that is, the auxiliary circuit is not working), the third input terminal of the second NAND gate 312 is not working in the auxiliary circuit, and the first delay
  • the circuit 211 receives a low level within the delay, so that the output terminal of the second NAND gate 312 outputs a high level.
  • the third transistor M3 is turned off at this time, that is, the pull-down circuit 31 is turned off , so that the discharge circuit 3 can be prevented from being turned on in advance, so that the loss of power consumption can be further reduced.
  • the first transistor M1 and the second transistor M2 are PMOS transistors
  • the third transistor M3 is an NMOS transistor for illustration; in practical applications, the first transistor M1, the second transistor M2 and the third transistor M3 are
  • the three transistors M3 can also be replaced with other transistors with similar functions, which is not specifically limited in the present application.
  • FIG. 9 shows a timing diagram of different signals in the auxiliary circuit for the LDO provided in FIG. 8 above.
  • the different signals may include: the clock signal CLK, the first control signal SC1, the first comparison signal SM1, the second The delay signal SD2 (ie the output signal of the second delay circuit 213), the first switch signal SW1, the first voltage V1, the third delay signal SD3 (ie the output signal of the third delay circuit 311), the second control A timing diagram of the signal SC2 and the second switching signal SW2.
  • the first switch signal SW1 when the clock signal CLK changes from low level to high level, the first voltage V1 undershoots; at time t2, when the first switch signal SW1 changes from high level to low level, M1 Turn on (to compensate for the first voltage V1); at time t3, the first control signal SC1 changes from low level to high level; at time t4, when it is detected that the first voltage V1 is greater than the reference voltage Vref, the first switch The signal SW1 is changed from low level to high level (that is, M1 is closed), the second control signal SC2 is changed from low level to high level (for turning on the second comparator CMP2 after M1 is closed), and then the second switch The signal SW2 is converted from a low level to a high level (that is, M3 is turned on); the second delay signal SD2 is converted from a high level to a low level after the time t4 (for closing M1 that may not be closed before); the third The delay signal SD3 is converted from high level to low level (for starting the closing of C
  • FIG. 10 shows a schematic diagram of fluctuations when the first voltage V1 emits an undershoot, and the curve L1 is obtained after the first voltage V1 is compensated by the compensation circuit 2 shown in FIG. 8 above.
  • the fluctuation curve of the first voltage V1 is the fluctuation curve of the first voltage V1 when the first voltage V1 is not compensated.
  • the compensation circuit 2 compensates the first voltage V1, which can reduce the transient variation range of the first voltage V1, thereby increasing the stabilization speed of the first voltage V1.
  • the discharge circuit 3 reduces the first voltage V1, which can increase the stabilization speed of the first voltage V1 after compensation, thereby further improving the response speed of the LDO1 and the first voltage V1 the accuracy.
  • FIG. 11 is a schematic structural diagram of another auxiliary circuit for LDO provided by the embodiment of the present application.
  • the auxiliary circuit can be used to reduce the first voltage V1 when the first voltage V1 overshoots, and to discharge the first voltage V1. When an undershoot occurs later, the first voltage V1 is compensated.
  • the pull-down circuit 31 may include: a fourth delay circuit 315 , a third NAND gate 316 , a fourth NOT gate 317 and a fourth transistor M4 .
  • the input end of the fourth delay circuit 315 is coupled to the first input end of the third NAND gate 316 and used to receive the clock signal CLK, the output end of the fourth delay circuit 315 is used to output the third control signal SC3, and the third delay circuit 315 is used to output the third control signal SC3.
  • the second input terminal of the NAND gate 316 is used to receive the third comparison signal SM3, the output terminal of the third NAND gate 316 is coupled to the third node P3 through the fourth NOT gate 317 and the control terminal of the fourth transistor M4, and the fourth The transistor M4 is coupled between the input terminal of the pull-down circuit 31 and the ground terminal GND, and the coupling point between the output terminal of the third NAND gate 316 and the input terminal of the fourth NOT gate 317 is denoted as Q.
  • the second detector 32 may include: a third comparator CMP3, the control terminal of the third comparator CMP3 is used to receive the third control signal SC3, and the two input terminals of the third comparator CMP3 are respectively used to receive the first voltage V1 and The reference voltage Vref, the output terminal of the third comparator CMP3 is used to output the third comparison signal SM3.
  • the pull-down circuit 31 may also include a fifth delay circuit 318 and a fifth NOT gate 319, the input end of the fifth delay circuit 318 is coupled to the output end of the fourth delay circuit 315, and the fifth delay circuit The output terminal of 318 is coupled with the third input terminal of the third NAND gate 316 through the fifth NOT gate 319 .
  • the pull-down circuit 31 and the second detector 32 can be used to reduce the first voltage V1, and the specific process may include: when the first voltage V1 undershoots, the clock signal CLK is high level, that is, the first input terminal of the third NAND gate 316 receives a high level, and at this time the second input terminal of the third NAND gate 316 is a preset high level, so that the output of the third NAND gate 316 terminal outputs a low level, the low level is high level after passing through the fourth NOT gate 317, that is, the signal of the third node P3 is high level; when the signal of the third node P3 is high level, the fourth transistor M4 is turned on, because the fourth transistor M4 is coupled to the ground terminal, the first voltage V1 is pulled down, that is, the reduction of the first voltage V1 is realized; when the high level of the clock signal CLK passes through the fourth delay circuit 315 After a time delay, the control terminal of the third comparator CMP3 receives
  • the pull-down circuit 31 also includes a fifth delay circuit 318 and a fifth NOT gate 319
  • the third NAND gate 316 also includes a third input terminal
  • the pull-down circuit 31 is not closed during the above process, the clock signal After the high level of CLK is delayed by the fourth delay circuit 315 and the fifth delay circuit 318 in turn, the fifth NOT gate 319 receives a high level and outputs a low level, so that the third NAND gate 316
  • the third input terminal receives a low level, and the output terminal of the third NAND gate 316 outputs a high level, so that the signal of the third node P3 is converted to a low level, so that the fourth transistor M4 is turned off, that is, the pull-down circuit 31 is closed.
  • the pull-up circuit 21 may include: a sixth delay circuit 215, a fourth NAND gate 216, a sixth NAND gate 217, a fifth transistor M5 and a sixth transistor M5. Six transistors M6.
  • the input terminal of the sixth delay circuit 215 is used to receive the clock signal CLK, the output terminal of the sixth delay circuit 215 is coupled with the first input terminal of the fourth NAND gate 216, and the second input terminal of the fourth NAND gate 216 terminal is used to receive the inverted signal SW3' of the third switching signal SW3, the output terminal of the fourth NAND gate 216 is coupled to the input terminal of the sixth NOT gate 217, and the output terminal of the sixth NOT gate 217 is used to output the fourth control Signal SC4, one pole of the fifth transistor M5 is coupled to the power supply terminal Vdd, the other pole of the fifth transistor M5 is coupled to one pole of the sixth transistor M6, and the other pole of the sixth transistor M6 is coupled to the output terminal of the pull-up circuit 21 Coupling, the output terminal of the pull-up circuit 21 is used for coupling with the output terminal of LDO1, the control terminal of the fifth transistor M5 is used for receiving the fourth comparison signal SM4, and the control terminal of the sixth transistor M6 is used for receiving the bias voltage VB.
  • the first detector 22 may include a fourth comparator CMP4, the control terminal of the fourth comparator CMP4 is used to receive the fourth control signal SC4, and the two input terminals of the fourth comparator CMP4 are respectively used to receive the first voltage V1 and the The reference voltage Vref, the output terminal of the fourth comparator CMP4 is used to output the fourth comparison signal SM4.
  • the third switching signal SW3 may be the signal output by the fourth NOT gate 317
  • the inverted signal SW3' of the third switching signal SW3 may be the signal generated by the output terminal of the third NAND gate 316, that is, the inverted signal SW3 ' can be the signal of coupling point Q.
  • the fourth NAND gate 216 further includes a third input terminal, and the third input terminal of the fourth NAND gate 216 is used for receiving the third control signal SC3.
  • the pull-up circuit 21 and the first detector 22 can be used to compensate the first voltage V1, and the specific process may include: the clock signal CLK is still High level, that is, the first input terminal of the fourth NAND gate 216 is high level, when the inversion signal SW3' of the third switch signal SW3 is high level, the second input terminal of the fourth NAND gate 216 receives to a high level, so that the output terminal of the fourth NAND gate 216 outputs a low level; the sixth NOT gate 217 receives the low level and outputs a high level (the fourth control signal SC4 is a high level), that is, the fourth The control end of comparator CMP4 receives high level, thereby the 4th comparator CMP4 is turned on; When the 4th comparator CMP4 detects that first voltage V1 is less than this reference voltage Vref (promptly detects that first voltage V1 reduces and occurs Undershoot) outputs low level, that is, the fourth comparison signal
  • the fifth The transistor M5 is turned off, that is, the pull-up circuit 21 is turned off.
  • the fourth NAND gate 216 also includes a third input terminal
  • the third input terminal of the fourth NAND gate 216 can receive the third control signal SC3, and the third control signal SC3 is the clock signal CLK passed through the first The signal after four time-delay circuit 315 delays, if this clock signal CLK is low level (that is this auxiliary circuit is not working), the 3rd input end of the 4th NAND gate 216 is not working in this auxiliary circuit, and the 4th
  • the delay circuit 315 receives a low level
  • the output terminal of the fourth NAND gate 216 outputs a high level
  • the high level is converted to a low level after passing through the sixth NOT gate 217, that is, the fourth control signal SC4 is at a low level, so that the fourth comparator CMP4 is turned off and outputs a high level.
  • the fifth transistor M5 is turned off at this time, that is, the pull-up circuit 21 is turned off, so that the compensation circuit can be avoided. 2 is turned on in advance, so that the loss of power consumption can be further reduced.
  • the fourth transistor M4 and the fifth transistor M5 are PMOS transistors, and the sixth transistor M6 is an NMOS transistor for illustration; in practical applications, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M5
  • the six transistors M6 can also be replaced with other transistors with similar functions, which is not specifically limited in the present application.
  • FIG. 12 shows a timing diagram of different signals in the auxiliary circuit for the LDO provided in FIG. 11 above.
  • the different signals may include: the clock signal CLK, the third control signal SC3, the third comparison signal SM3, the fifth The delay signal SD5 (ie the output signal of the fifth delay circuit 318), the third switch signal SW3, the inversion signal SW3' of the third switch signal SW3, the first voltage V1, the sixth delay signal SD6 (ie the sixth The timing diagram of the output signal of the delay circuit 215), the fourth control signal SC4 and the fourth comparison signal SM4.
  • the first voltage V1 overshoots; at time t2, when the third switch signal SW3 changes from low level to high level, M4 Turn on (to reduce the first voltage V1); at time t3, the third control signal SC3 changes from low level to high level; at time t4, when it is detected that the first voltage V1 is less than the reference voltage Vref, the third The switch signal SW3 is converted from a high level to a low level (that is, M4 is closed), and the fourth control signal SC4 is converted from a high level to a low level (for turning on the fourth comparator CMP4 after M4 is closed), and then the fourth The comparison signal SM4 is converted from a high level to a low level (that is, M5 is turned on); the fifth delay signal SD5 is converted from a high level to a low level after the t4 moment (for closing M4 that may not be closed before); The six-delay signal SD6 is converted from a
  • the compensation circuit 2 when LDO1 is powered on or the external load changes, if the first voltage V1 output by LDO1 undershoots, the compensation circuit 2 can be used to compensate the first voltage V1 and detect the first When the voltage V1 is greater than the reference voltage Vref, it is turned off. If the first voltage V1 output by the LDO1 overshoots, the discharge circuit 3 can be used to discharge through the first voltage to reduce the first voltage V1, and when it is detected that the first voltage V1 is lower than the reference voltage Vref is off.
  • the compensation circuit 2 and the discharge circuit 3 only work during the overshoot and undershoot of the first voltage V1, so that the additional area and power consumption can not be increased too much
  • the transient amplitude of the first voltage V1 when overshooting and undershooting occurs is effectively reduced, and the response speed of the LDO1 is improved, thereby increasing the stabilization speed of the first voltage V1.
  • the discharge circuit 3 can also reduce the first voltage V1 to increase the first voltage V1 after compensation.
  • the compensation circuit 2 can also compensate the first voltage V1 to increase the first voltage V1 after discharge recovery speed, thereby further improving the stabilization speed of the first voltage V1, and also improving the accuracy of the first voltage V1.
  • the embodiment of the present application also provides a chip system, the chip system includes a load and an auxiliary circuit for the LDO, the auxiliary circuit for the LDO can be any of the auxiliary circuits for the LDO provided above ;
  • the auxiliary circuit for LDO includes LDO, and a compensation circuit and a discharge circuit coupled with the LDO, the LDO is used to supply power to the load, and the compensation circuit and the discharge circuit are used to improve the first output of the LDO Voltage stabilization speed.
  • the embodiment of the present application also provides an electronic device, the electronic device includes a load and a circuit board, the circuit board includes any auxiliary circuit for the LDO provided above, the auxiliary circuit for the LDO includes an LDO, and A compensation circuit and a discharge circuit coupled with the LDO, the LDO is used to supply power to the load, and the compensation circuit and the discharge circuit are used to increase the stabilization speed of the first voltage output by the LDO.
  • auxiliary circuit for the LDO can be referred to the system-on-a-chip and the electronic device, and the embodiments of the present application will not repeat them here.

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Abstract

本申请提供一种用于LDO的辅助电路、芯片系统及设备，涉及电子技术领域，于在不过多增加额外的面积和功耗的同时，提高LDO的输出电压的稳定速度。所述用于LDO的辅助电路包括：LDO、以及分别与所述LDO耦合的补偿电路和放电电路；所述LDO，用于输出第一电压；所述补偿电路，用于在所述第一电压发生下冲时，补偿所述第一电压并在检测到所述第一电压大于第一参考电压时关闭；所述放电电路，用于在所述第一电压发生上冲时，减小所述第一电压并在检测到所述第一电压小于第二参考电压时关闭。

Description

一种用于LDO的辅助电路、芯片系统及设备 技术领域
本申请涉及电子技术领域，尤其涉及一种用于LDO的辅助电路、芯片系统及设备。
背景技术
低压差线性稳压器(low dropout regulator，LDO)作为电源管理系统的核心模块之一，通常可以分为片外(off-chip)LDO和片上(on-chip)LDO，片外LDO是指输出电容(通常为0.1～10μF)设置在片外的LDO，片上LDO是指输出电容(通常为0～100pF)设置在片上的LDO。片上LDO与片外LDO相比，由于具有输出电容小且易集成的特点，从而被广泛应用在新型存储器和高速数字电路中。目前，在片上LDO的应用过程中，当片上LDO的外部负载发生变化时，由于片上LDO的输出电容较小，其输出电压的瞬态幅度会出现较大的上冲或下冲。
现有技术中提供了一种应用于LDO的补偿电路，可用于在外部负载发生变化时提高LDO的输出电压的稳定速度。如图1所示，该补偿电路包括：延时链、比较器、非门、与非门和晶体管M0，该延时链的输入端和该与非门的第一输入端耦合且用于接收使能信号EN，该延时链的第一输出端和比较器的控制端耦合，该延时链的第二输出端通过该非门与该与非门的第二输入端耦合，该比较器的两个输入端用于接收参考电压Vref和LDO的输出电压Vout，该比较器的输出端与该与非门的第三输入端耦合，该与非门的输出端与晶体管M0的栅极耦合，该晶体管M0耦合在电源端Vdd与LDO的输出端之间，LDO的负载可通过使能信号EN开启。具体的，如图2中的(a)所示，该补偿过程包括：S1.当EN信号由低电平转换为高电平，即该EN信号开启LDO的负载时，该补偿电路中该与非门的第一输入端和第三输入端为高电平，该EN信号经过延时链后仍输出低电平，该与非门的第二输入端为高电平，从而导通晶体管M0(即该补偿电路开启)；S2.EN信号经过该延时链的第一段延时后通过第一输出端开启该比较器，该比较器比较Vout与Vref；S3a.若Vout大于Vref，则该比较器输出低电平以关断晶体管M0(即该补偿电路关闭)；S3b.若Vout小于Vref，EN信号经过该延时链的第二段延时后将该与非门的第二输入端变为低电平，以关断晶体管M0(即该补偿电路关闭)。
上述提供的补偿电路，能够在不增加较大面积和功耗的前提下，提高LDO的输出电压的稳定速度。但是，如图2中的(b)所示，该补偿电路在补偿Vout的过程中，是在该比较器检测到Vref大于Vout时通过输出低电平将该与非门的输出端变为低电平，再通过该低电平关闭晶体管M0来关闭的，从而在Vout大于Vref的时刻与该补偿电路关闭的时刻之间存在一定的延时ΔT，使得该补偿电路关闭时Vout已经远大于Vref，进而造成对该LDO的Vout的过度补偿，补偿之后的Vout只能通过LDO的反馈调节缓慢稳定至Vref。
发明内容
本申请提供一种用于LDO的辅助电路、芯片系统及设备，用于在不过多增加额外的面积和功耗的同时，提高LDO的输出电压的稳定速度。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种用于低压差线性稳压器LDO的辅助电路，包括：LDO、以及分别与该LDO耦合的补偿电路和放电电路；该LDO，用于输出第一电压，第一电压也可以称为该LDO的输出电压；该补偿电路，用于在该第一电压发生下冲时，补偿该第一电压并在检测到该第一电压大于第一参考电压时关闭，第一电压发生下冲可以是指LDO输出的第一电压V1的峰值或谷值小于设定的输出电压范围；该放电电路，用于在该第一电压发生上冲时，减小该第一电压并在检测到该第一电压小于第二参考电压时关闭，第一参考电压可以大于或等于第二参考电压，第一电压发生上冲可以是指LDO输出的第一电压的峰值或谷值大于设定的输出电压范围。
上述技术方案中，当LDO在上电过程、或者在外部负载发生变化时，若LDO输出的第一电压发生下冲，补偿电路可用于补偿第一电压并在检测到第一电压大于第一参考电压时关闭，若LDO输出的第一电压V1发生上冲，放电电路可用于通过第一电压放电以减小第一电压，并在检测到第一电压V1小于第二参考电压Vref时关闭，从而该方案无需增大LDO的输出电容，且补偿电路和放电电路仅在第一电压发生上冲和下冲的过程中工作，从而可以在不过多增加额外的面积和功耗的同时，有效减小第一电压在出现上冲和下冲时的瞬态幅度、以及提高LDO的响应速度，从而提高第一电压的稳定速度。此外，当补偿电路对发生下冲的第一电压存在过度补偿导致第一电压补偿后出现上冲时，放电电路还可以通过减小第一电压来提高第一电压补偿后的恢复速度，当放电电路对发生上冲的第一电压存在过度放电导致第一电压放电后出现下冲时，补偿电路还可以通过补偿第一电压来提高第一电压放电后的恢复速度，从而进一步提高第一电压的稳定速度，同时也提高了第一电压的精确度。
在第一方面的一种可能的实现方式中，该补偿电路和该放电电路相耦合；该补偿电路，还用于在检测到该第一电压大于第一参考电压时，开启该放电电路。上述可能的实现方式中，当LDO输出的第一电压发生下冲，补偿电路在补偿第一电压的过程中检测到第一电压大于第一参考电压时，补偿电路还可以开启放电电路，这样可以在关闭补偿电路的同时开启放电电路，以使放电电路能够将补偿电路对第一电压的过度补偿进行减小，即当存在过度补偿时可以及时通过放电电路减小第一电压来提高第一电压补偿后的恢复速度，以进一步提高第一电压的稳定速度，同时也提高了第一电压的精确度。
在第一方面的一种可能的实现方式中，该补偿电路和该放电电路相耦合；该放电电路，还用于在检测到该第一电压小于第二参考电压时，开启该补偿电路。上述可能的实现方式中，当LDO输出的第一电压发生上冲，放电电路在减小第一电压的过程中检测到第一电压小于第二参考电压时，放电电路还可以开启补偿电路，这样可以在关闭放电电路的同时开启补偿电路，以使补偿电路能够将放电电路对第一电压的过度放电进行补偿，即当存在过度放电时可以及时通过补偿电路补偿第一电压来提高第一电压放电后的恢复速度，以进一步提高第一电压的稳定速度，同时也提高了第一电压的精确度。
在第一方面的一种可能的实现方式中，该补偿电路包括上拉电路和第一检测器；该上拉电路，用于在该第一电压发生下冲时，补偿该第一电压；该第一检测器，用于在检测到该第一电压大于第一参考电压时关闭该上拉电路。上述可能的实现方式中，当LDO在上电过程、或者在外部负载发生变化时，若LDO输出的第一电压发生下冲，该上拉电路可用于补偿第一电压，并在第一检测器检测到该第一电压大于第一参考电压时关闭该上拉 电路，从而可以在不过多增加额外的面积和功耗的同时，有效减小第一电压在出现下冲时的瞬态幅度、以及提高LDO的响应速度。
在第一方面的一种可能的实现方式中，该放电电路包括下拉电路和第二检测器；该下拉电路，用于在该第一电压发生上冲时，减小该第一电压；该第二检测器，用于在检测到该第一电压小于第二参考电压时关闭该下拉电路。上述可能的实现方式中，当LDO在外部负载发生变化时，若LDO输出的第一电压发生上冲，该下拉电路可用于减小第一电压并在第二检测器检测到第一电压小于第二参考电压时关闭，从而可以在不过多增加额外的面积和功耗的同时，有效减小第一电压在出现下冲时的瞬态幅度、以及提高LDO的响应速度。
在第一方面的一种可能的实现方式中，该上拉电路包括：第一延时电路、第一与非门、第一晶体管和第二晶体管；其中，该第一延时电路的输入端和该第一与非门的第一输入端耦合且用于接收时钟信号，该第一延时电路的输出端用于输出第一控制信号，该第一与非门的第二输入端用于接收第一比较信号，该第一晶体管的一极与电源端耦合，该第一晶体管的另一极与该第二晶体管的一极耦合，该第二晶体管的另一极与该上拉电路的输出端之间，该第一晶体管的控制端和该第一与非门的输出端耦合，该第二晶体管的控制端用于接收偏置电压；该第一检测器包括：第一比较器；其中，该第一比较器的控制端用于接收该第一控制信号，该第一比较器的两个输入端分别用于接收该第一电压和第一参考电压，该第一比较器的输出端用于输出该第一比较信号。上述可能的实现方式中，提供了一种简单有效的下拉电路和第二比较器，通过该下拉电路和该第二比较器可以在LDO输出的第一电压发生上冲减小第一电压，并在检测到第一电压小于第一参考电压时关闭，从而能够有效减小第一电压出现上冲时的瞬态幅度、以及提高LDO的响应速度，从而提高第一电压的稳定速度。
在第一方面的一种可能的实现方式中，该上拉电路还包括第二延时电路和第一非门，该第二延时电路的输入端与该第一延时电路的输出端耦合，该第二延时电路的输出端通过该第一非门与该第一与非门的第三输入端耦合。上述可能的实现方式中，能够保证该上拉电路和第一检测器在对发生下冲的第一电压补偿后关闭，从而减小该上拉电路和第一检测器的功耗。
在第一方面的一种可能的实现方式中，该下拉电路包括：第三延时电路、第二与非门、第二非门、第三非门和第三晶体管；其中，该第三延时电路的输入端用于接收该时钟信号，该第三延时电路的输出端与该第二与非门的第一输入端耦合，该第二与非门的第二输入端用于接收第一开关信号，该第二与非门的输出端与该第二非门的输入端耦合，该第二非门的输出端用于输出第二控制信号，该第三非门的输入端用于接收第二比较信号，该第三非门的输出端与该第三晶体管的控制端耦合，该第三晶体管耦合在该下拉电路的输入端与接地端之间；该第二检测器包括：第二比较器；其中，该第二比较器的控制端用于接收该第二控制信号，该第二比较器的两个输入端分别用于接收该第一电压和第二参考电压，该第二比较器的输出端用于输出该第二比较信号。上述可能的实现方式中，提供了一种简单有效的下拉电路和第二比较器，通过该下拉电路和该第二比较器可以在LDO输出的第一电压发生上冲减小第一电压，并在检测到第一电压小于第二参考电压时关闭，从而能够有效减小第一电压出现上冲时的瞬态幅度、以及提高LDO的响应速度，从而提高第 一电压的稳定速度。
在第一方面的一种可能的实现方式中，该第一开关信号为该第一与非门的输出端产生的信号。上述可能的实现方式中，能够保证在关闭补偿电路的同时开启放电电路，从而当存在过度补偿时可以通过放电电路减小第一电压来提高第一电压补偿后的恢复速度，以进一步提高第一电压的稳定速度，同时也提高了第一电压的精确度。
在第一方面的一种可能的实现方式中，该第二与非门的第三输入端用于接收该第一控制信号。上述可能的实现方式中，能够保证该下拉电路和第二检测器在对进行第一电压放电后关闭，从而减小该下拉电路和第二检测器的功耗。
在第一方面的一种可能的实现方式中，该下拉电路包括：第四延时电路、第三与非门、第四非门和第四晶体管；其中，该第四延时电路的输入端和该第三与非门的第一输入端耦合且用于接收时钟信号，该第四延时电路的输出端用于输出第三控制信号，该第三与非门的第二输入端用于接收第三比较信号，该第三与非门的输出端通过该第四非门与该第四晶体管的控制端耦合，该第四晶体管耦合在该下拉电路的输入端与接地端之间；该第二检测器包括：第三比较器；其中，该第三比较器的控制端用于接收该第三控制信号，该第三比较器的两个输入端分别用于接收该第一电压和第二参考电压，该第三比较器的输出端用于输出该第三比较信号。上述可能的实现方式中，提供了一种简单有效的上拉电路和第一比较器，通过该上拉电路和该第一比较器可以在LDO输出的第一电压发生下冲补偿第一电压，并在检测到第一电压大于第二参考电压时关闭，从而能够有效减小第一电压出现下冲时的瞬态幅度、以及提高LDO的响应速度，从而提高第一电压的稳定速度。
在第一方面的一种可能的实现方式中，该下拉电路还包括第五延时电路和第五非门，该第五延时电路的输入端与该第四延时电路的输出端耦合，该第五延时电路的输出端通过该第五非门与该第三与非门的第三输入端耦合。上述可能的实现方式中，能够保证该下拉电路和第二检测器在对进行第一电压放电后关闭，从而减小该下拉电路和第二检测器的功耗。
在第一方面的一种可能的实现方式中，该上拉电路包括：第六延时电路、第四与非门、第六非门、第五晶体管和第六晶体管；其中，该第六延时电路的输入端用于接收该时钟信号，该第六延时电路的输出端与该第四与非门的第一输入端耦合，该第四与非门的第二输入端用于接收第二开关信号，该第四与非门的输出端与该第六非门的输入端耦合，该第六非门的输出端用于输出第四控制信号，该第五晶体管的一极与电源端耦合，该第五晶体管的另一极与该第六晶体管的一极耦合，该第六晶体管的另一极与该上拉电路的输出端之间，该第五晶体管的控制端用于接收第四比较信号，该第六晶体管的控制端用于接收偏置电压；该第一检测器包括：第四比较器；其中，该第四比较器的控制端用于接收该第四控制信号，该第四比较器的两个输入端分别用于接收该第一电压和第一参考电压，该第四比较器的输出端用于输出该第四比较信号。上述可能的实现方式中，提供了一种简单有效的下拉电路和第二比较器，通过该下拉电路和该第二比较器可以在LDO输出的第一电压发生上冲减小第一电压，并在检测到第一电压小于第一参考电压时关闭，从而能够有效减小第一电压出现上冲时的瞬态幅度、以及提高LDO的响应速度，从而提高第一电压的稳定速度。
在第一方面的一种可能的实现方式中，该第二开关信号为该第三与非门的输出端产 生的信号。上述可能的实现方式中，能够保证在关闭补偿电路的同时开启放电电路，从而当存在过度补偿时可以通过放电电路减小第一电压来提高第一电压补偿后的恢复速度，以进一步提高第一电压的稳定速度，同时也提高了第一电压的精确度。
在第一方面的一种可能的实现方式中，该第四与非门的第三输入端用于接收该第三控制信号。上述可能的实现方式中，能够保证该上拉电路和第一检测器在对发生下冲的第一电压补偿后关闭，从而减小该上拉电路和第一检测器的功耗。
第二方面，提供一种芯片系统，其特征在于，该芯片系统包括负载、以及权利要求1-14任一项该的用于低压差线性稳压器LDO的辅助电路；其中，该辅助电路包括LDO、以及与该LDO耦合的补偿电路和放电电路，该LDO用于为该负载供电，该补偿电路和该放电电路用于提高该LDO输出的第一电压的稳定速度。
第三方面，提供一种电子设备，该电子设备包括负载和电路板，该电路板包括第一方面或者第一方面的任一种可能的实现方式所提供的用于低压差线性稳压器LDO的辅助电路；其中，该辅助电路包括LDO、以及与该LDO耦合的补偿电路和放电电路，该LDO用于为该负载供电，该补偿电路和该放电电路用于提高该LDO输出的第一电压的稳定速度。
可以理解地，上述提供的芯片系统和电子设备均包括上文所提供的用于低压差线性稳压器LDO的辅助电路，因此，其所能达到的有益效果可参考上文所提供的用于低压差线性稳压器LDO的辅助电路中的有益效果，此处不再赘述。
附图说明
图1为现有技术提供的一种应用于LDO的补偿电路的结构示意图；
图2为现有技术提供的一种补偿电路的工作流程图；
图3为本申请实施例提供的一种LDO的电路示意图；
图4为本申请实施例提供的一种调节输出电压Vout的示意图；
图5为本申请实施例提供的一种输出电压与Vout的稳定速度的关系图；
图6为本申请实施例提供的一种用于LDO的辅助电路的结构示意图；
图7为本申请实施例提供的另一种用于LDO的辅助电路的结构示意图；
图8为本申请实施例提供的又一种用于LDO的辅助电路的结构示意图；
图9为本申请实施例提供的一种用于LDO的辅助电路中的不同信号的时序图；
图10为本申请实施例提供的一种第一电压V1发出下冲时的波动示意图；
图11为本申请实施例提供的另一种用于LDO的辅助电路的结构示意图；
图12为本申请实施例提供的一种用于LDO的辅助电路中的不同信号的时序图。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。
各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路系统)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组 件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
另外，本申请实施例中所涉及的晶体管可以是金属氧化物半导体(metal oxide semiconductor，MOS)场效应晶体管(可以简称为MOS管)。本申请实施例中晶体管的控制端可以是指晶体管的栅极；在一种可能的实施例中，晶体管的一极可以是指源极，另一极可以是指漏极；在另一种可能的实施例中，晶体管的一极可以是指漏极，另一极可以是指源极。
目前，低压差线性稳压器(low dropout regulator，LDO)作为电源管理系统的核心模块之一，通常可以分为片外(off-chip)LDO和片上(on-chip)LDO，片外LDO是指输出电容(通常为0.1～10μF)设置在片外的LDO，片上LDO是指输出电容(通常为0～100pF)设置在片上的LDO。片上LDO与片外LDO相比，由于具有输出电容小且易集成的特点，从而被广泛应用在新型存储器和高速数字电路中等对LDO的输出电压的稳定速度要求高的各种子系统或者系统中。比如，该新型存储器可以包括磁性随机存储器(magnetic random access memory，MRAM)、相变存储器(phase change memory，PCM)和阻变随机存储器(resistance random access memory，RRAM)等，该高速数字电路可以包括芯片系统(system of chip，SoC)和数字锁相环(phase loop lock，PLL)等。
图3为本申请实施例提供的一种LDO的电路示意图，该LDO可以包括：误差放大器(error amplifier，EA)、晶体管M0、反馈电路和输出电容C，该反馈电路包括第一电阻R1和第二电阻R2。其中，以晶体管M0为PMOS管为例，误差放大器EA的输出端与晶体管M0的控制端(即PMOS的栅极)耦合。晶体管M0的一极(比如，PMOS的源极)与电源端(Vdd)耦合。晶体管M0的另一极(比如，PMOS的漏极)作为该LDO的输出端，同时与该反馈电路的输入端相耦合。该反馈电路的输出端与误差放大器EA的正相输入端耦合，误差放大器EA的负相输入端用于接收参考电压Vref，输出电容C耦合在该LDO的输出端与接地端GND之间。
具体的，当该LDO在上电或者后级负载发生变化时，该LDO的输出电压Vout会出现上冲或下冲的现象，此时该反馈电路通过第一电阻R1和第二电阻R2对Vout进行采样， 并将采样到的反馈电压Vfb传输至误差放大器EA的正相输入端；误差放大器EA对该反馈电压Vfb和负相输入端接收的Vref进行比较并放大，放大后的电压作为晶体管M0的栅极电压Vg，该栅极电压Vg通过改变流过晶体管M0的导通电流Ip来动态的调整Vout，以实现该LDO的稳压输出。示例性的，如图4中的(a)所示，当Vout减小时Vfb减小，Vfb的减小会引起Vg减小，随着Vg的减小电流Ip增大，从而增大Vout；如图4中的(b)所示，当Vout增大时Vfb增大，Vfb的增大会引起Vg增大，随着Vg的增大电流Ip减小，从而减小Vout。
其中，该LDO的输出电压Vout出现上冲或下冲时的瞬态幅度主要取决于输出电容C的大小，如图5所示，当输出电容C为大电容(比如，容值为0.1～10μF)时Vout的瞬态幅度变化较小，当输出电容C为小电容(比如，容值为0～100pF)时Vout的瞬态幅度变化较大，即较小的输出电容C在负载发生变化时会导致Vout的稳定速度较慢。此外，该LDO的响应速度也会影响Vout的稳定速度，当响应速度越快时Vout的稳定速度也会提高，这种情况下往往需要增加误差放大器EA的输出电流，以提高晶体管M0的充放电速度。因此，在LDO的应用过程中，为了提高LDO在外部负载发生变化时的Vout的稳定速度，通常需要增大输出电容C(此时会增加面积)或者采用一些辅助电路来提高体管M0的充放电速度。但是，在将该LDO应用于新型存储器和高速数字电路中时，需要该LDO的Vout具有较小的上冲或下冲后能够快速地恢复稳定，同时不增加额外的面积，因此大都采用辅助电路的方式来提高该LDO的Vout的稳定速度。
基于此，本申请实施例提供一种用于LDO的辅助电路，用于保证该LDO在上电或者外部负载发生变化时，其输出电压在出现较小的上冲或下冲后能够快速地恢复稳定，即提高该LDO的输出电压的稳定速度，同时不增加额外的面积和功耗。
图6为本申请实施例提供的一种用于LDO的辅助电路的结构示意图，如图6所示，该辅助电路包括：LDO1、以及与LDO1耦合的补偿电路2和放电电路3。
LDO1，用于输出第一电压V1，第一电压V1可以是指LDO1用于为应用LDO1的各种器件、子系统或者系统供电的电压，第一电压V1也可以称为LDO1的输出电压。比如，LDO1为图3所示的LDO，第一电压V1为图3所示的输出电压Vout，将LDO1应用于新型存储器时第一电压V1可以是LDO1用于为该新型存储器供电的电压。
补偿电路2，用于在第一电压V1发生下冲时，补偿第一电压V1并在检测到第一电压V1大于第一参考电压时关闭。其中，第一电压V1发生下冲可以是指LDO1输出的第一电压V1的峰值或谷值小于设定的输出电压范围。
放电电路3，用于在第一电压V1发生上冲时，减小第一电压V1并在检测到第一电压V1小于第二参考电压时关闭。其中，第一电压V1发生上冲可以是指LDO1输出的第一电压V1的峰值或谷值大于设定的输出电压范围。在使用应用中，第一参考电压可以大于或等于第二参考电压，下文中以第一参考电压等于第二参考电压且表示为Vref为例进行说明。
具体的，当LDO1在上电过程、或者在外部负载发生变化时，若LDO1输出的第一电压V1发生下冲，补偿电路2可用于补偿第一电压V1并检测到在第一电压V1大于参考电压Vref时关闭，若LDO1输出的第一电压V1发生上冲，放电电路3可用于通过第一电压放电以减小第一电压V1，并在检测到第一电压V1小于该参考电压Vref时关闭。上述技 术方案中，无需增大LDO1的输出电容，且补偿电路2和放电电路3仅在第一电压V1发生上冲和下冲的过程中工作，从而可以在不过多增加额外的面积和功耗的同时，有效减小第一电压V1在出现上冲和下冲时的瞬态幅度、以及提高LDO1的响应速度，从而提高第一电压V1的稳定速度。此外，当补偿电路2对发生下冲的第一电压V1存在过度补偿导致第一电压补偿后出现上冲时，放电电路3还可以通过减小第一电压V1来提高第一电压V1补偿后的恢复速度，当放电电路3对发生上冲的第一电压V1存在过度放电导致第一电压V1放电后出现下冲时，补偿电路2还可以通过补偿第一电压V1来提高第一电压V1放电后的恢复速度，从而进一步提高第一电压V1的稳定速度，同时也提高了第一电压V1的精确度。
可选的，补偿电路2和放电电路3可以相耦合。补偿电路2还可用于开启放电电路3；和/或，放电电路3还可用于开启补偿电路2。
具体的，补偿电路2还用于：在检测到第一电压V1大于该参考电压Vref时，开启放电电路3；和/或，放电电路3还用于：在检测到第一电压V1小于该参考电压Vref时，开启补偿电路2。
在一种可能的实施例中，当LDO1输出的第一电压V1发生下冲，补偿电路2在补偿第一电压V1的过程中检测到第一电压V1大于参考电压Vref时，补偿电路2还可以开启放电电路3，这样可以在关闭补偿电路2的同时开启放电电路3，以使放电电路3能够将补偿电路2对第一电压V1的过度补偿进行减小，即当存在过度补偿时可以及时通过放电电路3减小第一电压V1来提高第一电压V1补偿后的恢复速度，以进一步提高第一电压V1的稳定速度，同时也提高了第一电压V1的精确度。
在另一种可能的实施例中，当LDO1输出的第一电压V1发生上冲，放电电路3在减小第一电压V1的过程中检测到第一电压V1小于参考电压Vref时，放电电路3还可以开启补偿电路2，这样可以在关闭放电电路3的同时开启补偿电路2，以使补偿电路2能够将放电电路3对第一电压V1的过度放电进行补偿，即当存在过度放电时可以及时通过补偿电路2补偿第一电压V1来提高第一电压V1放电后的恢复速度，以进一步提高第一电压V1的稳定速度，同时也提高了第一电压V1的精确度。
进一步的，如图7所示，补偿电路2可以包括上拉电路21和第一检测器22，放电电路3可以包括：下拉电路31和第二检测器32。在补偿电路2中，上拉电路21可用于在第一电压V1发生下冲时，补偿第一电压V1；第一检测器22可用于在检测到第一电压V1大于该参考电压Vref时关闭上拉电路21，以关闭补偿电路2。在放电电路3中，下拉电路31可用于在第一电压V1发生上冲时，减小第一电压V1；第二检测器32可用于在检测到第一电压V1小于该参考电压Vref时关闭下拉电路31，以关闭放电电路3。
在图7所示的用于LDO的辅助电路的结构下，当补偿电路2还用于开启放电电路3时，具体可以由补偿电路2中的上拉电路21通过开启放电电路3中的下拉电路31来实现，当放电电路3还用于开启补偿电路2时，具体可以由放电电路3中的下拉电路31通过开启补偿电路2中的上拉电路21来实现。
下面对上文中所提供的用于LDO的辅助电路的具体结构进行介绍说明，即对该用于LDO的辅助电路中的上拉电路21、第一检测器22、下拉电路31和第二检测器32的结构进行介绍说明。
图8为本申请实施例提供的一种用于LDO的辅助电路的结构示意图，该辅助电路可用于在第一电压V1发生下冲时补偿第一电压V1，以及在第一电压V1补偿后出现上冲时减小第一电压V1。
在一种示例中，如图8中的(a)所示，上拉电路21可以包括：第一延时电路211、第一与非门212、第一晶体管M1和第二晶体管M2。第一延时电路211的输入端和第一与非门212的第一输入端耦合且用于接收时钟信号CLK(该时钟信号CLK可以为LDO1的负载工作的时钟信号)，第一延时电路211的输出端用于输出第一控制信号SC1，第一与非门212的第二输入端用于接收第一比较信号SM1，第一晶体管M1的一极耦合于电源端Vdd，第一晶体管M1的另一极与第二晶体管M2的一极耦合，第二晶体管M2的另一极耦合于上拉电路21的输出端，上拉电路21的输出端用于与LDO1的输出端耦合，第一晶体管M1的控制端和第一与非门212的输出端耦合于第一节点P1，第二晶体管M2的控制端用于接收偏置电压VB，该偏置电压VB小于电源端Vdd与第二晶体管M2的导通电压Vth的差值(即VB＜Vdd-Vth)，该导通电压Vth可以为0.4V至0.7V之间的电压。第一检测器22可以包括第一比较器CMP1，第一比较器CMP1的控制端用于接收第一控制信号SC1，第一比较器CMP1的两个输入端分别用于接收第一电压V1和该参考电压Vref，第一比较器CMP1的输出端用于输出第一比较信号SM1。
可选的，上拉电路21还可以包括第二延时电路213和第一非门214，第一与非门212还包括第三输入端，第二延时电路213的输入端与第一延时电路211的输出端耦合，第二延时电路213的输出端通过第一非门214与第一与非门212的第三输入端耦合。
当第一电压V1发生下冲时，上拉电路21和第一检测器22可用于补偿第一电压V1，具体过程可以包括：当第一电压V1发生下冲时，该时钟信号CLK为高电平，即第一与非门212的第一输入端接收到高电平，此时第一与非门212的第二输入端为预置的高电平，从而第一与非门212的输出端输出低电平，即第一节点P1的信号为低电平；当第一节点P1的信号为低电平时，第一晶体管M1和第二晶体管M2被导通，由于第一晶体管M1与电源端Vdd耦合，从而第一电压V1被拉高，即实现对第一电压V1的补偿；当该时钟信号CLK的高电平经过第一延时电路211的延时后，第一比较器CMP1的控制器接收到高电平，即第一控制信号SC1为高电平，从而第一比较器CMP1被开启；当第一比较器CMP1检测到第一电压V1大于该参考电压Vref时输出低电平，即第一与非门212的第二输入端接收到低电平，从而第一与非门212的输出端由低电平转换为高电平，即第一节点P1的信号由低电平转换为高电平；当第一节点P1的信号为高电平时，第一晶体管M1和第二晶体管M2被关断，从而上拉电路21被关闭。进一步的，当上拉电路21还包括第二延时电路213和第一非门214，第一与非门212还包括第三输入端时，若上拉电路21在上述过程中未关闭，该时钟信号CLK的高电平在依次经过第一延时电路211和第二延时电路213的延时后，第一非门214接收到高电平并输出低电平，从而第一与非门212的第三输入端接收到低电平，从而第一与非门212的输出端输出高电平，即第一节点P1的信号为高电平，进而第一晶体管M1和第二晶体管M2被关断，从而上拉电路21被关闭。
在一种示例中，如图8中的(b)所示，下拉电路31可以包括：第三延时电路311、第二与非门312、第二非门313、第三非门314和第三晶体管M3。第三延时电路311的输入端用于接收该时钟信号CLK，第三延时电路311的输出端与第二与非门312的第一输入 端耦合，第二与非门312的第二输入端用于接收第一开关信号SW1，第二与非门312的输出端与第二非门313的输入端耦合，第二非门313的输出端用于输出第二控制信号SC2，第三非门314的输入端用于接收第二比较信号SM2，第三非门314的输出端与第三晶体管M3的控制端耦合于第二节点P2，第三晶体管M3耦合在下拉电路31的输入端与接地端之间，下拉电路31的输入端用于与LDO1的输出端耦合。第二检测器32可以包括第二比较器CMP2，第二比较器CMP2的控制端用于接收第二控制信号SC2，第二比较器CMP2的两个输入端分别用于接收第一电压V1和该参考电压Vref，第二比较器CMP2的输出端用于输出第二比较信号SM2。其中，第一开关信号SW1可以为第一与非门212的输出端产生的信号，即第一开关信号SW1可以为第一节点P1的信号。
可选的，第二与非门312还包括第三输入端，第二与非门312的第三输入端用于接收第一控制信号SC1。
在第一电压V1补偿后出现上冲时，下拉电路31和第二检测器32可用于减小第一电压V1，具体过程可以包括：该时钟信号CLK经过第三延时电路311后仍为高电平，第二与非门312的第一输入端接收到高电平，当第一开关信号SW1为高电平时，第二与非门312的第二输入端接收到高电平，从而第二与非门312的输出端输出低电平；第二非门313接收该低电平并输出高电平，即第二比较器CMP2的控制器接收到高电平，从而第二比较器CMP2被开启；当第二比较器CMP2检测到第一电压V1大于该参考电压Vref(即检测到第一电压V1补偿后出现上冲)时输出低电平；该低电平在通过第三非门314后转换为高电平，即第二节点P2的信号(可以称为第二开关信号SW2)为高电平，从而第三晶体管M3被导通，由于第三晶体管M3与接地端GND耦合，从而第一电压V1被拉低，即减小第一电压V1，以提高第一电压V1补偿后出现上冲时的恢复速度；当该时钟信号CLK经过第三延时电路311的延时后为低电平时，第二与非门312的第一输入端接收到低电平，从而第二与非门312的输出端输出高电平，根据上述类似的逻辑可知，此时第三晶体管M3被关断，即下拉电路31被关闭。进一步的，当第二与非门312还包括第三输入端时，第二与非门312的第三输入端可接收到第一控制信号SC1，第一控制信号SC1是该时钟信号CLK经过第一延时电路211后的信号，若该时钟信号CLK为低电平(即该辅助电路未工作)，第二与非门312的第三输入端在该辅助电路未工作、以及第一延时电路211的延时内接收到低电平，从而第二与非门312的输出端输出高电平，根据上述类似的逻辑可知，此时第三晶体管M3被关断，即下拉电路31被关闭，这样可以避免放电电路3提前开启，从而可以进一步降低功耗的损失。
需要说明的是，图8中以第一晶体管M1和第二晶体管M2为PMOS管、第三晶体管M3为NMOS管为例进行说明；在实际应用中，第一晶体管M1、第二晶体管M2和第三晶体管M3还可以替换为具有类似功能的其他晶体管，本申请对此不作具体限制。
图9示出了上述图8所提供的用于LDO的辅助电路中的不同信号的时序图，该不同信号可以包括：该时钟信号CLK、第一控制信号SC1、第一比较信号SM1、第二延时信号SD2(即第二延时电路213的输出信号)、第一开关信号SW1、第一电压V1、第三延时信号SD3(即第三延时电路311的输出信号)、第二控制信号SC2和第二开关信号SW2的时序图。其中，在t1时刻，当该时钟信号CLK由低电平转换为高电平时，第一电压V1出现下冲；在t2时刻，当第一开关信号SW1由高电平转换为低电平时，M1开启(以补偿 第一电压V1)；在t3时刻，第一控制信号SC1由低电平转换为高电平；在t4时刻，当检测到第一电压V1大于该参考电压Vref时，第一开关信号SW1由低电平转换为高电平(即M1关闭)，第二控制信号SC2由低电平转换为高电平(用于在M1关闭后开启第二比较器CMP2)，随后第二开关信号SW2由低电平转换为高电平(即M3开启)；第二延时信号SD2在t4时刻之后由高电平转换为低电平(用于关闭之前可能未关闭的M1)；第三延时信号SD3在t5时刻之前由高电平转换为低电平(用于启动CMP2的关闭)，第二控制信号SC2在第三延时信号SD3转换为低电平之后由高电平转换为低电平(用于关闭第二比较器CMP2)；随后在t5时刻，第二开关信号SW2由高电平转换为低电平(即M3关闭)，第一电压V1稳定。
示例性的，图10中的(a)示出了一种第一电压V1发出下冲时的波动示意图，曲线L1是应用上述图8所示的补偿电路2对第一电压V1进行补偿后的第一电压V1的波动曲线，曲线L2是未补偿第一电压V1时的第一电压V1的波动曲线。在第一电压V1发出下冲时，通过该补偿电路2对第一电压V1进行补偿，可以减小第一电压V1的瞬态变化幅度，从而提高第一电压V1的稳定速度。图10中的(b)示出了一种在第一电压V1补偿后出现上冲时的波动示意图，曲线L3是应用上述图8所示的放电电路3对第一电压V1进行减小后的第一电压V1的波动曲线，曲线L4是未减小第一电压V1时的第一电压V1的波动曲线。在第一电压V1补偿后出现上冲时，通过该放电电路3对第一电压V1进行减小，可以提高第一电压V1补偿后的稳定速度，从而进一步提高LDO1的响应速度和第一电压V1的精确度。
图11为本申请实施例提供的另一种用于LDO的辅助电路的结构示意图，该辅助电路可用于在第一电压V1发生上冲时减小第一电压V1，以及在第一电压V1放电后出现下冲时补偿第一电压V1。
在一种示例中，如图11中的(a)所示，下拉电路31可以包括：第四延时电路315、第三与非门316、第四非门317和第四晶体管M4。第四延时电路315的输入端和第三与非门316的第一输入端耦合且用于接收时钟信号CLK，第四延时电路315的输出端用于输出第三控制信号SC3，第三与非门316的第二输入端用于接收第三比较信号SM3，第三与非门316的输出端通过第四非门317与第四晶体管M4的控制端耦合于第三节点P3，第四晶体管M4耦合在该下拉电路31的输入端与接地端GND之间，将第三与非门316的输出端和第四非门317的输入端的耦合点表示为Q。第二检测器32可以包括：第三比较器CMP3，第三比较器CMP3的控制端用于接收第三控制信号SC3，第三比较器CMP3的两个输入端分别用于接收第一电压V1和该参考电压Vref，第三比较器CMP3的输出端用于输出第三比较信号SM3。
可选的，该下拉电路31还可以包括第五延时电路318和第五非门319，第五延时电路318的输入端与第四延时电路315的输出端耦合，第五延时电路318的输出端通过第五非门319与第三与非门316的第三输入端耦合。
当第一电压V1发生上冲时，下拉电路31和第二检测器32可用于减小第一电压V1，具体过程可以包括：当第一电压V1发生下冲时，该时钟信号CLK为高电平，即第三与非门316的第一输入端接收到高电平，此时第三与非门316的第二输入端为预置的高电平，从而第三与非门316的输出端输出低电平，该低电平经过第四非门317后为高电平，即第 三节点P3的信号为高电平；当第三节点P3的信号为高电平时，第四晶体管M4被导通，由于第四晶体管M4与接地端耦合，从而第一电压V1被拉低，即实现对第一电压V1的减小；当该时钟信号CLK的高电平经过第四延时电路315的延时后，第三比较器CMP3的控制端接收到高电平，即第三控制信号SC3为高电平，从而第三比较器CMP3被开启；当第三比较器CMP3检测到第一电压V1小于该参考电压Vref时输出低电平(第三比较信号SM3为低电平)，即第三与非门316的第二输入端接收到低电平，从而第三与非门316的输出端由低电平转换为高电平，进而第三节点P3的信号由高电平转换为低电平；当第三节点P3的信号为低电平时，第四晶体管M4被关断，从而下拉电路31被关闭。进一步的，当下拉电路31还包括第五延时电路318和第五非门319，第三与非门316还包括第三输入端时，若下拉电路31在上述过程中未关闭，该时钟信号CLK的高电平在依次经过第四延时电路315和第五延时电路318的延时后，第五非门319接收到高电平并输出低电平，从而第三与非门316的第三输入端接收到低电平，第三与非门316的输出端输出高电平，致使第三节点P3的信号转换为低电平，从而第四晶体管M4被关断，即下拉电路31被关闭。
在一种示例中，如图11中的(b)所示，上拉电路21可以包括：第六延时电路215、第四与非门216、第六非门217、第五晶体管M5和第六晶体管M6。第六延时电路215的输入端用于接收该时钟信号CLK，第六延时电路215的输出端与第四与非门216的第一输入端耦合，第四与非门216的第二输入端用于接收第三开关信号SW3的反相信号SW3’，第四与非门216的输出端与第六非门217的输入端耦合，第六非门217的输出端用于输出第四控制信号SC4，第五晶体管M5的一极与电源端Vdd耦合，第五晶体管M5的另一极与第六晶体管M6的一极耦合，第六晶体管M6的另一极与上拉电路21的输出端耦合，上拉电路21的输出端用于与LDO1的输出端耦合，第五晶体管M5的控制端用于接收第四比较信号SM4，第六晶体管M6的控制端用于接收偏置电压VB。第一检测器22可以包括第四比较器CMP4，第四比较器CMP4的控制端用于接收第四控制信号SC4，第四比较器CMP4的两个输入端分别用于接收第一电压V1和该参考电压Vref，第四比较器CMP4的输出端用于输出第四比较信号SM4。其中，第三开关信号SW3可以是第四非门317输出的信号，第三开关信号SW3的反相信号SW3’可以为第三与非门316的输出端产生的信号，即该反相信号SW3’可以为耦合点Q的信号。
可选的，第四与非门216还包括第三输入端，第四与非门216的第三输入端用于接收第三控制信号SC3。
在第一电压V1减小后出现下冲时，上拉电路21和第一检测器22可用于补偿第一电压V1，具体过程可以包括：该时钟信号CLK经过第六延时电路215后仍为高电平，即第四与非门216的第一输入端为高电平，当第三开关信号SW3的反相信号SW3’为高电平时，第四与非门216的第二输入端接收到高电平，从而第四与非门216的输出端输出低电平；第六非门217接收该低电平并输出高电平(第四控制信号SC4为高电平)，即第四比较器CMP4的控制端接收到高电平，从而第四比较器CMP4被开启；当第四比较器CMP4检测到第一电压V1小于该参考电压Vref(即检测到第一电压V1减小后出现下冲)时输出低电平，即第四比较信号SM4为低电平，从而第五晶体管M5被导通，由于第五晶体管M5和第六晶体管M6串联耦合在电源端Vdd与LDO1的输出端之间，从而第一电压V1被拉高，即补偿第一电压V1，以提高第一电压V1减小后出现下冲时的恢复速度；当该时钟信 号CLK经过第六延时电路215的延时后为低电平时，第四与非门216的第一输入端接收到低电平，从而第四与非门216的输出端输出高电平，根据上述类似的逻辑可知，此时第五晶体管M5被关断，即上拉电路21被关闭。进一步的，当第四与非门216还包括第三输入端时，第四与非门216的第三输入端可接收到第三控制信号SC3，第三控制信号SC3是该时钟信号CLK经过第四延时电路315延时后的信号，若该时钟信号CLK为低电平(即该辅助电路未工作)，第四与非门216的第三输入端在该辅助电路未工作、以及第四延时电路315的延时内接收到低电平，第四与非门216的输出端输出高电平，该高电平经过第六非门217后转换为低电平，即第四控制信号SC4为低电平，从而第四比较器CMP4被关闭且输出高电平，根据上述类似的逻辑可知，此时第五晶体管M5被关断，即上拉电路21被关闭，这样可以避免补偿电路2提前开启，从而可以进一步降低功耗的损失。
需要说明的是，图11中以第四晶体管M4和第五晶体管M5为PMOS管、第六晶体管M6为NMOS管为例进行说明；在实际应用中，第四晶体管M4、第五晶体管M5和第六晶体管M6还可以替换为具有类似功能的其他晶体管，本申请对此不作具体限制。
图12示出了上述图11所提供的用于LDO的辅助电路中的不同信号的时序图，该不同信号可以包括：该时钟信号CLK、第三控制信号SC3、第三比较信号SM3、第五延时信号SD5(即第五延时电路318的输出信号)、第三开关信号SW3、第三开关信号SW3的反相信号SW3’、第一电压V1、第六延时信号SD6(即第六延时电路215的输出信号)、第四控制信号SC4和第四比较信号SM4的时序图。其中，在t1时刻，当该时钟信号CLK由低电平转换为高电平时，第一电压V1出现上冲；在t2时刻，当第三开关信号SW3由低电平转换为高电平时，M4开启(以减小第一电压V1)；在t3时刻，第三控制信号SC3由低电平转换为高电平；在t4时刻，当检测到第一电压V1小于该参考电压Vref时，第三开关信号SW3由高电平转换为低电平(即M4关闭)，第四控制信号SC4由高电平转换为低电平(用于在M4关闭后开启第四比较器CMP4)，随后第四比较信号SM4由高电平转换为低电平(即M5开启)；第五延时信号SD5在t4时刻之后由高电平转换为低电平(用于关闭之前可能未关闭的M4)；第六延时信号SD6在t5时刻之前由高电平转换为低电平(用于启动CMP4的关闭)，第四控制信号SC4在第六延时信号SD6转换为低电平之后由高电平转换为低电平(用于关闭第四比较器CMP4)；随后在t5时刻，第四比较信号SM4由高电平转换为低电平(即M5关闭)，第一电压V1稳定。
在本申请实施例中，当LDO1在上电过程、或者在外部负载发生变化时，若LDO1输出的第一电压V1发生下冲，补偿电路2可用于补偿第一电压V1并在检测到第一电压V1大于参考电压Vref时关闭，若LDO1输出的第一电压V1发生上冲，放电电路3可用于通过第一电压放电以减小第一电压V1，并在检测到第一电压V1小于该参考电压Vref时关闭。上述技术方案中，无需增大LDO1的输出电容，且补偿电路2和放电电路3仅在第一电压V1发生上冲和下冲的过程中工作，从而可以在不过多增加额外的面积和功耗的同时，有效减小第一电压V1在出现上冲和下冲时的瞬态幅度、以及提高LDO1的响应速度，从而提高第一电压V1的稳定速度。此外，当补偿电路2对发生下冲的第一电压V1存在过度补偿导致第一电压补偿后出现上冲时，放电电路3还可以通过减小第一电压V1来提高第一电压V1补偿后的恢复速度，当放电电路3对发生上冲的第一电压V1存在过度放电导致第一电压V1放电后出现下冲时，补偿电路2还可以通过补偿第一电压V1来提高第一电压 V1放电后的恢复速度，从而进一步提高第一电压V1的稳定速度，同时也提高了第一电压V1的精确度。
基于此，本申请实施例还提供一种芯片系统，该芯片系统包括负载和用于LDO的辅助电路，该用于LDO的辅助电路可以为上文所提供的任一种用于LDO的辅助电路；其中，该用于LDO的辅助电路包括LDO、以及与该LDO耦合的补偿电路和放电电路，该LDO用于为该负载供电，该补偿电路和该放电电路用于提高该LDO输出的第一电压的稳定速度。
本申请实施例还提供一种电子设备，该电子设备包括负载和电路板、该电路板包括上文所提供的任一种用于LDO的辅助电路，该用于LDO的辅助电路包括LDO、以及与该LDO耦合的补偿电路和放电电路，该LDO用于为该负载供电，该补偿电路和该放电电路用于提高该LDO输出的第一电压的稳定速度。
需要说明的是，上文中提供的用于LDO的辅助电路的相关描述均可引援至该芯片系统和该电子设备中，本申请实施例在此不再赘述。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种用于低压差线性稳压器LDO的辅助电路，其特征在于，包括：LDO、以及分别与所述LDO耦合的补偿电路和放电电路；
    所述LDO，用于输出第一电压；
    所述补偿电路，用于在所述第一电压发生下冲时，补偿所述第一电压并在检测到所述第一电压大于第一参考电压时关闭；
    所述放电电路，用于在所述第一电压发生上冲时，减小所述第一电压并在检测到所述第一电压小于第二参考电压时关闭。
  2. 根据权利要求1所述的辅助电路，其特征在于，所述补偿电路和所述放电电路相耦合；
    所述补偿电路，还用于在检测到所述第一电压大于所述第一参考电压时，开启所述放电电路；和/或，
    所述放电电路，还用于在检测到所述第一电压小于所述第二参考电压时，开启所述补偿电路。
  3. 根据权利要求1或2所述的辅助电路，其特征在于，所述补偿电路包括上拉电路和第一检测器；
    所述上拉电路，用于在所述第一电压发生下冲时，补偿所述第一电压；
    所述第一检测器，用于在检测到所述第一电压大于所述第一参考电压时关闭所述上拉电路。
  4. 根据权利要求1-3任一项所述的辅助电路，其特征在于，所述放电电路包括下拉电路和第二检测器；
    所述下拉电路，用于在所述第一电压发生上冲时，减小所述第一电压；
    所述第二检测器，用于在检测到所述第一电压小于所述第二参考电压时关闭所述下拉电路。
  5. 根据权利要求3或4所述的辅助电路，其特征在于，所述上拉电路包括：第一延时电路、第一与非门、第一晶体管和第二晶体管；其中，所述第一延时电路的输入端和所述第一与非门的第一输入端耦合且用于接收时钟信号，所述第一延时电路的输出端用于输出第一控制信号，所述第一与非门的第二输入端用于接收第一比较信号，所述第一晶体管的一极与电源端耦合，所述第一晶体管的另一极与所述第二晶体管的一极耦合，所述第二晶体管的另一极与所述上拉电路的输出端之间，所述第一晶体管的控制端和所述第一与非门的输出端耦合，所述第二晶体管的控制端用于接收偏置电压；
    所述第一检测器包括：第一比较器；其中，所述第一比较器的控制端用于接收所述第一控制信号，所述第一比较器的两个输入端分别用于接收所述第一电压和所述第一参考电压，所述第一比较器的输出端用于输出所述第一比较信号。
  6. 根据权利要求5所述的辅助电路，其特征在于，所述上拉电路还包括第二延时电路和第一非门，所述第二延时电路的输入端与所述第一延时电路的输出端耦合，所述第二延时电路的输出端通过所述第一非门与所述第一与非门的第三输入端耦合。
  7. 根据权利要求4-6任一项所述的辅助电路，其特征在于，所述下拉电路包括：第三 延时电路、第二与非门、第二非门、第三非门和第三晶体管；其中，所述第三延时电路的输入端用于接收所述时钟信号，所述第三延时电路的输出端与所述第二与非门的第一输入端耦合，所述第二与非门的第二输入端用于接收第一开关信号，所述第二与非门的输出端与所述第二非门的输入端耦合，所述第二非门的输出端用于输出第二控制信号，所述第三非门的输入端用于接收第二比较信号，所述第三非门的输出端与所述第三晶体管的控制端耦合，所述第三晶体管耦合在所述下拉电路的输入端与接地端之间；
    所述第二检测器包括：第二比较器；其中，所述第二比较器的控制端用于接收所述第二控制信号，所述第二比较器的两个输入端分别用于接收所述第一电压和所述第二参考电压，所述第二比较器的输出端用于输出所述第二比较信号。
  8. 根据权利要求7所述的辅助电路，其特征在于，所述第一开关信号为所述第一与非门的输出端产生的信号。
  9. 根据权利要求7或8所述的辅助电路，其特征在于，所述第二与非门的第三输入端用于接收所述第一控制信号。
  10. 根据权利要求3或4所述的辅助电路，其特征在于，所述下拉电路包括：第四延时电路、第三与非门、第四非门和第四晶体管；其中，所述第四延时电路的输入端和所述第三与非门的第一输入端耦合且用于接收时钟信号，所述第四延时电路的输出端用于输出第三控制信号，所述第三与非门的第二输入端用于接收第三比较信号，所述第三与非门的输出端通过所述第四非门与所述第四晶体管的控制端耦合，所述第四晶体管耦合在所述下拉电路的输入端与接地端之间；
    所述第二检测器包括：第三比较器；其中，所述第三比较器的控制端用于接收所述第三控制信号，所述第三比较器的两个输入端分别用于接收所述第一电压和所述第二参考电压，所述第三比较器的输出端用于输出所述第三比较信号。
  11. 根据权利要求10所述的辅助电路，其特征在于，所述下拉电路还包括第五延时电路和第五非门，所述第五延时电路的输入端与所述第四延时电路的输出端耦合，所述第五延时电路的输出端通过所述第五非门与所述第三与非门的第三输入端耦合。
  12. 根据权利要求4、10或11所述的辅助电路，其特征在于，所述上拉电路包括：第六延时电路、第四与非门、第六非门、第五晶体管和第六晶体管；其中，所述第六延时电路的输入端用于接收所述时钟信号，所述第六延时电路的输出端与所述第四与非门的第一输入端耦合，所述第四与非门的第二输入端用于接收第二开关信号，所述第四与非门的输出端与所述第六非门的输入端耦合，所述第六非门的输出端用于输出第四控制信号，所述第五晶体管的一极与电源端耦合，所述第五晶体管的另一极与所述第六晶体管的一极耦合，所述第六晶体管的另一极与所述上拉电路的输出端之间，所述第五晶体管的控制端用于接收第四比较信号，所述第六晶体管的控制端用于接收偏置电压；
    所述第一检测器包括：第四比较器；其中，所述第四比较器的控制端用于接收所述第四控制信号，所述第四比较器的两个输入端分别用于接收所述第一电压和所述第一参考电压，所述第四比较器的输出端用于输出所述第四比较信号。
  13. 根据权利要求12所述的辅助电路，其特征在于，所述第二开关信号为所述第三与非门的输出端产生的信号。
  14. 根据权利要求12或13所述的辅助电路，其特征在于，所述第四与非门的第三输 入端用于接收所述第三控制信号。
  15. 一种芯片系统，其特征在于，所述芯片系统包括负载、以及权利要求1-14任一项所述的用于低压差线性稳压器LDO的辅助电路；其中，所述辅助电路包括LDO、以及与所述LDO耦合的补偿电路和放电电路，所述LDO用于为所述负载供电，所述补偿电路和所述放电电路用于提高所述LDO输出的第一电压的稳定速度。
  16. 一种设备，其特征在于，所述设备包括负载和电路板，所述电路板包括权利要求1-14任一项所述的用于低压差线性稳压器LDO的辅助电路；其中，所述辅助电路包括LDO、以及与所述LDO耦合的补偿电路和放电电路，所述LDO用于为所述负载供电，所述补偿电路和所述放电电路用于提高所述LDO输出的第一电压的稳定速度。
PCT/CN2021/102450 2021-06-25 2021-06-25 一种用于ldo的辅助电路、芯片系统及设备 WO2022267026A1 (zh)

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CN116301167A (zh) * 2023-05-17 2023-06-23 此芯科技(上海)有限公司 一种低压差线性稳压器及片上系统

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CN101231535A (zh) * 2007-01-25 2008-07-30 美国芯源系统股份有限公司 用于校正模拟低压差线性稳压器过冲和下冲的方法及装置
CN209980116U (zh) * 2019-05-10 2020-01-21 深圳市汇春科技股份有限公司 低压差线性稳压器过冲消除电路、下冲消除电路和芯片

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CN209980116U (zh) * 2019-05-10 2020-01-21 深圳市汇春科技股份有限公司 低压差线性稳压器过冲消除电路、下冲消除电路和芯片

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CN116301167A (zh) * 2023-05-17 2023-06-23 此芯科技(上海)有限公司 一种低压差线性稳压器及片上系统
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