WO2022262819A1 - 边缘计算模组及其功耗控制方法 - Google Patents

边缘计算模组及其功耗控制方法 Download PDF

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WO2022262819A1
WO2022262819A1 PCT/CN2022/099219 CN2022099219W WO2022262819A1 WO 2022262819 A1 WO2022262819 A1 WO 2022262819A1 CN 2022099219 W CN2022099219 W CN 2022099219W WO 2022262819 A1 WO2022262819 A1 WO 2022262819A1
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state
power consumption
pcie
consumption state
chip
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PCT/CN2022/099219
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English (en)
French (fr)
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张映俊
孙刘洋
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深圳云天励飞技术股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5072—Grid computing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4893—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues taking into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of edge computing, in particular to an edge computing module and a power consumption control method thereof.
  • edge computing modules to provide external computing power for the main controller (such as servers, industrial computers, etc.).
  • the edge computing module provides considerable external computing power, but at the same time, the edge computing module has a certain power consumption and generates a lot of heat when providing computing power.
  • the main controller and the edge computing module perform data interaction, due to the size of the data interaction and the uncertainty of the cycle, there is no control for different power consumption states, resulting in high system power consumption of this type of product. Heats up a lot.
  • a method for controlling power consumption of an edge computing module comprising:
  • the target power consumption state that the edge computing module should enter is obtained by the operating state of the intelligent computing chip and the power state of the PCIe link;
  • An edge computing module is connected to an external main controller through a PCIe interface to provide extended computing functions for the main controller, and the edge computing module includes an intelligent computing chip for providing computing functions and an Peripheral components supported by the computing chip; the intelligent computing chip includes:
  • the PCIe controller is used to send the status change interrupt signal
  • a power management unit for controlling the power state of the PCIe link
  • the intelligent computing subsystem is used to provide computing functions
  • the low power consumption control unit is connected with the PCIe controller, the power management unit, and the intelligent computing subsystem, and is used to execute the above method.
  • the above-mentioned edge computing module and its power consumption control method know the power state of the PCIe link according to the state change interrupt signal, and know the overall load of the smart computing chip through the operating state of the smart computing chip; when the power state of the PCIe link changes and reduces During power consumption, if the overall load of the intelligent computing chip is also low, it indicates that the operating state of the intelligent computing chip matches the PCIe link power state represented by the state change interrupt signal, thereby controlling the edge computing module to enter The target power consumption state can effectively reduce the overall power consumption of the edge computing module. Since the power consumption state of the edge computing module matches the overall load of the edge computing module, it will not inappropriately generate heat when there are no computing tasks or a small amount of computing tasks, thereby effectively reducing heat generation.
  • Figure 1a is a schematic diagram of two PCIe devices connected through the PCIe protocol
  • Fig. 1b is a system structure diagram composed of an edge computing module and a main controller in the embodiment of the present application;
  • Figure 1c is a hierarchical structure diagram of the PCIe protocol
  • Figure 1d is a partial state transition diagram of the LTSSM state machine
  • Figure 1e is a structural diagram of the intelligent computing chip implemented in the form of a system-on-chip in the embodiment of the present application;
  • FIG. 2 is a flowchart of a method for controlling power consumption of an edge computing module in an embodiment
  • FIG. 3 is a schematic diagram of the relationship and changes of various states in the system of FIG. 1 .
  • FIG. 1a is a schematic diagram of two PCIe (Peripheral Component Interconnect Express, high-speed peripheral component interconnection standards) devices connected through the PCIe protocol.
  • PCIe Peripheral Component Interconnect Express, high-speed peripheral component interconnection standards
  • Two or more PCIe devices can be interconnected through the PCIe protocol to form a system.
  • each PCIe device can only be used as one of Root Complex (master control, RC) and Endpoint (endpoint, EP), and there can only be one master control device in a system, but there can be multiple endpoint devices .
  • the master control device can initiate configuration commands to the endpoint devices, but not vice versa.
  • FIG. 1b is a structural diagram of a system composed of an edge computing module 100 and a main controller 200 in the embodiment of the present application.
  • the edge computing module 100 and the main controller 200 are connected through a PCIe interface.
  • the main controller 200 itself has a certain computing capability, and at the same time, by connecting to the external edge computing module 100 and using the computing power provided by the edge computing module 100, the purpose of expanding the computing capability of the main controller 200 itself is achieved.
  • Multiple edge computing modules 100 can be plugged into each main controller 200 .
  • the edge computing module 100 is an endpoint (EP) device
  • the main controller 200 is a main control (RC) device.
  • the main controller 200 may be a server, an industrial computer, or the like.
  • the edge computing module 100 may include a smart computing chip 102 and other necessary peripheral components that support the smart computing chip 102 , such as power supply, external storage, etc. (not shown).
  • the intelligent computing chip 102 is a component that provides computing power in the edge computing module 100 .
  • the intelligent computing chip 102 may include a low power consumption control unit 104 , a PCIe controller 106 , a power management unit 108 and an intelligent computing subsystem 110 .
  • the PCIe controller 106 is connected to the main controller 200 through a PCIe interface.
  • the PCIe controller 106 performs specific communication control.
  • the PCIe protocol defines a layered structure, that is, the PCIe controller 106 is designed and implemented according to the layered structure shown in FIG. 1c.
  • the layered structure includes a transaction layer, a data link layer and a physical layer.
  • the transaction layer receives commands and data from the application layer, encapsulates them into transaction layer packages (Transaction Layer Package, TLP) and then sends them to the data link layer; the transaction layer may also receive data link layer packages (Data Link Layer Package) from the data link layer Link Layer Package, DLLP), and parse the data link layer package into a transaction layer package.
  • TLP Transaction Layer Package
  • DLLP data link layer Package
  • the responsibilities of the transaction layer include transaction communication, such as reading data, writing data, and so on.
  • the data link layer is used to encapsulate the transaction layer packet into a data link layer packet and then send it to the physical layer, or to encapsulate the serial data from the physical layer into a data link layer packet.
  • the responsibilities of the data link layer include error detection and error correction.
  • the physical layer is used to send the data link layer packet to the PCIe link after further parallel-to-serial conversion (parallel-to-serial conversion) and electrical processing, and transmit it to the opposite end through the PCIe link.
  • the physical layer or receives signals through the PCIe link, and then obtains serial data through electrical processing, and sends them to the data link layer after serial-to-parallel conversion (serial-to-parallel conversion) into parallel data.
  • a PCIe link is a communication channel between PCIe devices.
  • the basic structure of the PCIe link is a differential link pair (Lanes) that transmits two differentially driven signal pairs respectively. That is, the transmit link (Transmit Lane) transmits the transmit pair (transmit pair), and the receive link (Receive Lane) transmits the receive pair (receive pair).
  • the PCIe link may include multiple basic differential link pairs, for example, 1, 2, 4, 8, 12, 16, and 32 pairs. Use x1, x2, x4, x8, x12, x16, x32 to represent the width of the communication channel.
  • the main controller 200 needs to perform a computing task, by calling the PCIe controller of the main controller 200, the commands and data related to the computing task are encapsulated into a transaction layer packet through the transaction layer, and then the transaction layer packet is encapsulated through the data link layer It is a data link layer packet, and the physical layer performs electrical processing on the data link layer packet and sends it out through the PCIe link.
  • the edge computing module 100 receives data through the PCIe link, and uses the PCIe controller 106 to analyze layer by layer from the physical layer, data link layer and transaction layer, and finally obtains relevant commands and data to perform computing tasks, and then sends them to Intelligent computing subsystem 110. After the calculation by the intelligent computing subsystem 110 is completed, the PCIe controller 106 is called to return the data in the opposite direction of the above path.
  • the power management unit 108 includes the implementation of active state link power management (Active State Link PM, ASPM) and software-controlled power management (PCI-PM) specified by the PCIe protocol.
  • ASPM Active State Link PM
  • PCI-PM software-controlled power management
  • ASPM active state link power management
  • PCI-PM software-controlled power management
  • ASPM active state link power management
  • PCI-PM software-controlled power management
  • the PCIe protocol provides five power states of the PCIe link (Link Power Management State), including:
  • L0 Normal working state (activated state, Active State). In the L0 state, all PCIe transactions and operations are available.
  • L0s Wait states for low latency recovery and energy saving. In the L0s state, the main power supply, clock, and phase-locked loop supporting the PCIe link are all active. Transmission of transaction layer packets and data link layer packets is not available.
  • L1 Wait state with high latency recovery and low power. In the L1 state, the main power supporting the PCIe link is active and the PLL can be disabled.
  • L2 The state in which the link is powered by auxiliary power and is deeply power-efficient. In the L2 state, the main power supply and clock supporting the PCIe link are turned off. powered by auxiliary power.
  • L3 Link power down state. In the L3 state, nothing is powered.
  • LTSSM Link training and status state machine, link training and status
  • PCIe devices use this LTSSM state machine to manage the PCIe link state.
  • the LTSSM state machine manages five types of states: link training state (Training States), retraining state (Re-Training State), software-driven power management state (Power Management States), active state power management state (ASPM States) and Other states other than the above 4 categories.
  • the change of the working state of the PCIe link mainly involves the change of the software-driven power management state (Power Management States) and the change of the active state power management state (ASPM States).
  • the software-driven power management states include the software-controlled first power consumption state PML1, the software-controlled second power consumption state PML2, and the software-controlled third power consumption state PML3.
  • Active state power management states include the zero power consumption state ASPM L0s of autonomous power management and the first power consumption state ASPM L1 of autonomous power management.
  • the LTSSM state machine supports the change of the PCIe link among the four states of L0, L0s, L1, and L2 (L3 is completely powered off and does not enter the LTSSM state machine). Entering the L1 state can be an autonomous change (ASPM control) or software control (PCI-PM control).
  • the power state change of the PCIe link can be managed, that is, according to which conditions the power state of the PCIe link is changed, and at the same time, the message of the power state change of the PCIe link and the power state of the PCIe link after the change are obtained .
  • FIG. 1d is a partial state change diagram of the LTSSM state machine (for ease of illustration, other states not involved in this application are simplified).
  • the power state of the PCIe link can enter L0s, L1, L2 and recovery state from L0, enter L0 from L0s, enter recovery state from L1, and enter detection state from L2.
  • the physical layer of the edge computing module 100 detects a certain idle time on the PCIe link. The length of this idle time depends on the specific implementation, usually 7-10us.
  • the control logic of the power management unit 108 is as follows:
  • the edge computing module 100 is preparing to make the PCIe link enter the L1 state, and the main controller 200 should be in the active state at the same time.
  • TLPs new transaction layer packets
  • the main controller 200 also puts the data link layer in the PCIe controller into an inactive state and puts the physical layer into an electrical idle state.
  • the PCIe link enters the L1 state and completes. Because the physical layer detects the idle state of the PCIe link and causes the power state to change, the ASPM implements hardware-autonomous and dynamic PCIe link power management.
  • the driver can also set the Link Control Register (Link Control Register) in the PCIe device configuration space to enable or disable ASPM L0s and/or ASPM L1.
  • Link Control Register Bits[1:0] indicates an enable condition.
  • the intelligent computing subsystem 110 is used to provide computing functions, and may include an intelligent computing acceleration processor, such as a neural network processor.
  • Intelligent computing acceleration processors can provide special instructions for common operations in intelligent computing, so that the computing speed is faster than that of general-purpose architecture processors. For example, in neural network calculations, convolution calculations are commonly used, and instructions for accelerating convolution calculations are provided in neural network processors.
  • the low power consumption control unit 104 is used to monitor the running state of the intelligent computing chip 102 and adjust the power consumption state of the edge computing module 100 in combination with the power state of the PCIe link, so as to realize the power consumption control of the edge computing module 100 in this application.
  • the running status of the intelligent computing chip 102 includes the overall load of the intelligent computing chip 102 and the computing load, busyness and idle conditions of the intelligent computing subsystem 110 . It can be understood that the computing load and busyness of the intelligent computing subsystem 110 may affect the overall load of the intelligent computing chip 102 , but is not equal to the overall load of the intelligent computing chip 102 .
  • the above-mentioned intelligent computing chip 102 may be implemented by using a system on chip (System on Chip, Soc).
  • Soc System on Chip
  • the intelligent computing chip 102 includes a neural network processor), a low power consumption control unit 104, other subsystems, and a bus.
  • the main processor 112 , PCIe controller 106 , system controller, intelligent computing subsystem 110 and other subsystems are all connected and communicated through the bus 114 .
  • the main processor 112 is the core of the entire intelligent computing chip 102, and the main processor 112 is used to manage and schedule each sub-module or subsystem (including the PCIe controller 106, the system controller, the intelligent computing subsystem 110 and other subsystems).
  • PCIe controller 106 may be included in host processor 112 .
  • the PCIe controller 106 may not be included in the main processor 112 .
  • the system controller is responsible for system-level control in the intelligent computing chip 102, such as bus control, storage control, and the like.
  • a power management unit 108 may be included in the system controller.
  • the intelligent computing subsystem 110 is used to perform specific computing tasks, such as neural network computing.
  • subsystems are used to provide other functions, which can be implemented in the form of IP cores and set according to the application requirements of the edge computing module 100 .
  • edge computing module 100 For the dedicated intelligent computing chip 102, other subsystems may not be available.
  • the main processor 112 calls the PCIe controller 106 to receive specific data, and the main processor 112 schedules the computing tasks Specific implementation is given to the intelligent computing subsystem 110 .
  • the main processor 112 calls the PCIe controller 106 to send the computing result back to the main controller 200 through the PCIe link.
  • the low power consumption control unit 104 monitors the load of the main processor 112, the load of the bus 114, the calculation load of the intelligent computing subsystem 110, the load of other subsystems, and the power state of the PCIe link during the operation of the intelligent computing chip 102 Wait.
  • the low power consumption control unit 104 monitors that the operating state of the intelligent computing chip 102 and the power state of the PCIe link meet certain conditions, it sends a corresponding system power consumption adjustment signal, and the main processor 112 adjusts the operation of the intelligent computing chip 102 Situations, such as adjusting the voltage of the power supply module, adjusting the running frequency of the main processor 112 itself, adjusting the frequency of the bus 114, shutting down or waking up the intelligent computing subsystem 110 or other subsystems, and so on. In this way, the power consumption control of the edge computing module 100 can be adjusted.
  • a power consumption control method of an edge computing module is provided, and the method describes the logic of power consumption control performed by the low power consumption control unit 104 .
  • the power consumption control method of the edge computing module includes the following steps:
  • Step S202 Obtain the running state of the intelligent computing chip 102 in the edge computing module 100 when receiving a state change interrupt signal from the PCIe controller 106 .
  • the change of the power state of the PCIe link can be obtained.
  • the PCIe controller 106 will send a corresponding state change interrupt signal to the low power consumption control unit 104 according to the situation.
  • the low power consumption control unit 104 When the low power consumption control unit 104 receives the state change interrupt signal, it needs to communicate with the intelligent computing chip 102 to obtain its current running state.
  • the intelligent computing chip 102 will also be in different operating states according to the computing tasks carried by it.
  • the low power consumption control unit 104 can be realized by hardware, and integrated in the Soc chip realizing the intelligent computing chip 102, and in each level of the intelligent computing chip 102 (including the subprocessor level, the subsystem level, the bus level) , main processor level, etc.) to collect information, so as to understand the current operating state of the intelligent computing chip 102 . Collecting the information of the intelligent computing chip 102 can be done actively or passively.
  • the intelligent computing chip 102 sets judgment logic in each level of collected information, and notifies the low power consumption control unit 104 when the conditions are met.
  • the intelligent computing chip 102 may notify the low power consumption control unit 104 by using an interrupt.
  • the operating states of the intelligent computing chip 102 are respectively defined as follows:
  • Chip normal operation state C0 the state where the intelligent computing chip 102 is in when it is working normally.
  • Chip zero running state C0s the overall load of the intelligent computing chip 102 is not high, for example not higher than 60%.
  • the intelligent computing chip 102 has the condition to reduce the frequency of the main processor 112 and the bus 114 , that is, the execution of the current computing task will not be affected after the frequency reduction.
  • First operating state C1 of the chip the overall load of the intelligent computing chip 102 is relatively low, for example not higher than 30%.
  • the intelligent computing chip 102 has the condition to reduce the frequency of the main processor 112, the bus 114 and most modules (including the intelligent computing subsystem 110), that is, the execution of the current computing task will not be affected after the frequency reduction.
  • Second operating state of the chip C2 the intelligent computing chip 102 is idle, and the condition for the intelligent computing chip 102 to enter the sleep state is met.
  • the third running state of the chip C3 the intelligent computing chip 102 is powered off.
  • Step S204 Determine whether the running state of the intelligent computing chip matches the power state of the PCIe link represented by the state change interrupt signal.
  • the operating state of the intelligent computing chip 102 is an objective condition for power consumption control.
  • the matching means that the running state of the intelligent computing chip can satisfy the requirement of changing the edge computing module 100 to a power consumption state, and the power consumption state corresponds to the power state of the PCIe link.
  • the operating state of the intelligent computing chip matches the power state of the PCIe link represented by the state change interrupt signal, it indicates that the conditions for corresponding power consumption control of the edge computing module are met. Because the power state of the PCIe link represents the activity of data transmission, and the running state of the intelligent computing chip 102 represents the activity of data processing. Only when the two match, can the entire edge computing module be controlled to the corresponding target power consumption state.
  • the computing load of the intelligent computing subsystem 110 when the computing load of the intelligent computing subsystem 110 is high, it indicates that the intelligent computing is in progress, but the data related to the computing task has already been transmitted, and there is no data transmission on the PCIe link.
  • the PCIe link may enter a low power consumption state , such as ASMP L0s or ASMP L1.
  • the intelligent computing chip 102 still needs to maintain a normal power supply to ensure the computing tasks of the intelligent computing subsystem 110 .
  • the intelligent computing subsystem 110 After the intelligent computing subsystem 110 completes the computing task, if there is no new computing task, it will be idle. After the PCIe controller 106 completes sending the calculation result, it will enter the low power consumption state again.
  • the edge computing module 100 is neither performing intelligent computing nor performing data transmission, and is in an idle state as a whole.
  • the power consumption of the edge computing module 100 can be reduced by lowering the power supply voltage, lowering the frequency of the main processor 112 , lowering the frequency of the bus 114 , and shutting down the intelligent computing subsystem 110 .
  • the power states of the PCIe links are respectively defined as follows:
  • Link normal working state L0 the state in which the PCIe link is working normally
  • Autonomous power management zero power consumption state ASPM L0s The low power consumption state of the PCIe link when it is idle for a short time, which meets the requirements of the above-mentioned PCIe protocol for L0s.
  • Autonomous power management first power consumption state ASPM L1 A low power consumption state in which the PCIe link consumes less power than the first autonomous power management state ASPM L0s, which meets the requirements of the above-mentioned PCIe protocol for L1.
  • Step S206 If they match, then according to the preset power consumption control rules, the target power consumption state that the edge computing module should enter is obtained from the running state of the intelligent computing chip and the power state of the PCIe link.
  • the target power consumption states that the edge computing module should enter are respectively defined as follows:
  • Normal working state of the module S0 the state where the edge computing module 100 is working normally, and supports the normal working of the intelligent computing chip 102 .
  • Module zero power consumption state S0s the low power consumption state of the edge computing module 100 when it is idle for a short time, and supports the intelligent computing chip 102 to work in the low power consumption state after the main processor 112 and the bus 114 are reduced in frequency.
  • the first power consumption state S1 of the module a low power consumption state with lower power consumption than the zeroth power consumption state S0s of the module.
  • the smart computing chip 102 is supported to work in a low power consumption state after the main processor 112 , the bus 114 and most modules (including the smart computing subsystem 110 ) are down-frequency.
  • Second power consumption state S2 of the module the intelligent computing chip 102 is in a dormant state.
  • the edge computing module 100 supports the dormancy and subsequent wake-up of the intelligent computing chip 102 in the second power consumption state S2 of the module.
  • the third power consumption state S3 of the module the intelligent computing chip 102 is in a power-off state.
  • the edge computing module 100 supports the intelligent computing chip 102 in a power-off state and subsequent power-on in the third power consumption state S3 of the module.
  • the matching relationship can be preset, and the corresponding target power consumption state that the edge computing module should enter can be used to obtain the preset power consumption control rule.
  • the preset power consumption control rules are as follows in Table 1:
  • the target power consumption state that the edge computing module should enter is set to S0s. and so on.
  • Step S208 Control the edge computing module to enter the target power consumption state.
  • the above method obtains the power state of the PCIe link according to the state change interrupt signal, and obtains the overall load of the intelligent computing chip through the operating state of the intelligent computing chip; when the power state of the PCIe link changes to reduce power consumption, if the overall load of the intelligent computing chip It is also lower, indicating that the power consumption of the intelligent computing chip can be reduced, and part of the computing power of the intelligent computing chip can be avoided, so that the overall power consumption of the edge computing module can also be reduced accordingly.
  • the power state of the PCIe link is related to data transmission.
  • the power state of the PCIe link is a normal working state.
  • the power state of the PCIe link will enter a low power consumption state;
  • setting the edge computing module will also make the power state of the PCIe link enter a low power consumption state; both cases indicate that data transmission affects the power state of the PCIe link.
  • Data transmission is the prerequisite for the smart computing chip to work. If there is no data processing, the smart computing chip will be idle; if the amount of processed data is small, the load will be low; if the amount of processed data is large, the load will be high. Therefore, data transmission affects data processing. That is, the load of processing data follows the data transmission. Take the change of the power state of the PCIe link as an opportunity to know the overall load of the intelligent computing chip, and then perform power consumption control according to the preset power consumption control rules, so that the edge computing module can work normally when there are many computing tasks, and the When there are fewer calculation tasks, the power consumption is reduced, thereby avoiding waste of power consumption. That is to say, the computing power of the intelligent computing chip is better utilized.
  • the power consumption state of the edge computing module matches the overall load of the edge computing module, it will not inappropriately generate heat when there are no computing tasks or a small amount of computing tasks, thereby effectively reducing heat generation.
  • the state change interrupt signal includes: an interrupt for entering the zeroth power consumption state, an interrupt for entering the first power consumption state, a first software-controlled interrupt, a second software-controlled interrupt, and a third software-controlled interrupt.
  • the interrupt of entering the zeroth power consumption state and the interrupt of entering the first power consumption state are triggered by the PCIe controller 106 to be issued by the PCIe link power state change; the first software control interrupt, the second software
  • the control interrupt and the third software control interrupt are issued by the PCIe controller 106 according to the status value written in the status register in the PCIe controller 106 .
  • the low power consumption control unit 104 receives the status change interrupt signal to know the status of the PCIe link, and combines the running status of the intelligent computing chip 102 to manage the power consumption of the edge computing module 100 .
  • the PCIe link enters the zero power consumption state ASPM L0s of autonomous power management when there is no data transmission, and triggers the PCIe controller 106 to send the zero power consumption state Interrupt; when the intelligent computing chip 102 is in the zeroth running state C0s of the chip that matches the zeroth power consumption state of the autonomous power supply management, then obtain the zeroth power consumption state S0s of the module as the target power consumption state, and control the edge computing module The group enters the zero power consumption state S0s of the module.
  • the zero power consumption state ASPM L0s of the autonomous power management is PCIe hardware (in this application, it can be the main controller 200 or the edge computing module 100, that is, either party can make the power state of the PCIe link enter ASPM L0s) autonomously
  • the low power consumption state of the first link is automatically set by the PCIe device and automatically triggered.
  • the PCIe link will automatically enter ASPM L0s, and the power consumption of the PCIe link will be relatively reduced.
  • the overall load of the intelligent computing chip 102 is lower than the first threshold.
  • the first threshold may be 60%.
  • the system can perform Downclocking (mainly the main processor 112 and the bus 114 can be downclocked).
  • the main processor 112 and the bus 114 in the intelligent computing chip 102 are in a down-frequency state.
  • the PCIe link in conjunction with Table 3 and FIG. 3, when one of the following conditions is met, the PCIe link enters the first power consumption state ASPM L1 of autonomous power management:
  • the PCIe link is in the zero power consumption state of autonomous power management ASPM L0s for the first preset duration; or
  • the edge computing module 100 requests the PCIe link to enter the first power consumption state ASPM L1 of the autonomous power management after the intelligent computing chip 102 completes the computing task.
  • the PCIe controller 106 When the PCIe link enters the first power consumption state ASPM L1 of autonomous power management, the PCIe controller 106 is triggered to send and enter the first power consumption state interrupt;
  • the intelligent computing chip 102 When the intelligent computing chip 102 is in the first running state C1 of the chip matching the first power consumption state ASPM L1 of the autonomous power supply management, the first power consumption state S1 of the module is obtained as the target power consumption state, and the edge computing module is controlled.
  • the group 100 enters the module's first power consumption state S1.
  • the first power consumption state ASPM L1 of the autonomous power management is the second link low power consumption state autonomously of the PCIe device (in this application, the edge computing module 100), which is set independently by the PCIe device and automatically triggered. It is a further low-power state (lower power consumption) than ASPM L0s.
  • the overall load of the intelligent computing chip 102 is lower than a second threshold, such as 30%.
  • a second threshold such as 30%.
  • the main processor 112 In the first power consumption state S1 of the module, the main processor 112, the bus 114, and the intelligent computing subsystem 110 in the intelligent computing chip 102 are in a down-frequency state.
  • the PCIe link can be restored to L0 within a certain period of time.
  • the entry and exit of the ASPM L1 can be notified by the PCIe controller 106 to the low power consumption control unit 104 in hardware.
  • the time for ASPM L1 to recover to L0 can reach up to 64us.
  • the PCIe link when the PCIe link has new data transmission, the PCIe link exits the zero power consumption state ASPM L0s of the autonomous power management or the first power consumption state ASPM L1 of the autonomous power management , and enter the normal working state L0, triggering the PCIe controller 106 to issue an interrupt for exiting the zeroth power consumption state or exiting the first power consumption state. Furthermore, after the low power consumption control unit 104 notifies the main processor 112, the main processor 112 controls the edge computing module to exit the zeroth power consumption state S0s of the module and enter the normal working state S0. Data transmission is guaranteed when there is data transmission.
  • an exit delay (Exit latency) is set for the exit from the zero power consumption state ASPM L0s of the autonomous power management or the first power consumption state ASPM L1 of the autonomous power management, so as to match the exit of the edge computing module 100 The time of the module's zero power consumption state S0s.
  • the exit delay can be adjusted.
  • the power consumption state of the edge computing module 100 is triggered and controlled by the state of the PCIe link itself. Because the PCIe protocol itself defines various states of the PCIe link, when the edge computing module 100 is connected to the main controller 200, the working state will cause the power state of the PCIe link to change, making full use of hardware state changes to trigger power consumption control , which implements an automatic power control.
  • the first software-controlled interrupt, the second software-controlled interrupt, and the third software-controlled interrupt are written by the PCIe controller according to the state of the status register in the PCIe controller The value is issued, and the PCIe link enters different software-controlled power consumption states according to the state value of the status register and the power state of the PCIe link;
  • the state value of the state register represents the device power management state (Device Power Management State, D-State), including D0, D1, D2, D3hot, D3cold, etc.
  • D-State Device Power Management State
  • D1 D1, D2, D3hot, D3cold, etc.
  • the power state of the PCIe link is determined by the power management state of the downstream device (Downstream component, the device currently receiving data). The relationship is as follows:
  • the power state of the PCIe link can be switched between L0, L0s, L1, and L2.
  • the power management value of the upstream device When the status value of the status register of the downstream device is set to D1, the power management value of the upstream device must be switched from D0 to D1. And the power state of the PCIe link must be L1 or L2, and can be switched between L1 and L2. The process is similar when setting other D values for the downstream device's status register.
  • the state register is written with a state value by the main controller 200 connected to the edge computing module 100 .
  • a state register is provided in the PCIe controller 106, and the state value of the state register can be three state values of D1/D2/D3hot. After setting D1/D2/D3hot, the PCIe link will The power state of the lane puts the PCIe link into a different power state. Since the setting of the state value of the state register can be set by the software on the upper layer of the main controller 200, the power consumption state entered by the PCIe link is called the software-controlled power consumption state PMLx.
  • the PCIe controller 106 when the status value written into the status register is the first status value, the PCIe controller 106 is triggered to send a first software control interrupt, and the PCIe link enters the software Controlling the first power consumption state PML1.
  • the intelligent computing chip 102 is in the first operating state C1 of the chip that matches the first power consumption state PML1 controlled by the software, then obtain the first power consumption state S1 of the module as the target power consumption state, and control the edge computing module Enter the first power consumption state S1 of the module.
  • the software controls the first power consumption state PML1 to be the low power consumption state of the PCIe link triggered when the device power state of the edge computing module 100 is set by the first state value (usually D1).
  • the overall load of the intelligent computing chip 102 is lower than the aforementioned second threshold.
  • the second threshold may be 30%, and the second threshold is less than the first threshold.
  • the system can perform frequency reduction (including the main processor 112, the bus 114 and most subsystems, such as the intelligent computing subsystem 110);
  • the main processor 112 In the first power consumption state S1 of the module, the main processor 112, the bus 114, and the intelligent computing subsystem 110 in the intelligent computing chip 102 are in a down-frequency state.
  • the PCIe controller 106 when the state value written into the state register is the second state value, the PCIe controller 106 is triggered to send a second software control interrupt, and the PCIe link enters the software Controlling the second power consumption state PML2.
  • the intelligent computing chip 102 is in the chip second operating state C2 matching the software-controlled second power consumption state PML2, then acquire the second power consumption state S2 of the module as the target power consumption state, and control the edge computing module Enter the second power consumption state S2 of the module.
  • the software controls the second power consumption state PML2 to be the low power consumption state of the PCIe link triggered when the device power state of the edge computing module 100 is set by the second state value (usually D2).
  • the edge computing module 100 has a low power consumption state of the PCIe link when the auxiliary power supply is powered.
  • the software controls the second power consumption state PML2 lower edge computing module 100 only and must have an auxiliary power supply, and is in a state of extremely low power consumption.
  • the intelligent computing subsystem 110 In the second operating state C2 of the chip, the intelligent computing subsystem 110 is in an idle state, no computing tasks are performed, and the main processor 112 has no or little scheduling;
  • the intelligent computing chip 102 enters a sleep state (sleep).
  • the exit of L2 requires the main controller 200 to initiate a wake-up.
  • retraining is required, and the recovery time is more than 10ms.
  • the PCIe controller 106 when the status value written into the status register is the third status value, the PCIe controller 106 is triggered to send a third software control interrupt, and the PCIe link enters the software Control the third power consumption state PML3; when the intelligent computing chip 102 is in the third running state C3 of the chip that matches the third power consumption state PML2 controlled by the software, then obtain the third power consumption state S3 of the module as the target function power consumption state, and control the edge computing module to enter the third power consumption state S3 of the module.
  • the software controls the third power consumption state PML3 to be the PCIe link low power consumption state triggered when the device power state of the edge computing module 100 is set by the third state value (usually D3hot); The power state of the PCIe link when the power management software of 200 initiates a power-off operation.
  • the intelligent computing subsystem 110 etc. are all in a power-off state (power state not containing the PCIe link);
  • the intelligent computing chip 102 is powered off.
  • the exit of L3 requires the main controller 200 to power on the edge computing module 100 again.
  • the power consumption state of the edge computing module is triggered and controlled by setting the state value of the register, and the state value of the register can be set through software as needed to control the power consumption of the edge computing module.
  • a control interface can be formed for user interaction; or a software interface can be formed for the scheduler in the main controller 200 to be called according to the number of computing tasks, thereby realizing a power consumption that can be actively controlled from the outside. control.
  • the above-mentioned edge computing module and its power consumption control method are aimed at the use in various scenarios.
  • the power consumption control of the edge computing module 100 is triggered by the autonomous power state change of the PCIe link.
  • the state value of the register in the edge computing module 100 is set by external software, so that the power state of the PCIe link changes , thereby triggering the power consumption control of the edge computing module 100, which is a software power consumption control solution. Therefore, the present application implements a software and hardware power consumption control solution, which triggers the edge computing module 100 to reduce power consumption when the power consumption of the PCIe link is reduced due to the change of the power state of the PCIe link.

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Abstract

本申请涉及一种边缘计算模组及其功耗控制方法。所述方法包括：当接收到来自PCIe控制器发出的状态变化中断信号时，获取边缘计算模组中的智能计算芯片所处的运行状态；判断所述智能计算芯片所处的运行状态是否与所述状态变化中断信号代表的PCIe链路电源状态匹配；若匹配，则根据预设功耗控制规则，由所述智能计算芯片所处的运行状态和PCIe链路电源状态获取边缘计算模组应进入的目标功耗状态；控制所述边缘计算模组进入所述目标功耗状态。上述边缘计算模组及其功耗控制方法根据PCIe链路的状态以及智能计算芯片的运行状态自动调节整个边缘计算模组的功耗，从而有效降低功耗、减少发热。

Description

边缘计算模组及其功耗控制方法
本申请要求于2021年6月17日提交中国专利局，申请号为202110669549.X、发明名称为“边缘计算模组及其功耗控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及边缘计算技术领域，特别是涉及一种边缘计算模组及其功耗控制方法。
背景技术
随着技术的发展，出现了采用边缘计算模组为主控器(例如服务器、工控机等)提供外部算力的方案。一方面边缘计算模组提供了可观的外部算力，但同时边缘计算模组具有一定的功耗，在提供计算力时也会产生大量的热量。传统技术方案中，主控器和边缘计算模组进行数据交互时，由于数据交互的大小，周期的不确定性，没有针对不同功耗状态进行控制，从而导致该类产品的系统功耗高、发热量大。
发明内容
基于此，有必要提供一种能够有效降低功耗且减少发热的边缘计算模组及其功耗控制方法。
为了实现本申请的目的，本申请采用如下技术方案：
一种边缘计算模组的功耗控制方法，包括：
当接收到来自PCIe控制器发出的状态变化中断信号时，获取边缘计算模组中的智能计算芯片所处的运行状态；
判断所述智能计算芯片所处的运行状态是否与所述状态变化中断信号代表的PCIe链路电源状态匹配；
若匹配，则根据预设功耗控制规则，由所述智能计算芯片所处的运行状态和PCIe链路电源状态获取边缘计算模组应进入的目标功耗状态；
控制所述边缘计算模组进入所述目标功耗状态。
一种边缘计算模组，通过PCIe接口与外部主控器连接，为所述主控器提供扩展的计算功能，所述边缘计算模组包括用于提供计算功能的智能计算芯片和对所述智能计算芯片提供支持的外围组件；所述智能计算芯片包括：
PCIe控制器，用于发出的状态变化中断信号；
电源管理单元，用于控制PCIe链路的电源状态；
智能计算子系统，用于提供计算功能；
低功耗控制单元，与所述PCIe控制器、所述电源管理单元、所述智能计算子系统相连，用于执行上述的方法。
上述边缘计算模组及其功耗控制方法根据状态变化中断信号获知PCIe链路的电源状态，并通过智能计算芯片所处的运行状态获知智能计算芯片整体负荷；当PCIe链路的电源状态改变降低功耗时，若智能计算芯片整体负荷也较低，表明所述智能计算芯片所处的运行状态与所述状态变化中断信号代表的PCIe链路电源状态匹配，从而控制所述边缘计算模组进入所述目标功耗状态，进而能有效降低所述边缘计算模组的整体功耗。由于边缘计算模组所处的功耗状态与边缘计算模组整体上的负荷相匹配，不会在没有计算任务或少量计算任务时也不恰当地产生热量，从而有效减少发热。
附图说明
图1a为两个PCIe设备通过PCIe协议进行连接的示意图；
图1b为本申请实施例中边缘计算模组与主控器组成的系统结构图；
图1c为PCIe协议的分层结构图；
图1d为LTSSM状态机的部分状态变化图；
图1e为本申请实施例中智能计算芯片以片上系统方式实现的组成结构图；
图2为一实施例中边缘计算模组的功耗控制方法流程图；
图3为图1的系统中的各状态联系及变化示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本 申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
图1a是两个PCIe(Peripheral Component Interconnect Express，高速外设部件互连标准)设备通过PCIe协议进行连接的示意图。两个或多个PCIe设备通过PCIe协议互联可以构成一个系统。根据PCIe协议，每个PCIe设备只能作为Root Complex(主控，RC)和Endpoint(端点，EP)中的一种，且一个系统中只能有一个主控设备，但可以有多个端点设备。主控设备可以发起对端点设备的配置命令，反过来则不行。
图1b为本申请实施例中边缘计算模组100与主控器200组成的系统结构图。请参考图1b，边缘计算模组100和主控器200通过PCIe接口连接。主控器200本身具有一定的计算能力，同时也通过接入外部的边缘计算模组100、使用边缘计算模组100提供的计算力，达到对主控器200自身计算能力的扩展的目的。每个主控器200上可以插接多个边缘计算模组100。结合图1a可以理解，边缘计算模组100为端点(EP)设备，主控器200则为主控(RC)设备。主控器200可以是服务器、工控机等。
请参考图1b，边缘计算模组100可以包括智能计算芯片102以及其他必要的对智能计算芯片102提供支持的外围组件，例如电源、外部存储等(图未示)。智能计算芯片102是边缘计算模组100中提供计算力的组件。
请参考图1b，智能计算芯片102可以包括低功耗控制单元104、PCIe控制器106、电源管理单元108以及智能计算子系统110。
PCIe控制器106通过PCIe接口与主控器200连接。在边缘计算模组100与主控器200进行基于PCIe协议的通信时，PCIe控制器106进行具体的通信控制。请参考图1c，PCIe协议定义了一种分层的结构，即PCIe控制器106按照图1c所示的分层结构进行设计和实现。具体地，该分层结构包括事务层、数据链路层和物理层。
事务层接收来自应用层的命令及数据，并封装为事务层包(Transaction Layer Package,TLP)然后发送给数据链路层；事务层或者还接收来自数据链路层的数据链路层包(Data Link Layer Package,DLLP)，并将数据链路层包解析为事务层包。事务层的职责包括事务通信，例如读数据、写数据等。
数据链路层用来将事务层包封装为数据链路层包然后发送给物理层，或者将来自物理层的串行数据封装为数据链路层包。数据链路层的职责包括错误检测(error detection)和错误纠正(error correction)。
物理层用来将数据链路层包进一步通过并串转换(parallel-to-serial conversion)以及电气处理后发送到PCIe链路上，并通过PCIe链路传送到对端。物理层或者通过PCIe链路接收信号，然后通过电气处理得到串行数据，通过串并转换(serial-to-parallel conversion)为并行数据后发送给数据链路层。
PCIe链路是PCIe设备之间的通信通道。PCIe链路的基本结构是分别传送两个差分信号对(differentially driven signal pair)的差分链路对(Lanes)。即发送链路(Transmit Lane)传送发送对(transmit pair)、接收链路(Receive Lane)传送接收对(receive pair)。PCIe链路可以包括多条上述基本的差分链路对，例如1条、2条、4条、8条、12条、16条以及32条等。用x1、x2、x4、x8、x12、x16、x32表示通信通道的宽度。
当主控器200需要进行计算任务时，通过调用主控器200的PCIe控制器，将计算任务相关的命令和数据通过事务层封装为事务层包，然后通过数据链路层将事务层包封装为数据链路层包，物理层将数据链路层包进行电气处理后通过PCIe链路发出。边缘计算模组100通过PCIe链路接收数据，并利用PCIe控制器106从物理层、数据链路层和事务层逐层进行解析，最终获得要进行计算任务的相关的命令和数据，然后发送给智能计算子系统110。在智能计算子系统110计算完成后，调用PCIe控制器106按上述路径相反的方向返回数据。
电源管理单元108包括对PCIe协议所规定的活动状态链路电源管理(Active State Link PM,ASPM)和软件控制的电源管理(PCI-PM)的实现。一般地，通过驱动程序实现ASPM和PCI-PM的控制逻辑。PCIe协议提供5种PCIe链路的电源状态(Link Power Management State)，包括：
L0：正常工作状态(激活状态，Active State)。在L0状态下，所有的PCIe事务(transaction)和操作(operation)均可用。
L0s：低延迟恢复且节能的等待状态。在L0s状态下，支持PCIe链路的主电源、时钟以及锁相回路都处于激活状态。事务层包和数据链路层包的传送不可用。
L1：高延迟恢复且低功率的等待状态。在L1状态下，支持PCIe链路的主 电源处于激活状态，锁相回路可以被关闭。
L2：链路由辅助电源供电且深度节能的状态。在L2状态下，支持PCIe链路的主电源、时钟都被关闭。由辅助电源供电。
L3：链路断电状态。在L3状态下，没有任何供电。
在PCIe设备的物理层的逻辑子层(Logic Sub Block)中，具有LTSSM(Link training and status state machine，链接训练和状态)状态机。PCIe设备使用该LTSSM状态机管理PCIe链路状态。LTSSM状态机管理5类状态：链路训练状态(Training States)、重训练状态(Re-Training State)、软件驱动功耗管理状态(Power Management States)、活动状态功耗管理状态(ASPM States)以及除上述4类之外的其他状态。
本申请中，PCIe链路的工作状态变化主要涉及软件驱动功耗管理状态(Power Management States)的变化和活动状态功耗管理状态(ASPM States)的变化。其中，软件驱动功耗管理状态(Power Management States)包括软件控制第一功耗状态PM L1、软件控制第二功耗状态PM L2、软件控制第三功耗状态PM L3。活动状态功耗管理状态(ASPM States)包括自主电源管理第零功耗状态ASPM L0s、自主电源管理第一功耗状态ASPM L1。
即LTSSM状态机支持PCIe链路在L0、L0s、L1、L2这四个状态之间的变化(L3完全断电，不进入LTSSM状态机)。其中进入到L1状态可以是自主变化(ASPM控制)，也可以是软件控制(PCI-PM控制)。根据LTSSM状态机，可以管理PCIe链路的电源状态变化，即根据何种条件将PCIe链路的电源状态进行改变，同时获得PCIe链路的电源状态改变的消息以及PCIe链路改变后的电源状态。
请参考图1d，是LTSSM状态机的部分状态变化图(为便于说明，简化了其他本申请中不涉及的状态)。如图1d所示，PCIe链路的电源状态可以从L0进入L0s、L1、L2以及恢复状态，从L0s进入L0、从L1进入恢复状态以及从L2进入探测状态。
对电源管理单元108实现ASPM而言，以从L0进入ASPM L1为例进行说明。具体到本申请，在L0状态下，边缘计算模组100物理层检测PCIe链路上一定的空闲时间。这个空闲时间长度依赖于具体实现，通常是7-10us。电源管理单元108的控制逻辑如下：
A、边缘计算模组100准备使PCIe链路进入L1状态，同时主控器200应处 于活动状态。
B、使边缘计算模组100的PCIe控制器106中的事务层置于非活动状态，从而阻塞新的事务层包(TLP)。
C、使PCIe控制器106中数据链路层重复发送“进入L1状态请求”(PM_Active_State_Request_L1)数据，该数据通过数据链路层包(DLLP)发送。
D、等待主控器200对“进入L1状态请求”的响应。此时主控器200一方面会阻塞新的事务层包，一方面会重复发送“请求确认”(PM_Request_Ack)数据，同样通过数据链路层包(DLLP)发送。
E、将数据链路层置于非活动状态以及将物理层置于电气空闲状态。此后主控器200也将PCIe控制器中的数据链路层置于非活动状态以及将物理层置于电气空闲状态。
至此，PCIe链路进入L1状态完成。由于是物理层检测PCIe链路的空闲状态引起电源状态的改变，因此ASPM实现了硬件自治(Hardware-autonomous)的、动态的PCIe链路电源管理。
此外，对于ASPM而言，作为运行于所述PCIe设备之上的操作系统的驱动程序读取PCIe设备配置空间中的链路功能寄存器(Link Capabilities Register)，获取该链路功能寄存器位[11:10]的组合了解PCIe设备对ASPM的支持情况，[11:10]＝01表示支持ASPM L0s，[11:10]＝11表示同时支持ASPM L0s和ASPM L1。驱动程序还可以设置PCIe设备配置空间中的链路控制寄存器(Link Control Register)来启用或禁用ASPM L0s和/或ASPM L1。链路控制寄存器位[1:0]的组合表示启用情况。[1:0]＝01表示启用了ASPM L0s，禁用ASPM L1；[1:0]＝10表示禁用了ASPM L0s，启用了ASPM L1；[1:0]＝11表示同时启用了ASPM L0s和ASPM L1。
智能计算子系统110用来提供计算功能，可以包括智能计算加速处理器，例如神经网络处理器。智能计算加速处理器可以对智能计算中的常用运算提供专用指令，从而比通用架构的处理器的运算速度更快。例如在神经网络计算中，常用的计算为卷积计算，则在神经网络处理器中提供为卷积计算进行加速的指令。
低功耗控制单元104用于监控智能计算芯片102的运行状态并结合PCIe链路的电源状态调整边缘计算模组100的功耗状态，实现本申请中边缘计算模 组100的功耗控制。智能计算芯片102的运行状态包括智能计算芯片102整体上的负荷以及智能计算子系统110的计算负荷、忙闲情况等。可以理解，智能计算子系统110的计算负荷、忙闲情况可能会影响智能计算芯片102整体上的负荷，但不等于智能计算芯片102整体上的负荷。
在一个实施例中，上述智能计算芯片102可以采用片上系统(System on Chip,Soc)来实现。在智能计算芯片102采用Soc实现时，如图1e所示，智能计算芯片102可以包括主处理器112、PCIe控制器106、系统控制器(其中包括电源管理单元108)、智能计算子系统110(例如包括神经网络处理器)、低功耗控制单元104、其他的子系统以及总线。主处理器112、PCIe控制器106、系统控制器、智能计算子系统110以及其他的子系统都通过总线114连接和通信。
主处理器112是整个智能计算芯片102的核心，主处理器112用于管理调度各子模块或子系统(包括PCIe控制器106、系统控制器、智能计算子系统110以及其他的子系统)。通常地，PCIe控制器106可以包含在主处理器112中。当然，在一些实施例中，PCIe控制器106也可以不包括在主处理器112中。
系统控制器负责智能计算芯片102中的系统级的控制，例如总线控制、存储控制等。系统控制器中可以包括电源管理单元108。
智能计算子系统110用来执行特定计算任务，例如神经网络计算。
其他子系统用于提供其他功能，可以以IP核的形式实现，根据边缘计算模组100的应用需求设置。对于专用的智能计算芯片102，其他子系统也可以没有。
结合图1e和图1b，当主控器200通过PCIe链路向边缘计算模组100发送计算任务时，主处理器112调用PCIe控制器106进行具体的数据接收，主处理器112将计算任务调度给智能计算子系统110进行具体执行。主处理器112在智能计算子系统110完成计算任务后，调用PCIe控制器106计算结果通过PCIe链路发回给主控器200。
低功耗控制单元104在智能计算芯片102的运行过程中，监控主处理器112的负荷、总线114的负荷、智能计算子系统110的计算负荷、其他子系统的负荷以及PCIe链路的电源状态等。当低功耗控制单元104监控到智能计算芯片102的运行状态和PCIe链路的电源状态符合一定的条件时，发出相应的系统功耗调整信号，由主处理器112调整智能计算芯片102的运行情况，例如调整电 源模组的电压、调整主处理器112自身的运行频率、调整总线114频率、关闭或唤醒智能计算子系统110或其他子系统等。从而实现调整边缘计算模组100的功耗控制。
基于上述结构，提供一种边缘计算模组的功耗控制方法，该方法描述所述低功耗控制单元104进行功耗控制的逻辑。如图2所示，所述边缘计算模组的功耗控制方法包括以下步骤：
步骤S202：当接收到来自PCIe控制器106发出的状态变化中断信号时，获取边缘计算模组100中的智能计算芯片102所处的运行状态。
根据LTSSM状态机可以获取PCIe链路的电源状态的变化，当PCIe链路的电源状态发生变化时，PCIe控制器106根据情况会向低功耗控制单元104发出相应的状态变化中断信号。
当低功耗控制单元104收到状态变化中断信号时，需要与智能计算芯片102通信以获取其当前所处的运行状态。智能计算芯片102根据其所承载的计算任务的情况，也会处于不同的运行状态。结合图1e，低功耗控制单元104可以采用硬件实现，并集成在实现智能计算芯片102的Soc芯片中，并且在智能计算芯片102的各个层次(包括子处理器层次、子系统层次、总线层次、主处理器层次等)采集信息，从而了解智能计算芯片102当前所处的运行状态。采集智能计算芯片102的信息可以主动进行，也可以被动接收。例如智能计算芯片102在各个采集信息的层次中设置判断逻辑，当条件满足时，通知低功耗控制单元104。具体地，智能计算芯片102可以采用中断通知低功耗控制单元104。
本申请实施例中，对智能计算芯片102的运行状态分别定义如下：
芯片正常运行状态C0：智能计算芯片102进行正常工作时所处的状态。
芯片第零运行状态C0s：智能计算芯片102的整体负荷不高，例如不高于60％。智能计算芯片102具备对主处理器112和总线114降频的条件，即在降频后不影响当前计算任务的执行。
芯片第一运行状态C1：智能计算芯片102的整体负荷偏低，例如不高于30％。智能计算芯片102具备对主处理器112、总线114和大部分模块(包括智能计算子系统110)降频的条件，即在降频后不影响当前计算任务的执行。
芯片第二运行状态C2：智能计算芯片102空闲，满足使智能计算芯片102进入睡眠状态的条件。
芯片第三运行状态C3：智能计算芯片102断电。
步骤S204：判断所述智能计算芯片所处的运行状态是否与所述状态变化中断信号代表的PCIe链路电源状态匹配。
智能计算芯片102的运行状态是进行功耗控制的客观条件。所述的匹配是指，智能计算芯片所处的运行状态可以满足使边缘计算模组100改变到一种功耗状态，该功耗状态对应于PCIe链路的电源状态。当所述智能计算芯片所处的运行状态与所述状态变化中断信号代表的PCIe链路电源状态匹配时，表明此时具备了将边缘计算模组进行相应的功耗控制的条件。由于PCIe链路的电源状态代表了数据传输的活跃度，而智能计算芯片102的运行状态则代表数据处理的活跃度。只有当两者匹配时，才能将整个边缘计算模组控制到相应的目标功耗状态。例如当智能计算子系统110的计算负荷较高时，表明智能计算正在进行，但计算任务相关的数据早已传输完成，PCIe链路上没有数据传输，此时PCIe链路可能会进入低功耗状态，例如ASMP L0s或ASMP L1。但此时智能计算芯片102仍需维持正常的供电，以保障为了保障智能计算子系统110的计算任务。当智能计算子系统110完成计算任务后，如果没有新的计算任务，则会空闲。在PCIe控制器106将计算结果发送完成后，也会再次进入低功耗状态。此时，边缘计算模组100既没有在进行智能计算，也没有在进行数据传输，整体上处于空闲状态。此时可以将电源电压降低、主处理器112的频率降低、总线114频率降低、将智能计算子系统110休眠等，来达到降低边缘计算模组100的功耗的目的。
本申请实施例中，对PCIe链路的电源状态分别定义如下：
链路正常工作状态L0：PCIe链路进行正常工作时所处的状态、
自主电源管理第零功耗状态ASPM L0s：PCIe链路在短暂空闲时的低功耗状态，符合上述PCIe协议对L0s的要求。
自主电源管理第一功耗状态ASPM L1：PCIe链路比自主电源管理第一功耗状态ASPM L0s功耗更低的低功耗状态，符合上述PCIe协议对L1的要求。
软件控制第一功耗状态PM L1：由软件控制进入的L1状态，符合上述PCIe协议对L1的要求。
软件控制第二功耗状态PM L2：由软件控制进入的L2状态，符合上述PCIe协议对L2的要求。
软件控制第三功耗状态PM L3：由软件控制进入的L3状态，符合上述PCIe协议对L3的要求。
步骤S206：若匹配，则根据预设功耗控制规则，由所述智能计算芯片所处的运行状态和PCIe链路电源状态获取边缘计算模组应进入的目标功耗状态。
本申请实施例中，边缘计算模组的应进入的目标功耗状态分别定义如下：
模组正常工作状态S0：边缘计算模组100进行正常工作时所处的状态，支持智能计算芯片102正常工作。
模组第零功耗状态S0s：边缘计算模组100在短暂空闲时的低功耗状态，支持智能计算芯片102在对主处理器112和总线114降频后的低功耗状态下工作。
模组第一功耗状态S1：比模组第零功耗状态S0s功耗更低的低功耗状态。支持智能计算芯片102在对主处理器112、总线114和大部分模块(包括智能计算子系统110)降频后的低功耗状态下工作。
模组第二功耗状态S2：智能计算芯片102处于休眠的状态。边缘计算模组100在模组第二功耗状态S2下支持智能计算芯片102休眠及后续的唤醒。
模组第三功耗状态S3：智能计算芯片102处于断电的状态。边缘计算模组100在模组第三功耗状态S3下支持智能计算芯片102处于断电状态及后续的上电。
根据步骤S202中所定义的运行状态和步骤204中定义的PCIe链路的电源状态，可以预先设置匹配关系，以及对应的边缘计算模组应进入的目标功耗状态得到预设功耗控制规则。
所述预设功耗控制规则如下表1：
Figure PCTCN2022099219-appb-000001
表1
由表1可知，当PCIe链路电源状态为L0时，若检测到智能计算芯片102的运行状态为C0，则边缘计算模组应进入的目标功耗状态被设置为S0。
当PCIe链路电源状态为ASPM L0s时，若检测到智能计算芯片102的功耗状态为C0s，则边缘计算模组应进入的目标功耗状态被设置为S0s。以此类推。
步骤S208：控制所述边缘计算模组进入所述目标功耗状态。
上述方法根据状态变化中断信号获知PCIe链路的电源状态，通过智能计算芯片所处的运行状态获知智能计算芯片整体负荷；当PCIe链路的电源状态改变降低功耗时，若智能计算芯片整体负荷也较低，表明可以降低智能计算芯片的功耗，避免智能计算芯片部分计算能力空闲，从而使边缘计算模组的整体功耗也相应降低。
PCIe链路的电源状态与数据传输相关，当数据通过PCIe链路传输时，PCIe链路的电源状态是正常工作状态，当没有数据传输时，PCIe链路的电源状态将进入低功耗状态；或者在没有计算任务时，对边缘计算模组进行设置，也会使PCIe链路的电源状态进入低功耗状态；这两种情况都说明数据的传输影响PCIe链路的电源状态。
数据传输是智能计算芯片工作的前提，若没有数据处理，智能计算芯片将会空闲；若处理数据量较少，则负荷较低；若处理数据量较大，则负荷较高。因此，数据传输影响数据处理。也即处理数据的负荷是跟随数据传输的。以PCIe链路的电源状态的变化为时机，获知智能计算芯片的整体负荷，然后根据预设的功耗控制规则进行功耗控制，使得边缘计算模组可以在计算任务较多时，正常工作，而在计算任务较少时，降低功耗，从而避免了功耗的浪费。也即智能计算芯片的计算能力被比较好地利用。
由于边缘计算模组所处的功耗状态与边缘计算模组整体上的负荷相匹配，不会在没有计算任务或少量计算任务时也不恰当地产生热量，从而有效减少发热。
在一个实施例中，所述状态变化中断信号包括：进入第零功耗状态中断、进入第一功耗状态中断、第一软件控制中断、第二软件控制中断、第三软件控制中断。所述进入第零功耗状态中断及所述进入第一功耗状态中断由所述PCIe链路电源状态变化触发所述PCIe控制器106发出；所述第一软件控制中断、所述第二软件控制中断及所述第三软件控制中断由所述PCIe控制器106根据所述PCIe控制器106中的状态寄存器被写入的状态值发出。所述低功耗控制单元104接收该状态变化中断信号，以了解PCIe链路的状态，并结合智能计算芯片102的运行状态，即可对边缘计算模组100进行功耗管理。
在一个实施例中，结合表2和图3，所述PCIe链路在无数据传输时，进入自主电源管理第零功耗状态ASPM L0s，触发所述PCIe控制器106发出进入第零功耗状态中断；当智能计算芯片102处于与所述自主电源管理第零功耗状态匹配的芯片第零运行状态C0s时，则获取模组第零功耗状态S0s作为目标功耗状态，并控制边缘计算模组进入模组第零功耗状态S0s。
所述自主电源管理第零功耗状态ASPM L0s为PCIe硬件(本申请中，可以是主控器200或者边缘计算模组100，即任一方都能使PCIe链路的电源状态进入ASPM L0s)自主的第一链路低功耗状态，由PCIe设备自主设置，自动触发。当主控器200或者边缘计算模组100在一定时间内没有数据传输时候，PCIe链路会自动进入ASPM L0s，PCIe链路功耗相对下降。
在所述芯片第零运行状态C0s下，所述智能计算芯片102的整体负荷低于第一阈值，在一个实施例中，所述第一阈值可以为60％，在该状态下，系统可以进行降频(主要是主处理器112和总线114可以降频)。
在所述模组第零功耗状态S0s下，所述智能计算芯片102中的主处理器112和总线114处于降频状态。
即
Figure PCTCN2022099219-appb-000002
表2
在一个实施例中，结合表3和图3，当满足以下条件之一时，PCIe链路进入自主电源管理第一功耗状态ASPM L1：
1)所述PCIe链路处于自主电源管理第零功耗状态ASPM L0s第一预设时长；或
2)所述PCIe链路处于正常工作状态L0，在无数据传输情况下未进入自主电源管理第零功耗状态ASPM L0s，且保持第二预设时长；或
3)边缘计算模组100在智能计算芯片102完成计算任务后，请求使PCIe 链路进入所述自主电源管理第一功耗状态ASPM L1。
当所述PCIe链路进入自主电源管理第一功耗状态ASPM L1时，触发所述PCIe控制器106发出进入第一功耗状态中断；
当智能计算芯片102处于与所述自主电源管理第一功耗状态ASPM L1匹配的芯片第一运行状态C1时，则获取模组第一功耗状态S1作为目标功耗状态，并控制边缘计算模组100进入模组第一功耗状态S1。
所述自主电源管理第一功耗状态ASPM L1为PCIe设备(本申请中，是边缘计算模组100)自主的第二链路低功耗状态，由PCIe设备自主设置，自动触发。是比ASPM L0s更进一步的低功耗状态(功耗更低)。
在所述芯片第一运行状态C1下，所述智能计算芯片102的整体负荷低于第二阈值，例如30％，在该状态下，系统可以进行降频(包括主处理器112、总线114和大部分子系统，例如智能计算子系统110)；
在所述模组第一功耗状态S1下，所述智能计算芯片102中的主处理器112、总线114、智能计算子系统110处于降频状态。
即
Figure PCTCN2022099219-appb-000003
表3
当主控器200或者边缘计算模组100有新的数据传输时候，或者主动请求退出ASPM L1，PCIe链路可以在一定时间内恢复到L0。ASPM L1的进入和退出可以由PCIe控制器106在硬件上通知低功耗控制单元104。ASPM L1恢复到L0的时间最大可达64us。
在上述两种状态(ASPM L0s、ASPM L1)下，当PCIe链路有新的数据传输时，PCIe链路退出自主电源管理第零功耗状态ASPM L0s或自主电源管理第一 功耗状态ASPM L1，并进入正常工作状态L0，触发所述PCIe控制器106发出退出第零功耗状态中断或退出第一功耗状态中断。进而由低功耗控制单元104通知主处理器112后，由主处理器112控制所述边缘计算模组退出模组第零功耗状态S0s，并进入正常工作状态S0。在有数据传输时即可保障数据传输。
在一个实施例中，为所述退出自主电源管理第零功耗状态ASPM L0s或自主电源管理第一功耗状态ASPM L1设置退出延时(Exit latency)，以匹配所述边缘计算模组100退出模组第零功耗状态S0s的时间。该退出延时可以调整。
在上述实施例中，边缘计算模组100的功耗状态由PCIe链路自身的状态触发控制。因为PCIe协议本身定义了PCIe链路的各种状态，边缘计算模组100连接在主控器200上时，工作状态会使PCIe链路的电源状态发生变化，充分利用硬件状态变化触发功耗控制，实现了一种自动功耗控制。
在一个实施例中，所述第一软件控制中断、所述第二软件控制中断及所述第三软件控制中断由所述PCIe控制器根据所述PCIe控制器中的状态寄存器被写入的状态值发出，并且PCIe链路根据状态寄存器的状态值和PCIe链路的电源状态进入不同的软件控制功耗状态；
状态寄存器的状态值代表的是设备电源管理状态(Device Power Management State,D-State)，包括D0、D1、D2、D3hot、D3cold等。根据PCIe协议，PCIe链路的电源状态由下行设备(Downstream component，当前接收数据的设备)的电源管理状态决定。关系如下：
Figure PCTCN2022099219-appb-000004
在下行设备处于D0状态时，如果上行设备也处于D0状态，在PCIe链路的电源状态可以在L0、L0s、L1、L2之间转换。
在下行设备的状态寄存器的状态值被设置为D1时，上行设备的电源管理值必须由D0转换到D1。且PCIe链路的电源状态必须为L1或L2，并且能够在L1 和L2之间转换。为下行设备的状态寄存器设置其他D值时，过程类似。
其中，所述状态寄存器由与边缘计算模组100连接的主控器200写入状态值。在PCIe控制器106中设有状态寄存器，状态寄存器的状态值值可以为D1/D2/D3hot这3种状态值，设置D1/D2/D3hot后，PCIe链路根据状态寄存器的状态值和PCIe链路的电源状态使PCIe链路进入不同的电源状态。由于该对状态寄存器的状态值的设置可以由主控器200上层的软件进行设置，因此将PCIe链路进入的功耗状态称为软件控制功耗状态PM Lx。
在一个实施例中，结合表4和图3，当所述状态寄存器被写入的状态值为第一状态值时，触发所述PCIe控制器106发出第一软件控制中断，PCIe链路进入软件控制第一功耗状态PM L1。当智能计算芯片102处于与所述软件控制第一功耗状态PM L1匹配的芯片第一运行状态C1时，则获取模组第一功耗状态S1作为目标功耗状态，并控制边缘计算模组进入模组第一功耗状态S1。
所述软件控制第一功耗状态PM L1为通过所述第一状态值(通常为D1)设置边缘计算模组100的设备电源状态时触发的PCIe链路低功耗状态。
在所述芯片第一运行状态C1下，所述智能计算芯片102的整体负荷低于前述的第二阈值，在一个实施例中，所述第二阈值可以为30％，所述第二阈值小于所述第一阈值。在该状态下，系统可以进行降频(包括主处理器112、总线114和大部分子系统，例如智能计算子系统110)；
在所述模组第一功耗状态S1下，所述智能计算芯片102中的主处理器112、总线114、智能计算子系统110处于降频状态。
即
Figure PCTCN2022099219-appb-000005
表4
在一个实施例中，结合表5和图3，当所述状态寄存器被写入的状态值为第二状态值时，触发所述PCIe控制器106发出第二软件控制中断，PCIe链路进入软件控制第二功耗状态PM L2。当智能计算芯片102处于与所述软件控制第二功耗状态PM L2匹配的芯片第二运行状态C2时，则获取模组第二功耗状态S2作为目标功耗状态，并控制边缘计算模组进入模组第二功耗状态S2。
所述软件控制第二功耗状态PM L2为通过所述第二状态值(通常为D2)设置边缘计算模组100的设备电源状态时触发的PCIe链路低功耗状态，是当主控器200的电源管理软件发起主电源断电和参考时钟禁能操作时，同时边缘计算模组100具有辅助电源供电时的PCIe链路的低功耗状态。软件控制第二功耗状态PM L2下边缘计算模组100仅有且必须有辅助电源供电，处于极低功耗的状态。
在所述芯片第二运行状态C2下，所述智能计算子系统110等都处于空闲状态，没有进行计算任务，主处理器112没有或者很少调度；
在所述模组第二功耗状态S2下，所述智能计算芯片102进入睡眠状态(sleep)。
即
Figure PCTCN2022099219-appb-000006
表5
L2的退出需要主控器200发起唤醒。L2恢复到L0需要重新链路训练，恢复时间为10ms以上。
在一个实施例中，结合表6和图3，当所述状态寄存器被写入的状态值为第三状态值时，触发所述PCIe控制器106发出第三软件控制中断，PCIe链路进入软件控制第三功耗状态PM L3；当智能计算芯片102处于与所述软件控制第三功耗状态PM L2匹配的芯片第三运行状态C3时，则获取模组第三功耗状态S3作为目标功耗状态，并控制边缘计算模组进入模组第三功耗状态S3。
所述软件控制第三功耗状态PM L3为通过所述第三状态值(通常为D3hot)设置边缘计算模组100的设备电源状态时触发的PCIe链路低功耗状态；是当主控器200的电源管理软件发起断电操作时PCIe链路的电源状态。
在所述芯片第三运行状态C3下，所述智能计算子系统110等都处于断电状态(不含PCIe链路的电源状态)；
在所述模组第三功耗状态S3下，所述智能计算芯片102断电。
即
Figure PCTCN2022099219-appb-000007
表6
L3的退出需要主控器200重新对边缘计算模组100上电。
在上述实施例中，边缘计算模组的功耗状态由设置寄存器的状态值触发控制，可以根据需要通过软件的方式对寄存器设置状态值，对边缘计算模组进行功耗控制，而通过软件的方式则可以形成控制界面，提供给用户交互；或者形成软件接口，提供给主控器200中的调度程序，根据计算任务的多少来调用，从而实现了一种可以从外部进行主动控制的功耗控制。
上述边缘计算模组及其功耗控制方法，针对在各个场景下的使用，在利用ASPM方式触发控制时机的方案中，由PCIe链路的自主电源状态变化触发边缘计算模组100的功耗控制，这是一种硬件的功耗控制方案；在利用PCI-PM方式触发控制时机的方案中，通过外部软件设置边缘计算模组100中的寄存器的状态值，使PCIe链路的电源状态发生变化，从而触发边缘计算模组100的功耗控制，这是一种软件的功耗控制方案。因此本申请实现了一种软硬件的功耗控制方案，均通过PCIe链路的电源状态的变化导致功耗降低时，触发对边缘计算模组100降低功耗。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基 本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种边缘计算模组的功耗控制方法，包括：
    当接收到来自PCIe控制器发出的状态变化中断信号时，获取边缘计算模组中的智能计算芯片所处的运行状态；
    判断所述智能计算芯片所处的运行状态是否与所述状态变化中断信号代表的PCIe链路电源状态匹配；
    若匹配，则根据预设功耗控制规则，由所述智能计算芯片所处的运行状态和所述PCIe链路电源状态获取所述边缘计算模组应进入的目标功耗状态；
    控制所述边缘计算模组进入所述目标功耗状态。
  2. 根据权利要求1所述的边缘计算模组的功耗控制方法，其特征在于，所述状态变化中断信号包括：进入第零功耗状态中断、进入第一功耗状态中断、第一软件控制中断、第二软件控制中断、第三软件控制中断；所述进入第零功耗状态中断及所述进入第一功耗状态中断由所述PCIe链路电源状态变化触发所述PCIe控制器发出；所述第一软件控制中断、所述第二软件控制中断及所述第三软件控制中断由所述PCIe控制器根据所述PCIe控制器中的状态寄存器被写入的状态值发出。
  3. 根据权利要求2所述的边缘计算模组的功耗控制方法，其特征在于，所述方法还包括：所述PCIe链路在无数据传输时，进入自主电源管理第零功耗状态，触发所述PCIe控制器发出所述进入第零功耗状态中断；
    当所述智能计算芯片处于与所述自主电源管理第零功耗状态匹配的芯片第零运行状态时，则获取模组第零功耗状态作为目标功耗状态，并控制边缘计算模组进入所述模组第零功耗状态；
    所述自主电源管理第零功耗状态为PCIe设备自主的第一链路低功耗状态；
    在所述芯片第零运行状态下，所述智能计算芯片的整体负荷低于第一阈值；
    在所述模组第零功耗状态下，所述智能计算芯片中的主处理器和总线处于降频状态。
  4. 根据权利要求2所述的边缘计算模组的功耗控制方法，其特征在于，所述方法还包括：当满足以下条件之一时，所述PCIe链路进入自主电源管理第一功耗状态：
    所述PCIe链路处于自主电源管理第零功耗状态达到第一预设时长；
    所述PCIe链路处于正常工作状态，在无数据传输情况下未进入自主电源管 理第零功耗状态，且保持第二预设时长；
    所述边缘计算模组在所述智能计算芯片完成计算任务后，请求使所述PCIe链路进入所述自主电源管理第一功耗状态；
    所述方法还包括：当所述PCIe链路进入所述自主电源管理第一功耗状态时，触发所述PCIe控制器发出所述进入第一功耗状态中断；
    当所述智能计算芯片处于与所述自主电源管理第一功耗状态匹配的芯片第一运行状态时，则获取所述模组第一功耗状态作为目标功耗状态，并控制所述边缘计算模组进入所述模组第一功耗状态；
    所述自主电源管理第一功耗状态为PCIe硬件自主的第二链路低功耗状态；
    在所述芯片第一运行状态下，所述智能计算芯片的整体负荷低于第二阈值；
    在所述模组第一功耗状态下，所述智能计算芯片中的主处理器、总线、智能计算子系统处于降频状态。
  5. 根据权利要求2所述的边缘计算模组的功耗控制方法，其特征在于，所述PCIe链路根据所述状态寄存器的所述状态值从所述PCIe链路当前所处的电源状态进入不同的软件控制功耗状态；所述状态值由与所述边缘计算模组相连的主控器写入所述状态寄存器。
  6. 根据权利要求5所述的边缘计算模组的功耗控制方法，其特征在于，所述方法还包括：当所述状态寄存器被写入的状态值为第一状态值时，触发所述PCIe控制器发出所述第一软件控制中断，所述PCIe链路进入软件控制第一功耗状态；
    当智能计算芯片处于与所述软件控制第一功耗状态匹配的芯片第一运行状态时，则获取模组第一功耗状态作为目标功耗状态，并控制边缘计算模组进入模组第一功耗状态；
    所述软件控制第一功耗状态为通过所述第一状态值设置所述边缘计算模组的设备电源状态时触发的PCIe链路低功耗状态；
    在所述芯片第一运行状态下，所述智能计算芯片的整体负荷低于第二阈值；
    在所述模组第一功耗状态下，所述智能计算芯片中的主处理器、总线、智能计算子系统处于降频状态。
  7. 根据权利要求5所述的边缘计算模组的功耗控制方法，其特征在于，所述方法还包括：当所述状态寄存器被写入的状态值为第二状态值时，触发所述PCIe控制器发出所述第二软件控制中断，所述PCIe链路进入软件控制第二功 耗状态；
    当智能计算芯片处于与所述软件控制第二功耗状态匹配的芯片第二运行状态时，则获取模组第二功耗状态作为目标功耗状态，并控制边缘计算模组进入模组第二功耗状态；
    所述软件控制第二功耗状态为通过所述第二状态值设置所述边缘计算模组的设备电源状态时触发的PCIe链路低功耗状态；
    在所述芯片第二运行状态下，所述智能计算芯片处于空闲状态；
    在所述模组第二功耗状态下，所述智能计算芯片进入睡眠状态。
  8. 根据权利要求5所述的边缘计算模组的功耗控制方法，其特征在于，所述方法还包括：当所述状态寄存器被写入的状态值为第三状态值时，触发所述PCIe控制器发出所述第三软件控制中断，PCIe链路进入软件控制第三功耗状态；
    当智能计算芯片处于与所述软件控制第三功耗状态匹配的芯片第三运行状态时，则获取模组第三功耗状态作为目标功耗状态，并控制边缘计算模组进入模组第三功耗状态；
    所述软件控制第三功耗状态为通过所述第三状态值设置所述边缘计算模组的设备电源状态时触发的PCIe链路低功耗状态；
    在所述芯片第三功耗状态下，所述智能计算芯片断电；
    在所述模组第三功耗状态下，所述智能计算芯片断电。
  9. 根据权利要求3或4所述的边缘计算模组的功耗控制方法，其特征在于，当所述PCIe链路有新的数据传输时，所述PCIe链路退出所述自主电源管理第零功耗状态或所述自主电源管理第一功耗状态，进入正常工作状态，并触发所述PCIe控制器发出退出第零功耗状态中断或退出第一功耗状态中断；
    若所述PCIe控制器发出所述退出所述第零功耗状态中断，则控制所述边缘计算模组退出模组第零功耗状态，并进入正常工作状态；
    若所述PCIe控制器发出所述退出第一功耗状态中断，则控制所述边缘计算模组退出模组第一功耗状态，并进入正常工作状态。
  10. 一种边缘计算模组，通过PCIe接口与外部主控器连接，为所述主控器提供扩展的计算功能，其特征在于，所述边缘计算模组包括用于提供计算功能的智能计算芯片和对所述智能计算芯片提供支持的外围组件；所述智能计算芯片包括：
    PCIe控制器，用于发出的状态变化中断信号；
    电源管理单元，用于控制PCIe链路的电源状态；
    智能计算子系统，用于提供计算功能；
    低功耗控制单元，与所述PCIe控制器、所述电源管理单元、所述智能计算子系统相连，用于执行权利要求1-10任一项所述的方法。
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