WO2019104947A1 - 系统级芯片、通用串行总线主设备、系统及唤醒方法 - Google Patents

系统级芯片、通用串行总线主设备、系统及唤醒方法 Download PDF

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Publication number
WO2019104947A1
WO2019104947A1 PCT/CN2018/086309 CN2018086309W WO2019104947A1 WO 2019104947 A1 WO2019104947 A1 WO 2019104947A1 CN 2018086309 W CN2018086309 W CN 2018086309W WO 2019104947 A1 WO2019104947 A1 WO 2019104947A1
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Prior art keywords
usb
soc
bus
level
cpu
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PCT/CN2018/086309
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English (en)
French (fr)
Inventor
钱进
任博
刘宇
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华为技术有限公司
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Publication of WO2019104947A1 publication Critical patent/WO2019104947A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of electronic communications, and in particular, to a system-on-a-chip, a universal serial bus master, a system, and a wake-up method.
  • USB 2.0 protocol specifies that the USB 2.0 bus contains two D+, D- data lines that enter a low-power state when idle. After entering the low power state, either the USB master device and the USB slave device can initiate recovery. When the system enters a low-power state, the bus level can be monitored by the Universal Serial Bus Physical Layer Protocol (USB PHY) and the USB controller. Once the wake-up signal appears, the recovery data is immediately entered. The flow of communication. In the process of low power consumption, since the USB controller and the USB PHY part of the circuit are always in the power-on state, the power consumption is continuously consumed, resulting in a large power consumption of the USB host device.
  • USB PHY Universal Serial Bus Physical Layer Protocol
  • the embodiment of the present application provides a system-level chip, a universal serial bus master device, a system, and a wake-up method, which can power down the USB PHY and the USB controller when the bus enters a low power state, thereby saving power consumption.
  • the embodiment of the present application provides a system-level chip SOC, including: a system wake-up control module, a processor CPU, a USB controller, and a universal serial bus physical layer module USB PHY; wherein:
  • the system wake-up control module is configured to power down the CPU, the USB controller, and the USB PHY after the SOC receives an instruction to indicate entering a low power consumption state;
  • the system wake-up control module is further configured to power on the CPU, the USB controller, and the USB PHY after the SOC receives an instruction to indicate to exit the low power consumption state.
  • the CPU, the USB controller, and the USB PHY are powered off after the SOC receives the low power consumption state, thereby saving power consumption.
  • the SOC is further configured to maintain a power of the target bus by the bus hold circuit after the SOC receives an instruction for indicating to enter a low power consumption state
  • the bus hold circuit includes a system wake-up controller or a pull-down resistor, and the target bus is a bus between the SOC and a USB slave device.
  • the bus hold circuit keeps the bus level unchanged after entering the low power consumption state, so that the USB controller and the USB PHY can be powered off.
  • the receiving, by the SOC, an instruction for indicating to enter a low power consumption state includes: detecting, by the SOC, the target bus The level does not change within the preset time period.
  • the embodiment of the present application provides a judgment condition for entering a low power consumption state, and enters a low power consumption state in time when the condition of entering the low power consumption state is satisfied, thereby saving power consumption.
  • the receiving, by the SOC, an instruction for indicating to enter a low power consumption state includes: receiving, by the SOC, a USB slave device a data packet, wherein the data packet is a response data packet for the SOC to send a link layer power management LPM data packet to the USB slave device, or the data packet is sent by the USB slave device to the SOC LPM packet.
  • the embodiment of the present application provides another judgment condition for entering a low power consumption state, and enters a low power consumption state in time when the condition of entering the low power consumption state is satisfied, thereby saving power consumption.
  • the receiving, by the SOC, an instruction for indicating to exit the low power consumption state includes: the SOC passing The system wake-up control module detects a change in the target bus level.
  • the embodiment of the present application provides a judgment condition for exiting a low power consumption state.
  • the low power consumption state is exited in time without affecting user usage.
  • the SOC is further configured to wake up the CPU, the USB controller, and the USB in the system wake-up control module. After the PHY, the bus hold circuit is turned off.
  • the bus hold circuit is cancelled in time after the data communication is resumed, and the data communication is normally performed without affecting the user's use.
  • the embodiment of the present application provides a universal serial bus USB host device, including: a system level chip SOC and a bus hold circuit; wherein the SOC is any of the first aspect or the first aspect of the application embodiment.
  • An implementation provides an SOC.
  • an embodiment of the present application provides a universal serial bus USB system, including: a USB host device and a USB slave device; wherein the USB host device includes a system level chip SOC and a bus hold circuit;
  • the SOC is the SOC provided by the first aspect of the embodiment of the present application or any one of the implementation manners of the first aspect.
  • the embodiment of the present application provides a universal serial bus USB wake-up method, including:
  • the SOC powers down the processor CPU, the USB controller, and the universal serial bus physical layer module USB PHY;
  • the SOC powers up the CPU, USB controller, and USB PHY if the SOC receives an instruction to indicate exiting the low power state.
  • the method further includes:
  • the SOC maintains a level of a target bus through the bus hold circuit, the target bus being a bus between the SOC and a USB slave device;
  • the SOC when the SOC receives an instruction to indicate exiting the low power state, powering up the CPU, the USB controller, and the USB PHY, including:
  • the CPU, the USB controller, and the USB PHY are powered on if the target bus level changes, include:
  • the CPU, USB controller, and USB PHY are powered up by the system wake-up control module.
  • the system-level chip SOC is configured to indicate that the low-power is entered
  • the consumption state instruction includes: if the system level chip SOC detects that the level of the target bus has not changed within a preset time period.
  • the system-level chip SOC is configured to indicate that the low-power is entered
  • the consumption state instruction includes: if the system-level chip receives a data packet sent by the USB slave device; wherein the data packet is a response packet for the SOC to send the link layer power management LPM data packet to the USB slave device, Or the data packet is an LPM data packet sent by the USB slave device to the SOC.
  • the method further includes :
  • the SOC turns off the bus hold circuit.
  • the bus hold circuit includes a bus keeper or a pull-down resistor.
  • the embodiment of the present application controls the CPU, the USB controller, and the USB PHY to be powered off by the system wakeup control module; After the low power state command, power on the CPU, USB controller, and USB PHY. In the low power state, the USB controller and the USB PHY are powered off, which can reduce the power consumption of the USB host device.
  • the CPU, the USB controller, and the USB PHY are powered on in time to reduce the power consumption while ensuring the normal operation of the data communication and improving the user experience.
  • FIG. 1 is a schematic structural diagram of a USB system in the prior art
  • FIG. 2 is a schematic diagram of a SOC structure in the prior art
  • FIG. 3 is a schematic structural diagram of an SOC according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a USB host device according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a USB system according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a USB wake-up method according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a USB system in the prior art
  • FIG. 2 is a schematic diagram of a SOC structure in the prior art.
  • the USB system in the prior art includes a USB host device 10, a USB slave device 20, and a USB cable 30.
  • the USB master device 10 and the USB slave device 20 can be connected through a USB cable 30 for data transmission.
  • the USB host device 10 is a computer host
  • the USB slave device 20 is a mobile phone
  • the USB cable 30 is a data cable.
  • the computer host and the mobile phone can transmit data through the data line.
  • the USB slave device 20 may include a USB cable 30.
  • the USB host device 10 is a computer host
  • the USB slave device 20 is a wired mouse. The computer host and the wired mouse can directly perform data transmission.
  • a USB system in the prior art may only include the USB host device 10 and the USB slave device 20, and the USB slave device 20 may directly connect to the USB host device 10 for data transmission.
  • the USB host device 10 is a computer host
  • the USB slave device 20 is a USB flash drive.
  • the USB flash drive can be directly inserted into the host computer for data transmission.
  • the USB host device 10 may be a USB host that can be connected to the USB slave device 20, and when the USB host is connected to the USB slave device 20, data transfer can be performed with the USB slave device 20.
  • the USB main device 10 can also be a USB On-The-Go (OTG) device.
  • OTG On-The-Go
  • the primary and secondary identity of the OTG device can be converted, that is, the OTG device can serve as both the USB host device 10 and the USB slave device 20.
  • an OTG device can be a digital camera. When a digital camera is connected to a computer to upload photos to a computer, the digital camera plays the identity of the USB slave device. If the digital camera is directly connected to the printer, the photo in the digital camera is printed, and the digital camera plays the identity of the USB host device.
  • the USB OTG device in the embodiment of the present application is used to implement the function of the USB host, and can be connected to other USB slave devices 20 for data transmission with the USB slave device 20.
  • the USB host device 10 can include at least a system on chip (SOC) 110, a data bus (D+, D-) 120, and a USB interface 130.
  • the data bus 120 is used to connect the SOC 110 and the USB interface 130.
  • the USB interface 130 is used to provide a connection interface for the USB host device 10 and the USB slave device 20. After the USB slave device 20 is connected to the USB host device 10 via the USB cable 30, the SOC 110 performs data transfer with the USB slave device 20 via the data bus 120.
  • the structure of the SOC 110 is as shown in FIG. 2.
  • the SOC 110 can include at least a system wake-up control module 1110, a central processing unit (CPU) 1120, a USB controller 1130, and a USB PHY 1140.
  • the CPU 1120 is configured to generate a corresponding control signal according to the received command, and control the corresponding component to perform according to the specified requirement.
  • the USB controller 1130 is used to provide a USB control function to perform a data transfer function together with the USB PHY 1140.
  • the USB PHY 1140 is used for data transmission with the USB slave device 20 via the data bus 120.
  • the USB PHY 1140 can also be used to maintain the level of the data bus 120 in a low power state to avoid a change in bus level due to a false trigger signal, causing the system to exit a low power state.
  • the low power state is a state in which the USB host device operates in a lower power consumption than in the case of data communication in progress.
  • the low power state in the prior art may be that the USB host device is in a suspended state. That is, the data bus activity is not seen for a period of time and the USB host device is in a state of low power consumption.
  • the existing USB protocol stipulates that the time period here is 3 ms.
  • the low power consumption state in the prior art may also be that the USB host device is in a sleep state, that is, the USB master device or the USB slave device sends the link layer power management (LPM) data packet to the other party to make the USB master device. In a state of low power consumption.
  • LPM link layer power management
  • the USB controller 1130 and the USB PHY 1140 can also be used to detect a change in the level of the bus in a low power state, ensuring that a wake-up signal can be detected. It will be appreciated that the change in bus level at this time can be triggered by the USB slave device 20, which can be changed when the USB slave device 20 needs to perform data transfer. In this case, since the magnitude of the change in the bus level triggered by the USB slave device 20 is much larger than the magnitude of the change in the bus level triggered by the false trigger signal, the USB PHY 1140 cannot maintain the bus level and cause the CPU to be woken up. Therefore, the USB PHY1140 maintains the bus level in a low power state to avoid variations in the bus level caused by false trigger signals.
  • the system wake-up control module 1110 is configured to manage the operating mode of the SOC 110. Specifically, when receiving an instruction for instructing to exit the low power consumption state, the system wakeup control module 1110 may send a wakeup signal to wake up the CPU 1110, and then wake up the USB controller 1130 and the USB PHY 1140 through the CPU 1110, that is, the CPU 1110, the USB controller 1130, and The USB PHY1140 powers up, allowing the USB system to resume data communication.
  • the system wake-up control module 1110 may be a processor or a logic control circuit for implementing the foregoing functions. It can be known that the system wake-up control module 1110 can also have other forms of existence. Regardless of the state of the system, the system wake-up control module 1110 is always in the power-on state, and the system wake-up function can be implemented, which is not limited herein.
  • the SOC 110 can be divided into a power-down area and a power-off area.
  • the CPU 1120 is located in the power-off area, and the system wake-up control module 1110, the USB controller 1130, and the USB PHY 1140 are located in the unpowered area.
  • the power-down area turns off the power after the system enters a low-power state to save system power consumption.
  • the unpowered area is the area that remains powered when the system is in any state. That is, in the prior art, when the system enters a low power consumption state, the CPU 1120 turns off the power to save power consumption of the system, and the system wakeup control module 1110, the USB controller 1130, and the USB PHY 1140 remain powered.
  • the CPU 1120, the USB controller 1130, and the USB PHY 1140 are located in the power-off area, and the system wake-up control module 1110 is located in the unpowered area.
  • the CPU1120, the USB controller 1130, and the USB PHY1140 can be completely powered off. Only the system control module 1110 located in the unpowered area remains powered, which reduces the low power consumption compared with the prior art. The power consumption of the system in the state.
  • FIG. 3 is a schematic structural diagram of a SOC provided by an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a USB main device according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a USB system according to an embodiment of the present disclosure.
  • the SOC 110 may include at least a system wake-up control module 1110, a CPU 1120, a USB controller 1130, and a USB PHY 1140. As can be seen from the figure, the SOC 110 is divided into a power-down area and a power-off area. The CPU 1120, the USB controller 1130, and the USB PHY 1140 are in the power-off area, and the system wake-up control module 1110 is in the unpowered area.
  • the CPU 1120 is configured to generate a corresponding control signal according to the received command, and control the corresponding component to perform according to the specified requirement.
  • the USB controller 1130 is used to provide a USB control function to perform a data transfer function together with the USB PHY 1140.
  • the USB PHY 1140 is used for data transmission with the USB slave device 20.
  • the system wake-up control module 1110 is configured to manage the operating mode of the SOC 110. Specifically, after the SOC 110 receives the instruction for instructing to enter the low power consumption state, the CPU 1120, the USB controller 1130, and the USB PHY 1140 are powered off; and the system wakeup control module 1110 is further configured to receive the low power at the SOC 110. After the instruction of the state is consumed, the CPU 1120, the USB controller 1130, and the USB PHY 1140 are powered on.
  • the SOC 110 is further configured to maintain the level of the target bus by the bus hold circuit 140 after the SOC 110 receives the instruction for indicating the entry into the low power state; wherein the bus hold circuit 140 Including the bus keeper or pull-down resistor, the target bus is the data bus (D+, D-) 120 between the SOC and the USB slave device. It is to be understood that the bus hold circuit 140 is not limited to the above-listed components, and may be other components for maintaining the target bus level during actual use, which is not limited herein.
  • the manner of setting the bus hold circuit 140 includes but is not limited to the following:
  • the bus hold circuit 140 is located between the SOC 110 and the USB interface 130, and is connected to the pin b on the unpowered area in the SOC 110, and can be controlled by the CPU 1120.
  • the CPU 1120 can control the bus hold circuit 140 to operate, maintain the target bus level unchanged, and then power down the power down zone.
  • the system wakeup control module 1110 wakes up the CPU 1120, the USB controller 1130, and the USB PHY 1140, so that after the power is turned on, the CPU 1120 controls the bus hold circuit 140 to stop working. Restore the USB system to normal data communication.
  • the bus hold circuit 140 can also be directly disposed in the unpowered area in the SOC 110, and the bus 1120 is controlled to operate and shut down by the CPU 1120.
  • the manner in which the SOC 110 receives an instruction for indicating a low power consumption state includes but is not limited to the following:
  • the receiving, by the SOC 110, the instruction to enter the low power consumption state includes: the SOC 110 detects that the level of the target bus 120 has not changed within a preset time period.
  • the change of the bus level can be detected by the USB PHY1140.
  • the preset time period may be, for example, 3 ms, 5 ms, 10 ms, or the like.
  • the change in bus level can be caused by the level of the two data buses D+, D- being inverted. For example, when entering a low-power state, the level of D+ is high, and the level of D- is low. When exiting the low-power state, the level of D+ should be flipped to low level, D- The level should be flipped high.
  • the receiving, by the SOC 110, the instruction for entering the low power consumption state includes: the SOC 110 receives the data packet sent by the USB slave device 20; wherein the data packet is the SOC 110, and the USB slave device 20 sends the LPM data packet after the USB The response packet fed back from device 20, or the packet is an LPM packet sent by USB slave device 20 to SOC 110.
  • the receiving of the instruction to indicate the exit of the low power state by the SOC 110 includes the SOC 110 detecting that the level of the target bus 120 has changed by the system wakeup control module 1110. Among them, the level changes include the level flipping.
  • the wake-up control mode 1110 is connected to at least one bus of the target bus 120 (D+, D-) through the pin a, and detects that the level value is inverted to receive the low-power state for indicating the exit. instruction.
  • the system wake-up control module 1110 is connected to at least one bus of the target bus 120 (D+, D-) by pulling at least one wire through the pin a to detect a change in the level of the target bus 120.
  • a wire can be connected to D+ through pin a, or a wire can be connected to D- through pin a, or two wires can be connected through pin a to D+ and D-, respectively.
  • the system control module 1110 can detect the change in the level of the target bus 120 even after the system enters the low power consumption state.
  • the flipping of the target bus 120 level value can be triggered by the USB slave device 20, which can cause the target bus 120 level to change when the USB slave device 20 needs to transmit data to the SOC 110.
  • the bus hold circuit 140 cannot maintain the target bus 120 level unchanged.
  • the magnitude of the change in the level of the target bus 120 triggered by the USB slave device 20 is much greater than the magnitude of the change in the level of the target bus 120 triggered by the false trigger signal. Therefore, the bus hold circuit 140 maintains the target bus 120 level in a low power consumption state to avoid variations in the target bus 120 level caused by the false trigger signal.
  • the system After the system enters the low-power state, the system detects the bus level through the system wake-up control module, maintains the bus level through the bus hold circuit, and replaces the work of the USB controller and the USB PHY in the low-power state, so that the system enters In the low power state, the USB controller and USB PHY can also be powered down, saving power consumption in the system under low power consumption.
  • the USB host device 10 can include at least a SOC 110, a target bus 120, a USB interface 130, and a bus hold circuit 140.
  • the SOC 110 may include at least: a system wake-up control module 1110, a CPU 1120, a USB controller 1130, and a USB PHY 1140.
  • the SOC 110 is divided into a power-down area and a power-off area.
  • the CPU 1120, the USB controller 1130, and the USB PHY 1140 are in the power-off area, and the system wake-up control module 1110 is in the unpowered area.
  • the target bus 120 is coupled to the USB PHY 1140 in the SOC 110 for data communication with the USB slave device.
  • the USB interface 130 is used to provide a connection interface for the USB host device 10 and the USB slave device 20.
  • the bus hold circuit 140 is connected to the unpowered area of the SOC 110 for keeping the level of the target bus 120 unchanged after the system enters the low power consumption state. At this time, the CPU 1120, the USB controller 1130, and the USB PHY 1140 can all be powered off. Save system power consumption.
  • the structure and working principle of the SOC 110 in the embodiment of the present application can refer to the SOC described in the embodiment of FIG. 3.
  • the USB system may include a USB host device 10, a USB slave device 20, and a USB cable 30.
  • the USB slave device 10 and the USB slave device 20 may be connected via a USB cable 30 for data transmission.
  • the USB host device 10 is a computer host
  • the USB slave device 20 is a mobile phone
  • the USB cable 30 is a data cable.
  • the computer host and the mobile phone can transmit data through the data line.
  • the USB slave device 20 in a USB system provided by the embodiment of the present application may include a USB connection line 30.
  • the USB host device 10 is a computer host
  • the USB slave device 20 is a wired mouse. The computer host and the wired mouse can directly perform data transmission.
  • the USB system provided by the embodiment of the present application may include only the USB host device 10 and the USB slave device 20.
  • the USB slave device 20 may directly connect to the USB host device 10 for data transmission.
  • the USB host device 10 is a computer host
  • the USB slave device 20 is a USB flash drive.
  • the USB flash drive can be directly inserted into the host computer for data transmission.
  • the USB host device 10 may be a USB host that can be connected to the USB slave device 20, and when the USB host is connected to the USB slave device 20, data transfer can be performed with the USB slave device 20.
  • the USB host device 10 can also be a USB OTG device that can function as both a USB host and a USB slave device 20.
  • the USB OTG device in the embodiment of the present application is used to implement the function of the USB host, and can be connected to other USB slave devices 20 for data transmission with the USB slave device 20.
  • the USB host device 10 may include at least a SOC 110, a data bus (D+, D-) 120, a USB interface 130, and a bus hold circuit 140.
  • the data bus 120 is used to connect the SOC 110 and the USB interface 130.
  • the USB interface 130 is used to provide a connection interface for the USB host device 10 and the USB slave device 20.
  • the SOC 110 performs data transfer with the USB slave device 20 via the data bus 120.
  • the SOC 110 maintains the level of the data bus 120 through the bus hold circuit 140 while the SOC 110 detects a change in the level of the data bus 120 through the system wakeup control module 1110.
  • the embodiment of the present application further provides a USB wake-up method.
  • the USB wakeup method may include at least the following steps:
  • S401 If the SOC receives an instruction for instructing to enter a low power consumption state, the SOC powers down the CPU, the USB controller, and the USB PHY.
  • the manner in which the SOC 110 receives an instruction for indicating a low power consumption state includes but is not limited to the following:
  • the receiving, by the SOC 110, the instruction to enter the low power consumption state includes: the SOC detects that the level of the target bus (ie, the data bus 120) has not changed within a preset time period.
  • the change of the target bus level can be detected by the USB PHY1140.
  • the preset time period may be, for example but not limited to, 3 ms, 5 ms, 10 ms, and the like.
  • the change in the level of the target bus 120 may be such that the levels of the two data buses D+, D- are inverted. For example, when entering a low-power state, the level of D+ is high, and the level of D- is low. When exiting the low-power state, the level of D+ should be flipped to low level, D- The level should be flipped high.
  • the instruction that the SOC 110 receives to indicate the entry into the low power consumption state includes: the SOC 110 receives the data packet sent by the USB slave device 20; wherein the data packet is a response packet that the SOC 110 sends the LPM data packet to the USB slave device 20 Or the data packet is an LPM packet sent by the USB slave device 20 to the SOC 110.
  • the method further includes:
  • S402 The SOC maintains the level of the target bus through the bus hold circuit.
  • the bus hold circuit 140 includes a bus keeper or a pull-down resistor.
  • the manner in which the bus hold circuit is set includes the following:
  • the bus hold circuit 140 is located between the SOC 110 and the USB interface 130, and is connected to the unpowered area in the SOC 110, and the bus hold circuit can be controlled by the CPU 1120. After the SOC 110 receives the instruction for instructing to enter the low power consumption state, the CPU 1120 can control the bus hold circuit 140 to operate, maintain the target bus 120 level unchanged, and then power down the power down zone.
  • the bus hold circuit 140 can also be directly disposed in the unpowered area in the SOC 110, and the bus hold circuit 140 is controlled to be turned on and off by the CPU 1120.
  • S403 If the SOC receives an instruction for instructing to exit the low power state, the SOC powers up the CPU, the USB controller, and the USB PHY.
  • the instruction that the SOC 110 receives to indicate the exit of the low power consumption state includes that the SOC 110 detects that the level of the target bus 120 has changed by the system wakeup control module 1110.
  • the level changes include the level flipping.
  • the system wakeup control module 1110 wakes up the CPU 1120, the USB controller 1130, and the USB PHY 1140. After the power is turned on, the CPU 1120 controls the bus hold circuit 140 to stop working, that is, The bus hold circuit 140 is turned off to resume normal data communication with the USB system.
  • the wake-up control mode 1110 is connected to at least one bus in the target bus 120, and detects that the level value is inverted to receive an instruction for instructing to exit the low power consumption state.
  • the flipping of the target bus 120 level value can be triggered by the USB slave device 20.
  • the USB slave device 20 needs to transmit data to the SOC 110, the USB slave device 20 can change the level of the target bus 120.
  • the bus hold circuit 140 cannot maintain the target bus 120 level unchanged.
  • the magnitude of the change in the level of the target bus 120 triggered by the USB slave device 20 is much greater than the magnitude of the change in the level of the target bus 120 triggered by the false trigger signal. Therefore, the bus hold circuit 140 maintains the target bus 120 level in a low power consumption state to avoid variations in the target bus 120 level caused by the false trigger signal.
  • the system After the system enters the low-power state, the system detects the bus level through the system wake-up control module, maintains the bus level through the bus hold circuit, and replaces the work of the USB controller and the USB PHY in the low-power state, so that the system enters In the low power state, the USB controller and USB PHY can also be powered down, saving power consumption in the system under low power consumption.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).
  • the modules in the apparatus of the embodiment of the present application may be combined, divided, and deleted according to actual needs.

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Abstract

本申请实施例提供了一种系统级芯片、通用串行总线主设备、系统及唤醒方法。该系统级芯片SOC包括系统唤醒控制模块、处理器CPU、USB控制器和通用串行总线物理层模块USB PHY。在SOC接收到用于指示进入低功耗状态的指令后，通过系统唤醒控制模块将CPU、USB控制器及USB PHY下电；在SOC接收到用于指示退出低功耗状态的指令后，将CPU、USB控制器及USB PHY上电。在低功耗状态时使USB控制器及USB PHY处于下电状态，可以降低USB主设备的功耗。在接收到用于指示退出低功耗状态的指令时将CPU、USB控制器及USB PHY上电，在降低功耗的同时保证数据通信的正常运行，提升用户体验。

Description

系统级芯片、通用串行总线主设备、系统及唤醒方法 技术领域
本申请涉及电子通信领域，尤其涉及一种系统级芯片、通用串行总线主设备、系统及唤醒方法。
背景技术
通用串行总线(Universal Serial Bus，USB)2.0协议规定了USB 2.0总线包含D+，D-两根数据线，在空闲时进入低功耗的状态。进入低功耗状态后，USB主设备和USB从设备中的任意一方可以发起恢复。当系统进入低功耗状态后，可以通过通用串行总线物理层模块(Universal Serial Bus Physical Layer Protocol，USB PHY)和USB控制器监视总线电平的变化，一旦出现唤醒信号，则立刻进入恢复数据通信的流程。而在处于低功耗的过程中，由于USB控制器及USB PHY部分电路一直处于上电状态，会持续消耗电量，导致USB主设备电量消耗较大。
发明内容
本申请实施例提供了一种系统级芯片、通用串行总线主设备、系统及唤醒方法，能够在总线进入低功耗状态时将USB PHY和USB控制器下电，节省功耗。
第一方面，本申请实施例提供了一种系统级芯片SOC，包括：系统唤醒控制模块、处理器CPU、USB控制器和通用串行总线物理层模块USB PHY；其中：
所述系统唤醒控制模块用于在所述SOC接收到用于指示进入低功耗状态的指令后，将所述CPU、USB控制器及USB PHY下电；
所述系统唤醒控制模块还用于在所述SOC接收到用于指示退出所述低功耗状态的指令后，将所述CPU、USB控制器及USB PHY上电。
本申请实施例在SOC接收到进入低功耗状态后将CPU、USB控制器及USB PHY下电，节省功耗。
结合第一方面，在第一方面的第一种实现方式中，所述SOC还用于在所述SOC接收到用于指示进入低功耗状态的指令后，通过总线保持电路保持目标总线的电平；其中，所述总线保持电路包括系统唤醒控制器或下拉电阻，所述目标总线为所述SOC与USB从设备之间的总线。
本申请实施例通过总线保持电路使总线在进入低功耗状态后维持总线电平保持不变，使USB控制器及USB PHY可以下电。
结合第一方面的第一种实现方式，在第一方面的第二种实现方式中，所述SOC接收到用于指示进入低功耗状态的指令包括：所述SOC检测到所述目标总线的电平在预设时间段内没有发生变化。
本申请实施例提供了一种进入低功耗状态的判断条件，当满足进入低功耗状态的条件时及时进入低功耗状态，节省功耗。
结合第一方面的第一种实现方式，在第一方面的第三种实现方式中，所述SOC接收到用于指示进入低功耗状态的指令包括：所述SOC接收到USB从设备发送的数据包；其中，所述数据包为所述SOC向所述USB从设备发送链路层电源管理LPM数据包的响应数据包，或者所述数据包为所述USB从设备向所述SOC发送的LPM数据包。
本申请实施例提供了另一种进入低功耗状态的判断条件，当满足进入低功耗状态的条件时及时进入低功耗状态，节省功耗。
结合第一方面的第二种或第三种实现方式，在第一方面的第四种实现方式中，所述SOC接收到用于指示退出所述低功耗状态的指令包括：所述SOC通过所述系统唤醒控制模块检测到所述目标总线电平发生变化。
本申请实施例提供了一种退出低功耗状态的判断条件，当有数据需要传输时，及时退出低功耗状态，不影响用户使用。
结合第一方面的第二种或第三种实现方式，在第一方面的第五种实现方式中，所述SOC还用于在所述系统唤醒控制模块唤醒所述CPU、USB控制器及USB PHY之后，关闭所述总线保持电路。
本申请实施例在恢复数据通信后及时撤销总线保持电路，保证数据通信的正常进行，不影响用户使用。
第二方面，本申请实施例提供了一种通用串行总线USB主设备，包括：系统级芯片SOC和总线保持电路；其中，所述SOC为本申请实施例第一方面或第一方面的任意一种实现方式提供的SOC。
第三方面，本申请实施例提供了一种通用串行总线USB系统，包括：USB主设备和USB从设备；其中，所述USB主设备包括系统级芯片SOC和总线保持电路；
其中，所述SOC为本申请实施例第一方面或第一方面的任意一种实现方式提供的SOC。
第四方面，本申请实施例提供了一种通用串行总线USB唤醒方法，包括：
若系统级芯片SOC接收到用于指示进入低功耗状态的指令，则所述SOC将处理器CPU、USB控制器和通用串行总线物理层模块USB PHY下电；
若所述SOC接收到用于指示退出所述低功耗状态的指令，则所述SOC将所述CPU、USB控制器和USB PHY上电。
结合第四方面，在第四方面的第一种实现方式中，所述若系统级芯片SOC接收到用于指示进入低功耗状态的指令之后，所述方法还包括：
所述SOC通过所述总线保持电路来保持目标总线的电平，所述目标总线为所述SOC与USB从设备之间的总线；
所述若SOC接收到用于指示退出所述低功耗状态的指令，则所述SOC将所述CPU、USB控制器和USB PHY上电，包括：
若所述目标总线电平发生变化，则将所述CPU、USB控制器和USB PHY上电。
结合第四方面的第一种实现方式，在第四方面的第二种实现方式中，所述若所述目标总线电平发生变化，则将所述CPU、USB控制器和USB PHY上电，包括：
通过系统唤醒控制模块检测所述目标总线的电平；
若所述目标总线电平发生变化，则通过所述系统唤醒控制模块将所述CPU、USB控制器和USB PHY上电。
结合第四方面或第四方面第一种至第二种中的任意一种实现方式，在第四方面的第三种实现方式中，所述若系统级芯片SOC接收到用于指示进入低功耗状态的指令包括：若系统级芯片SOC检测到所述目标总线的电平在预设时间段内没有发生变化。
结合第四方面或第四方面第一种至第二种中的任意一种实现方式，在第四方面的第四种实现方式中，所述若系统级芯片SOC接收到用于指示进入低功耗状态的指令包括：若所述系统级芯片接收到USB从设备发送的数据包；其中，所述数据包为SOC向所述USB从设备发送链路层电源管理LPM数据包的响应数据包，或者所述数据包为所述USB从设备向所述SOC发送的LPM数据包。
结合第四方面的第三种或第四种实现方式，在第四方面的第五种实现方式中，所述SOC将所述CPU、USB控制器及USB PHY上电之后，所述方法还包括：
所述SOC关闭所述总线保持电路。
结合第四方面的第一种实现方式，在第四方面的第六种实现方式中，所述总线保持电路包括总线保持器或者下拉电阻。
可以看出，本申请实施例在SOC接收到用于指示进入低功耗状态的指令后，通过系统唤醒控制模块控制将CPU、USB控制器及USB PHY下电；在SOC接收到用于指示退出低功耗状态的指令后，将CPU、USB控制器及USB PHY上电。在低功耗状态时使USB控制器及USB PHY处于下电状态，可以降低USB主设备的电量消耗。在接收到用于指示退出低功耗状态的指令时及时将CPU、USB控制器及USB PHY上电，在降低功耗的同时保证数据通信的正常运行，提升用户体验。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1为现有技术中的一种USB系统结构示意图；
图2为现有技术中SOC结构示意图；
图3为本申请实施例提供的一种SOC结构示意图；
图4为本申请实施例提供的一种USB主设备结构示意图；
图5为本申请实施例提供的一种USB系统结构示意图；
图6为本申请实施例提供的一种USB唤醒方法流程示意图。
具体实施方式
下面将结合附图对本申请实施例中的技术方案进行清楚、详尽地描述。
首先结合图1-图2介绍现有技术中USB系统结构及SOC结构，其中，图1为现有技术中的一种USB系统结构示意图，图2为现有技术中SOC结构示意图。
请参见图1。如图1所示，现有技术中USB系统包括USB主设备10、USB从设备20及USB连接线30，USB主设备10与USB从设备20可以通过USB连接线30连接，进行 数据传输。例如，USB主设备10为电脑主机，USB从设备20为手机，USB连接线30为数据线，电脑主机和手机可以通过数据线进行数据传输。或者，现有技术中的一种USB系统中，USB从设备20可以包括USB连接线30。例如，USB主设备10为电脑主机，USB从设备20为有线鼠标，电脑主机和有线鼠标可以直接进行数据传输。或者，现有技术中的一种USB系统可以只包括USB主设备10及USB从设备20，USB从设备20可以直接与USB主设备10连接进行数据传输。例如，USB主设备10为电脑主机，USB从设备20为USB闪存盘，USB闪存盘可以直接插在电脑主机上进行数据传输。
USB主设备10可以是能够与USB从设备20连接的USB主机，当该USB主机与USB从设备20连接后，可以与该USB从设备20进行数据传输。USB主设备10还可以是USB On-The-Go(OTG)设备，根据不同应用场景，OTG设备的主、从身份可转换，即OTG设备既可以作为USB主设备10又可以作为USB从设备20。例如，OTG设备可以是一个数码相机。当数码相机连接在电脑主机上将照片上传至电脑时，数码相机扮演的是USB从设备的身份。而若数码相机直接与打印机相连，将数码相机内的照片打印出来使，数码相机扮演的是USB主设备的身份。在本申请实施例中的USB OTG设备用来实现USB主机的功能，可以与其他的USB从设备20连接，与USB从设备20进行数据传输。
从图1中可以看出，USB主设备10至少可以包括：系统级芯片(System on Chip，SOC)110、数据总线(D+、D-)120及USB接口130。其中，数据总线120用于连接SOC110与USB接口130。USB接口130用于为USB主设备10和USB从设备20提供连接接口。当USB从设备20与USB主设备10通过USB连接线30连接之后，SOC110通过数据总线120与USB从设备20进行数据传输。
具体地，SOC110结构如图2所示。从图2可以看出，SOC110至少可以包括系统唤醒控制模块1110、中央处理器(Central Processing Unit，CPU)1120、USB控制器1130及USB PHY1140。
其中，CPU1120用于根据接收到的指令产生相应的控制信号，控制相应部件按照指定的要求进行动作。
USB控制器1130用于提供USB控制功能，与USB PHY1140一起完成数据传输功能。
USB PHY1140用于通过数据总线120与USB从设备20进行数据传输。USB PHY1140还可以用于在低功耗状态下保持数据总线120的电平，用于避免由于误触发信号导致总线电平发生变化，使系统退出低功耗状态。
可以理解的是，低功耗状态是USB主设备运行的一种与正在进行数据通信时相比功耗较低的状态，现有技术中的低功耗状态可以是USB主设备处于挂起状态，即一段时间内未见数据总线活动而使USB主设备处于功耗较低的状态，现有的USB协议中规定此处的一段时间为3ms。现有技术中的低功耗状态还可以是USB主设备处于休眠状态，即USB主设备或USB从设备通过向对方发送链路层电源管理(Link Power Management，LPM)数据包而使USB主设备处于功耗较低的状态。
USB控制器1130和USB PHY1140还可以用于在低功耗状态下检测总线的电平变化，保证能检测到唤醒信号。可以知道的是，此时总线电平的变化可以由USB从设备20触发，当USB从设备20需要进行数据传输时，可以使总线电平发生变化。在这种情况下，由于 USB从设备20触发的总线电平发生变化的幅值远大于误触发信号触发的总线电平发生变化的幅值，从而USB PHY1140无法保持总线电平导致CPU被唤醒。因此，USB PHY1140在低功耗状态下保持总线电平可以避免由误触发信号引起的总线电平的变化。
系统唤醒控制模块1110用于管理SOC110的运行模式。具体地，当接收到用于指示退出低功耗状态的指令时，系统唤醒控制模块1110可以发送唤醒信号唤醒CPU1110，进而通过CPU1110唤醒USB控制器1130及USB PHY1140，即将CPU1110、USB控制器1130及USB PHY1140上电，使USB系统恢复数据通信。
在一种具体的实现方式中，系统唤醒控制模块1110可以是一个处理器，也可以是一个逻辑控制电路，用于实现上述功能。可以知道的是，系统唤醒控制模块1110还可以有其他的存在形式，无论系统处于什么状态，系统唤醒控制模块1110都一直处于上电状态，可以实现系统唤醒功能即可，在此不做限制。
此外，从图2中可以看出SOC110可以划分为下电区域及不下电区域。其中，CPU1120位于下电区域，系统唤醒控制模块1110、USB控制器1130及USB PHY1140位于不下电区域。对于下电区域与不下电区域的划分，只需在设计该SOC110时对其进行划分后配置每个区域的工作逻辑即可。下电区域在系统进入低功耗状态后，关闭电源以节省系统的功耗。不下电区域是在系统处于任何状态下都保持上电的区域。即在现有技术中，当系统进入低功耗状态后，CPU1120关闭电源以节省系统的功耗，而系统唤醒控制模块1110、USB控制器1130及USB PHY1140则保持上电。
而在本申请中，CPU1120、USB控制器1130及USB PHY1140位于下电区域，系统唤醒控制模块1110位于不下电区域。当系统进入低功耗状态后，CPU1120、USB控制器1130及USB PHY1140均可以完全下电，只有位于不下电区的系统控制模块1110保持上电，与现有技术相比，降低了低功耗状态下系统的功耗。
接下来结合图3-图5介绍本申请实施例中提供的SOC、USB主设备及USB系统。其中，图3为本申请实施例提供的SOC结构示意图，图4为本申请实施例提供的USB主设备结构示意图，图5为本申请实施例提供的USB系统结构示意图。
请参见图3。如图3所示，SOC110至少可以包括：系统唤醒控制模块1110、CPU1120、USB控制器1130及USB PHY1140。从图中可以看出，SOC110被划分为下电区域与不下电区域。其中，CPU1120、USB控制器1130及USB PHY1140处于下电区域，系统唤醒控制模块1110处于不下电区域。
其中，CPU1120用于根据接收到的指令产生相应的控制信号，控制相应部件按照指定的要求进行动作。
USB控制器1130用于提供USB控制功能，与USB PHY1140一起完成数据传输功能。
USB PHY1140用于与USB从设备20进行数据传输。
系统唤醒控制模块1110用于管理SOC110的运行模式。具体地，在SOC110接收到用于指示进入低功耗状态的指令后，将CPU1120、USB控制器1130及USB PHY1140下电；系统唤醒控制模块1110还用于在SOC110接收到用于指示退出低功耗状态的指令后，将CPU1120、USB控制器1130及USB PHY1140上电。
在系统进入低功耗状态以后，由于USB控制器1130及USB PHY1140下电，无法检测 总线电平的变化，USB PHY1140也无法保持总线电平以免误触发信号导致总线电平的变化，使系统退出低功耗状态，因此在本申请实施例中SOC110还用于在SOC110接收到用于指示进入低功耗状态的指令后，通过总线保持电路140保持目标总线的电平；其中，总线保持电路140包括总线保持器或下拉电阻，目标总线即为SOC与USB从设备之间的数据总线(D+、D-)120。可以知道的是，总线保持电路140不限于以上列举的部件，在实际使用过程中，还可以是其他用于保持目标总线电平的部件，在此不做限制。
具体地，总线保持电路140的设置方式包括但不限于以下几种：
在一种可能的实现方式中，总线保持电路140位于SOC110与USB接口130之间，与SOC110中的不下电区域上的管脚b相连，可以通过CPU1120控制该管脚b。当SOC110接收到用于指示进入低功耗状态的指令后，可以通过CPU1120控制总线保持电路140工作，维持目标总线电平保持不变，再将下电区下电。当SOC110接收到用于指示退出低功耗状态的指令后，系统唤醒控制模块1110唤醒CPU1120、USB控制器1130及USB PHY1140，使其上电后，CPU1120再控制总线保持电路140停止工作。使USB系统恢复正常的数据通信。
在另外一种可能的实现方式中，总线保持电路140还可以直接设置于SOC110中的不下电区域，通过CPU1120控制总线保持电路工作与关闭。
具体地，SOC110接收到用于指示进入低功耗状态的指令的方式包括但不限于以下几种：
可选的，SOC110接收到用于指示进入低功耗状态的指令包括：SOC110检测到目标总线120的电平在预设时间段内没有发生变化。其中，可以通过USB PHY1140来检测总线电平的变化。预设时间段例如可以是3ms、5ms、10ms等。总线电平的变化可以是两根数据总线D+、D-的电平发生翻转。例如，进入低功耗状态时，D+的电平为高电平，D-的电平为低电平，那么在退出低功耗状态时，D+的电平应该翻转为低电平，D-的电平应该翻转为高电平。
可选的，SOC110接收到用于指示进入低功耗状态的指令包括：SOC110接收到USB从设备20发送的数据包；其中，数据包为SOC110向所述USB从设备20发送LPM数据包后USB从设备20反馈回来的响应数据包，或者数据包为USB从设备20向SOC110发送的LPM数据包。
SOC110接收到用于指示退出低功耗状态的指令包括：SOC110通过系统唤醒控制模块1110检测到目标总线120的电平发生变化。其中，电平发生变化包括电平发生翻转。
具体地，唤醒控制模1110通过管脚a与目标总线120(D+、D-)中的至少一根总线连接，检测到其电平值发生翻转即为接收到用于指示退出低功耗状态的指令。具体地，通过管脚a引出至少一根导线将系统唤醒控制模块1110与目标总线120(D+、D-)中的至少一根总线连接，来检测目标总线120电平的变化。例如，可以通过管脚a引出一根导线与D+相连，也可以通过管脚a引出一根导线与D-相连，或者还可以通过管脚a引出两根导线分别与D+和D-相连。由于系统唤醒控制模块1110处于不下电区域，因此，即使系统进入低功耗状态后，系统控制模块1110依然可以检测目标总线120电平的变化。目标总线120电平值发生翻转可以由USB从设备20触发，当USB从设备20需要向SOC110发送数据时， USB从设备20可以使目标总线120电平发生变化。在这种情况下，总线保持电路140无法保持目标总线120电平不变。USB从设备20触发的目标总线120电平发生变化的幅值远大于误触发信号触发的目标总线120电平发生变化的幅值。因此，总线保持电路140在低功耗状态下保持目标总线120电平可以避免由误触发信号引起的目标总线120电平的变化。
本申请实施例在系统进入低功耗状态后，通过系统唤醒控制模块检测总线电平，通过总线保持电路维持总线电平，取代低功耗状态下USB控制器和USB PHY的工作，使系统进入低功耗状态时，USB控制器和USB PHY也可以下电，节约低功耗状态下系统的电能消耗。
本申请实施例提供了一种USB主设备。如图4所示，USB主设备10至少可以包括SOC110、目标总线120、USB接口130及总线保持电路140。其中，SOC110至少可以包括：系统唤醒控制模块1110、CPU1120、USB控制器1130及USB PHY1140。从图中可以看出，SOC110被划分为下电区域与不下电区域。其中，CPU1120、USB控制器1130及USB PHY1140处于下电区域，系统唤醒控制模块1110处于不下电区域。目标总线120与SOC110中的USB PHY1140连接，用于与USB从设备完成数据通信。USB接口130用于为USB主设备10和USB从设备20提供连接接口。总线保持电路140与SOC110中的不下电区域连接，用于在系统进入低功耗状态后保持目标总线120的电平不变，此时可以将CPU1120、USB控制器1130及USB PHY1140全部下电，节约系统的电量消耗。
具体地，本申请实施例中SOC110的结构及工作原理可参见图3实施例描述的SOC。
本申请实施例提供了一种USB系统。如图5所示，USB系统可以包括USB主设备10、USB从设备20及USB连接线30，USB主设备10与USB从设备20可以通过USB连接线30连接，进行数据传输。例如，USB主设备10为电脑主机，USB从设备20为手机，USB连接线30为数据线，电脑主机和手机可以通过数据线进行数据传输。或者，本申请实施例提供的一种USB系统中的USB从设备20可以包括USB连接线30。例如，USB主设备10为电脑主机，USB从设备20为有线鼠标，电脑主机和有线鼠标可以直接进行数据传输。或者，本申请实施例提供的一种USB系统中可以只包括USB主设备10及USB从设备20，USB从设备20可以直接与USB主设备10连接进行数据传输。例如，USB主设备10为电脑主机，USB从设备20为USB闪存盘，USB闪存盘可以直接插在电脑主机上进行数据传输。
USB主设备10可以是能够与USB从设备20连接的USB主机，当该USB主机与USB从设备20连接后，可以与该USB从设备20进行数据传输。USB主设备10还可以是既可以作为USB主机又可以作为USB从设备20的USB OTG设备。在本申请实施例中的USB OTG设备用来实现USB主机的功能，可以与其他的USB从设备20连接，与USB从设备20进行数据传输。
具体地，USB主设备10至少可以包括SOC110、数据总线(D+、D-)120、USB接口130及总线保持电路140。其中，数据总线120用于连接SOC110与USB接口130。USB接口130用于为USB主设备10和USB从设备20提供连接接口。当USB从设备20与USB主设备10通过USB连接线30连接之后，SOC110通过数据总线120与USB从设备20进行数据传输。当系统进入低功耗状态时，SOC110通过总线保持电路140保持数据总线120 的电平，同时SOC110通过系统唤醒控制模块1110检测数据总线120电平的变化。本申请实施例中SOC110的结构及工作原理可参见图3实施例描述的SOC。
本申请实施例还相应提供了一种USB唤醒方法。如图6所示，USB唤醒方法至少可以包括以下几个步骤：
S401：若SOC接收到用于指示进入低功耗状态的指令，则SOC将CPU、USB控制器和USB PHY下电。
具体地，SOC110接收到用于指示进入低功耗状态的指令的方式包括但不限于以下几种：
可选的，SOC110接收到用于指示进入低功耗状态的指令包括：SOC检测到目标总线(即为数据总线120)的电平在预设时间段内没有发生变化。其中，可以通过USB PHY1140来检测目标总线电平的变化。预设时间段例如可以但不限于是3ms、5ms、10ms等。目标总线120电平的变化可以是两根数据总线D+、D-的电平发生翻转。例如，进入低功耗状态时，D+的电平为高电平，D-的电平为低电平，那么在退出低功耗状态时，D+的电平应该翻转为低电平，D-的电平应该翻转为高电平。
可选的，SOC110接收到用于指示进入低功耗状态的指令包括：SOC110接收到USB从设备20发送的数据包；其中，数据包为SOC110向USB从设备20发送LPM数据包的响应数据包，或者数据包为USB从设备20向SOC110发送的LPM数据包。
具体地，若SOC110接收到用于指示进入低功耗状态的指令之后，该方法还包括：
S402：SOC通过总线保持电路保持目标总线的电平。
其中，总线保持电路140包括总线保持器或下拉电阻。
具体地，总线保持电路的设置方式包括以下几种：
在一种可能的实现方式中，总线保持电路140位于SOC110与USB接口130之间，与SOC110中的不下电区域相连，可以通过CPU1120控制总线保持电路。当SOC110接收到用于指示进入低功耗状态的指令后，可以通过CPU1120控制总线保持电路140工作，维持目标总线120电平保持不变，再将下电区下电。
在另外一种可能的实现方式中，总线保持电路140还可以直接设置于SOC110中的不下电区域，通过CPU1120控制总线保持电路140工作与关闭。
S403：若SOC接收到用于指示退出低功耗状态的指令，则SOC将CPU、USB控制器和USB PHY上电。
具体地，SOC110接收到用于指示退出低功耗状态的指令包括：SOC110通过系统唤醒控制模块1110检测到目标总线120的电平发生变化。其中，电平发生变化包括电平发生翻转。
当SOC110接收到用于指示退出低功耗状态的指令后，系统唤醒控制模块1110唤醒CPU 1120、USB控制器1130及USB PHY1140，使其上电后，CPU1120再控制总线保持电路140停止工作，即关闭总线保持电路140，使USB系统恢复正常的数据通信。
具体地，唤醒控制模1110与目标总线120中的至少一根总线连接，检测到其电平值发生翻转即为接收到用于指示退出低功耗状态的指令。目标总线120电平值发生翻转可以由USB从设备20触发，当USB从设备20需要向SOC110发送数据时，USB从设备20可以 使目标总线120电平发生变化。在这种情况下，总线保持电路140无法保持目标总线120电平不变。USB从设备20触发的目标总线120电平发生变化的幅值远大于误触发信号触发的目标总线120电平发生变化的幅值。因此，总线保持电路140在低功耗状态下保持目标总线120电平可以避免由误触发信号引起的目标总线120电平的变化。
本申请实施例在系统进入低功耗状态后，通过系统唤醒控制模块检测总线电平，通过总线保持电路维持总线电平，取代低功耗状态下USB控制器和USB PHY的工作，使系统进入低功耗状态时，USB控制器和USB PHY也可以下电，节约低功耗状态下系统的电能消耗。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
本申请实施例方法中的步骤可以根据实际需要进行顺序调整、合并和删减。
本申请实施例装置中的模块可以根据实际需要进行合并、划分和删减。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种系统级芯片SOC，其特征在于，包括：系统唤醒控制模块、处理器CPU、USB控制器和通用串行总线物理层模块USB PHY；其中：
    所述系统唤醒控制模块用于在所述SOC接收到用于指示进入低功耗状态的指令后，将所述CPU、USB控制器及USB PHY下电；
    所述系统唤醒控制模块还用于在所述SOC接收到用于指示退出所述低功耗状态的指令后，将所述CPU、USB控制器及USB PHY上电。
  2. 如权利要求1所述的SOC，其特征在于，所述SOC还用于在所述SOC接收到用于指示进入低功耗状态的指令后，通过总线保持电路保持目标总线的电平；其中，所述总线保持电路包括系统唤醒控制器或下拉电阻，所述目标总线为所述SOC与USB从设备之间的总线。
  3. 如权利要求2所述的SOC，其特征在于，所述SOC接收到用于指示进入低功耗状态的指令包括：所述SOC检测到所述目标总线的电平在预设时间段内没有发生变化。
  4. 如权利要求2所述的SOC，其特征在于，所述SOC接收到用于指示进入低功耗状态的指令包括：所述SOC接收到USB从设备发送的数据包；其中，所述数据包为所述SOC向所述USB从设备发送链路层电源管理LPM数据包的响应数据包，或者所述数据包为所述USB从设备向所述SOC发送的LPM数据包。
  5. 如权利要求3或4所述的SOC，其特征在于，所述SOC接收到用于指示退出所述低功耗状态的指令包括：所述SOC通过所述系统唤醒控制模块检测到所述目标总线电平发生变化。
  6. 如权利要求3或4所述的SOC，其特征在于，所述SOC还用于在所述系统唤醒控制模块唤醒所述CPU、USB控制器及USB PHY之后，关闭所述总线保持电路。
  7. 一种通用串行总线USB主设备，其特征在于，包括：系统级芯片SOC和总线保持电路；其中，所述SOC为权利要求1-6任一项所述的SOC。
  8. 一种通用串行总线USB系统，其特征在于，包括：USB主设备和USB从设备；其中，所述USB主设备包括系统级芯片SOC和总线保持电路；
    其中，所述SOC为权利要求1-6任一项所述的SOC。
  9. 一种通用串行总线USB唤醒方法，其特征在于，包括：
    若系统级芯片SOC接收到用于指示进入低功耗状态的指令，则所述SOC将处理器 CPU、USB控制器和通用串行总线物理层模块USB PHY下电；
    若所述SOC接收到用于指示退出所述低功耗状态的指令，则所述SOC将所述CPU、USB控制器和USB PHY上电。
  10. 根据权利要求9所述的方法，其特征在于，所述若系统级芯片SOC接收到用于指示进入低功耗状态的指令之后，所述方法还包括：
    所述SOC通过所述总线保持电路保持目标总线的电平，所述目标总线为所述SOC与USB从设备之间的总线；
    所述若SOC接收到用于指示退出所述低功耗状态的指令，则所述SOC将所述CPU、USB控制器和USB PHY上电，包括：
    若所述目标总线电平发生变化，则将所述CPU、USB控制器和USB PHY上电。
  11. 如权利要求10所述的方法，其特征在于，所述若所述目标总线电平发生变化，则将所述CPU、USB控制器和USB PHY上电，包括：
    通过系统唤醒控制模块检测所述目标总线的电平；
    若所述目标总线电平发生变化，则通过所述系统唤醒控制模块将所述CPU、USB控制器和USB PHY上电。
  12. 如权利要求9-11任一项所述的方法，其特征在于，所述若系统级芯片SOC接收到用于指示进入低功耗状态的指令包括：若系统级芯片SOC检测到所述目标总线的电平在预设时间段内没有发生变化。
  13. 如权利要求9-11任一项所述的方法，其特征在于，所述若系统级芯片SOC接收到用于指示进入低功耗状态的指令包括：若所述系统级芯片接收到USB从设备发送的数据包；其中，所述数据包为SOC向所述USB从设备发送链路层电源管理LPM数据包的响应数据包，或者所述数据包为所述USB从设备向所述SOC发送的LPM数据包。
  14. 如权利要求12或13所述的方法，其特征在于，所述SOC将所述CPU、USB控制器及USB PHY上电之后，所述方法还包括：
    所述SOC关闭所述总线保持电路。
  15. 如权利要求10所述的方法，其特征在于，所述总线保持电路包括总线保持器或者下拉电阻。
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