WO2022257535A1 - 芯片组件 - Google Patents

芯片组件 Download PDF

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Publication number
WO2022257535A1
WO2022257535A1 PCT/CN2022/081981 CN2022081981W WO2022257535A1 WO 2022257535 A1 WO2022257535 A1 WO 2022257535A1 CN 2022081981 W CN2022081981 W CN 2022081981W WO 2022257535 A1 WO2022257535 A1 WO 2022257535A1
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WO
WIPO (PCT)
Prior art keywords
chip
circuit board
limiting portion
side wall
reinforcing
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PCT/CN2022/081981
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English (en)
French (fr)
Inventor
宋婷婷
庞健
孙拓北
Original Assignee
深圳市中兴微电子技术有限公司
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Publication of WO2022257535A1 publication Critical patent/WO2022257535A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure relates to the field of electronic equipment, and in particular, to chip components.
  • the chip is packaged on a circuit board, it is assembled into a corresponding electronic device.
  • the function of the chip is becoming more and more powerful, the number of layers of the circuit board carrying the chip is also increasing, and the package size is also increasing.
  • Packaging chips inevitably introduces stress strains that can cause board warpage.
  • the present disclosure provides a chip assembly, including a circuit board and at least one chip packaged on the circuit board; the chip assembly further includes a reinforcement ring, the reinforcement ring is arranged around the circuit board, and the reinforcement ring includes A plurality of reinforced side walls and a plurality of limiting parts, the plurality of reinforced side walls are connected in turn to form a frame shape, and the reinforced side walls are attached to the side of the circuit board, at least one of the reinforced side walls At least one limiting portion is provided, and each limiting portion extends from the reinforced side wall provided with the limiting portion toward the middle of the circuit board.
  • FIG. 1 is a schematic front view of an embodiment of a chip assembly provided by the present disclosure
  • Fig. 2 is a schematic cross-sectional view of the chip assembly shown in Fig. 1;
  • Figure 3 is a schematic rear view of the chip assembly shown in Figure 1;
  • FIG. 4 is a schematic cross-sectional view of a chip assembly provided in a comparative example.
  • a chip assembly is provided. As shown in FIGS. 1 and 2, the chip assembly includes a circuit board 400 and at least one chip packaged on the circuit board 400 (shown in FIGS. In the illustrated embodiment, three chips are packaged on the circuit board 400, namely chip 321, chip 322 and chip 323).
  • the chip assembly also includes a reinforcement ring 100. As shown in FIG. 2, the reinforcement ring 100 is arranged around the circuit board 400.
  • the reinforcement ring 100 includes a plurality of reinforcement side walls 120 and a plurality of stoppers 110, and the plurality of reinforcement side walls 120 are in turn connected to form a frame (see FIG. 3 ), and the reinforced side wall 120 is bonded to the side of the circuit board 400 .
  • At least one limiting portion 110 is disposed on at least one reinforcing side wall 120 , and each limiting portion 110 extends from the reinforcing side wall 120 on which the limiting portion 110 is disposed toward the middle of the circuit board 400 .
  • the reinforcing ring 100 including the reinforcing side wall 120 and the limiting portion 110 plays a role of wrapping the circuit board 400.
  • the rigidity at the edge of the circuit board 400 can be enhanced, so that Avoid or alleviate the warping of the circuit board caused by the stress and strain caused by the packaged chip, so as to improve the service life of the chip component.
  • the reinforcing side wall 120 of the reinforcing ring 100 and the limiting portion 110 of the reinforcing ring 100 can enhance the edge rigidity of the circuit board 400 from two directions, and the reinforcing side wall 120 and the limiting portion 110 also form a limiting Therefore, no matter whether it is the reinforced side wall 120 or the limiting part 110, it does not need a particularly large thickness (for example, the dimension of the reinforced side wall 120 in the direction perpendicular to the side of the circuit board 400 in the plane where the circuit board 400 is located , the size of the limiting portion 110 in the direction perpendicular to the plane where the circuit board 400 is located), will not interfere with the subsequent setting of other components (such as heat sinks) on the chip, which is beneficial to the subsequent processing and installation of the chip assembly .
  • other components such as heat sinks
  • a through hole is defined between the limiting parts 110 to expose the chip and the components on the chip, so as to facilitate the maintenance of the chip and the components on the chip.
  • the number of reinforcing sidewalls 120 in the reinforcing ring 100 there is no special limitation on the number of reinforcing sidewalls 120 in the reinforcing ring 100 , and the number of reinforcing sidewalls 120 can be set according to the shape of the circuit board 400 .
  • the circuit board 400 is a rectangular plate, and the reinforcing ring 100 is also a rectangular ring. Therefore, the reinforcing ring 100 includes four reinforcing side walls 120 .
  • the number of limiting portions 110 in the reinforcing ring 100 there is no special limitation on the number of limiting portions 110 in the reinforcing ring 100 .
  • the number of the limiting portions 110 may be the same as the number of the reinforced sidewalls 120 , or may be less than or greater than the number of the reinforced sidewalls 120 .
  • one limiting portion 110 may be provided on each reinforced side wall 120 , or only a portion of the reinforced side wall 120 may be provided with a limiting portion 110 , or multiple limiting portions may be set on each reinforced side wall 120 Section 110.
  • all of the reinforcing side walls 120 may be provided with limiting portions 110 .
  • the limiting part 110 can be arranged on the top of the reinforced side wall 120, and the top surface of the limiting part 110 (the upper surface in FIG. The top surfaces of the chip 322 and the chip 323) are flush, and this arrangement makes it more convenient to arrange other components (for example, heat dissipation elements) on the chip.
  • the length of the limiting portion 110 there is no special limitation on the length of the limiting portion 110 (ie, the dimension in the direction extending along the side of the circuit board 400 within the plane where the circuit board 400 is located).
  • the length of the limiting portion 110 may be the same as the length of the reinforced side wall 120 provided with the limiting portion 110 (that is, the dimension in the direction extending along the side of the circuit board 400 in the plane where the circuit board 400 is located) same.
  • the chip can be packaged on a circuit board through an interposer.
  • the adapter board is arranged on the circuit board, and the chip is arranged on the adapter board.
  • spaces between adjacent chips are filled with a first filling resin.
  • the first filling resin may be epoxy resin.
  • a second filling resin 310 may be filled outside the edge of the chip, and the edge of the second filling resin 310 is aligned with the edge of the interposer board.
  • the chip may be any one of a logic control chip, a memory chip, and a dummy chip. Multiple chips can be 2.5D packaged COW (Chip on Wafer) and integrated fan-out wafer-level package (Integrated Fan Out, InFO) chip structure.
  • 2.5D packaged COW Chip on Wafer
  • integrated fan-out wafer-level package Integrated Fan Out, InFO
  • the reinforcing ring 100 may be fixedly connected to the circuit board 400 through an adhesive.
  • the coefficient of thermal expansion of the reinforcement ring 100 needs to be considered.
  • the coefficient of thermal expansion of the reinforcing ring 100 and the thermal expansion coefficient of the circuit board 400 should be similar, so that the degree of deformation of the reinforcing ring 100 and the circuit board 400 at different temperatures is approximately the same, thus, the reinforcing ring 100 does not It is easy to fall off from the circuit board 400 and not easy to cause damage to the circuit board 400 .
  • the absolute value of the difference between the coefficient of thermal expansion of the reinforcing ring 100 and the coefficient of thermal expansion of the circuit board 400 does not exceed a predetermined threshold, and the predetermined threshold can be selected and set according to actual applications.
  • the predetermined threshold may be selected from the range of [0,5 ⁇ 10 ⁇ 6 /°C].
  • the reinforcing ring 100 can be made of a material with a higher elastic modulus, that is, the elastic modulus of the reinforcing ring 100 is not lower than a predetermined Elastic modulus, the predetermined elastic modulus can be selected and set according to actual application.
  • the predetermined modulus of elasticity may be 90Gpa.
  • the reinforcement ring 100 may be made of a metallic material (eg, copper, or a copper alloy).
  • the chip assembly may further include a heat dissipation element disposed on the chip. Since the top surface of the limiting part 110 is flush with the top surface of the chip, the thermal conductive material can be directly coated on the surface of the chip and fixedly connected with the heat dissipation element.
  • the circuit board 400 has a three-layer structure. Specifically, the circuit board 400 includes a first wiring layer 410 , a core layer 420 and a second wiring layer 430 stacked in sequence.
  • FIG. 4 Shown in FIG. 4 is a comparative example of the chip assembly provided by the present disclosure.
  • the difference between this comparative example and the chip assembly provided by the embodiment of the present disclosure is that the reinforcing ring 100 in the comparative example (shown in FIG. 4 ) is only set on the top surface of the circuit board 400 .
  • the reinforcement ring 100 it is necessary to set the reinforcement ring 100 to have a relatively large thickness (dimension along the direction perpendicular to the plane where the circuit board 400 is located), that is, the top surface of the reinforcement ring 100 exceeds the chip ( includes chip 321 , not shown, and the top surface of chip 322 and chip 323 ).
  • the heat dissipation element in order to arrange the heat dissipation element on the chip, it is necessary to provide a boss at the bottom of the heat dissipation element, which increases the heat conduction path.
  • the heat dissipation element in the chip assembly provided by the present disclosure, can be directly arranged on the chip, and the heat conduction path is short, so the chip provided by the present disclosure also has a good heat dissipation effect.
  • the warpage value of the circuit board 400 obtained is 138.85 microns, and after the chip component shown in FIG. 4 is tested by the reflow process, the obtained circuit board 400 has a The warpage value is 153.46 microns, which means that the anti-warping ability of the chip assembly provided by the embodiment of the present disclosure (ie, FIG. 2 ) is 10% higher than that of the chip assembly provided by the comparative example (ie, FIG. 4 ).

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
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  • Structure Of Printed Boards (AREA)

Abstract

本公开提供一种芯片组件，包括电路板和被封装在所述电路板上的至少一个芯片；所述芯片组件还包括加强环，所述加强环环绕所述电路板设置，所述加强环包括多个加强侧壁和多个限位部，所述多个加强侧壁依次相连围成框状，且所述加强侧壁与所述电路板的侧面贴合，至少一个所述加强侧壁上设置有至少一个所述限位部，且每个所述限位部从设置有该限位部的加强侧壁朝向所述电路板的中部延伸。

Description

芯片组件
相关申请的交叉引用
本申请要求于2021年6月08日提交的中国专利申请No.202110636699.0的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本公开涉及电子设备领域，具体地，涉及芯片组件。
背景技术
通常，芯片被封装在电路板上之后，被组装进相应的电子设备中。随着芯片技术的发展，芯片的功能越来越强大，承载芯片的电路板的层数也越来越多，封装尺寸也越来越大。封装芯片会不可避免地引入应力应变，进而会导致电路板翘曲。
公开内容
本公开提供一种芯片组件，包括电路板和被封装在所述电路板上的至少一个芯片；所述芯片组件还包括加强环，所述加强环环绕所述电路板设置，所述加强环包括多个加强侧壁和多个限位部，所述多个加强侧壁依次相连围成框状，且所述加强侧壁与所述电路板的侧面贴合，至少一个所述加强侧壁上设置有至少一个所述限位部，且每个所述限位部从设置有该限位部的加强侧壁朝向所述电路板的中部延伸。
附图说明
图1是本公开所提供的芯片组件的一种实施方式的主视示意图；
图2是图1中所示的芯片组件的剖视示意图；
图3是图1中所示的芯片组件的后视示意图；以及
图4是对比例所提供的芯片组件的剖视示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的芯片组件进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现，且本公开不应当被解释为限于本文阐述的实施例。提供这些实施例的目的在于使本公开更加透彻和完整，并使本领域技术人员更充分地理解本公开的范围。
在不冲突的情况下，本公开各实施例及实施例中的各特征可相互组合。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在特定特征、整体、步骤、操作、元件和/或组件，但不排除存在或可添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
作为本公开的一个方面，提供一种芯片组件，如图1和图2所示，该芯片组件包括电路板400和被封装在该电路板400上的至少一个芯片(在图1和图2所示的实施方式中，电路板400上封装有三个芯片，分别为芯片321、芯片322以及芯片323)。所述芯片组件还包括加强环100，如图2所示，加强环100环绕电路板400设置，加 强环100包括多个加强侧壁120和多个限位部110，多个加强侧壁120依次相连，围成框状(参见图3)，且加强侧壁120与电路板400的侧面贴合。至少一个加强侧壁120上设置有至少一个限位部110，且每个限位部110从设置有该限位部110的加强侧壁120朝向电路板400的中部延伸。
在本公开中，包括加强侧壁120和限位部110的加强环100对电路板400起到了包边的作用，设置了加强环100后，可以增强电路板400的边缘处的刚度，从而可以避免或缓减由封装芯片导致的应力应变引起电路板翘曲，以提高芯片组件的使用寿命。
除此之外，加强环100的加强侧壁120和加强环100的限位部110可以从两个方向增强电路板400的边缘刚度，并且加强侧壁120和限位部110还形成了一个限位空间，因此，无论是加强侧壁120还是限位部110，都不需要特别大的厚度(例如，加强侧壁120在电路板400所在平面内垂直于电路板400的侧面的方向上的尺寸，限位部110在垂直于电路板400所在平面的方向上的尺寸)，也不会对后续在芯片上设置其他元器件(例如，散热件)造成干涉，有利于芯片组件的后续加工和安装。
限位部110之间限定有通孔，以露出芯片、以及芯片上的元件，从而便于对芯片以及芯片上的元件进行维护。
在本公开中，对加强环100中加强侧壁120的数量不做特殊的限定，可以根据电路板400的形状来设置加强侧壁120的数量。在图1和图2中所示的实施方式中，电路板400为矩形板，加强环100也是矩形环，因此，加强环100包括四个加强侧壁120。
在本公开中，对加强环100中限位部110的数量也不做特殊的限定。限位部110的数量可以与加强侧壁120的数量相同、也可以小于或大于加强侧壁120的数量。例如，每个加强侧壁120上可设置一个限位部110，也可以只在部分加强侧壁120上设置限位部110，或者，也可以在每个加强侧壁120上设置多个限位部110。当然，为了获得更好的防翘曲效果，可在所有加强侧壁120上都设置限位部110。
如上文中所述，无需对加强侧壁120和限位部110设置较大的 厚度、以便于后续安装其他与芯片配合的元器件。在一些实施方式中，可以将限位部110设置在加强侧壁120的顶端，且限位部110的顶面(图2中的上表面)与被封装在电路板400上的芯片(图2中的芯片322和芯片323)的顶面平齐，通过这种设置，使得在芯片上设置其他元器件(例如，散热元件)更加方便。
在本公开中，对限位部110的长度(即在电路板400所在平面内沿电路板400的侧面延伸的方向上的尺寸)不做特殊的限定。为了便于加工和制造，限位部110的长度可以与设置有该限位部110的加强侧壁120的长度(即在电路板400所在平面内沿电路板400的侧面延伸的方向上的尺寸)相同。
在本公开中，对将芯片封装在电路板上的方式没有特殊的要求。例如，可以通过转接板将芯片封装在电路板上。具体地，转接板设置在所述电路板上、以及所述芯片设置在所述转接板上。为了对芯片进行保护，在一些实施方式中，在相邻芯片之间的间隔中填充第一填充树脂。在一些实施方式中，所述第一填充树脂可以为环氧树脂。
为了进一步保护芯片，如图1和图2所示，在一些实施方式中，可以在芯片的边缘外侧填充第二填充树脂310，且该第二填充树脂310的边缘与转接板的边缘对齐。
所述芯片可以是逻辑控制芯片、存储芯片、和假片中的任意一者。多个芯片可以是2.5D封装的COW(Chip on Wafer)和集成扇出晶圆级封装(Integrated Fan Out，InFO)芯片结构。
在本公开中，对将加强环100与电路板400固定连接的方法不做特殊的限定，在一些实施方式中，加强环100可以通过粘结剂与电路板400固定连接。
在选择加强环100的材料时，需要考虑加强环100的热膨胀系数。在一些实施方式中，加强环100的热膨胀系数与电路板400的热膨胀系数应当是近似的，从而使得不同温度下加强环100与电路板400的变形程度是大致相同的，从而，加强环100不容易从电路板400上脱落、也不容易对电路板400造成损伤。具体地，加强环100的热膨胀系数与电路板400的热膨胀系数之差的绝对值不超过预定阈值， 所述预定阈值可根据实际应用选择和设定。在一些实施方式中，所述预定阈值可以选自[0,5×10 -6/℃]的范围内。
如上文中所述，加强环100的主要功能是增加电路板400边缘处的刚度，因此，加强环100可由弹性模量较高的材料制成，即，加强环100的弹性模量不低于预定弹性模量，所述预定弹性模量可根据实际应用选择和设定。例如，所述预定弹性模量可以为90Gpa。
在一些实施方式中，可以利用金属材料(例如，铜、或铜合金)制成加强环100。
如上文中所述，所述芯片组件还可以包括设置在芯片上的散热元件。由于限位部110的顶面与芯片的顶面平齐，可以直接在芯片表面涂覆导热材料，并与散热元件固定连接。
在本公开中，对电路板400的具体结构也不做特殊的限定。在图2中所示的实施方式中，电路板400为三层结构，具体地，电路板400包括依次层叠设置的第一走线层410、核心层420和第二走线层430。
图4中所示的是本公开所提供的芯片组件的对比例，此对比例与本公开实施例所提供的芯片组件的区别在于，对比例(图4所示)中的加强环100仅设置在电路板400的顶面上。为了实现较好的防翘曲效果，需要将加强环100设置为具有相对较大的厚度(沿垂直于电路板400所在平面的方向上的尺寸)，即，加强环100的顶面超过芯片(包括未示出的芯片321、以及芯片322和芯片323)的顶面。这种情况下，为了在芯片上设置散热元件，需要在散热元件底部设置凸台，增加了导热路径。相较之下，本公开所提供的芯片组件中，可以直接将散热元件设置在芯片上，导热路径短，因此，本公开所提供的芯片还具有良好的散热效果。
通过在回流工艺中对图2所示的芯片组件进行测试，获得电路板400的翘曲值为138.85微米，而对图4中所示的芯片组件进行回流工艺测试后，获得的电路板400的翘曲值为153.46微米，相当于本公开实施例(即图2)提供的芯片组件的防翘曲能力比对比例(即图4)提供的芯片组件的防翘曲能力提高了10％。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则与特定实施例相结合描述的特征、特性和/或元素可单独使用，或可与结合其它实施例描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种芯片组件，包括电路板和被封装在所述电路板上的至少一个芯片；其中，所述芯片组件还包括加强环，所述加强环环绕所述电路板设置，所述加强环包括多个加强侧壁和多个限位部，所述多个加强侧壁依次相连围成框状，且所述加强侧壁与所述电路板的侧面贴合，至少一个所述加强侧壁上设置有至少一个所述限位部，且每个所述限位部从设置有该限位部的加强侧壁朝向所述电路板的中部延伸。
  2. 根据权利要求1所述的芯片组件，其中，所述限位部设置在所述加强侧壁的顶端，且所述限位部的顶面与所述芯片的顶面平齐。
  3. 根据权利要求2所述的芯片组件，其中，所述限位部的长度与设置有该限位部的加强侧壁的长度相同。
  4. 根据权利要求1所述的芯片组件，还包括转接板，所述转接板设置在所述电路板上，所述芯片设置在所述转接板上，相邻所述芯片之间的间隔内填充有第一填充树脂。
  5. 根据权利要求4所述的芯片组件，其中，所述芯片的外边缘外侧设置有第二填充树脂，且所述第二填充树脂的边缘与所述转接板的边缘对齐。
  6. 根据权利要求1至5中任意一项所述的芯片组件，其中，所述加强环通过粘结剂与所述电路板固定连接。
  7. 根据权利要求1至5中任意一项所述的芯片组件，其中，所述加强环的热膨胀系数与所述电路板的热膨胀系数之差的绝对值不超过预定阈值。
  8. 根据权利要求1至5中任意一项所述的芯片组件，其中，所述加强环由金属材料制成。
  9. 根据权利要求8所述的芯片组件，其中，所述加强环的材料为铜或铜合金。
  10. 根据权利要求1至5中任意一项所述的芯片组件，还包括散热元件，所述散热元件设置在所述芯片上。
PCT/CN2022/081981 2021-06-08 2022-03-21 芯片组件 WO2022257535A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949137A (en) * 1997-09-26 1999-09-07 Lsi Logic Corporation Stiffener ring and heat spreader for use with flip chip packaging assemblies
WO2005081310A1 (ja) * 2004-02-23 2005-09-01 Takeshi Hori Ｉｃモジュール、ｉｃモジュールを含む基板、ｉｃモジュールを含む基板の製造方法
US20080042263A1 (en) * 2006-08-21 2008-02-21 Advanced Semiconductor Engineering, Inc. Reinforced semiconductor package and stiffener thereof
US20100309628A1 (en) * 2009-06-03 2010-12-09 Kabushiki Kaisha Toshiba Electronic device
CN214753761U (zh) * 2021-06-08 2021-11-16 深圳市中兴微电子技术有限公司 一种芯片组件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949137A (en) * 1997-09-26 1999-09-07 Lsi Logic Corporation Stiffener ring and heat spreader for use with flip chip packaging assemblies
WO2005081310A1 (ja) * 2004-02-23 2005-09-01 Takeshi Hori Ｉｃモジュール、ｉｃモジュールを含む基板、ｉｃモジュールを含む基板の製造方法
US20080042263A1 (en) * 2006-08-21 2008-02-21 Advanced Semiconductor Engineering, Inc. Reinforced semiconductor package and stiffener thereof
US20100309628A1 (en) * 2009-06-03 2010-12-09 Kabushiki Kaisha Toshiba Electronic device
CN214753761U (zh) * 2021-06-08 2021-11-16 深圳市中兴微电子技术有限公司 一种芯片组件

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