WO2022257517A1 - 一种近阈值单元电路延时模型 - Google Patents

一种近阈值单元电路延时模型 Download PDF

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WO2022257517A1
WO2022257517A1 PCT/CN2022/080128 CN2022080128W WO2022257517A1 WO 2022257517 A1 WO2022257517 A1 WO 2022257517A1 CN 2022080128 W CN2022080128 W CN 2022080128W WO 2022257517 A1 WO2022257517 A1 WO 2022257517A1
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delay
formula
input
unit circuit
current
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曹鹏
徐冰倩
姜海洋
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Southeast University
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/337—Design optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/373—Design optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Definitions

  • the invention relates to the field of integrated circuit design, in particular to a delay model of a near-threshold unit circuit.
  • the near-threshold unit circuit delay model is of great significance to the timing information of the circuit in the early design, and it can quickly predict the delay data of the unit circuit under different working scenarios.
  • the current industry method is the look-up table method, that is, the look-up table is obtained through simulation, and then the look-up table is interpolated to obtain the unit delay.
  • the establishment of the look-up table requires a lot of simulation and time overhead. big. Therefore, it is necessary to establish a fast and accurate delay model for near-threshold cell circuits.
  • the challenges to be addressed in establishing a delay model for near-threshold cell circuits can be mainly divided into two aspects.
  • the input transition time leads to a nonlinear change in the delay, and the linear and nonlinear relationships between the delay and the input transition time need to be modeled separately, and the complexity of the near-threshold current formula makes the integral-based modeling method under the conventional voltage No longer applicable;
  • the current unit circuit delay model based on the equivalent current method is only for the case of a specific input transition time, and does not fully consider the impact of the input transition time on the delay.
  • the purpose of this invention is to set up a kind of fast and accurate near-threshold cell circuit delay model considering the input conversion time, and obtain the delay of the inverter and the composite unit by the equivalent current method and the nature of the logarithmic partial normal distribution
  • Time-nominal model and time-delay statistical model have the advantages of high precision and low time overhead.
  • the unit circuit includes an inverter, a stacked structural unit and a parallel structural unit, and the model includes the following steps:
  • S1 Obtain parameters, including process parameters of each transistor of the unit circuit, unit circuit parameters and slow input delay parameters;
  • S2 Judging the unit circuit type, including judging whether the unit circuit is an inverter, a stacked structure unit, or a parallel structure unit, calculating the large current, small current and current integral of the unit circuit according to the unit circuit type, and calculating the large current and small current The mean, variance and skewness of the natural logarithm of the sum, and calculate the mean and variance of the equivalent threshold voltage;
  • judge delay type according to the unit circuit type that step S2 obtains, calculate the overshoot time and the time delay of unit circuit, then, according to the relative size relation of overshoot time, time delay and input conversion time, judge delay type is Very fast input, fast input, or slow input; if the overshoot time is greater than the input transition time, the delay type is very fast input; if the overshoot time is less than the input transition time and the delay is greater than half the input transition time, the delay type is It is a fast input; if the overshoot time is less than the input transition time and the delay is less than half of the input transition time, the delay type is slow input;
  • step S4 according to the unit circuit type that step S2 obtains and the time delay type that step S3 obtains, set up unit circuit time delay nominal model, obtain time delay nominal value;
  • a unit circuit delay statistical model is established according to the unit circuit type obtained in step S2 and the delay type obtained in step S3 to obtain delay statistics: variance, maximum value and minimum value.
  • the process parameters include the sub-threshold slope factor, the drain-side induction source-side barrier reduction effect coefficient, and the circuit parameters include transistor size, load, input transition time, supply voltage, temperature, process angle, and slow input delay parameters Including fitting parameters a, b in formula (1), fitting parameters c, d in formula (2), fitting parameters a, b, c, d are obtained by delay fitting under slow input simulation,
  • step S2 if the unit circuit is an inverter, the step S2 includes:
  • V gs and V ds are the gate-source voltage and source-drain voltage
  • I ds is the source-drain current
  • V dd is the supply voltage
  • V ds ( ⁇ ) is the source-drain voltage at the moment of the input transition time, through the formula (4 ) is calculated
  • ⁇ is the effect coefficient of drain-side-induced source-side barrier reduction
  • n is the subthreshold slope factor
  • ⁇ t is the thermal voltage
  • I 0 is a parameter affected by process parameters
  • K 0 , K 1 , and K 2 are determined by Process-dependent fitting coefficients
  • C M is the coupling capacitance of input and output
  • C L is the load capacitance
  • the natural logarithm Y of the sum of the current is the natural logarithm of the sum of the large current and the small current, that is, I H + I L , expressed as formula (5), and the sum logarithm Y of the current is calculated according to formula (6) Mean ⁇ Y , variance ⁇ Y 2 and skewness ⁇ 1 ;
  • m is calculated by formula (7) under extremely fast input
  • m is calculated by formula (8) under fast input
  • k 2 is a fitting coefficient determined by the process
  • ⁇ V th is the threshold voltage Fluctuation
  • ⁇ V th' is calculated by formula (9)
  • E[ ] is the mean value of the corresponding random variable
  • k 1 is a fitting coefficient determined by the process
  • V th0 is the nominal value of the threshold voltage
  • the step S2 if the unit circuit is a stacked structural unit, the step S2 includes:
  • V g and V d are the gate voltage and drain voltage
  • V s is the source voltage
  • V XH and V XL are the intermediate node voltage under different gate voltage and drain voltage.
  • V XH is V XH1 , which is the intermediate node voltage when the gate voltage and drain voltage are both supply voltages.
  • V XH is V XH2 , which is the gate voltage is the supply voltage and the drain voltage is the intermediate node voltage when the drain terminal voltage at the input conversion time is calculated according to formula (11), V d ( ⁇ ) is the drain terminal voltage at the input conversion time;
  • V thU and V thD are the threshold voltage of the upper tube and the lower tube in the stacked structural unit, respectively, W U and W D are the width of the upper tube and the lower tube in the stacked structural unit, respectively, and m2 is the pseudo combined coefficient;
  • D[ ⁇ ] is the variance of the corresponding random variable
  • S k [ ⁇ ] is the skewness of the corresponding random variable
  • Cov[ ⁇ ] is the covariance of the corresponding random variable
  • Y 1 and Y 2 It can be calculated by formula (13)
  • V th1 and V th2 are the threshold voltages of the left and right transistors in the parallel structure
  • ⁇ V th1 and ⁇ V th2 are the threshold voltage fluctuations of the left and right transistors in the parallel structure
  • the step S3 judging the delay type includes calculating the overshoot time t ov and the delay td according to the unit circuit type, comparing the input conversion time, the overshoot time and the delay time, and judging whether the input is extremely fast input or fast input Or slow input, specifically including:
  • step S31 Substituting the large current I H1 under extremely fast input, high current I H2 under fast input, small current I L and current integral k obtained in step S2 into formula (20) to calculate the overshoot time t ov , and substitute it into formula 21 to calculate the delay time when td,
  • the establishment of the unit circuit delay statistical model includes according to the unit circuit type and the delay type, based on the delay nominal model in step S4, to obtain the delay statistics: variance, maximum value and minimum value, if the delay type is very fast input, the step S5 includes:
  • step S51 Based on the nature of the logarithmic partial normal distribution, the current sum logarithmic mean value ⁇ Y , variance ⁇ Y 2 and skewness ⁇ 1 obtained in step S2 are substituted into formula (23) to calculate the distribution parameters: position parameter ⁇ Y , scale parameter ⁇ Y and the second shape parameter ⁇ Y
  • ⁇ ( ⁇ ) is the cumulative density distribution function of the standard normal distribution.
  • the step S5 includes:
  • step S51 Based on the nature of the logarithmic partial normal distribution, the current sum logarithmic mean value ⁇ Y , variance ⁇ Y 2 and skewness ⁇ 1 obtained in step S2 are substituted into formula (23) to calculate the distribution parameters: position parameter ⁇ Y , scale parameter ⁇ Y and a second shape parameter ⁇ Y ;
  • step S51 based on the mean value and variance of the equivalent threshold voltage obtained in step S2, calculate the mean value E (td), variance D (td) and skewness S k (td) of the time delay according to formula (26);
  • p i and q i are coefficients, which are functions of threshold voltage and current
  • the invention discloses a delay model of a near-threshold unit circuit considering the input conversion time, and obtains the nominal delay model and
  • the delay statistical model has the advantages of high precision and low time overhead.
  • the error of the nominal delay value of the inverter is less than 5.55%, the error of the delay variance is less than 14.87%, and the error of the -3 ⁇ value is less than 15.16%, + The error of the 3 ⁇ value is less than 10.87%;
  • the error of the nominal value of the delay of the stacked structure unit is less than 10.78%, the error of the variance is less than 16.43%, the error of the -3 ⁇ value is less than 19.34%, and the error of the +3 ⁇ value is less than 14.91% ;
  • the nominal value error of the parallel structure unit delay is less than 7.31%, the variance error is less than 15.91%, the error of -3 ⁇ value is less than 9.78%, and the error of +3 ⁇ value is less than 9.63%
  • Fig. 1 is the flowchart of the near-threshold unit circuit delay model of the specific embodiment of the present invention
  • Fig. 2 is the classification situation of the time-delay type of the near-threshold value unit circuit of the specific embodiment of the present invention; (a) is the situation that the time-delay type is very fast input; (b) is the situation that the time-delay type is fast input; (c) This is the case where the delay type is slow input.
  • Fig. 1 is the flowchart of the near-threshold unit circuit delay model of the embodiment of the present invention. The main steps are as follows:
  • the process parameters of each transistor in the unit circuit include the sub-threshold slope factor, the drain-side induction source-side barrier reduction effect coefficient, which are obtained through the nominal DC simulation of the smallest size transistor;
  • the unit circuit parameters include transistor size, load, input conversion time, Supply voltage, temperature, process angle, transistor size is minimum size, load is 1fF, input transition time is 50ps, 500ps and 1ns, supply voltage is 0.4V, temperature is 25°C, process angle is TT process angle, slow input delay
  • the parameters include the slow input delay expression, which can be obtained by fitting the simulated slow input lower delay.
  • the process parameters and circuit parameters are substituted into formula (1) and formula (2), and the large current I H1 under extremely fast input, the large current I H2 under fast input, and the small current I L are respectively obtained , the current integral k and the mean value ⁇ Y , the variance ⁇ Y 2 , and the skewness ⁇ 1 of the current sum logarithm Y; if the unit circuit type is a stacked structural unit, then substitute the process parameters and circuit parameters into formula (3), formula ( 4) and formula (5), respectively get the mean value ⁇ Y and variance ⁇ Y of the large current I H1 under extremely fast input, the large current I H2 under fast input, the small current I L , the current integral k, and the logarithm Y of the sum of the current 2.
  • the mean value and variance of the skewness ⁇ 1 and the equivalent threshold voltage if the unit circuit type is a parallel structural unit, then substituting the process parameters and circuit parameters into formula (6), formula (7) and formula (8), respectively get High current I H1 under extremely fast input, large current I H2 under fast input, small current I L , current integral k, mean value ⁇ Y of the logarithm Y of the sum of currents, variance ⁇ Y 2 , skewness ⁇ 1 and equivalent threshold The mean and variance of the voltage;
  • m is the coefficient
  • k2 is the fitting coefficient determined by the process
  • ⁇ V th is the threshold voltage fluctuation
  • ⁇ V th' is the function of the threshold voltage
  • E[ ⁇ ] is the mean value of the corresponding random variable.
  • V g and V d are gate voltage and drain voltage
  • V s is source voltage
  • V XH and V XL are intermediate node voltages under different gate voltages and drain voltages.
  • V XH is V XH1 , which is the intermediate node voltage when the gate voltage and drain voltage are both supply voltages.
  • V XH is V XH2 , which is the gate voltage is the supply voltage and the drain voltage is the intermediate node voltage when the drain terminal voltage at the input conversion time is input
  • V d ( ⁇ ) is the drain terminal voltage at the input conversion time
  • k 1 is a fitting coefficient determined by the process;
  • D[ ⁇ ] is the variance of the corresponding random variable
  • S k [ ⁇ ] is the skewness of the corresponding random variable
  • Cov[ ⁇ ] is the covariance of the corresponding random variable.
  • ⁇ V th_eff is the equivalent threshold voltage
  • ⁇ V thH and ⁇ V thL are linear functions of the threshold voltage fluctuation ⁇ V thU of the upper tube and the threshold voltage fluctuation ⁇ V thD of the lower tube.
  • ⁇ V th1 and ⁇ V th2 are the threshold voltage fluctuations of the left and right transistors in the parallel structure.
  • step S3 Determine the delay type, according to the unit circuit type, substitute the large current I H1 under extremely fast input, high current I H2 under fast input, small current I L , current integral k and input conversion time calculated in step S2 into the formula (9) and formula (10), calculate the overshoot time t ov and delay td, compare the relationship between the input conversion time, overshoot time and delay, and judge whether the delay type is extremely fast input, fast input or slow input .
  • the input transition time is 50ps, compare the calculated overshoot time t ov , delay td and input transition time, and find that the overshoot time t ov is greater than the input transition time and the delay td is greater than half of the input transition time, it is extremely fast Input; if the input transition time is 500ps, compare the calculated overshoot time t ov , delay td and input transition time, and find that the overshoot time t ov is less than the input transition time and the delay td is greater than half of the input transition time, then it is Fast input; if the input transition time is 1ns, compare the calculated overshoot time t ov , delay td and input transition time, and find that the overshoot time t ov is less than the input transition time and the delay td is less than half of the input transition time, then For slow input.
  • td is the unit circuit delay
  • ⁇ is the input conversion time
  • C M is the coupling capacitance of input and output
  • C L is the load capacitance
  • td s is the step delay time
  • a and b are fitting parameters.
  • step S5 Establish a unit circuit delay statistical model, according to the unit circuit type and delay type, based on the unit delay nominal model, obtain the delay statistics: variance, maximum value and minimum value. If the delay type is extremely fast input, step S2 obtains the logarithmic mean ⁇ Y , variance ⁇ Y 2 and skewness ⁇ 1 of the sum of the large and small currents into equation (13), and calculates the distribution parameters: position parameter ⁇ Y , Proportional parameter ⁇ Y and second shape parameter ⁇ Y , the distribution parameter is substituted into formula (14) to calculate the variance D(td) of the delay time, and the distribution parameter is substituted into formula (15) to calculate the maximum value td max and the minimum time delay value td min ; if the delay type is fast input, step S2 obtains the logarithmic mean value ⁇ Y , variance ⁇ Y 2 and skewness ⁇ 1 of the sum of the large current and the small current into equation (13), and calculates the distribution parameter: position parameter
  • ⁇ ( ) is the cumulative density distribution function of the standard normal distribution
  • FIG. 2 is a classification of delay types of near-threshold unit circuits according to a specific embodiment of the present invention.
  • the delay type in Figure 2(a) is extremely fast input, the overshoot time is greater than the input transition time and the delay is greater than half of the input transition time;
  • the delay type in Figure 2(b) is fast input, the overshoot time is less than the input Conversion time and the delay is greater than half of the input conversion time;
  • the delay type is slow input, the overshoot time is less than the input conversion time and the delay is less than half of the input conversion time.

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Abstract

一种近阈值单元电路延时模型，其中，获取参数包括获取工艺参数、电流参数和慢输入延时参数，判断单元电路类型包括判断单元是否为反相器、堆叠结构单元、并联结构单元，根据单元电路类型计算电流和电流积分，计算电流之和对数的均值、方差和偏度，计算等效阈值电压的均值、方差，判断延时类型包括根据单元电路类型计算得到过冲时间和延时，比较输入转换时间、过冲时间和延时的大小关系，判断延时类型是极快输入、快输入或者慢输入，建立单元电路延时标称模型是根据单元电路类型和延时类型，建立单元电路延时标称模型，得到延时标称值，建立单元电路延时统计模型是根据单元电路类型和延时类型，建立单元电路延时统计模型。

Description

一种近阈值单元电路延时模型 技术领域
本发明涉及集成电路设计领域，特别是涉及一种近阈值单元电路延时模型。
背景技术
随着物联网等低功耗技术的兴起，如何在低功耗下提高电路性能成为了集成电路发展的关键问题，降低电源电压是降低功耗的有效手段之一。由于近阈值电路的能效优势，近阈值电路的设计和研究受到了广泛的关注。
近阈值单元电路延时模型对于设计初期研究电路的时序信息具有重大意义，它能快速预测不同工作场景下单元电路的延时数据。对于近阈值单元电路延时模型，目前工业界的方法是查找表法，即通过仿真获得查找表，然后对查找表进行插值来获得单元延时，但查找表的建立需要进行大量仿真，时间开销大。因此，需要建立一个快速准确的近阈值单元电路延时模型。建立近阈值单元电路延时模型所需应对的挑战主要可以分为两个方面。第一，输入转换时间导致延时的非线性变化，需要对延时与输入转换时间的线性和非线性关系分别建模，而近阈值电流公式的复杂性使得常规电压下基于积分的建模方法不再适用；第二，由于单元延时与工艺参数之间的非线性关系，近阈值下单元延时服从非高斯分布，导致原来基于高斯分布的单元延时模型不再适用。因此，需要建立一个快速准确的近阈值单元电路延时模型，在保证精度的前提下尽可能减小仿真开销。目前基于等效电流法的单元电路延时模型只针对特定输入转换时间下的情况，没有全面考虑输入转换时间对于延时的影响。
发明内容
技术问题：本发明的目的是建立一种快速准确的考虑输入转换时间的近阈值单元电路延时模型，通过等效电流法和对数偏正态分布的性质得到反相器和复合单元的延时标称模型和延时统计模型，具有高精度和低时间开销的优点。
技术方案：为达到此目的，本发明的一种近阈值单元电路延时模型采用以下技术方案：
所述单元电路包括反相器、堆叠结构单元和并联结构单元，所述模型包括以下步骤：
S1:获取参数，包括单元电路各晶体管的工艺参数、单元电路参数和慢输入延时参数；
S2:判断单元电路类型，包括判断单元电路是否为反相器、堆叠结构单元、并联结构单元，根据单元电路类型计算该单元电路的大电流、小电流和电流积分，计算该大电流和小电流之和的自然对数的均值、方差和偏度，计算等效阈值电压的均值、方差；
S3:判断延时类型，根据步骤S2得到的单元电路类型，计算单元电路的过冲时间和延时，然后，根据过冲时间、延时和输入转换时间的相对大小关系，判断延时类型是极快输入、快输入或者慢输入；如果过冲时间大于输入转换时间，则延时类型为极快输入；如果过冲时间小于输入转换时间且延时大于输入转换时间的一半，则延时类型为快输入；如果过冲时间小于输入转换时间且延时小于输入转换时间的一半，则延时类型为慢输入；
S4:根据步骤S2得到的单元电路类型和步骤S3得到的延时类型建立单元电路延时标称模型，得到延时标称值；
S5:基于延时标称模型，根据步骤S2得到的单元电路类型和步骤S3得到的延时类型建立单元电路延时统计模型，得到延时统计量：方差、最大值和最小值。
其中：
步骤S1中，所述工艺参数包括亚阈值斜率因子、漏端感应源端势垒降低效应系数，电路参数包括晶体管尺寸、负载、输入转换时间、供电电压、温度、工艺角，慢输入延时参数包 括式(1)中的拟合参数a、b，式(2)中的拟合参数c、d，拟合参数a、b、c、d通过仿真慢输入下的延时拟合获得，
Figure PCTCN2022080128-appb-000001
a＝cV th+d       (2)
式(1)中，td为单元电路延时，τ为输入转换时间，td s为阶跃延时，式(2)中，V th为阈值电压。
所述的步骤S2中，如果单元电路为反相器，所述步骤S2包括：
S21：根据式(3)计算单元电路的大电流I H、小电流I L和电流积分k，在极快输入情况下，大电流I H为极快输入下大电流I H1，是栅源电压和源漏电压均为供电电压时的源漏电流；在快输入情况下，大电流I H为快输入下大电流I H2，是栅源电压为供电电压，源漏电压为输入转换时间时刻的源漏电压时的源漏电流；
Figure PCTCN2022080128-appb-000002
式3中，V gs和V ds是栅源电压和源漏电压，I ds是源漏电流，V dd是供电电压，V ds(τ)是输入转换时间时刻的源漏电压，通过式(4)计算得到，λ是漏端感应源端势垒降低效应系数，n是亚阈值斜率因子，Φ t是热电压，I 0是受工艺参数影响的参数，K 0、K 1、K 2是由工艺决定的拟合系数；
Figure PCTCN2022080128-appb-000003
式(4)中，C M是输入输出的耦合电容，C L是负载电容；
S22：电流之和自然对数Y是所述大电流和小电流之和即I H+I L的自然对数，表示为式(5)，根据式(6)计算电流之和对数Y的均值μ Y、方差σ Y 2和偏度γ 1；
Y＝-ln(I H+I L)       (5)
Figure PCTCN2022080128-appb-000004
Figure PCTCN2022080128-appb-000005
式(6)中，在极快输入下m通过式(7)计算得到，在快输入下，m通过式(8)计算得到，k 2是由工艺决定的拟合系数，ΔV th为阈值电压波动量，ΔV th’通过式(9)计算得到，E[·]为相应的随机变量的均值，
Figure PCTCN2022080128-appb-000006
式(7)中，k 1是由工艺决定的拟合系数，V th0为阈值电压标称值
Figure PCTCN2022080128-appb-000007
Figure PCTCN2022080128-appb-000008
所述的步骤S2中，如果单元电路为堆叠结构单元，所述步骤S2包括：
S21：根据式(10)计算极快输入下大电流I H1、快输入下大I H2、小电流I L和电流积分k；
Figure PCTCN2022080128-appb-000009
式(10)中，V g和V d是栅端电压和漏端电压，V s是源端电压，V XH和V XL是不同栅端电压和漏端电压下中间节点电压，在极快输入情况下，V XH为V XH1，是栅端电压和漏端电压均为供电电压时的中间节点电压，在快输入情况下，V XH为V XH2，是栅端电压为供电电压，漏端电压为输入转换时间时刻的漏端电压时的中间节点电压，根据式(11)计算得到，V d(τ)是输入转换时间处的漏端电压；
Figure PCTCN2022080128-appb-000010
式(11)中，V thU和V thD分别是堆叠结构单元中上管阈值电压和下管阈值电压，W U和W D分别是堆叠结构单元中上管宽度和下管宽度，m 2为拟合系数；
S22：根据式(12)计算电流之和对数Y的均值E(Y)、方差D(Y)和偏度S k(Y)；
Figure PCTCN2022080128-appb-000011
式(12)中，D[·]为相应的随机变量的方差，S k[·]为相应的随机变量的偏度，Cov[·]为相应的随机变量的协方差，Y 1和Y 2可以通过式(13)计算得到
Figure PCTCN2022080128-appb-000012
式(13)中，ΔV thH和ΔV thL为上管阈值电压波动量ΔV thU和下管阈值电压波动量ΔV thD的线性函数，表示为式(14)，式(14)中α 1、α 2、α 3和α 4为系数；
Figure PCTCN2022080128-appb-000013
S23:根据式(15)计算等效阈值电压ΔV th_eff的均值和方差
Figure PCTCN2022080128-appb-000014
所述的步骤S2中，如果单元为并联结构单元，所述步骤S2包括：
S21：根据式(16)计算极快输入下大电流I H1、快输入下大电流I H2、小电流I L和电流积分k；
Figure PCTCN2022080128-appb-000015
式(16)中，V th1、V th2分别是并联结构左右两个晶体管的阈值电压，
S22：根据式(17)计算电流之和对数Y的均值E(Y)、方差D(Y)和偏度S k(Y)；
Figure PCTCN2022080128-appb-000016
式(17)中，Y 1和Y 2可以通过式(18)计算得到
Figure PCTCN2022080128-appb-000017
式(18)中，ΔV th1和ΔV th2为并联结构左右两个晶体管的阈值电压波动量，
S23:根据式(19)计算等效阈值电压ΔV th_eff的均值和方差
Figure PCTCN2022080128-appb-000018
所述的步骤S3判断延时类型包括根据单元电路类型计算得到过冲时间t ov和延时td，比较输入转换时间、过冲时间和延时的大小关系，判断输入是极快输入、快输入或者慢输入，具体包括：
S31：将步骤S2得到的极快输入下大电流I H1、快输入下大电流I H2、小电流I L和电流积分k代入式(20)计算得到过冲时间t ov，代入式21计算延时td，
Figure PCTCN2022080128-appb-000019
Figure PCTCN2022080128-appb-000020
S32：比较过冲时间t ov与输入转换时间τ的大小，如果t ov>τ，则为极快输入，反之，则为快输入或慢输入；
S33：比较延时td与输入转换时间的一半τ/2的大小，如果td>τ/2，则为快输入，反之，则为慢输入。
所述的步骤S4中，建立单元电路延时标称模型包括根据单元电路类型和延时类型，得到延时标称值，如果延时类型为极快输入，延时标称值通过式(22)计算得到；如果延时类型为快输入，延时标称值通过式(21)计算得到；如果延时类型为慢输入，延时标称值通过式(1)计算得到，
Figure PCTCN2022080128-appb-000021
所述的S5中，建立单元电路延时统计模型包括根据单元电路类型和延时类型，基于步骤S4的延时标称模型，得到延时统计量：方差、最大值和最小值，如果延时类型是极快输入，所述步骤S5包括：
S51:基于对数偏正态分布的性质将步骤S2得到电流之和对数均值μ Y、方差σ Y 2和偏度γ 1代入式(23)计算得到分布参数：位置参数ξ Y，比例参数ω Y和第二形状参数β Y
Figure PCTCN2022080128-appb-000022
S52:基于分布参数，根据式(24)计算延时的方差D(td)，根据式(25)计算延时的最大值td max和最小值td min，
Figure PCTCN2022080128-appb-000023
Figure PCTCN2022080128-appb-000024
式(24)和式(25)中，φ(·)是标准正态分布的累加密度分布函数。
所述的步骤S2中，如果延时类型是快输入，所述步骤S5包括：
S51:基于对数偏正态分布的性质将步骤S2得到电流之和对数均值μ Y、方差σ Y 2和偏度γ 1代入式(23)计算分布参数：位置参数ξ Y，比例参数ω Y和第二形状参数β Y；
S52:基于分布参数，根据式(24)计算延时的方差D(td)，根据式(25)计算延时的最大值td max和最小值td min。
所述的步骤S2中，如果延时类型是慢输入，所述步骤S5包括：
S51:基于步骤S2得到的等效阈值电压的均值和方差，根据式(26)计算延时的均值E(td)、方差D(td)和偏度S k(td)；
Figure PCTCN2022080128-appb-000025
式(26)中，p i和q i为系数，是阈值电压、电流的函数，
S52:基于偏正态分布的性质，根据式(23)计算延时的分布参数：位置参数ξ td，比例参数ω td和第二形状参数β td，
S53:基于分布参数，根据式(27)计算延时的最大值td max和最小值td min。
Figure PCTCN2022080128-appb-000026
有益效果：本发明公开了一种考虑输入转换时间的近阈值单元电路延时模型，通过等效电流法和对数偏正态分布的性质得到反相器和复合单元的延时标称模型和延时统计模型，具有高精度和低时间开销的优点。在SMIC40nm工艺下，与蒙特卡洛仿真方法相比，反相器延时标称值的误差均小于5.55％，延时方差的误差均小于14.87％，-3σ值的误差均小于15.16％，+3σ值的误差均小于10.87％；堆叠结构单元延时的标称值误差均小于10.78％，方差误差均小于16.43％，-3σ值的误差均小于19.34％，+3σ值的误差均小于14.91％；并联结构单元延时的标称值误差均小于7.31％，方差误差均小于15.91％，-3σ值的误差均小于9.78％，+3σ值的误差均小于9.63％。
附图说明
图1为本发明具体实施方式的近阈值单元电路延时模型的流程图；
图2为本发明具体实施方式的近阈值单元电路延时类型的分类情况；(a)为延时类型为极快输入的情况；(b)为延时类型为快输入的情况；(c)为延时类型为慢输入的情况。
具体实施方式：
下面结合基于SMIC40nm工艺的具体实施方式对本发明的技术方案作进一步的介绍。
图1为本发明具体实施方式的近阈值单元电路延时模型的流程图主要步骤如下：
S1：获取参数，参数包括单元电路各晶体管工艺参数、单元电路参数和慢输入延时参数。其中，单元电路各晶体管工艺参数包括亚阈值斜率因子、漏端感应源端势垒降低效应系数，通过对最小尺寸晶体管进行标称直流仿真获得；单元电路参数包括晶体管尺寸、负载、输入转换时间、供电电压、温度、工艺角，晶体管尺寸为最小尺寸，负载为1fF，输入转换时间为50ps、500ps和1ns，供电电压为0.4V，温度为25℃，工艺角为TT工艺角，慢输入延时参数包括慢输入延时表达式，可以通过拟合仿真得到的慢输入下延时获得。
S2：判断单元电路类型，判断单元电路是反相器、堆叠结构单元或者并联结构单元，根据单元电路类型计算极快输入下大电流I H1、快输入下大电流I H2、小电流I L和电流积分k，计算大电流和小电流之和对数Y的均值μ Y、方差σ Y 2和偏度γ 1，计算等效阈值电压的均值、方差。如果单元电路类型为反相器，则将工艺参数、电路参数代入式(1)和式(2)，分别得到极快输入下大电流I H1、快输入下大电流I H2、小电流I L、电流积分k和电流之和对数Y的均值μ Y、方差σ Y 2、偏度γ 1；如果单元电路类型为堆叠结构单元，则将工艺参数、电路参数代入式(3)、式(4)和式(5)，分别得到极快输入下大电流I H1、快输入下大电流I H2、小电流I L、电流积分k、电流之和对数Y的均值μ Y、方差σ Y 2、偏度γ 1和等效阈值电压的均值、方差；如果单元电路类型为并联结构单元，则将工艺参数、电路参数代入式(6)、式(7)和式(8)，分别得到极快输入下大电流I H1、快输入下大电流I H2、小电流I L、电流积分k、电流之和对数Y的均值μ Y、方差σ Y 2、偏度γ 1和等效阈值电压的均值、方差；
Figure PCTCN2022080128-appb-000027
式(1)中，I ds是源漏电流，V gs和V ds是栅源电压和源漏电压，V dd是供电电压，V ds(τ)是输入转换时间处的源漏电压，λ是漏端感应源端势垒降低效应系数，n是亚阈值斜率因子，Φ t是热电压，I 0是受工艺参数影响的参数，K 0、K 1、K 2是由工艺决定的拟合系数
Figure PCTCN2022080128-appb-000028
式(2)中，m为系数，k 2是由工艺决定的拟合系数，ΔV th为阈值电压波动量，ΔV th’为阈值电压的函数，E[·]为相应的随机变量的均值。
Figure PCTCN2022080128-appb-000029
式(3)中，V g和V d是栅端电压和漏端电压，V s是源端电压，V XH和V XL是不同栅端电压和漏端电压下中间节点电压，在极快输入情况下，V XH为V XH1，是栅端电压和漏端电压均为供电电压时的中间节点电压，在快输入情况下，V XH为V XH2，是栅端电压为供电电压，漏端电压为输入转换时间时刻的漏端电压时的中间节点电压，V d(τ)是输入转换时间处的漏端电压，k 1是由工艺决定的拟合系数；
Figure PCTCN2022080128-appb-000030
式(4)中，D[·]为相应的随机变量的方差，S k[·]为相应的随机变量的偏度，Cov[·]为相应的随机变量的协方差。
Figure PCTCN2022080128-appb-000031
式(5)中，ΔV th_eff为等效阈值电压，ΔV thH和ΔV thL为上管阈值电压波动量ΔV thU和下管阈值电压波动量ΔV thD的线性函数。
Figure PCTCN2022080128-appb-000032
式(6)中，V th1、V th2分别是并联结构左右两个晶体管的阈值电压。
Figure PCTCN2022080128-appb-000033
Figure PCTCN2022080128-appb-000034
式(8)中，ΔV th1和ΔV th2为并联结构左右两个晶体管的阈值电压波动量。
S3：判断延时类型，根据单元电路类型，将步骤S2计算得到的极快输入下大电流I H1、快输入下大电流I H2、小电流I L、电流积分k和输入转换时间分别代入式(9)和式(10)，计算得到过冲时间t ov和延时td，比较输入转换时间、过冲时间和延时的大小关系，判断延时类型是极快输入、快输入或者慢输入。如果输入转换时间为50ps，比较计算得到的过冲时间t ov、延时td和输入转换时间，发现过冲时间t ov大于输入转换时间且延时td大于输入转换时间的一半，则为极快输入；如果输入转换时间为500ps，比较计算得到的过冲时间t ov、延时td和输入转换时间，发现过冲时间t ov小于输入转换时间且延时td大于输入转换时间的一半，则为快输入；如果输入转换时间为1ns，比较计算得到的过冲时间t ov、延时td和输入转换时间，发现过冲时间t ov小于输入转换时间且延时td小于输入转换时间的一半，则为慢输入。
Figure PCTCN2022080128-appb-000035
式(9)中，td为单元电路延时，τ为输入转换时间，C M是输入输出的耦合电容，C L是负载电容。
Figure PCTCN2022080128-appb-000036
S4:建立单元电路延时标称模型，根据单元电路类型和延时类型，得到延时标称值。如 果延时类型为极快输入，将步骤S2计算得到的极快输入下大电流I H1、快输入下大电流I H2、小电流I L、电流积分k和输入转换时间代入式(10)，计算得到延时标称值；如果延时类型为快输入，将步骤S2计算得到的极快输入下大电流I H1、快输入下大电流I H2、小电流I L、电流积分k和输入转换时间代入式(11)，计算得到延时标称值；如果延时类型为慢输入，将步骤S2计算得到的极快输入下大电流I H1、快输入下大电流I H2、小电流I L、电流积分k和输入转换时间代入式(12)，计算得到延时标称值。
Figure PCTCN2022080128-appb-000037
Figure PCTCN2022080128-appb-000038
式(12)中，td s为阶跃延时，a、b为拟合参数。
S5：建立单元电路延时统计模型，根据单元电路类型和延时类型，基于单元延时标称模型，得到延时统计量：方差、最大值和最小值。如果延时类型为极快输入，步骤S2得到大电流和小电流之和对数均值μ Y、方差σ Y 2和偏度γ 1代入式(13)，计算得到分布参数：位置参数ξ Y，比例参数ω Y和第二形状参数β Y，将分布参数代入式(14)计算得到延时的方差D(td)，将分布参数代入式(15)计算得到延时的最大值td max和最小值td min；如果延时类型为快输入，步骤S2得到大电流和小电流之和对数均值μ Y、方差σ Y 2和偏度γ 1代入式(13)，计算得到分布参数：位置参数ξ Y，比例参数ω Y和第二形状参数β Y，将分布参数代入式(14)计算得到延时的方差D(td)，将分布参数代入式(15)计算得到延时的最大值td max和最小值td min；如果延时类型为慢输入，步骤S2得到等效阈值电压的均值和方差代入式(16)计算得到延时的均值E(td)、方差D(td)和偏度S k(td)，将延时的均值E(td)、方差D(td)和偏度S k(td)代入式(13)，计算得到分布参数：位置参数ξ td，比例参数ω td和第二形状参数β td，将分布参数代入式(17)计算得到延时的最大值td max和最小值td min；
Figure PCTCN2022080128-appb-000039
Figure PCTCN2022080128-appb-000040
Figure PCTCN2022080128-appb-000041
式(14)中，φ(·)是标准正态分布的累加密度分布函数
Figure PCTCN2022080128-appb-000042
式(16)中，p i(i＝0,1,2,3)和q i(i＝0,2,4,6,8)为系数，是阈值电压、电流的函数
Figure PCTCN2022080128-appb-000043
图2为本发明具体实施方式的近阈值单元电路延时类型的分类情况。其中图2(a)中延时类型为极快输入，过冲时间大于输入转换时间且延时大于输入转换时间的一半；图2(b)中延时类型为快输入，过冲时间小于输入转换时间且延时大于输入转换时间的一半；图2(c)中延时类型为慢输入，过冲时间小于输入转换时间且延时小于输入转换时间的一半。

Claims (10)

  1. 一种近阈值单元电路延时模型，其特征在于：所述单元电路包括反相器、堆叠结构单元和并联结构单元，所述模型包括以下步骤：
    S1:获取参数，包括单元电路各晶体管的工艺参数、单元电路参数和慢输入延时参数；
    S2:判断单元电路类型，包括判断单元电路是否为反相器、堆叠结构单元、并联结构单元，根据单元电路类型计算该单元电路的大电流、小电流和电流积分，计算该大电流和小电流之和的自然对数的均值、方差和偏度，计算等效阈值电压的均值、方差；
    S3:判断延时类型，根据步骤S2得到的单元电路类型，计算单元电路的过冲时间和延时，然后，根据过冲时间、延时和输入转换时间的相对大小关系，判断延时类型是极快输入、快输入或者慢输入；如果过冲时间大于输入转换时间，则延时类型为极快输入；如果过冲时间小于输入转换时间且延时大于输入转换时间的一半，则延时类型为快输入；如果过冲时间小于输入转换时间且延时小于输入转换时间的一半，则延时类型为慢输入；
    S4:根据步骤S2得到的单元电路类型和步骤S3得到的延时类型建立单元电路延时标称模型，得到延时标称值；
    S5:基于延时标称模型，根据步骤S2得到的单元电路类型和步骤S3得到的延时类型建立单元电路延时统计模型，得到延时统计量：方差、最大值和最小值。
  2. 如权利要求1所述的一种近阈值单元电路延时模型，其特征在于：步骤S1中，所述工艺参数包括亚阈值斜率因子、漏端感应源端势垒降低效应系数，电路参数包括晶体管尺寸、负载、输入转换时间、供电电压、温度、工艺角，慢输入延时参数包括式(1)中的拟合参数a、b，式(2)中的拟合参数c、d，拟合参数a、b、c、d通过仿真慢输入下的延时拟合获得，
    Figure PCTCN2022080128-appb-100001
    a＝cV th+d         (2)
    式(1)中，td为单元电路延时，τ为输入转换时间，td s为阶跃延时，式(2)中，V th为阈值电压。
  3. 如权利要求1所述的一种近阈值单元电路延时模型，其特征在于：所述的步骤S2中，如果单元电路为反相器，所述步骤S2包括：
    S21：根据式(3)计算单元电路的大电流I H、小电流I L和电流积分k，在极快输入情况下，大电流I H为极快输入下大电流I H1，是栅源电压和源漏电压均为供电电压时的源漏电流；在快输入情况下，大电流I H为快输入下大电流I H2，是栅源电压为供电电压，源漏电压为输入转换时间时刻的源漏电压时的源漏电流；
    Figure PCTCN2022080128-appb-100002
    式(3)中，V gs和V ds是栅源电压和源漏电压，I ds是源漏电流，V dd是供电电压，V ds(τ)是输入转换时间时刻的源漏电压，通过式(4)计算得到，λ是漏端感应源端势垒降低效应系数，n是亚阈值斜率因子，Φ t是热电压，I 0是受工艺参数影响的参数，K 0、K 1、K 2是由工艺决定 的拟合系数；
    Figure PCTCN2022080128-appb-100003
    式(4)中，C M是输入输出的耦合电容，C L是负载电容；
    S22：电流之和自然对数Y是所述大电流和小电流之和即I H+I L的自然对数，表示为式(5)，根据式(6)计算电流之和对数Y的均值μ Y、方差σ Y 2和偏度γ 1；
    Y＝-ln(I H+I L)         (5)
    Figure PCTCN2022080128-appb-100004
    式(6)中，m为系数，在极快输入下m通过式(7)计算得到，在快输入下，m通过式(8)计算得到，k 2是由工艺决定的拟合系数，ΔV th为阈值电压波动量，ΔV th’通过式(9)计算得到，E[·]为相应的随机变量的均值，
    Figure PCTCN2022080128-appb-100005
    式(7)中，k 1是由工艺决定的拟合系数，V th0为阈值电压标称值
    Figure PCTCN2022080128-appb-100006
    Figure PCTCN2022080128-appb-100007
  4. 如权利要求1所述的一种近阈值单元电路延时模型，其特征在于：所述的步骤S2中，如果单元电路为堆叠结构单元，所述步骤S2包括：
    S21：根据式(10)计算极快输入下大电流I H1、快输入下大I H2、小电流I L和电流积分k；
    Figure PCTCN2022080128-appb-100008
    式(10)中，V g和V d是栅端电压和漏端电压，V s是源端电压，V XH和V XL是不同栅端电压和漏端电压下中间节点电压，在极快输入情况下，V XH为V XH1，是栅端电压和漏端电压均为供电电压时的中间节点电压，在快输入情况下，V XH为V XH2，是栅端电压为供电电压，漏端电压为输入转换时间时刻的漏端电压时的中间节点电压，根据式(11)计算得到，V d(τ)是输入转换时间处的漏端电压；
    Figure PCTCN2022080128-appb-100009
    式(11)中，V thU和V thD分别是堆叠结构单元中上管阈值电压和下管阈值电压，W U和W D分别是堆叠结构单元中上管宽度和下管宽度，m 2为拟合系数；
    S22：根据式(12)计算电流之和对数Y的均值E(Y)、方差D(Y)和偏度S k(Y)；
    Figure PCTCN2022080128-appb-100010
    式(12)中，D[·]为相应的随机变量的方差，S k[·]为相应的随机变量的偏度，Cov[·]为相应的随机变量的协方差，Y 1和Y 2可以通过式(13)计算得到
    Figure PCTCN2022080128-appb-100011
    式(13)中，ΔV thH和ΔV thL为上管阈值电压波动量ΔV thU和下管阈值电压波动量ΔV thD的线性函数，表示为式(14)，式(14)中α 1、α 2、α 3和α 4为系数；
    Figure PCTCN2022080128-appb-100012
    S23:根据式(15)计算等效阈值电压ΔV th_eff的均值和方差
    Figure PCTCN2022080128-appb-100013
  5. 如权利要求1所述的一种近阈值单元电路延时模型，其特征在于：所述的步骤S2中，如果单元为并联结构单元，所述步骤S2包括：
    S21：根据式(16)计算极快输入下大电流I H1、快输入下大电流I H2、小电流I L和电流积分k；
    Figure PCTCN2022080128-appb-100014
    式(16)中，V th1、V th2分别是并联结构左右两个晶体管的阈值电压，
    S22：根据式(17)计算电流之和对数Y的均值E(Y)、方差D(Y)和偏度S k(Y)；
    Figure PCTCN2022080128-appb-100015
    式(17)中，Y 1和Y 2可以通过式(18)计算得到
    Figure PCTCN2022080128-appb-100016
    式(18)中，ΔV th1和ΔV th2为并联结构左右两个晶体管的阈值电压波动量，
    S23:根据式(19)计算等效阈值电压ΔV th_eff的均值和方差
    Figure PCTCN2022080128-appb-100017
  6. 如权利要求1所述的一种近阈值单元电路延时模型，其特征在于：所述的步骤S3判断延时类型包括根据单元电路类型计算得到过冲时间t ov和延时td，比较输入转换时间、过冲时间和延时的大小关系，判断输入是极快输入、快输入或者慢输入，具体包括：
    S31：将步骤S2得到的极快输入下大电流I H1、快输入下大电流I H2、小电流I L和电流积分k代入式(20)计算得到过冲时间t ov，代入式21计算延时td，
    Figure PCTCN2022080128-appb-100018
    Figure PCTCN2022080128-appb-100019
    S32：比较过冲时间t ov与输入转换时间τ的大小，如果t ov>τ，则为极快输入，反之，则为快输入或慢输入；
    S33：比较延时td与输入转换时间的一半τ/2的大小，如果td>τ/2，则为快输入，反之，则为慢输入。
  7. 如权利要求1所述的一种近阈值单元电路延时模型，其特征在于：所述的步骤S4中，建立单元电路延时标称模型包括根据单元电路类型和延时类型，得到延时标称值，如果延时类型为极快输入，延时标称值通过式(22)计算得到；如果延时类型为快输入，延时标称值通过式(21)计算得到；如果延时类型为慢输入，延时标称值通过式(1)计算得到，
    Figure PCTCN2022080128-appb-100020
  8. 如权利要求1所述的一种近阈值单元电路延时模型，其特征在于：所述的S5中，建立单元电路延时统计模型包括根据单元电路类型和延时类型，基于步骤S4的延时标称模型，得到延时统计量：方差、最大值和最小值，如果延时类型是极快输入，所述步骤S5包括：
    S51:基于对数偏正态分布的性质将步骤S2得到电流之和对数均值μ Y、方差σ Y 2和偏度γ 1代入式(23)计算分布参数：位置参数ξ Y，比例参数ω Y和第二形状参数β Y；
    Figure PCTCN2022080128-appb-100021
    S52:基于分布参数，根据式(24)计算延时的方差D(td)，根据式(25)计算延时的最大值td max和最小值td min，
    Figure PCTCN2022080128-appb-100022
    Figure PCTCN2022080128-appb-100023
    式(24)中，φ(·)是标准正态分布的累加密度分布函数。
  9. 如权利要求8所述的一种近阈值单元电路延时模型，其特征在于：所述的步骤S2中，如果延时类型是快输入，所述步骤S5包括：
    S51:基于对数偏正态分布的性质将步骤S2得到电流之和对数均值μ Y、方差σ Y 2和偏度γ 1代入式(23)计算分布参数：位置参数ξ Y，比例参数ω Y和第二形状参数β Y；
    S52:基于分布参数，根据式(24)计算延时的方差D(td)，根据式(25)计算延时的最大值td max和最小值td min。
  10. 如权利要求8所述的一种近阈值单元电路延时模型，其特征在于：所述的步骤S2中，如果延时类型是慢输入，所述步骤S5包括：
    S51:基于步骤S2得到的等效阈值电压的均值和方差，根据式(26)计算延时的均值E(td)、方差D(td)和偏度S k(td)；
    Figure PCTCN2022080128-appb-100024
    式(26)中，p i(i＝0,1,2,3)和q i(i＝0,2,4,6,8)为系数，是阈值电压、电流的函数，
    S52:基于偏正态分布的性质，根据式(23)计算延时的分布参数：位置参数ξ td，比例参数ω td和第二形状参数β td，
    S53:基于分布参数，根据式(27)计算延时的最大值td max和最小值td min。
    Figure PCTCN2022080128-appb-100025
PCT/CN2022/080128 2021-06-07 2022-03-10 一种近阈值单元电路延时模型 Ceased WO2022257517A1 (zh)

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