WO2022257111A1

WO2022257111A1 - Field effect transistor and preparation method therefor, and power amplifier and electronic circuit

Info

Publication number: WO2022257111A1
Application number: PCT/CN2021/099712
Authority: WO
Inventors: 李文; 薛晓咏; 段焕涛
Original assignee: 华为技术有限公司
Priority date: 2021-06-11
Filing date: 2021-06-11
Publication date: 2022-12-15
Also published as: CN117461140A

Abstract

Disclosed in the present application are a field effect transistor and a preparation method therefor, and a power amplifier and an electronic circuit. The field effect transistor comprises: an SiC substrate, a first AlN layer, a first GaN layer, a first AlGaN layer, a second GaN layer, a second AlGaN layer, a source electrode, a drain electrode and a gate electrode, wherein the SiC substrate, the first AlN layer, the first GaN layer, the first AlGaN layer, the second GaN layer and the second AlGaN layer are sequentially arranged in a stacked manner; and the source electrode, the drain electrode and the gate electrode are all arranged on the side of the second AlGaN layer that faces away from the second GaN layer. By means of the present application, a first GaN layer is inserted between a first AlN layer and a first AlGaN layer; since the difference between lattice constants of AlN and GaN is greater than that between lattice constants of AlN and AlGaN, the compressive stress introduced by a lattice mismatch is greater; and by means of a field effect transistor into which a first GaN layer is introduced, the tensile stress can be more effectively compensated, thereby ameliorating the problem of a relatively great warping degree faced by an epitaxial wafer in a field effect transistor.

Description

Field effect transistor, its preparation method, power amplifier and electronic circuit

technical field

The present application relates to the technical field of semiconductors, in particular to a field effect transistor, its preparation method, power amplifier and electronic circuit.

Background technique

Gallium nitride (GaN)-based high electron mobility field effect transistor (High Electron Mobility Transistor, HEMT) is a new type of electronic device based on a nitride heterostructure. A high-concentration two-dimensional electron gas (2DEG) channel is formed in the potential well, and the channel electrons are controlled by the gate voltage to realize work.

GaN HEMTs are generally obtained by heteroepitaxial growth on SiC substrates based on Metal Organic Chemical Vapor Deposition (MOCVD) method. However, the prepared HEMT epitaxial structure has the problem of large warpage, which will affect the performance of the device.

Contents of the invention

The application provides a field effect transistor, its preparation method, a power amplifier and an electronic circuit, aiming at improving the warpage problem of the field effect transistor.

In the first aspect, a field effect transistor is provided, and the field effect transistor mainly includes: a SiC substrate, a first AlN layer, a first GaN layer, a first AlGaN layer, a second GaN layer, a second AlGaN layer, a source , drain and gate. Among them, the SiC substrate, the first AlN layer, the first GaN layer, the first AlGaN layer, the second GaN layer and the second AlGaN layer are stacked in sequence, and the source, drain and gate are all arranged on the second AlGaN layer The side facing away from the second GaN layer. In this application, a first GaN layer is inserted between the first AlN layer and the first AlGaN layer. Since the lattice constant difference between AlN and GaN is larger than that of AlN and AlGaN, the compressive stress caused by lattice mismatch is more Large, the introduction of the field effect transistor of the first GaN layer can more effectively compensate the tensile stress, thereby improving the problem of large warpage faced by the epitaxial wafer in the field effect transistor.

As the basic component of the field effect transistor, the SiC substrate is used to carry various functional layers of the field effect transistor. The SiC substrate is a semi-insulating SiC substrate, one side of which is a silicon (Si) surface, and the other side is a carbon (C) surface, and the first AlN layer is arranged on the side of the Si surface of the SiC substrate.

In a field effect transistor, the first AlN layer is generally used as a nucleation layer, the first AlGaN layer is used as a buffer layer, the second GaN layer is used as a channel layer, and the second AlGaN layer is used as a barrier layer.

In specific implementation, the first AlN layer can be formed by the MOCVD epitaxial process, the Al source and the N source for growing the first AlN layer can be trimethylaluminum (TMAl) and ammonia gas (NH3) respectively, and the growth temperature can be controlled at 1000 °C to 1100 °C, which is not limited here.

The present application does not limit the thickness of the first AlN layer. Optionally, the thickness of the first AlN layer can be controlled between 20nm-100nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc., which is not limited herein.

In specific implementation, the first AlGaN layer can be formed by MOCVD epitaxial process, the Al source for growing the first AlGaN layer, the Ga source and the N source can be trimethylaluminum (TMAl), trimethylgallium (TMGA) and ammonia Gas (NH3), the growth temperature can be controlled between 1000°C and 1050°C, which is not limited here.

The present application does not limit the thickness of the first AlGaN layer. Optionally, the thickness of the first AlGaN layer can be controlled between 0.2 μm˜3 μm, for example, 0.2 μm, 1 μm, 2 μm or 3 μm, etc., which is not limited herein.

In specific implementation, the first GaN layer can be formed by MOCVD epitaxial process, the Ga source and N source for growing the first GaN layer can be trimethylgallium (TMGA) and ammonia gas (NH3) respectively, and the growth temperature can be controlled at 950 °C to 1050 °C, which is not limited here.

The present application does not limit the thickness of the first GaN layer. Optionally, the thickness of the first GaN layer can be controlled between 20nm˜100nm, for example, 20nm, 40nm, 50nm, 70nm, 90nm or 100nm, etc., which is not limited herein.

Optionally, in this application, a second AlN layer can also be provided between the second GaN layer and the second AlGaN layer, thereby increasing the effective conduction band step of the second AlGaN layer, thereby improving the performance and electrical properties of the heterojunction material .

Exemplarily, a third GaN layer may also be disposed on the side of the second AlGaN layer away from the second AlN layer, and the source, drain and gate are all disposed on the side of the third GaN layer away from the second AlGaN layer. Setting the third GaN layer can increase the barrier height of the second AlGaN layer, thereby improving the heterojunction material performance and electrical performance of the field effect transistor.

Exemplarily, in the present application, the source, the drain and the gate can be arranged in the same layer, the source and the drain both form conductive ohmic contacts with the second AlGaN layer, and the gate forms a Schottky contact with the second AlGaN layer. When the field effect transistor includes the third GaN layer, the source and the drain form a conductive ohmic contact with the second AlGaN layer through the third GaN layer, and the gate forms a Schottky contact with the second AlGaN layer through the third GaN layer.

In a second aspect, a method for manufacturing a field effect transistor is provided. The method includes the following steps: forming a first aluminum nitride layer on a SiC substrate; forming a first gallium nitride layer on the bottom side; forming a first aluminum gallium nitride layer on the side of the first gallium nitride layer away from the first aluminum nitride layer; forming a first aluminum gallium nitride layer on the side away from the first aluminum gallium nitride layer; A second gallium nitride layer is formed on the side of the first gallium nitride layer; a second aluminum gallium nitride layer is formed on the side of the second gallium nitride layer away from the first aluminum gallium nitride layer; A side of the AlGaN layer away from the second GaN layer forms a source, a drain and a gate.

Optionally, the thickness of the first gallium nitride layer can be controlled between 20nm and 100nm, the thickness of the first aluminum nitride layer can be controlled between 20nm and 100nm, and the thickness of the first aluminum gallium nitride layer It can be controlled between 0.2 μm and 3 μm.

During specific implementation, the first aluminum nitride layer is generally formed on the side of the Si surface of the SiC substrate.

As an optional solution, after forming a second gallium nitride layer on the side of the first aluminum gallium nitride layer away from the first gallium nitride layer, on the side of the second gallium nitride layer away from the first gallium nitride layer, Before forming the second AlGaN layer on the side of the AlGaN layer, the method further includes: forming a second AlN layer on the side of the second GaN layer away from the first AlGaN layer.

As an optional solution, after the second AlGaN layer is formed on the side of the second GaN layer away from the first AlGaN layer, Before the source, drain and gate are formed on one side of the gallium nitride layer, it further includes: a third gallium nitride layer on the side of the second aluminum gallium nitride layer away from the second aluminum nitride layer.

In a third aspect, an electronic circuit is provided, and the electronic circuit includes a circuit board and the field effect transistor as described in the first aspect or various implementation manners of the first aspect arranged on the circuit board.

A fourth aspect provides a power amplifier, which includes a circuit board and the field effect transistor as described in the first aspect or various implementation manners of the first aspect arranged on the circuit board.

The technical effects that can be achieved by any one of the above-mentioned second to fourth aspects can be described with reference to the technical effects that can be achieved by any possible design in the above-mentioned first aspect, and will not be repeated here.

Description of drawings

FIG. 1 is a schematic structural view of a field effect transistor provided by the related art;

FIG. 2 is a schematic structural view of a field effect transistor provided by an embodiment of the present application;

FIG. 3 is a schematic structural view of a field effect transistor provided in another embodiment of the present application;

FIG. 4 is a schematic structural view of a field effect transistor provided in another embodiment of the present application;

Fig. 5 is the flowchart of the preparation method of the field effect tube provided by an embodiment of the present application;

Figures 6a to 6e are structural schematic diagrams of the preparation process of the field effect tube of the embodiment of the present application;

FIG. 7 is a flow chart of a method for manufacturing a field effect transistor provided in another embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings.

The AlGaN/GaN heterojunction HEMT structure based on GaN materials has excellent characteristics such as high electron mobility, high 2DEG surface density, high chemical stability, high frequency, high power, etc., making GaN material devices in the field of radio frequency and power electronics. obvious advantage. Therefore, the field effect transistor provided by the embodiment of the present application can be widely used in various scenarios as a component of an electronic circuit, for example, it is widely used in the fifth generation of wireless communications technologies (5th generation of wireless communications technologies, 5G) wireless communication Base stations, power electronic devices and other information transmission and reception, energy conversion, high-frequency switching and other fields. For example, it is applied to the radio frequency power amplifier (Power Amplifier, PA) circuit of the base station, wherein the main function of the radio frequency power amplifier circuit is to amplify the radio frequency model and then transmit it through the antenna unit of the base station, and pass it to the mobile phone for reception. By using the RF power amplifier circuit of GaN HEMT, relatively high power and power efficiency can be achieved, and relatively small volume. In the future, GaN HEMT-based electronic circuits may also be applied to mobile phones, WIFI and other products, which are not limited here.

As shown in Figure 1, a GaN HEMT generally includes a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, a source 6, a drain 7, and a gate 8. Wherein, the substrate 1 is generally a sapphire substrate, a silicon carbide (SiC) substrate or a single crystal silicon (Si) substrate. For HEMTs with aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructure commonly used, both the buffer layer 3 and the channel layer 4 are GaN, and the barrier layer 5 is AlGaN. In this single heterostructure, since both the channel layer 4 and the buffer layer 3 are GaN, the conduction band step cannot be formed between them, so the channel two-dimensional electron gas ((Two-dimensional electron gas, 2DEG) ) has poor confinement, and electrons easily overflow the channel into the buffer layer, thereby reducing the pinch-off performance of the channel, resulting in an increase in the output conductance of the device and a decrease in breakdown performance, thereby reducing the frequency performance and power characteristics of the device. In order to enhance the 2DEG confinement of GaN HEMTs and improve device performance, an effective method is to use low-composition AlGaN as the buffer layer3. In this structure, a GaN/AlGaN heterojunction is formed between the channel layer 4 and the buffer layer 3. Since AlGaN has a large band gap and polarization effect, negative polarization charges can be generated at the GaN/AlGaN boundary, thereby raising the The conduction band energy level enhances the confinement of 2DEG.

However, this structure is based on the metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD) method obtained by heteroepitaxial growth on SiC substrates. Due to the large thermal mismatch between SiC and AlGaN, when MOCVD epitaxy After the growth is completed, when the temperature drops from high temperature (about 1000°C) to room temperature, a large tensile stress will be generated in the AlGaN buffer layer, which will lead to a large warpage of the prepared HEMT epitaxial structure. The large tensile stress will reduce the degree of lattice mismatch between it and the GaN channel layer, thereby affecting the piezoelectric polarization effect in the heterojunction, and also has a certain impact on the surface density of the two-dimensional electron gas. thereby affecting device performance.

Therefore, an embodiment of the present application provides a field effect transistor for improving warpage of an AlGaN buffer layer, which will be described in detail below with reference to specific drawings and embodiments.

The terms used in the following examples are for the purpose of describing particular examples only, and are not intended to limit the application. As used in the specification and appended claims of this application, the singular expressions "a", "an", "said", "above", "the" and "this" are intended to also Expressions such as "one or more" are included unless the context clearly dictates otherwise.

Reference to "one embodiment" or "some embodiments" or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in other embodiments," etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically stated otherwise.

Referring to FIG. 2 , FIG. 2 shows a schematic structural diagram of a field effect transistor provided by an embodiment of the present application. The field effect transistor provided in the embodiment of the present application mainly includes: a SiC substrate 01, a first aluminum nitride (AlN) layer 02, a first gallium nitride (GaN) layer 03, a first aluminum gallium nitride (AlGaN) layer 04, A second gallium nitride (GaN) layer 05 , a second aluminum gallium nitride (AlGaN) layer 06 , a source 11 , a drain 12 and a gate 13 . For the convenience of description, taking the placement direction of the field effect transistor shown in FIG. Two AlGaN layers 06 are sequentially stacked along the direction X, and the source 11 , drain 12 and gate 13 are all disposed on the side of the second AlGaN layer 06 away from the second GaN layer 05 .

In the field effect transistor, the first AlN layer 02 is generally used as a nucleation layer, the first AlGaN layer 04 is used as a buffer layer, the second GaN layer 05 is used as a channel layer, and the second AlGaN layer 06 is used as a barrier layer.

The SiC substrate 01 is used as a basic component of the field effect transistor to carry various functional layers of the field effect transistor. The SiC substrate 01 is a semi-insulating SiC substrate, one side of which is a silicon (Si) surface, and the other side is a carbon (C) surface, and the first AlN layer 02 is provided on the side of the Si surface of the SiC substrate 01 .

As an optional solution, the SiC substrate 01 may have a rectangular structure layer. However, it should be understood that the shape of the SiC substrate 01 provided in the embodiment of the present application is not limited to a rectangular structure, and other shapes such as circle, ellipse, polygon, etc. other functional layers.

The first AlN layer 02 and the first AlGaN layer 04 serve as transition layers for the heterogeneous growth of the second GaN layer 05, and are used to match the lattice mismatch and thermal mismatch between the SiC substrate 01 and the second GaN layer 05 to obtain better A second GaN layer 05 of good crystal quality. In this application, a GaN/AlGaN heterojunction can be formed between the second GaN layer 05 and the first AlGaN layer 04. Since AlGaN has a large band gap and polarization effect, negative polarization charges can be generated at the GaN/AlGaN boundary, thereby The energy level of the conduction band can be raised, thereby enhancing the 2DEG confinement of the FET.

However, since the a-axis lattice constant of AlGaN is larger than the a-axis lattice constant of AlN, the direct epitaxy of the first AlGaN layer 04 on the first AlN layer 02 will cause the first AlGaN layer 04 to be affected by the first AlN layer 02 The compressive stress can be used to compensate the tensile stress caused by the inconsistent thermal expansion coefficient during the cooling process, but the compensation ability is limited, and it is not enough to completely offset the tensile stress caused by the thermal expansion coefficient, resulting in the first AlGaN layer based on HEMT epitaxial wafer warpage is still relatively large. For this reason, this application inserts a layer of first GaN layer 03 between the first AlN layer 02 and the first AlGaN layer 04. Since the lattice constant difference between AlN and GaN is obviously larger than that of AlN and AlGaN, the lattice The compressive stress introduced by the mismatch is larger, so compared with the epitaxial wafer of the single first AlGaN layer 04, the field effect transistor introduced into the first GaN layer 03 can more effectively compensate the tensile stress, thereby improving the performance of the single first AlGaN layer 04. The problem of large warpage faced by epitaxial wafers in field effect transistors.

In specific implementation, the first AlN layer 02 can be formed by MOCVD epitaxial process, the Al source and N source for growing the first AlN layer 02 can be trimethylaluminum (TMAl) and ammonia (NH3) respectively, and the growth temperature can be controlled Between 1000°C and 1100°C, it is not limited here.

The present application does not limit the thickness of the first AlN layer 02 . Optionally, the thickness of the first AlN layer 02 can be controlled between 20nm-100nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc., which is not limited herein.

In specific implementation, the first AlGaN layer 04 can be formed by MOCVD epitaxial process, and the Al source, Ga source and N source for growing the first AlGaN layer 04 can be trimethylaluminum (TMAl), trimethylgallium (TMGA) respectively. and ammonia (NH3), the growth temperature can be controlled between 1000°C and 1050°C, which is not limited here.

The present application does not limit the thickness of the first AlGaN layer 04 . Optionally, the thickness of the first AlGaN layer 04 may be controlled between 0.2 μm˜3 μm, for example, 0.2 μm, 1 μm, 2 μm or 3 μm, etc., which is not limited herein.

In specific implementation, the first GaN layer 03 can be formed by MOCVD epitaxial process, the Ga source and N source for growing the first GaN layer 03 can be trimethylgallium (TMGA) and ammonia gas (NH3) respectively, and the growth temperature can be controlled Between 950°C and 1050°C, it is not limited here.

The present application does not limit the thickness of the first GaN layer 03 . Optionally, the thickness of the first GaN layer 03 can be controlled between 20nm˜100nm, for example, 20nm, 40nm, 50nm, 70nm, 90nm or 100nm, etc., which is not limited herein.

The second GaN layer 05 and the second AlGaN layer 06 are used as functional layers of the field effect transistor to form a two-dimensional electron gas of the field effect transistor. A channel may be formed at the contact surface of the second GaN layer 05 and the second AlGaN layer 06 , and the two-dimensional electron gas is located at the contact surface of the second GaN layer 05 and the second AlGaN layer 06 .

Optionally, as shown in FIG. 3, a second AlN layer 07 may also be provided between the second GaN layer 05 and the second AlGaN layer 06, thereby increasing the effective conduction band step of the second AlGaN layer 06, thereby improving Heterojunction material properties and electrical properties. In addition, the second AlN layer 07 can increase the in-plane compressive stress of the second GaN layer 05. On the one hand, the increased compressive stress can enhance the piezoelectric polarization electric field of the second GaN layer 05, improving the two-dimensional The surface density of electron gas (2DEG), on the other hand, makes the two effects of the second AlGaN layer 06 on the surface density of 2DEG cancel each other out. At the same time, the second AlN layer 07 can reduce the lattice mismatch between the second GaN layer 05 and the second AlGaN layer 06, improve the characteristics of the AlGaN/GaN heterojunction interface, help to weaken the interface roughness scattering, and improve the mobility of 2DEG .

Exemplarily, as shown in FIG. 4, a third GaN layer 08 may also be provided on the side of the second AlGaN layer 06 away from the second AlN layer 07, and the source 11, the drain 12, and the gate 13 are all provided on the third GaN layer. Layer 08 faces away from the side of the second AlGaN layer 06 . Setting the third GaN layer 08 can increase the barrier height of the second AlGaN layer 06 , thereby improving the heterojunction material performance and electrical performance of the field effect transistor.

The present application does not limit the thicknesses of the second GaN layer 05 , the second AlN layer 07 , the second AlGaN layer 06 and the third GaN layer 08 , which can be set according to actual products.

The source 11 , the drain 12 and the gate 13 serve as the functional layers of the field effect transistor. Referring to FIG. 2 to FIG. 4 , the source 11 , the drain 12 and the gate 13 can be arranged in the same layer. Wherein, the source 11 and the drain 12 are respectively used for connecting external circuits, and the gate 13 is used for controlling the on-off of the channel. When the gate 13 controls the conduction of the channel, the field effect transistor is in the closed state, and the circuit connected between the source 11 and the drain 12 can be conducted; when the gate 13 controls the channel to be turned off, the field effect transistor is in the off state , the circuit connecting the source 11 and the drain 12 is in an open state.

Both the source 11 and the drain 12 can form a conductive ohmic contact with the second AlGaN layer 06 , and the gate 13 can form a Schottky contact with the second AlGaN layer 06 . When the field effect transistor includes the third GaN layer 08, the source 11 and the drain 12 can form a conductive ohmic contact with the second AlGaN layer 06 through the third GaN layer 08, and the gate 13 can be connected to the second AlGaN layer 08 through the third GaN layer 08. The layer 06 forms a Schottky contact, of course, there may be other implementation manners, which are not limited in this application. The source 11 and the drain 12 may communicate with the channel through the second AlGaN layer 06 . The gate 13 can be connected to the channel through the second AlGaN layer 06, and can absorb electrons located in the channel. When the gate 13 controls the conduction of the channel, the electrons are located in the channel, and the source 11 and the drain 12 can be conducted through the electrons in the channel; when the gate 13 controls the channel to be disconnected, the electrons are absorbed by the gate 13, There are no free electrons in the channel and the source 11 and drain 12 are disconnected.

Among them, the Schottky contact means that when the metal and the semiconductor material are in contact, the energy band of the semiconductor is bent at the interface to form a Schottky barrier, and the existence of the barrier leads to a large interface resistance. The ohmic contact means that when the metal and the semiconductor material are in contact, the potential barrier at the interface is very small or there is no contact barrier. In this application, the gate needs a Schottky contact with rectification characteristics. Exemplarily, the gate may include nickel (Ni) and gold (Au) stacked, Ni is located on the side close to the second AlGaN layer 06, and Au is located on the away from the side of the second AlGaN layer 06 . The structure of the source electrode and the drain electrode can be the same. Exemplarily, both the source electrode and the drain electrode can include titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au) stacked in sequence, and Ti is located near the first On the side of the second AlGaN layer 06, Au is located away from the side of the second AlGaN layer 06. After the deposition of the 4 layers of metal, rapid thermal annealing is required to form ohmic characteristics.

When specifically setting the source 11 , the drain 12 and the gate 13 , the gate 13 may be located between the source 11 and the drain 12 and separate the source 11 and the drain 12 . It should be understood that when specifically setting the gate 13, the drain 12 and the source 11, the distance between the gate 13, the source 11 and the drain 12 is set to ensure that the distance between the gate 13, the source 11 and the drain 12 Galvanic isolation.

Referring to FIG. 3 and FIG. 4 , the field effect transistor further includes a passivation layer 09 covering the semiconductor layer below the source 11 , the drain 12 and the gate 13 to protect various functional layers in the field effect transistor. When setting, as shown in Figure 3, when the third GaN layer 08 is not provided in the field effect transistor, the passivation layer 09 covers the second AlGaN layer 06; as shown in Figure 4, when the third GaN layer 08 is provided in the field effect transistor , the passivation layer 09 covers the third GaN layer 08 . During manufacture, the passivation layer 09 can be formed before the source 11 , the drain 12 and the gate 13 , or can be formed after the source 11 , the drain 12 and the gate 13 are formed. It should be understood that when the passivation layer 09 is formed before the source 11, the drain 12 and the gate 13, in order to ensure the electrical connection between the source 11, the drain 12 and the gate 13 and the second AlGaN layer 06, the passivation layer 09 There are openings in regions corresponding to the source 11 , the drain 12 and the gate 13 . The source 11 , the drain 12 and the gate 13 are electrically connected to the second AlGaN layer 06 through the opening of the passivation layer 09 . When the passivation layer 09 is formed after the source electrode 11, the drain electrode 12 and the gate electrode 13 are formed, in order to ensure that the source electrode 11, the drain electrode 12 and the gate electrode 13 can be connected with the external circuit and the control circuit, the passivation layer 09 is connected with the external circuit and the control circuit. Areas corresponding to the source 11 , the drain 12 and the gate 13 have openings. The source 11 , the drain 12 and the gate 13 are connected to the external circuit and the control circuit through the opening of the passivation layer 09 .

As an optional solution, the passivation layer 09 can be made of silicon nitride, aluminum oxide, silicon oxynitride or other insulating materials.

It should be understood that the passivation layer 09 is an optional structural layer of the field effect transistor. When the application environment of the FET is relatively safe, the passivation layer 09 may not be provided.

In order to facilitate the understanding of the field effect transistor provided in the embodiment of the present application, its preparation method will be described in detail below with reference to the accompanying drawings. In the embodiment of the present application, the field effect transistor can be prepared by the following preparation method. Referring to FIG. 5 in combination with FIGS. The method includes the following steps:

Step S101: forming a first AlN layer 02 on the SiC substrate 01 to form a structure as shown in FIG. 6a.

In specific implementation, you can choose a 4-inch SiC substrate or a 6-inch SiC substrate, place the SiC substrate in an MOCVD equipment, bake it in an H2 atmosphere at 1000°C-1200°C for 5-10 minutes, and then Feed NH3 and TMAl at ~1100°C to grow the first AlN layer on the SiC substrate. Optionally, the thickness of the first AlN layer can be controlled at 20nm; between 20nm-100nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc., which is not limited herein.

Wherein, the first AlN layer 02 is generally formed on the side of the Si surface of the SiC substrate 01 .

Step S102: forming a first GaN layer 03 on the side of the first AlN layer 02 facing away from the SiC substrate 01, forming a structure as shown in FIG. 6b.

In specific implementation, when the SiC substrate is 4 inches, ammonia gas and TMGa can be injected at a temperature of about 1000° C. to grow the first GaN layer on the AlN buffer layer. When the SiC substrate is 6 inches, ammonia gas and TMGa can be injected at a temperature of about 1050° C. to grow the first GaN layer above the AlN buffer layer.

Optionally, the thickness of the first GaN layer can be controlled between 20nm˜100nm, for example, 20nm, 40nm, 50nm, 70nm, 90nm or 100nm, etc., which is not limited herein.

Step S103: forming a first AlGaN layer 04 on the side of the first GaN layer 03 facing away from the first AlN layer 02, forming a structure as shown in FIG. 6c.

In a specific implementation, ammonia gas, TMGa and TMAl may be fed simultaneously at a temperature of about 1000° C. to grow the first AlGaN layer on the first GaN layer. Optionally, the thickness of the first AlGaN layer may be controlled between 0.2 μm˜3 μm, for example, 0.2 μm, 1 μm, 2 μm or 3 μm, etc., which is not limited herein.

Step S104: forming a second GaN layer 05 on the side of the first AlGaN layer 04 facing away from the first GaN layer 03, forming a structure as shown in FIG. 6d.

Step S105: forming a second AlGaN layer 06 on the side of the second GaN layer 05 facing away from the first AlGaN layer 04, forming a structure as shown in FIG. 6e.

In a specific implementation, ammonia gas, TMGa and TMAl may be fed simultaneously at a temperature of 1000° C. to grow the second AlGaN layer on the second GaN layer. Optionally, the thickness of the second AlGaN layer can be controlled at about 20nm.

Step S106 : forming a source 11 , a drain 12 and a gate 13 on the side of the second AlGaN layer 06 facing away from the second GaN layer 05 , forming the structure shown in FIG. 2 .

In an optional implementation manner, referring to FIG. 7 , after step S104 and before step S105 , step S107 may be further included: forming a second AlN layer on the side of the second GaN layer away from the first AlGaN layer.

In an optional implementation manner, referring to FIG. 7 , after step S105 and before step S106 , step S108 may also be included: forming a third GaN layer on the side of the second AlGaN layer away from the second AlN layer. Exemplarily, the thickness of the third GaN layer can be controlled at about 5 nm.

Optionally, during the preparation, forming a passivation layer may also be included, and the passivation layer may be formed before step S106 or after step S106. When the passivation layer is before step S106, the passivation layer has openings in regions corresponding to the source, drain and gate, so that the source, drain and gate pass through the openings of the passivation layer and the second AlGaN layer electrical connection. When the passivation layer is formed after step S106, the passivation layer has openings in regions corresponding to the source, drain, and gate, so that the source, drain, and gate are connected to external circuits and gates through the openings of the passivation layer. Control circuit connections.

It can be seen from the above description that in the field effect transistor provided by the embodiment of the present application, a first GaN layer is inserted between the first AlN layer and the first AlGaN layer. And AlGaN is obviously larger, because the compressive stress introduced by the lattice mismatch is larger, so compared with the single first AlGaN layer epitaxial wafer, the field effect transistor introducing the first GaN layer can more effectively compensate the tensile stress, thereby improving The problem of large warpage faced by epitaxial wafers in field effect transistors with a single first AlGaN layer.

During preparation, the larger the size of the SiC substrate, the easier it is to produce cracks caused by a large degree of warpage. Therefore, for large-sized SiC substrates, the requirements for warpage are more stringent, and this application inserts a first GaN layer between the first AlN layer and the first AlGaN layer, which can more effectively improve this a question.

In practical applications, the improvement of performance parameters such as heat dissipation and drain current drift (Idq-drift) of field effect transistors usually reduces the thickness of the buffer layer, and reducing the thickness of the buffer layer means that the stress problem will be more prominent , resulting in larger warpage of the prepared epitaxial structure. However, in the present application, a first GaN layer is inserted between the first AlN layer and the first AlGaN layer, which can more effectively improve this problem.

The embodiment of the present application also provides an electronic circuit, which may include a circuit board and any field effect transistor provided in the above embodiments of the present application, and the field effect transistor is arranged on the circuit board. Since the problem-solving principle of the electronic circuit is similar to that of the above-mentioned field effect tube, the implementation of the electronic circuit can refer to the implementation of the above-mentioned field effect tube, and the repetition will not be repeated.

The embodiment of the present application also provides a power amplifier, which may include a circuit board and any field effect transistor provided in the above embodiments of the present application, and the field effect transistor is arranged on the circuit board. Since the problem-solving principle of the power amplifier is similar to that of the aforementioned field effect tube, the implementation of the power amplifier can refer to the implementation of the aforementioned field effect tube, and the repetition will not be repeated.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A field effect transistor is characterized in that it comprises:

SiC substrate;

a first aluminum nitride layer disposed on the SiC substrate;

a first gallium nitride layer disposed on a side of the first aluminum nitride layer away from the SiC substrate;

a first aluminum gallium nitride layer disposed on a side of the first gallium nitride layer away from the first aluminum nitride layer;

a second gallium nitride layer disposed on a side of the first aluminum gallium nitride layer away from the first gallium nitride layer;

a second aluminum gallium nitride layer disposed on a side of the second gallium nitride layer away from the first aluminum gallium nitride layer;

The source, the drain and the gate are arranged on the side of the second AlGaN layer away from the second GaN layer.
The field effect transistor according to claim 1, wherein the thickness of the first gallium nitride layer is 20nm˜100nm.
The field effect transistor according to claim 1, wherein the thickness of the first aluminum nitride layer is 20 nm˜100 nm.
The field effect transistor according to claim 1, wherein the thickness of the first AlGaN layer is 0.2 μm˜3 μm.
The field effect tube according to any one of claims 1-4, wherein the field effect tube further comprises:

A second aluminum nitride layer disposed between the second gallium nitride layer and the second aluminum gallium nitride layer.
The field effect transistor according to claim 5, wherein the field effect transistor further comprises a third gallium nitride layer disposed on a side of the second aluminum gallium nitride layer away from the second aluminum nitride layer The source, the drain and the gate are all disposed on the side of the third GaN layer away from the second AlGaN layer.
The field effect transistor according to any one of claims 1-6, wherein the source, the drain and the gate are arranged in the same layer, and both the source and the drain are connected to the second The AlGaN layer forms a conductive ohmic contact, and the gate forms a Schottky contact with the second AlGaN layer.
The field effect transistor according to any one of claims 1-7, wherein the first aluminum nitride layer is a nucleation layer, the first aluminum gallium nitride layer is a buffer layer, and the second nitrogen The GaN layer is a channel layer, and the second AlGaN layer is a barrier layer.
The field effect transistor according to any one of claims 1-8, characterized in that the first aluminum nitride layer is disposed on the side of the Si surface of the SiC substrate.
A preparation method for a field effect tube, characterized in that, comprising:

forming a first aluminum nitride layer on the SiC substrate;

forming a first gallium nitride layer on the side of the first aluminum nitride layer away from the SiC substrate;

forming a first aluminum gallium nitride layer on a side of the first gallium nitride layer away from the first aluminum nitride layer;

forming a second gallium nitride layer on the side of the first aluminum gallium nitride layer away from the first gallium nitride layer;

forming a second aluminum gallium nitride layer on a side of the second gallium nitride layer away from the first aluminum gallium nitride layer;

A source, a drain and a gate are formed on a side of the second AlGaN layer away from the second GaN layer.
The preparation method according to claim 10, characterized in that, the thickness of the first gallium nitride layer is 20nm˜100nm.
The preparation method according to claim 10, characterized in that, the thickness of the first aluminum nitride layer is 20nm-100nm.
The preparation method according to claim 10, wherein the thickness of the first AlGaN layer is 0.2 μm˜3 μm.
The preparation method according to any one of claims 10-13, characterized in that, after the second gallium nitride layer is formed on the side of the first aluminum gallium nitride layer away from the first gallium nitride layer, the Before forming the second aluminum gallium nitride layer on the side of the second gallium nitride layer away from the first aluminum gallium nitride layer, it also includes:

A second aluminum nitride layer is formed on a side of the second gallium nitride layer away from the first aluminum gallium nitride layer.
The preparation method according to claim 14, characterized in that, after the second AlGaN layer is formed on the side of the second GaN layer away from the first AlGaN layer, the second AlGaN layer is Before the source, drain and gate are formed on the side of the nitrogen layer away from the second gallium nitride layer, it further includes:

A third gallium nitride layer on a side of the second aluminum gallium nitride layer away from the second aluminum nitride layer.
The preparation method according to any one of claims 10-15, characterized in that, the first aluminum nitride layer is formed on the side of the Si surface of the SiC substrate.
An electronic circuit, characterized by comprising a circuit board and the field effect transistor according to any one of claims 1-9 arranged on the circuit board.
A power amplifier, characterized by comprising a circuit board and the field effect transistor according to any one of claims 1-9 arranged on the circuit board.