CN117461140A

CN117461140A - Field effect transistor, preparation method thereof, power amplifier and electronic circuit

Info

Publication number: CN117461140A
Application number: CN202180099130.3A
Authority: CN
Inventors: 李文; 薛晓咏; 段焕涛
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-11
Filing date: 2021-06-11
Publication date: 2024-01-26
Also published as: WO2022257111A1

Abstract

The application discloses a field effect transistor, a preparation method thereof, a power amplifier and an electronic circuit. The field effect transistor includes: the semiconductor device comprises a SiC substrate, a first AlN layer, a first GaN layer, a first AlGaN layer, a second GaN layer, a second AlGaN layer, a source electrode, a drain electrode and a grid electrode. The SiC substrate, the first AlN layer, the first GaN layer, the first AlGaN layer, the second GaN layer and the second AlGaN layer are sequentially stacked, and the source electrode, the drain electrode and the grid electrode are arranged on one side, away from the second GaN layer, of the second AlGaN layer. According to the method, the first GaN layer is inserted between the first AlN layer and the first AlGaN layer, and as the lattice constant difference of AlN and GaN is larger than that of AlN and AlGaN, the compressive stress introduced by lattice mismatch is larger, and the field effect tube introduced with the first GaN layer can more effectively compensate tensile stress, so that the problem of larger warping degree of an epitaxial wafer in the field effect tube is improved.

Description

Field effect transistor, preparation method thereof, power amplifier and electronic circuit

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a field effect transistor, a method for manufacturing the field effect transistor, a power amplifier, and an electronic circuit.

Background

Gallium nitride (GaN) -based high electron mobility field effect transistors (High Electron Mobility Transistor, HEMT) are novel electronic devices based on nitride heterostructures, and the unique polarization effect of nitride materials enables the formation of high-concentration two-dimensional electron gas (2 DEG) channels in heterojunction interface potential wells, and channel electrons are controlled by gate voltages to realize operation.

GaN HEMTs are typically heteroepitaxially grown on SiC substrates based on metal organic chemical vapor deposition (Metal organic Chemical Vapor Deposition, MOCVD) methods. However, the prepared HEMT epitaxial structure has the problem of larger warping degree, and the performance of the device can be affected.

Disclosure of Invention

The application provides a field effect tube, a preparation method thereof, a power amplifier and an electronic circuit, and aims to improve the warping degree problem of the field effect tube.

In a first aspect, a field effect transistor is provided, the field effect transistor mainly comprising: the semiconductor device comprises a SiC substrate, a first AlN layer, a first GaN layer, a first AlGaN layer, a second GaN layer, a second AlGaN layer, a source electrode, a drain electrode and a grid electrode. The SiC substrate, the first AlN layer, the first GaN layer, the first AlGaN layer, the second GaN layer and the second AlGaN layer are sequentially stacked, and the source electrode, the drain electrode and the grid electrode are arranged on one side, away from the second GaN layer, of the second AlGaN layer. According to the method, the first GaN layer is inserted between the first AlN layer and the first AlGaN layer, and as the lattice constant difference of AlN and GaN is larger than that of AlN and AlGaN, the compressive stress introduced by lattice mismatch is larger, and the field effect tube introduced with the first GaN layer can more effectively compensate tensile stress, so that the problem of larger warping degree of an epitaxial wafer in the field effect tube is improved.

The SiC substrate is used as a basic component of the field effect transistor and is used for bearing each functional layer of the field effect transistor. The SiC substrate is a semi-insulating SiC substrate, one side of the SiC substrate is a silicon (Si) surface, the other side of the SiC substrate is a carbon (C) surface, and the first AlN layer is arranged on one side of the Si surface of the SiC substrate.

In a field effect transistor, a first AlN layer is generally used as a nucleation layer, a first AlGaN layer is used as a buffer layer, a second GaN layer is used as a channel layer, and a second AlGaN layer is used as a barrier layer.

In a specific implementation, the first AlN layer may be formed by an MOCVD epitaxial process, and an Al source and an N source for growing the first AlN layer may be trimethylaluminum (TMAl) and ammonia (NH 3), respectively, and a growth temperature may be controlled between 1000 ℃ and 1100 ℃, which is not limited herein.

The thickness of the first AlN layer is not limited in this application. Alternatively, the thickness of the first AlN layer may be controlled to be between 20nm and 100nm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or the like, without limitation.

In a specific implementation, the first AlGaN layer may be formed by an MOCVD epitaxial process, the Al source, the Ga source and the N source for growing the first AlGaN layer may be trimethylaluminum (TMAl), trimethylgallium (TMGA) and ammonia (NH 3), and the growth temperature may be controlled between 1000 ℃ and 1050 ℃, which is not limited herein.

The thickness of the first AlGaN layer is not limited in this application. Alternatively, the thickness of the first AlGaN layer may be controlled to be between 0.2 μm and 3 μm, for example, 0.2 μm, 1 μm, 2 μm, or 3 μm, etc., without limitation.

In a specific implementation, the first GaN layer may be formed by an MOCVD epitaxial process, and the Ga source and the N source for growing the first GaN layer may be Trimethylgallium (TMGA) and ammonia (NH 3), respectively, and the growth temperature may be controlled between 950 ℃ and 1050 ℃, which is not limited herein.

The thickness of the first GaN layer is not limited in this application. Alternatively, the thickness of the first GaN layer may be controlled between 20nm and 100nm, for example, 20nm, 40nm, 50nm, 70nm, 90nm, 100nm, or the like, without limitation.

Optionally, the second AlN layer may be further disposed between the second GaN layer and the second AlGaN layer, so as to increase an effective conduction band offset of the second AlGaN layer, thereby improving heterojunction material performance and electrical performance.

For example, a third GaN layer may be further disposed on a side of the second AlGaN layer away from the second AlN layer, and the source, the drain, and the gate may be disposed on a side of the third GaN layer away from the second AlGaN layer. The third GaN layer can be arranged to increase the barrier height of the second AlGaN layer, so that the heterojunction material performance and the electrical performance of the field effect transistor are improved.

For example, the source, the drain and the gate may be disposed on the same layer, where the source and the drain form a conductive ohmic contact with the second AlGaN layer, and the gate forms a schottky contact with the second AlGaN layer. When the field effect transistor includes the third GaN layer, the source and the drain form conductive ohmic contact with the second AlGaN layer through the third GaN layer, and the gate forms schottky contact with the second AlGaN layer through the third GaN layer.

In a second aspect, a method for manufacturing a field effect transistor is provided, the method comprising the steps of: forming a first aluminum nitride layer on the SiC substrate; then sequentially forming a first gallium nitride layer on one side of the first aluminum nitride layer, which is away from the SiC substrate; forming a first aluminum gallium nitride layer on one side of the first gallium nitride layer, which is away from the first aluminum nitride layer; forming a second gallium nitride layer on one side of the first aluminum gallium nitride layer, which is away from the first gallium nitride layer; forming a second AlGaN layer on one side of the second GaN layer, which is away from the first AlGaN layer; and forming a source electrode, a drain electrode and a grid electrode on one side of the second AlGaN layer, which is away from the second GaN layer.

Alternatively, the thickness of the first gallium nitride layer may be controlled between 20nm and 100nm, the thickness of the first aluminum nitride layer may be controlled between 20nm and 100nm, and the thickness of the first aluminum gallium nitride layer may be controlled between 0.2 μm and 3 μm.

In a specific implementation, the first aluminum nitride layer is generally formed on the Si-face side of the SiC substrate.

As an alternative, after forming a second gallium nitride layer on a side of the first aluminum gallium nitride layer facing away from the first gallium nitride layer, before forming a second aluminum gallium nitride layer on a side of the second gallium nitride layer facing away from the first aluminum gallium nitride layer, the method further includes: and forming a second aluminum nitride layer on one side of the second gallium nitride layer, which is away from the first aluminum gallium nitride layer.

As an alternative, after forming the second aluminum gallium nitride layer on a side of the second gallium nitride layer facing away from the first aluminum gallium nitride layer, before forming the source, the drain and the gate on a side of the second aluminum gallium nitride layer facing away from the second gallium nitride layer, the method further includes: and a third gallium nitride layer on one side of the second aluminum gallium nitride layer facing away from the second aluminum nitride layer.

In a third aspect, an electronic circuit is provided, which comprises a circuit board and a field effect transistor according to the first aspect or various embodiments of the first aspect, which is arranged on the circuit board.

In a fourth aspect, a power amplifier is provided, which includes a circuit board and a field effect transistor according to the first aspect or various embodiments of the first aspect, which is disposed on the circuit board.

The technical effects achieved by any one of the second aspect to the fourth aspect may be described with reference to any one of the possible designs of the first aspect, and the description is not repeated here.

Drawings

Fig. 1 is a schematic structural diagram of a field effect transistor provided in the related art;

fig. 2 is a schematic structural diagram of a field effect transistor according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a field effect transistor according to another embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a field effect transistor according to another embodiment of the present disclosure;

FIG. 5 is a flowchart of a method for manufacturing a field effect transistor according to an embodiment of the present disclosure;

fig. 6a to 6e are schematic structural diagrams illustrating a manufacturing process of a field effect transistor according to an embodiment of the present application;

fig. 7 is a flowchart of a method for manufacturing a field effect transistor according to another embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings.

The AlGaN/GaN heterojunction HEMT structure based on the GaN material has the excellent characteristics of high electron mobility, high 2DEG surface density, high chemical stability, high frequency, high power and the like, so that the GaN material device has obvious advantages in the radio frequency field and the power electronics field. Therefore, the field effect transistor provided by the embodiment of the application can be widely applied to various scenes as a component of an electronic circuit, for example, the field of information transceiving, energy conversion, high-frequency switches and the like of a fifth-generation mobile communication technology (5th generation of wireless communications technologies,5G) wireless communication base station, a power electronic device and the like. For example, the circuit is applied to a radio frequency Power Amplifier (PA) circuit of a base station, wherein the main function of the PA circuit is to amplify a radio frequency model, transmit the amplified radio frequency model through an antenna unit of the base station, and transmit the amplified radio frequency model to a mobile phone for receiving. By using a radio frequency power amplifier circuit of a GaN HEMT, a relatively high power and power efficiency can be achieved, with a relatively small volume. In the future, electronic circuits based on GaN HEMTs may be applied to products such as mobile phones, WIFI, and the like, which are not limited herein.

As shown in fig. 1, the GaN HEMT generally includes a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, a source 6, a drain 7, and a gate 8. Among them, the substrate 1 is typically a sapphire substrate, a silicon carbide (SiC) substrate, or a single crystal silicon (Si) substrate. For HEMTs of commonly used aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructures, the buffer layer 3 and the channel layer 4 are both GaN, and the barrier layer 5 is AlGaN. In this single heterostructure, since both the channel layer 4 and the buffer layer 3 are GaN, a conduction band offset cannot be formed therebetween, so that the confinement of the channel Two-dimensional electron gas ((Two-dimensional electron gas,2 DEG)) is poor, electrons easily overflow the channel and enter the buffer layer, thereby reducing the pinch-off performance of the channel, causing the output conductance of the device to be increased and the breakdown performance to be reduced, and further reducing the frequency performance and the power characteristic of the device. In order to enhance the 2DEG confinement of the GaN HEMT and improve the device performance, an effective method is to use AlGaN with a low composition as the buffer layer 3. In this structure, a GaN/AlGaN heterojunction is formed between the channel layer 4 and the buffer layer 3, and negative polarization charges can be generated in the GaN/AlGaN interface due to AlGaN having a large band gap and polarization effect, so that the conduction band energy level can be raised, and the 2DEG confinement can be enhanced.

However, the structure is obtained by heteroepitaxial growth on a SiC substrate based on a Metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD) method, because of larger thermal mismatch of SiC and AlGaN, when the MOCVD epitaxial growth is finished and the temperature is reduced to room temperature from high temperature (about 1000 ℃), large tensile stress can be generated in an AlGaN buffer layer, so that the warpage of the prepared HEMT epitaxial structure is larger, and in addition, the larger tensile stress of the AlGaN buffer layer can reduce the degree of lattice mismatch between the AlGaN buffer layer and a GaN channel layer, thereby affecting the piezoelectric polarization effect in a heterojunction and also having a certain influence on the two-dimensional electron gas surface density. Thereby affecting device performance.

For this reason, the embodiments of the present application provide a field effect transistor for improving the warpage of an AlGaN buffer layer, and the detailed description thereof is described below with reference to the specific drawings and embodiments.

The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Referring to fig. 2, fig. 2 shows a schematic structural diagram of a field effect transistor according to an embodiment of the present application. The field effect transistor provided by the embodiment of the application mainly comprises: siC substrate 01, first aluminum nitride (AlN) layer 02, first gallium nitride (GaN) layer 03, first aluminum gallium nitride (AlGaN) layer 04, second gallium nitride (GaN) layer 05, second aluminum gallium nitride (AlGaN) layer 06, source electrode 11, drain electrode 12, and gate electrode 13. For convenience of description, taking the placement direction of the field effect transistor shown in fig. 2 as a reference direction, the SiC substrate 01, the first AlN layer 02, the first GaN layer 03, the first AlGaN layer 04, the second GaN layer 05 and the second AlGaN layer 06 are sequentially stacked along the direction X, and the source 11, the drain 12 and the gate 13 are all disposed on one side of the second AlGaN layer 06 facing away from the second GaN layer 05.

In a field-effect transistor, the first AlN layer 02 generally serves as a nucleation layer, the first AlGaN layer 04 serves as a buffer layer, the second GaN layer 05 serves as a channel layer, and the second AlGaN layer 06 serves as a barrier layer.

The SiC substrate 01 serves as a basic component of the field effect transistor and is used for carrying the functional layers of the field effect transistor. The SiC substrate 01 is a semi-insulating SiC substrate, in which one side is a silicon (Si) surface and the other side is a carbon (C) surface, and the first AlN layer 02 is provided on the Si surface side of the SiC substrate 01.

As an alternative, the SiC substrate 01 may be a rectangular structural layer. However, it should be understood that the shape of the SiC substrate 01 provided in the embodiments of the present application is not limited to a rectangular structure, and may take other shapes, such as a circle, an ellipse, a polygon, and other shapes, and only needs to have a sufficient area to carry other functional layers of the field effect transistor.

The first AlN layer 02 and the first AlGaN layer 04 serve as transition layers for heterogeneous growth of the second GaN layer 05 for matching lattice mismatch and thermal mismatch of the SiC substrate 01 and the second GaN layer 05 to obtain the second GaN layer 05 of better crystal quality. In the application, a GaN/AlGaN heterojunction can be formed between the second GaN layer 05 and the first AlGaN layer 04, and negative polarization charges can be generated in the GaN/AlGaN interface due to the large band gap and polarization effect of AlGaN, so that the conduction band energy level can be raised, and the 2DEG finite field performance of the field effect transistor is further enhanced.

However, since the a-axis lattice constant of AlGaN is larger than that of AlN, the first AlGaN layer 04 directly extends on the first AlN layer 02, so that the first AlGaN layer 04 is subjected to compressive stress imparted by the first AlN layer 02, the compressive stress can be used to compensate for tensile stress caused by inconsistent thermal expansion coefficients in the cooling process, and the compensation capability is limited and insufficient to completely compensate for tensile stress caused by the thermal expansion coefficients, so that the warpage of the HEMT epitaxial wafer based on the first AlGaN layer is still large. Therefore, the first GaN layer 03 is inserted between the first AlN layer 02 and the first AlGaN layer 04, and the lattice constant difference between AlN and GaN is obviously larger than that between AlN and AlGaN, so that the compressive stress introduced by lattice mismatch is larger, and the field effect transistor introducing the first GaN layer 03 can more effectively compensate the tensile stress than that of a single first AlGaN layer 04 epitaxial wafer, thereby improving the problem of larger warpage faced by the epitaxial wafer in the field effect transistor of the single first AlGaN layer 04.

In a specific implementation, the first AlN layer 02 may be formed by an MOCVD epitaxial process, and an Al source and an N source for growing the first AlN layer 02 may be trimethylaluminum (TMAl) and ammonia (NH 3), respectively, and a growth temperature may be controlled between 1000 ℃ and 1100 ℃, which is not limited herein.

The thickness of the first AlN layer 02 is not limited in this application. Alternatively, the thickness of the first AlN layer 02 may be controlled to be between 20nm and 100nm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or the like, without limitation.

In a specific implementation, the first AlGaN layer 04 may be formed by an MOCVD epitaxial process, and the Al source, ga source and N source for growing the first AlGaN layer 04 may be trimethylaluminum (TMAl), trimethylgallium (TMGA) and ammonia (NH 3), respectively, and the growth temperature may be controlled between 1000 ℃ and 1050 ℃, which is not limited herein.

The thickness of the first AlGaN layer 04 is not limited in this application. Alternatively, the thickness of the first AlGaN layer 04 may be controlled to be between 0.2 μm and 3 μm, for example, 0.2 μm, 1 μm, 2 μm, or 3 μm, etc., which is not limited herein.

In a specific implementation, the first GaN layer 03 may be formed by an MOCVD epitaxial process, and the Ga source and the N source for growing the first GaN layer 03 may be Trimethylgallium (TMGA) and ammonia (NH 3), respectively, and the growth temperature may be controlled between 950 ℃ and 1050 ℃, which is not limited herein.

The thickness of the first GaN layer 03 is not limited in this application. Alternatively, the thickness of the first GaN layer 03 may be controlled between 20nm and 100nm, for example, 20nm, 40nm, 50nm, 70nm, 90nm, 100nm, or the like, without limitation.

The second GaN layer 05 and the second AlGaN layer 06 serve as functional layers of a field effect transistor for forming a two-dimensional electron gas of the field effect transistor. A channel may be formed at the contact surface of the second GaN layer 05 and the second AlGaN layer 06, and the two-dimensional electron gas is located at the contact surface of the second GaN layer 05 and the second AlGaN layer 06.

Optionally, as shown in fig. 3, a second AlN layer 07 may also be disposed between the second GaN layer 05 and the second AlGaN layer 06, thereby increasing the effective conduction band offset of the second AlGaN layer 06, and further improving heterojunction material properties and electrical properties. In addition, the second AlN layer 07 may increase the in-plane compressive stress of the second GaN layer 05, and the increased compressive stress may increase the AlGaN/GaN heterojunction two-dimensional electron gas (2 DEG) surface density by enhancing the piezoelectric polarization electric field of the second GaN layer 05 on the one hand, and cancel the two effects of the second AlGaN layer 06 on the 2DEG surface density on the other hand. Meanwhile, the second AlN layer 07 can reduce lattice mismatch between the second GaN layer 05 and the second AlGaN layer 06, improve the interface characteristic of AlGaN/GaN heterojunction, and is beneficial to weakening interface roughness scattering and improving the mobility of 2 DEG.

As shown in fig. 4, the third GaN layer 08 may be disposed on the second AlGaN layer 06 side facing away from the second AlN layer 07, and the source 11, the drain 12, and the gate 13 may be disposed on the third GaN layer 08 side facing away from the second AlGaN layer 06. The third GaN layer 08 is provided to increase the barrier height of the second AlGaN layer 06, thereby improving the heterojunction material performance and the electrical performance of the field effect transistor.

The thicknesses of the second GaN layer 05, the second AlN layer 07, the second AlGaN layer 06, and the third GaN layer 08 are not limited, and may be set according to actual products.

The source 11, the drain 12 and the gate 13 serve as functional layers of the field effect transistor, and as shown in fig. 2 to 4, the source 11, the drain 12 and the gate 13 may be arranged in the same layer. The source 11 and the drain 12 are respectively used for being connected with an external circuit, and the grid 13 is used for controlling on-off of a channel. When the grid electrode 13 controls the channel to be conducted, the field effect transistor is in a closed state, and a circuit connected with the source electrode 11 and the drain electrode 12 can be conducted; when the gate 13 controls the channel to be disconnected, the field effect transistor is in a disconnected state, and a circuit connected with the source 11 and the drain 12 is in a disconnected state.

The source 11 and the drain 12 may both form a conductive ohmic contact with the second AlGaN layer 06, and the gate 13 may form a schottky contact with the second AlGaN layer 06. When the field effect transistor includes the third GaN layer 08, the source 11 and the drain 12 may form a conductive ohmic contact with the second AlGaN layer 06 through the third GaN layer 08, and the gate 13 may form a schottky contact with the second AlGaN layer 06 through the third GaN layer 08, which is not limited in this application. The source 11 and the drain 12 may communicate with the channel through the second AlGaN layer 06. And the gate 13 may be connected to the channel through the second AlGaN layer 06 and may absorb electrons located in the channel. When the gate 13 controls the channel to be turned on, electrons are located in the channel, and the source 11 and the drain 12 can be turned on by the electrons in the channel; when the gate 13 controls the channel to be disconnected, electrons are absorbed by the gate 13, no free electrons are in the channel, and the source 11 and the drain 12 are disconnected.

The schottky contact refers to that when metal and semiconductor materials are contacted, the energy band of the semiconductor at the interface bends to form a schottky barrier, and the existence of the schottky barrier leads to large interface resistance. Ohmic contact refers to the fact that when metal and semiconductor materials are in contact, the potential barrier at the interface is very small or there is no contact potential barrier. In this application, the gate electrode needs schottky contact with rectifying characteristics, and illustratively, the gate electrode may include nickel (Ni) and gold (Au) stacked, where Ni is located on a side close to the second AlGaN layer 06 and Au is located on a side far from the second AlGaN layer 06. The source and drain may have the same structure, and exemplary, the source and drain may include titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) stacked in order, where Ti is located on a side near the second AlGaN layer 06, au is located on a side far from the second AlGaN layer 06, and rapid thermal annealing is required to form ohmic characteristics after the 4-layer metal deposition.

When the source electrode 11, the drain electrode 12, and the gate electrode 13 are specifically provided, the gate electrode 13 may be located between the source electrode 11 and the drain electrode 12, and separate the source electrode 11 and the drain electrode 12. It should be understood that when the gate electrode 13, the drain electrode 12, and the source electrode 11 are specifically disposed, the gate electrode 13 is spaced apart from the source electrode 11 and the drain electrode 12 to ensure electrical isolation between the gate electrode 13, the source electrode 11, and the drain electrode 12.

Referring to fig. 3 and 4, the field effect transistor further includes a passivation layer 09, and the passivation layer 09 covers the semiconductor layers under the source electrode 11, the drain electrode 12, and the gate electrode 13 to protect the respective functional layers in the field effect transistor. When the third GaN layer 08 is not provided in the field-effect transistor, the passivation layer 09 covers the second AlGaN layer 06 as shown in fig. 3; as shown in fig. 4, when the third GaN layer 08 is provided in the field-effect transistor, the passivation layer 09 covers the third GaN layer 08. In the preparation, the passivation layer 09 may be formed before the source electrode 11, the drain electrode 12, and the gate electrode 13, or may be formed after the source electrode 11, the drain electrode 12, and the gate electrode 13 are formed. It should be understood that when the passivation layer 09 is formed before the source electrode 11, the drain electrode 12, and the gate electrode 13, the passivation layer 09 has openings in regions corresponding to the source electrode 11, the drain electrode 12, and the gate electrode 13 in order to ensure that the source electrode 11, the drain electrode 12, and the gate electrode 13 are electrically connected to the second AlGaN layer 06. The source 11, the drain 12, and the gate 13 are electrically connected to the second AlGaN layer 06 through the opening of the passivation layer 09. When the passivation layer 09 is formed after the source electrode 11, the drain electrode 12, and the gate electrode 13 are formed, in order to ensure that the source electrode 11, the drain electrode 12, and the gate electrode 13 can be connected to external circuits and control circuits, the passivation layer 09 has openings in regions corresponding to the source electrode 11, the drain electrode 12, and the gate electrode 13. The source electrode 11, the drain electrode 12, and the gate electrode 13 are connected to external circuits and control circuits through openings of the passivation layer 09.

Alternatively, the passivation layer 09 may be made of silicon nitride, aluminum oxide, silicon oxynitride, or other insulating materials.

It should be appreciated that passivation layer 09 is an optional structural layer for the field effect transistor. When the application environment of the field effect transistor is safer, the passivation layer 09 can be omitted.

In order to facilitate understanding of the field effect transistor provided in the embodiments of the present application, a method for manufacturing the same is described in detail below with reference to the accompanying drawings. In the embodiment of the present application, the field effect transistor may be manufactured by a manufacturing method, and referring to fig. 5 in combination with fig. 6a to 6e, fig. 5 is a schematic flow chart of the manufacturing method of the field effect transistor according to the embodiment of the present application. The method comprises the following steps:

step S101: a first AlN layer 02 was formed on a SiC substrate 01, resulting in the structure shown in fig. 6 a.

In specific implementation, a 4 inch SiC substrate or a 6 inch SiC substrate can be selected, the SiC substrate is placed in MOCVD equipment, baked for 5-10 minutes in an H2 atmosphere at 1000-1200 ℃, NH3 and TMAL are introduced at the temperature of 1000-1100 ℃, and a first AlN layer is grown on the SiC substrate. Alternatively, the thickness of the first AlN layer may be controlled at 20nm;20nm to 100nm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc., and is not limited thereto.

The first AlN layer 02 is generally formed on the Si-plane side of the SiC substrate 01.

Step S102: a first GaN layer 03 is formed on the side of the first AlN layer 02 facing away from the SiC substrate 01, resulting in the structure shown in fig. 6 b.

In a specific implementation, when the SiC substrate is 4 inches, ammonia and TMGa may be introduced at a temperature of about 1000 ℃ to grow a first GaN layer over the AlN buffer layer. When the SiC substrate is 6 inches, ammonia and TMGa may be introduced at a temperature of about 1050 ℃ to grow a first GaN layer over the AlN buffer layer.

Alternatively, the thickness of the first GaN layer may be controlled between 20nm and 100nm, for example, 20nm, 40nm, 50nm, 70nm, 90nm, 100nm, or the like, without limitation.

Step S103: a first AlGaN layer 04 is formed on the side of the first GaN layer 03 facing away from the first AlN layer 02, resulting in the structure shown in fig. 6 c.

In a specific implementation, ammonia, TMGa, and TMAl may be simultaneously introduced at a temperature of about 1000 ℃ to grow a first AlGaN layer on the first GaN layer. Alternatively, the thickness of the first AlGaN layer may be controlled to be between 0.2 μm and 3 μm, for example, 0.2 μm, 1 μm, 2 μm, or 3 μm, etc., without limitation.

Step S104: a second GaN layer 05 is formed on the side of the first AlGaN layer 04 facing away from the first GaN layer 03, resulting in the structure shown in fig. 6 d.

Step S105: a second AlGaN layer 06 is formed on the side of the second GaN layer 05 facing away from the first AlGaN layer 04, resulting in the structure shown in fig. 6 e.

In the implementation, ammonia, TMGa and TMAL can be simultaneously introduced at the temperature of 1000 ℃ to grow a second AlGaN layer on the second GaN layer. Alternatively, the thickness of the second AlGaN layer may be controlled to be around 20 nm.

Step S106: a source electrode 11, a drain electrode 12 and a gate electrode 13 are formed on the side of the second AlGaN layer 06 facing away from the second GaN layer 05, forming a structure as shown in fig. 2.

In an alternative implementation, referring to fig. 7, after step S104, before step S105, step S107 may further include: and forming a second AlN layer on one side of the second GaN layer, which is away from the first AlGaN layer.

In an alternative implementation, referring to fig. 7, after step S105, before step S106, step S108 may further be included: and a third GaN layer on a side of the second AlGaN layer facing away from the second AlN layer. The thickness of the third GaN layer may be controlled to be about 5nm, for example.

Optionally, the method may further include forming a passivation layer, where the passivation layer may be formed before step S106 or may be formed after step S106. When the passivation layer precedes step S106, the passivation layer has openings in regions corresponding to the source, drain and gate electrodes such that the source, drain and gate electrodes are electrically connected to the second AlGaN layer through the openings of the passivation layer. When the passivation layer is formed after step S106, the passivation layer has openings in regions corresponding to the source, drain and gate electrodes so that the source, drain and gate electrodes are connected to external circuits and control circuits through the openings of the passivation layer.

As can be seen from the above description, in the field effect transistor provided in the embodiment of the present application, a first GaN layer is interposed between a first AlN layer and a first AlGaN layer, and since the lattice constant difference between AlN and GaN is obviously greater than that between AlN and AlGaN, the compressive stress introduced by lattice mismatch is greater, and thus, compared with a single first AlGaN layer epitaxial wafer, the field effect transistor introduced with the first GaN layer can more effectively compensate for tensile stress, thereby improving the problem of greater warpage faced by the epitaxial wafer in the field effect transistor with the single first AlGaN layer.

The larger the size of the SiC substrate at the time of production, the more likely the crack problem caused by the larger warpage is generated. Therefore, for a large-size SiC substrate, the requirement on the warpage is more strict, and the problem can be effectively improved by inserting a first GaN layer between the first AlN layer and the first AlGaN layer.

In practical applications, improvement of performance parameters such as heat dissipation and drain current drift (Idq-drift) of a field effect transistor generally reduces the thickness of the buffer layer, and reducing the thickness of the buffer layer means that the stress problem is more prominent, resulting in greater warpage of the prepared epitaxial structure. The first GaN layer is inserted between the first AlN layer and the first AlGaN layer, so that the problem can be effectively solved.

The embodiment of the application also provides an electronic circuit, which can comprise a circuit board and any field effect transistor provided by the embodiment of the application, wherein the field effect transistor is arranged on the circuit board. Because the principle of the electronic circuit for solving the problem is similar to that of the field effect transistor, the implementation of the electronic circuit can be referred to the implementation of the field effect transistor, and the repetition is omitted.

The embodiment of the application also provides a power amplifier which can comprise a circuit board and any field effect transistor provided by the embodiment of the application, wherein the field effect transistor is arranged on the circuit board. Because the principle of the power amplifier for solving the problem is similar to that of the field effect transistor, the implementation of the power amplifier can be referred to the implementation of the field effect transistor, and the repetition is omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

A field effect transistor, comprising:

a SiC substrate;

a first aluminum nitride layer disposed on the SiC substrate;

the first gallium nitride layer is arranged on one side of the first aluminum nitride layer, which is away from the SiC substrate;

the first aluminum gallium nitride layer is arranged on one side of the first gallium nitride layer, which is away from the first aluminum nitride layer;

the second gallium nitride layer is arranged on one side of the first aluminum gallium nitride layer, which is away from the first gallium nitride layer;

the second AlGaN layer is arranged on one side of the second GaN layer, which is away from the first AlGaN layer;

the source electrode, the drain electrode and the grid electrode are arranged on one side of the second AlGaN layer, which is away from the second GaN layer.
The field effect tube of claim 1, wherein the first gallium nitride layer has a thickness of 20nm to 100nm.
The field effect tube of claim 1, wherein the first aluminum nitride layer has a thickness of 20nm to 100nm.
The field effect transistor of claim 1, wherein the first aluminum gallium nitride layer has a thickness of 0.2 μm to 3 μm.
The field effect tube of any one of claims 1-4, wherein the field effect tube further comprises:

and the second aluminum nitride layer is arranged between the second gallium nitride layer and the second aluminum gallium nitride layer.
The field effect transistor of claim 5, further comprising a third gallium nitride layer disposed on a side of the second aluminum gallium nitride layer facing away from the second aluminum gallium nitride layer, wherein the source, the drain, and the gate are all disposed on a side of the third gallium nitride layer facing away from the second aluminum gallium nitride layer.
The field effect transistor of any of claims 1-6, wherein the source, drain and gate are co-layer and wherein the source and drain both form a conductive ohmic contact with the second aluminum gallium nitride layer and the gate forms a schottky contact with the second aluminum gallium nitride layer.
The field effect transistor of any of claims 1-7, wherein the first aluminum nitride layer is a nucleation layer, the first aluminum gallium nitride layer is a buffer layer, the second gallium nitride layer is a channel layer, and the second aluminum gallium nitride layer is a barrier layer.
The field effect transistor according to any one of claims 1 to 8, wherein the first aluminum nitride layer is provided on a Si-face side of the SiC substrate.
The preparation method of the field effect transistor is characterized by comprising the following steps:

forming a first aluminum nitride layer on the SiC substrate;

forming a first gallium nitride layer on one side of the first aluminum nitride layer, which is away from the SiC substrate;

forming a first aluminum gallium nitride layer on one side of the first gallium nitride layer, which is away from the first aluminum nitride layer;

forming a second gallium nitride layer on one side of the first aluminum gallium nitride layer, which is away from the first gallium nitride layer;

forming a second AlGaN layer on one side of the second GaN layer, which is away from the first AlGaN layer;

and forming a source electrode, a drain electrode and a grid electrode on one side of the second AlGaN layer, which is away from the second GaN layer.
The method of claim 10, wherein the first gallium nitride layer has a thickness of 20nm to 100nm.
The method of claim 10, wherein the first aluminum nitride layer has a thickness of 20nm to 100nm.
The method of claim 10, wherein the first aluminum gallium nitride layer has a thickness of 0.2 μm to 3 μm.
The method of any one of claims 10-13, further comprising, after forming a second gallium nitride layer on a side of the first aluminum gallium nitride layer facing away from the first gallium nitride layer, before forming a second aluminum gallium nitride layer on a side of the second gallium nitride layer facing away from the first aluminum gallium nitride layer:

and forming a second aluminum nitride layer on one side of the second gallium nitride layer, which is away from the first aluminum gallium nitride layer.
The method of preparing of claim 14, wherein after forming a second aluminum gallium nitride layer on a side of the second gallium nitride layer facing away from the first aluminum gallium nitride layer, before forming a source, a drain, and a gate on a side of the second aluminum gallium nitride layer facing away from the second gallium nitride layer, further comprising:

and a third gallium nitride layer on one side of the second aluminum gallium nitride layer facing away from the second aluminum nitride layer.
The method of any one of claims 10 to 15, wherein the first aluminum nitride layer is formed on the Si-face side of the SiC substrate.
An electronic circuit comprising a circuit board and the field effect transistor according to any one of claims 1 to 9 disposed on the circuit board.
A power amplifier comprising a circuit board and the field effect transistor according to any one of claims 1 to 9 disposed on the circuit board.