WO2022254841A1 - Procédé de polissage double face et tranche de silicium ayant fait l'objet d'un polissage double face - Google Patents

Procédé de polissage double face et tranche de silicium ayant fait l'objet d'un polissage double face Download PDF

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Publication number
WO2022254841A1
WO2022254841A1 PCT/JP2022/008891 JP2022008891W WO2022254841A1 WO 2022254841 A1 WO2022254841 A1 WO 2022254841A1 JP 2022008891 W JP2022008891 W JP 2022008891W WO 2022254841 A1 WO2022254841 A1 WO 2022254841A1
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WO
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Prior art keywords
polishing
double
wafer
back surface
silicon wafer
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Application number
PCT/JP2022/008891
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English (en)
Japanese (ja)
Inventor
容輝 吉田
佑宜 田中
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信越半導体株式会社
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Publication date
Application filed by 信越半導体株式会社 filed Critical 信越半導体株式会社
Priority to KR1020237037430A priority Critical patent/KR20240016945A/ko
Priority to CN202280032299.1A priority patent/CN117561143A/zh
Publication of WO2022254841A1 publication Critical patent/WO2022254841A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/24—Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Definitions

  • the present invention relates to a double-sided polishing method for a wafer and a double-sided polished silicon wafer.
  • Patent Document 4 watermark defects generated in the first (coarse) polishing step in single-sided polishing are removed by adding a water-soluble polymer to the finishing slurry in the subsequent second (finishing) polishing step to finish the polishing.
  • a method of forming a protective film and reducing wetter mark defects by polishing with a polishing cloth is described.
  • JP 2017-155242 A International Publication No. WO2017/163942 pamphlet JP 2019-169687 A JP 2016-51763 A
  • a double-sided polished wafer with a roughened back surface is desired because a rougher back surface can reduce the friction between the pins and the wafer with respect to the vacuum pin chuck in the photolithography process.
  • the surface quality of wafers has come to be emphasized, and demand for roughened double-sided polished wafers is increasing as part of these needs.
  • conventional polishing methods and use of members roughen the processed surface (for example, AFM roughness Ra per 2 ⁇ m 2 0.2 nm or more) is difficult.
  • the present invention has been made to solve the above problems, and an object of the present invention is to provide a double-sided polishing method for obtaining a double-sided polished wafer with a roughened back surface, and a double-sided polished silicon wafer with a roughened back surface.
  • (volume-based average particle size measured by dynamic scattering method) / (number-based average actual particle size measured using a scanning electron microscope) Association obtained by performing a first polishing on the wafer using a slurry of abrasive grains with a degree of less than 1.0;
  • a double-side polishing method characterized in that after the first polishing, the wafer is subjected to second polishing for 15 seconds or less using a slurry containing a water-soluble polymer.
  • a double-sided polished wafer with a roughened back surface for example, a double-sided polished wafer with an AFM roughness Ra of 0.3 nm or more per 2 ⁇ m 2 on the back surface.
  • second polishing hereinafter also referred to as final polishing
  • front and back protection can be achieved.
  • the first polishing can be performed using a urethane foam-based or non-woven fabric-based polishing cloth having a Shore A hardness of 70 or more.
  • the first polishing can be performed using a polishing cloth having such hardness.
  • the present invention also provides a double-sided polished silicon wafer characterized by having an AFM roughness Ra of 0.3 nm or more per 2 ⁇ m 2 of the back surface.
  • Such a double-side polished silicon wafer has a sufficiently roughened back surface even though both sides have been polished.
  • Such double-sided polished silicon wafers can meet the needs of customers who desire double-sided polished wafers with roughened back surfaces.
  • the friction between the pins of the vacuum pin chuck and the wafer can be reduced.
  • the double-sided polished silicon wafer of the present invention can meet the needs of customers who desire a double-sided polished wafer with a roughened back surface.
  • FIG. 1 is a schematic cross-sectional view showing an example of a double-sided polished silicon wafer of the present invention
  • FIG. 5 is a graph showing AFM roughness Ra of wafers after first polishing in Examples and Comparative Examples.
  • 7 is a graph showing the relationship between the second polishing time and AFM roughness Ra;
  • the present inventors found that (volume-based average particle size measured by dynamic scattering method) / (number-based average actual particle size measured using a scanning electron microscope)
  • the wafer is polished using a slurry of abrasive grains having an association degree of less than 1.0, and then the wafer is subjected to final polishing for 15 seconds or less using a slurry containing a water-soluble polymer.
  • a double-sided polished wafer having a roughened back surface can be obtained, and completed the present invention.
  • the degree of association obtained by (volume-based average particle size measured by dynamic scattering method) / (number-based average actual particle size measured using a scanning electron microscope) is less than 1.0.
  • performing first polishing on the wafer using a slurry of abrasive grains of The double-side polishing method is characterized in that after the first polishing, the wafer is subjected to second polishing for 15 seconds or less using a slurry containing a water-soluble polymer.
  • the present invention is a double-sided polished silicon wafer characterized by having an AFM roughness Ra of 0.3 nm or more per 2 ⁇ m 2 of the rear surface.
  • first polishing and second polishing are performed on the wafer in this order.
  • the first polishing and the second polishing will be described below.
  • the wafer to be polished in the double-side polishing method of the present invention is not particularly limited, but may be, for example, a silicon wafer. Moreover, the double-side polishing apparatus used in the double-side polishing method of the present invention is not particularly limited.
  • the degree of association obtained by (volume-based average particle diameter measured by dynamic scattering method) / (number-based average actual particle diameter measured using a scanning electron microscope) is less than 1.0.
  • the degree of association can be roughly said to be an index representing the vertical/horizontal ratio of abrasive grains.
  • the dynamic scattering method can be used to measure the degree of association at the concentration of abrasive grains in the solution state actually used during polishing.
  • the particle size distribution of abrasive grains obtained from the dynamic scattering method is the volume-based particle size distribution obtained from the scattering intensity.
  • the volume-based average particle size measured by the dynamic scattering method is the volume-based average particle size (mode size; it can also be called abrasive particle size) obtained from the particle size distribution thus obtained.
  • the particle size distribution of abrasive grains obtained using a scanning electron microscope is the number-based particle size distribution, and is the particle size distribution of only the primary particles of abrasive grains.
  • the number-based average actual particle size measured using a scanning electron microscope is the number-based average particle size (mode size) obtained from the particle size distribution thus obtained.
  • an AFM roughness Ra of the back surface of the wafer of 0.3 nm or more per 2 ⁇ m 2 .
  • the degree of association is 1.0 or more, the AFM roughness Ra of the back surface of the wafer per 2 ⁇ m 2 is only 0.2 nm or less.
  • the degree of association is preferably 0.97 or less. Although the lower limit of the degree of association is not particularly limited, the degree of association can be, for example, 0.9 or more.
  • a surfactant is added to an aqueous solution in which a basic compound (e.g., KOH) is added to abrasive grains, and the amount of the surfactant added is adjusted to adjust the degree of association of the abrasive grains. .
  • a basic compound e.g., KOH
  • the material of the abrasive grains is not particularly limited, but silica (water glass, colloidal silica), SiC, etc. can be used as abrasive grains, for example.
  • the slurry used in the first polishing can contain a dispersion medium for abrasive grains.
  • the dispersion medium is not particularly limited, for example, water can be used as the dispersion medium.
  • the pH of the slurry used in the first polishing is not particularly limited, but can be, for example, 10 or more and 12 or less.
  • the slurry used in the first polishing may further contain a basic compound.
  • the basic compound is not particularly limited, for example, potassium hydroxide or tetramethylammonium hydroxide (TMAH) can be used.
  • the slurry used in the first polishing can further contain a surfactant.
  • the polishing cloth used in the first polishing is not particularly limited, for example, a urethane foam-based or non-woven cloth-based polishing cloth having a Shore A hardness of 70 or more can be used.
  • the upper limit of the Shore A hardness of the polishing cloth is not particularly limited, for example, a polishing cloth having a Shore A hardness of 90 or less can be used.
  • SC-1 cleaning may be performed on the double-sided polished wafer before the second polishing described below.
  • polishing finish polishing
  • the wafer subjected to the first polishing is subjected to second polishing (finish polishing) for 15 seconds or less using a slurry containing a water-soluble polymer for the purpose of protecting the front and back surfaces.
  • front and rear surface protection can be achieved while maintaining the rear surface AFM roughness Ra at 0.3 nm or more per 2 ⁇ m 2 .
  • the second polishing time is set to 5 seconds or more and 15 seconds or less, it is possible to more reliably achieve protection of the front and back surfaces while maintaining high roughness of the back surface.
  • the second polishing for more than 15 seconds corrects the roughened surface obtained by the first polishing, and the AFM roughness Ra falls below 0.3 nm per 2 ⁇ m 2 .
  • the water-soluble polymer contained in the slurry used in the second polishing is not particularly limited, but examples include HEC (hydroxycellulose) and PVA (polyvinyl alcohol).
  • the slurry used in the second polishing may or may not contain abrasive grains.
  • the polishing cloth used in the second polishing is not particularly limited, and a polishing cloth generally used in final polishing can be used.
  • a double-sided polished wafer After the second polishing, a double-sided polished wafer can be obtained.
  • This double-sided polished wafer has a sufficiently roughened rear surface, while being polished on both sides, and specifically can exhibit an AFM roughness Ra of 0.3 nm or more per 2 ⁇ m 2 .
  • protective films are formed on the front and back surfaces of the double-sided polished wafer.
  • the surface opposite to the back surface of the double-sided polished wafer is also roughened.
  • This surface may be subjected to single-sided polishing or the like in order to achieve a desired surface roughness.
  • FIG. 1 is a schematic cross-sectional view showing an example of the double-sided polished silicon wafer of the present invention.
  • a double-side polished silicon wafer 1 has a front surface 2 and an opposite back surface 3 .
  • the AFM roughness Ra per 2 ⁇ m 2 of the back surface 3 of the double-sided polished silicon wafer 1 is 0.3 nm or more.
  • the upper limit of the AFM roughness Ra per 2 ⁇ m 2 of the back surface 3 of the double-sided polished silicon wafer 1 is not particularly limited, it can be, for example, 0.8 nm or less.
  • the double-sided polished silicon wafer 1 of the present invention can be obtained, for example, by the double-sided polishing method of the present invention.
  • the AFM roughness Ra per 2 ⁇ m 2 of the front surface 2 of the double-side polished silicon wafer 1 obtained by the double-side polishing method of the present invention can be 0.3 nm or more, like the back surface 3 .
  • surface 2 may later be subjected to single-side polishing or the like to achieve the desired surface roughness.
  • Such a double-sided polished silicon wafer 1 has a sufficiently roughened back surface 3 even though it has been polished on both sides. can be done.
  • the double-sided polished silicon wafer 1 of the present invention in, for example, a photolithography process, the friction between the pins of the vacuum pin chuck and the wafer can be reduced.
  • the AFM roughness Ra of the back surface of the double-sided polished silicon wafer 1 can be obtained by atomic force microscope analysis.
  • Comparative Example 1 a polyoxyalkylene glycol-based (EO/PO-based) surfactant was added as a surfactant to an aqueous solution obtained by adding KOH to colloidal silica in an amount of 5 ppm by mass with respect to 100 parts by mass of colloidal silica.
  • slurry A with a pH of 10.5 was prepared.
  • Comparative Example 2 a pH 10.5 slurry B was prepared in the same manner as in Comparative Example 1 except that the same surfactant as in Comparative Example 1 was added in an amount of 10 ppm by mass with respect to 100 parts by mass of colloidal silica. was prepared.
  • Comparative Example 3 a pH 10.5 slurry C was prepared in the same manner as in Comparative Example 1 except that the same surfactant as in Comparative Example 1 was added in an amount of 30 ppm by mass with respect to 100 parts by mass of colloidal silica. was prepared.
  • Example 1 a pH 10.5 slurry D was prepared in the same manner as in Comparative Example 1, except that the same surfactant as in Comparative Example 1 was added in an amount of 50 ppm by mass with respect to 100 parts by mass of colloidal silica. was prepared.
  • Table 1 below shows the volume-based average particle size, number-based average actual particle size, and (volume-based average particle size) / (number-based average actual particle size) for the abrasive grains of slurries A to D. It indicates the required degree of association.
  • the volume-based average particle size was measured by a dynamic scattering method using a Delsa-nano manufactured by BECKMAN COULTER.
  • the number-based average actual particle size was measured by observation using a SEM (Scanning Electron Microscope) manufactured by JEOL.
  • a single crystal silicon wafer with a diameter of 300 mm was prepared as an object to be polished.
  • the area above the dotted line in Fig. 2 is the area where the AFM roughness Ra is 0.3 nm or more.
  • the AFM roughness Ra on the back surface of the wafer was only 0.2 nm or less per 2 ⁇ m 2 . , a back surface roughness of 0.3 nm or more could not be achieved.
  • Example 1 using the slurry D having an abrasive grain association degree of less than 1 the AFM roughness Ra of the back surface of the wafer was 0.3 nm or more per 2 ⁇ m 2 , and the back surface was roughened.
  • a slurry containing silica as abrasive grains, HEC (hydroxycellulose) as water-soluble polymer, and a pH of 10 was used.
  • the AFM roughness Ra of the back surface of each double-sided polished silicon wafer after the second polishing was measured at 2 ⁇ m 2 using AFM Park manufactured by ParkSYSTEMS. The results are shown in FIG.
  • the AFM roughness Ra per 2 ⁇ m 2 of the back surface is 0.3 nm or more, and while achieving sufficient roughening, the formation of the protective film was possible.
  • a second polish of more than 15 seconds straightens the roughened surface and the AFM roughness Ra per 2 ⁇ m 2 is less than 0.3 nm.
  • a more appropriate time for final polishing is 5 seconds or more and 15 seconds or less.
  • the present invention is not limited to the above embodiments.
  • the above-described embodiment is an example, and any device having substantially the same configuration as the technical idea described in the claims of the present invention and exhibiting the same effect is the present invention. is included in the technical scope of

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Organic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

La présente invention concerne un procédé de polissage double face caractérisé en ce qu'il effectue, sur une tranche, un premier polissage en utilisant une suspension épaisse d'un grain abrasif ayant un degré d'association inférieur à 1,0, qui est donné par (diamètre moyen de particule basé sur le volume mesuré par un procédé de diffusion dynamique) / (diamètre moyen réel de particule basé sur le nombre mesuré à l'aide d'un microscope électronique à balayage), et effectue, après le premier polissage, un second polissage en utilisant une suspension épaisse contenant un polymère soluble dans l'eau, sur la tranche pendant 15 secondes ou moins. Ainsi, il est possible de fournir un procédé de polissage double face par lequel une tranche ayant fait l'objet d'un polissage double face ayant une surface arrière rugueuse peut être obtenue, et de fournir une tranche de silicium ayant fait l'objet d'un polissage double face ayant une surface arrière rugueuse.
PCT/JP2022/008891 2021-06-01 2022-03-02 Procédé de polissage double face et tranche de silicium ayant fait l'objet d'un polissage double face WO2022254841A1 (fr)

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KR1020237037430A KR20240016945A (ko) 2021-06-01 2022-03-02 양면연마방법 및 양면연마 실리콘 웨이퍼
CN202280032299.1A CN117561143A (zh) 2021-06-01 2022-03-02 双面抛光方法及双面抛光硅晶圆

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JP2021-092173 2021-06-01
JP2021092173A JP7494799B2 (ja) 2021-06-01 2021-06-01 両面研磨方法

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139033A (ja) * 1994-11-14 1996-05-31 Shin Etsu Handotai Co Ltd エピタキシャルウエーハ及びその製造方法
JP2007142455A (ja) * 2000-04-27 2007-06-07 Shin Etsu Handotai Co Ltd 半導体デバイス作製プロセス用装置
JP2012231170A (ja) * 2007-02-27 2012-11-22 Hitachi Chem Co Ltd 金属用研磨液及び研磨方法
JP2016122806A (ja) * 2014-12-25 2016-07-07 花王株式会社 シリコンウェーハ用研磨液組成物
WO2018105306A1 (fr) * 2016-12-09 2018-06-14 信越半導体株式会社 Support de dispositif de polissage double face, dispositif de polissage double face et procédé de polissage double face
WO2019043890A1 (fr) * 2017-08-31 2019-03-07 株式会社Sumco Procédé de fabrication d'une plaquette de semi-conducteur
JP2021057453A (ja) * 2019-09-30 2021-04-08 株式会社フジミインコーポレーテッド 研磨用組成物

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6156207B2 (ja) 2013-04-02 2017-07-05 信越化学工業株式会社 合成石英ガラス基板の製造方法
JP6206360B2 (ja) 2014-08-29 2017-10-04 株式会社Sumco シリコンウェーハの研磨方法
JP6806765B2 (ja) 2016-03-25 2021-01-06 株式会社フジミインコーポレーテッド 金属を含む層を有する研磨対象物の研磨用組成物
JP7128005B2 (ja) 2018-03-26 2022-08-30 株式会社フジミインコーポレーテッド 研磨用組成物

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139033A (ja) * 1994-11-14 1996-05-31 Shin Etsu Handotai Co Ltd エピタキシャルウエーハ及びその製造方法
JP2007142455A (ja) * 2000-04-27 2007-06-07 Shin Etsu Handotai Co Ltd 半導体デバイス作製プロセス用装置
JP2012231170A (ja) * 2007-02-27 2012-11-22 Hitachi Chem Co Ltd 金属用研磨液及び研磨方法
JP2016122806A (ja) * 2014-12-25 2016-07-07 花王株式会社 シリコンウェーハ用研磨液組成物
WO2018105306A1 (fr) * 2016-12-09 2018-06-14 信越半導体株式会社 Support de dispositif de polissage double face, dispositif de polissage double face et procédé de polissage double face
WO2019043890A1 (fr) * 2017-08-31 2019-03-07 株式会社Sumco Procédé de fabrication d'une plaquette de semi-conducteur
JP2021057453A (ja) * 2019-09-30 2021-04-08 株式会社フジミインコーポレーテッド 研磨用組成物

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KR20240016945A (ko) 2024-02-06
TW202311459A (zh) 2023-03-16
CN117561143A (zh) 2024-02-13
JP2022184372A (ja) 2022-12-13

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