WO2022238794A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2022238794A1 WO2022238794A1 PCT/IB2022/053801 IB2022053801W WO2022238794A1 WO 2022238794 A1 WO2022238794 A1 WO 2022238794A1 IB 2022053801 W IB2022053801 W IB 2022053801W WO 2022238794 A1 WO2022238794 A1 WO 2022238794A1
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- Prior art keywords
- insulator
- oxide
- transistor
- conductor
- oxygen
- Prior art date
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Definitions
- One aspect of the present invention relates to a method for producing a metal oxide.
- one embodiment of the present invention relates to transistors, semiconductor devices, and electronic devices.
- one embodiment of the present invention relates to a method for manufacturing a semiconductor device.
- one aspect of the present invention relates to semiconductor wafers and modules.
- a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
- a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are examples of semiconductor devices.
- a display device (such as a liquid crystal display device or a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like can be said to include a semiconductor device in some cases.
- One aspect of the present invention is not limited to the above technical field.
- One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method.
- One aspect of the invention also relates to a process, machine, manufacture, or composition of matter.
- a CPU is an assembly of semiconductor elements that are processed from a semiconductor wafer, have semiconductor integrated circuits (at least transistors and memories) that are chipped, and have electrodes that are connection terminals.
- IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components of various electronic devices.
- transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
- ICs integrated circuits
- image display devices also simply referred to as display devices.
- Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
- Patent Document 1 discloses a low-power-consumption CPU and the like that utilize a characteristic that a transistor including an oxide semiconductor has a small leakage current.
- Patent Document 2 discloses a memory device or the like that can retain stored data for a long period of time by utilizing the characteristic that a transistor including an oxide semiconductor has low leakage current.
- An object of one embodiment of the present invention is to provide a semiconductor device capable of multipoint measurement. Another object of one embodiment of the present invention is to provide a semiconductor device in which variations in electrical characteristics of transistors are small. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.
- One embodiment of the present invention is a semiconductor device including a first layer, a second layer over the first layer, a first wiring, a second wiring, and a third wiring.
- the first layer has a first multiplexer, a second multiplexer and first to fourth analog switches
- the second layer has first to fourth transistors.
- Each of the first to fourth transistors has a source, a drain and a first gate.
- the first wiring is electrically connected to one of the source and drain of each of the first to fourth transistors.
- a first terminal of each of the first analog switch and the second analog switch is electrically connected to the first multiplexer, and a second terminal of each of the first analog switch and the second analog switch is connected to the second 2 are electrically connected.
- a third terminal of the first analog switch is electrically connected to the other of the source and the drain of each of the first transistor and the second transistor, and a third terminal of the second analog switch is connected to the third transistor. , and the other of the source and drain of each of the fourth transistors.
- a first terminal of each of the third analog switch and the fourth analog switch is electrically connected to the second multiplexer, and a second terminal of each of the third analog switch and the fourth analog switch is connected to the second It is electrically connected to the wiring of 3.
- a third terminal of the third analog switch electrically connected to the first gates of each of the first transistor and the third transistor; a third terminal of the fourth analog switch electrically connected to the second transistor; and the first gates of the fourth transistors.
- the semiconductor device further includes a fourth wiring, each of the first to fourth transistors further includes a second gate, and the fourth wiring is a fourth wiring of each of the first to fourth transistors. 2 is preferably electrically connected to the second gate.
- each of the first to fourth transistors preferably has a metal oxide in a channel formation region.
- the metal oxide preferably contains indium, gallium, and zinc.
- each of the first to fourth analog switches is preferably composed of a CMOS circuit.
- the transistor included in the CMOS circuit preferably has silicon in a channel formation region.
- Another embodiment of the present invention is a semiconductor device including a first layer, a second layer over the first layer, a first wiring, a second wiring, and a third wiring.
- the first layer has a first multiplexer, a second multiplexer, and first to third analog switches
- the second layer has a first transistor, a third transistor, have Each of the first transistor and the third transistor has a source, a drain and a first gate.
- the first wiring is electrically connected to one of the source and drain of each of the first transistor and the third transistor.
- a first terminal of each of the first analog switch and the second analog switch is electrically connected to the first multiplexer, and a second terminal of each of the first analog switch and the second analog switch is connected to the second 2 are electrically connected.
- a third terminal of the first analog switch is electrically connected to the other of the source and the drain of the first transistor, and a third terminal of the second analog switch is electrically connected to the other of the source and the drain of the third transistor. electrically connected.
- a first terminal of the third analog switch is electrically connected to the second multiplexer, a second terminal of the third analog switch is electrically connected to the third wiring, and the The third terminal is electrically connected to the first gates of the first transistor and the third transistor.
- the semiconductor device further includes a fourth wiring, each of the first transistor and the third transistor further includes a second gate, and the fourth wiring is connected to the first transistor and the third transistor. It is preferably electrically connected to the second gate of each transistor.
- each of the first transistor and the third transistor preferably has a metal oxide in a channel formation region.
- the metal oxide preferably contains indium, gallium, and zinc.
- each of the first to third analog switches is preferably composed of a CMOS circuit.
- the transistor included in the CMOS circuit preferably has silicon in a channel formation region.
- Another embodiment of the present invention is a semiconductor device including a first layer, a second layer over the first layer, a first wiring, a second wiring, and a third wiring.
- the first layer has a first multiplexer, a second multiplexer, a first analog switch, a third analog switch, and a fourth analog switch; 1 transistor and a second transistor.
- Each of the first transistor and the second transistor has a source, a drain and a first gate.
- the first wiring is electrically connected to one of the source and the drain of each of the first transistor and the second transistor.
- a first terminal of the first analog switch is electrically connected to the first multiplexer, a second terminal of the first analog switch is electrically connected to the second wiring, and a The third terminal is electrically connected to the other of the source and drain of each of the first transistor and the second transistor.
- a first terminal of each of the third analog switch and the fourth analog switch is electrically connected to the second multiplexer, and a second terminal of each of the third analog switch and the fourth analog switch is connected to the second It is electrically connected to the wiring of 3.
- a third terminal of the third analog switch is electrically connected to the first gate of the first transistor and a third terminal of the fourth analog switch is electrically connected to the first gate of the second transistor. connected to.
- the semiconductor device further includes a fourth wiring, each of the first transistor and the second transistor further includes a second gate, and the fourth wiring is connected to the first transistor and the second transistor. It is preferably electrically connected to the second gate of each transistor.
- each of the first transistor and the second transistor preferably has a metal oxide in a channel formation region.
- the metal oxide preferably contains indium, gallium, and zinc.
- each of the first analog switch, the third analog switch, and the fourth analog switch is preferably composed of a CMOS circuit.
- the transistor included in the CMOS circuit preferably has silicon in a channel formation region.
- a semiconductor device capable of multipoint measurement can be provided.
- a semiconductor device with little variation in electrical characteristics of transistors can be provided.
- a highly reliable semiconductor device can be provided.
- a semiconductor device with favorable electrical characteristics can be provided.
- a semiconductor device with high on-state current can be provided.
- a semiconductor device that can be miniaturized or highly integrated can be provided.
- a semiconductor device with low power consumption can be provided.
- FIG. 1A is a top view of a semiconductor device which is one embodiment of the present invention.
- 1B to 1D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
- 2A and 2B are cross-sectional views of a semiconductor device that is one embodiment of the present invention.
- FIG. 3A is a top view of a semiconductor device which is one embodiment of the present invention.
- 3B to 3D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
- FIG. 4A is a top view of a semiconductor device which is one embodiment of the present invention.
- 4B to 4D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
- FIG. 5A is a top view of a semiconductor device which is one embodiment of the present invention.
- FIG. 5B to 5D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
- FIG. 6A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 7A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 8A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 9A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 10A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 11A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 12A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 13A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 14A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 15A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 16A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 17A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
- FIG. 18 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention.
- FIG. 19 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention.
- FIG. 20 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention.
- FIG. 21 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention.
- FIG. 22A is a plan view of a semiconductor device according to one embodiment of the present invention.
- 22B and 22C are cross-sectional views of a semiconductor device that is one embodiment of the present invention.
- FIG. 23 is a diagram showing a circuit diagram of a semiconductor device.
- FIG. 24A is a perspective view of a semiconductor device.
- FIG. 24B is a perspective view illustrating the configuration of the semiconductor device;
- 25A and 25B are top views illustrating layouts of transistor groups included in a semiconductor device of one embodiment of the present invention.
- 26A and 26B are top views illustrating layouts of transistor groups included in a semiconductor device of one embodiment of the present invention.
- 27A and 27B are top views illustrating layouts of transistor groups included in a semiconductor device of one embodiment of the present invention.
- 28A and 28B are top views illustrating layouts of transistor groups included in a semiconductor device of one embodiment of the present invention.
- FIG. 24A is a perspective view of a semiconductor device.
- FIG. 24B is a perspective view illustrating the configuration of the semiconductor device
- 25A and 25B are top views illustrating layouts of transistor groups included in a semiconductor device of one embodiment of the present invention.
- 26A and 26B are
- FIG. 29 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 30 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
- FIG. 31 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- 32A and 32B are cross-sectional views of semiconductor devices according to one embodiment of the present invention.
- FIG. 33 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- FIG. 34A is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
- FIG. 34B is a perspective view illustrating a configuration example of a storage device according to one embodiment of the present invention.
- 35A to 35H are circuit diagrams illustrating configuration examples of memory devices according to one embodiment of the present invention.
- 36A and 36B are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
- FIG. 37 is a diagram illustrating a configuration example of a CPU; 38A and 38B are diagrams illustrating configuration examples of a CPU.
- FIG. 39 is a diagram illustrating a configuration example of a CPU; 40A and 40B are diagrams illustrating an example of an electronic component.
- 41A to 41E are schematic diagrams of a memory device according to one embodiment of the present invention.
- 42A to 42H are diagrams illustrating electronic devices according to one embodiment of the present invention.
- FIG. 43 is a diagram for explaining the correlation between the heat treatment temperature and the sheet resistance of the oxide.
- 44A and 44B are graphs showing the Id-Vg characteristics of prototype transistors.
- 45A1, 45B1, 45C1, and 45D1 are diagrams for explaining capacitance.
- 45A2, 45B2, 45C2, and 45D2 are diagrams showing the gate voltage-capacitance characteristics of prototype transistors.
- FIG. 46 is a diagram showing the temperature-off current characteristics of the prototype transistor in the measurement environment.
- FIG. 47 is a cross-sectional TEM photograph of the semiconductor device.
- FIG. 48 is a diagram for explaining the arrangement of TEGs.
- 49A to 49F are diagrams for explaining threshold voltage variations of transistors.
- 50A to 50F are diagrams for explaining threshold voltage variations of transistors.
- 51A to 51F are diagrams for explaining variations in field-effect mobility of transistors.
- FIG. 52A to 52F are diagrams for explaining variations in field effect mobility of transistors.
- 53A and 53B are diagrams for explaining a method of arranging transistors.
- 54A and 54B are diagrams showing Id-Vg characteristics of transistors.
- 55A to 55C are diagrams for explaining threshold voltage variations of transistors.
- FIG. 56A is a top view of the semiconductor device according to this example.
- 56B to 56D are cross-sectional views of the semiconductor device according to this example.
- FIG. 57 is a diagram showing the stress time dependence of ⁇ Vsh in the +GBT stress test according to this example.
- FIG. 58 is a diagram for explaining the time dependence of Vth of an OS transistor after X-ray irradiation.
- FIG. 60A is a diagram for explaining the dependence of the Vth of the OS transistor on the total dose of X-rays.
- FIG. 60B is a diagram for explaining the dependency of the S value of the OS transistor on the total dose of X-rays.
- 60C and 60D are diagrams showing the results of the calculations.
- 61A to 61C are diagrams illustrating transistor structures used for calculation.
- FIG. 62 is an optical microscope photograph of the prototype chip.
- FIG. 63 is a circuit diagram of a prototype OS flip-flop.
- 64A and 64B are diagrams showing the dependence of the threshold voltage of the OS transistor on the total dose of X-rays.
- 65 is a diagram showing the dependence of the threshold voltage of the OS transistor on the total dose of X-rays.
- 66A and 66B are diagrams showing the dependence of the threshold voltage of the OS transistor on the total dose of X-rays.
- FIG. 67 is a diagram showing the dependence of the threshold voltage of the OS transistor on the total dose of X-rays.
- FIG. 68 is a flow chart showing an X-ray irradiation test method.
- 69A and 69B are diagrams showing Id-Vg characteristics of OS transistors.
- 70A and 70B are diagrams showing differences in threshold voltages of OS transistors.
- 71A and 71B are diagrams showing variations in the threshold voltage of the OS transistor.
- 72A and 72B are diagrams showing the amount of change in the threshold voltage of the OS transistor.
- 73A and 73B are diagrams showing the amount of change in the threshold voltage of the OS transistor.
- FIG. 74 is a diagram for explaining the evaluation environment of the X-ray irradiation test.
- 75A and 75B are diagrams showing variations in the threshold voltage of the OS transistor.
- FIG. 76A is a diagram showing variations in threshold voltage of an OS transistor.
- FIG. 76B is a diagram showing the amount of change in SS of the OS transistor.
- FIG. 76C is a diagram showing the amount of change in field effect mobility of the OS transistor.
- 77A and 77B are graphs showing the Id-Vg characteristics of prototype transistors.
- top views also called “plan views”
- perspective views descriptions of some components may be omitted in order to facilitate understanding of the invention. Also, description of some hidden lines may be omitted.
- the ordinal numbers such as first and second are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, “first” can be appropriately replaced with “second” or “third”. Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
- connection relationships other than the connection relationships shown in the drawings or the text are not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or the text.
- X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).
- a transistor is an element having at least three terminals including a gate, a drain, and a source.
- a region in which a channel is formed (hereinafter also referred to as a channel formation region) is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode).
- a current can flow between the source and the drain through the formation region.
- a channel formation region means a region where current mainly flows.
- the function of the source or drain may be switched when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably in some cases.
- the channel length is, for example, a region in which a semiconductor (or a portion of the semiconductor in which current flows when the transistor is on) overlaps with a gate electrode in a top view of a transistor, or the source length in a channel formation region.
- the channel length does not always have the same value in all regions of one transistor. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one value, maximum value, minimum value, or average value in the channel forming region.
- the channel width is the region in which the semiconductor (or the portion of the semiconductor where current flows when the transistor is on) and the gate electrode overlap each other, or the channel length direction in the channel formation region.
- a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) and a channel width shown in a top view of a transistor ( hereinafter also referred to as “apparent channel width”) may be different.
- the effective channel width becomes larger than the apparent channel width, and its influence cannot be ignored.
- the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
- channel width may refer to the apparent channel width.
- channel width may refer to the effective channel width.
- the values of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.
- impurities in a semiconductor refer to, for example, substances other than the main components that constitute the semiconductor.
- an element whose concentration is less than 0.1 atomic percent can be said to be an impurity.
- the inclusion of impurities may cause, for example, an increase in the defect level density of the semiconductor, a decrease in crystallinity, and the like.
- impurities that change the characteristics of the semiconductor include, for example, group 1 elements, group 2 elements, group 13 elements, group 14 elements, group 15 elements, and oxide semiconductors.
- transition metals other than the main component such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
- water may also function as an impurity.
- oxygen vacancies also referred to as V 2 O 3
- silicon oxynitride contains more oxygen than nitrogen as its composition.
- Silicon nitride oxide contains more nitrogen than oxygen in its composition.
- aluminum oxynitride has a higher content of oxygen than nitrogen as its composition.
- aluminum oxynitride has a composition in which the content of nitrogen is higher than that of oxygen.
- hafnium oxynitride has a higher content of oxygen than nitrogen as its composition.
- hafnium oxynitride has a composition in which the content of nitrogen is higher than that of oxygen.
- insulator can be replaced with an insulating film or an insulating layer.
- conductor can be replaced with a conductive film or a conductive layer.
- semiconductor can be interchanged with a semiconductor film or a semiconductor layer.
- parallel means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of ⁇ 5 degrees or more and 5 degrees or less is also included.
- substantially parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
- Perfect means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
- substantially perpendicular means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
- a metal oxide is a metal oxide in a broad sense.
- Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like.
- oxide semiconductors also referred to as oxide semiconductors or simply OSs
- an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.
- the term “normally-off” means that the drain current per 1 ⁇ m of the channel width flowing through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate is 1 ⁇ 10 ⁇ 1 at room temperature. 20 A or less, 1 ⁇ 10 ⁇ 18 A or less at 85° C., or 1 ⁇ 10 ⁇ 16 A or less at 125° C.
- Voltage is a potential difference from a reference potential.
- the reference potential is ground potential
- “voltage” can be replaced with “potential”. Note that the ground potential does not necessarily mean 0V.
- the potential is relative, and when the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, etc., and the potential output from the circuit etc. also change.
- FIG. 1A-1D are top and cross-sectional views of a semiconductor device having a transistor 200.
- FIG. 1A is a top view of the semiconductor device.
- 1B to 1D are cross-sectional views of the semiconductor device.
- FIG. 1B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
- FIG. 1C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG.
- FIG. 1A is also a cross-sectional view of the transistor 200 in the channel width direction.
- FIG. 1D is sectional drawing of the site
- a semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, and an insulator 280 over the transistor 200. , insulator 282 on insulator 280 , insulator 283 on insulator 282 , insulator 274 on insulator 283 , insulator 285 on insulator 283 and insulator 274 .
- the insulator 212, the insulator 214, the insulator 216, the insulator 280, the insulator 282, the insulator 283, the insulator 285, and the insulator 274 function as interlayer films.
- conductor 240 (a conductor 240a and a conductor 240b) that is electrically connected to the transistor 200 and functions as a plug.
- insulators 241 (insulators 241a and 241b) are provided in contact with side surfaces of conductors 240 functioning as plugs.
- Conductors 246 (conductors 246 a and 246 b ) which are electrically connected to the conductor 240 and function as wirings are provided over the insulator 285 and the conductor 240 .
- the insulator 283 is in contact with part of the top surface of the insulator 214, the side surface of the insulator 216, the side surface of the insulator 222, the side surface of the insulator 275, the side surface of the insulator 280, and the side surface and top surface of the insulator 282. .
- An insulator 241a is provided in contact with the inner wall of the opening of the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and the conductor 240a is provided in contact with the side surface of the insulator 241a.
- An insulator 241b is provided in contact with the inner wall of the opening of the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and the conductor 240b is provided in contact with the side surface of the insulator 241b.
- the insulator 241 has a structure in which a first insulator is provided in contact with the inner wall of the opening, and a second insulator is provided inside.
- the conductor 240 has a structure in which a first conductor is provided in contact with the side surface of the insulator 241 and a second conductor is provided inside.
- the height of the top surface of the conductor 240 and the height of the top surface of the insulator 285 in the region overlapping with the conductor 246 can be made approximately the same.
- the transistor 200 shows a structure in which the first insulator of the insulator 241 and the second insulator of the insulator 241 are stacked, the present invention is not limited to this.
- the insulator 241 may be provided as a single layer or a stacked structure of three or more layers.
- the transistor 200 shows the structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this.
- the conductor 240 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.
- the transistor 200 includes an insulator 216 over the insulator 214, a conductor 205 (a conductor 205a and a conductor 205b) embedded in the insulator 216, and an insulator.
- the insulator 252 includes the top surface of the insulator 222, the sides of the insulator 224, the sides of the oxide 230a, the sides and top of the oxide 230b, the sides of the conductor 242, It is in contact with the side surface of insulator 271 , the side surface of insulator 275 , the side surface of insulator 280 , and the bottom surface of insulator 250 .
- the top surface of the conductor 260 is arranged so that the top surface of the insulator 254 , the top surface of the insulator 250 , the top surface of the insulator 252 , and the top surface of the insulator 280 are substantially flush with each other.
- the insulator 282 is in contact with at least part of the upper surface of each of the conductor 260 , the insulator 252 , the insulator 250 , the insulator 254 , and the insulator 280 .
- oxide 230a and the oxide 230b may be collectively referred to as the oxide 230 below.
- the conductor 242a and the conductor 242b are collectively referred to as the conductor 242 in some cases.
- the insulator 271a and the insulator 271b are collectively referred to as the insulator 271 .
- the insulator 280 and the insulator 275 are provided with openings reaching the oxide 230b.
- An insulator 252, an insulator 250, an insulator 254, and a conductor 260 are positioned within the opening.
- a conductor 260, an insulator 252, an insulator 250, and an insulator 254 are provided between the insulator 271a and the conductor 242a and the insulator 271b and the conductor 242b.
- the insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260 .
- the oxide 230 preferably has an oxide 230a overlying the insulator 224 and an oxide 230b overlying the oxide 230a.
- the transistor 200 has a structure in which the oxide 230 has two layers of the oxide 230a and the oxide 230b stacked, the present invention is not limited to this.
- a single layer of the oxide 230b or a stacked structure of three or more layers may be provided, or each of the oxides 230a and 230b may have a stacked structure.
- the conductor 260 functions as a first gate (also called top gate) electrode, and the conductor 205 functions as a second gate (also called back gate) electrode.
- insulator 252, insulator 250, and insulator 254 function as a first gate insulator
- insulator 222 and insulator 224 function as a second gate insulator.
- the gate insulator is sometimes called a gate insulating layer or a gate insulating film.
- the conductor 242a functions as one of the source electrode and the drain electrode
- the conductor 242b functions as the other of the source electrode and the drain electrode. At least part of the region of the oxide 230 overlapping with the conductor 260 functions as a channel formation region.
- FIG. 2A shows an enlarged view of the vicinity of the channel forming region in FIG. 1B.
- the oxide 230b includes a region 230bc functioning as a channel formation region of the transistor 200, and regions 230ba and 230bb functioning as a source region or a drain region and provided to sandwich the region 230bc.
- the region 230bc overlaps the conductor 260 .
- the region 230bc is provided in a region between the conductors 242a and 242b.
- the region 230ba is provided so as to overlap with the conductor 242a
- the region 230bb is provided so as to overlap with the conductor 242b.
- region 230bc functioning as a channel forming region is a high-resistance region with a lower carrier concentration because it has less oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb.
- region 230bc can be said to be i-type (intrinsic) or substantially i-type.
- the region 230ba and the region 230bb functioning as a source region or a drain region have many oxygen vacancies or have a high impurity concentration such as hydrogen, nitrogen, or a metal element, so that the carrier concentration is increased and the resistance is lowered.
- the regions 230ba and 230bb are n-type regions having a higher carrier concentration and a lower resistance than the region 230bc.
- the carrier concentration of the region 230bc functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , and 1 ⁇ 10 16 cm It is more preferably less than ⁇ 3 , more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
- the lower limit of the carrier concentration of the region 230bc functioning as a channel forming region is not particularly limited, but can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
- the carrier concentration is equal to or lower than the carrier concentration of the region 230ba and the region 230bb, and equal to or higher than the carrier concentration of the region 230bc.
- a region may be formed. That is, the region functions as a junction region between the region 230bc and the region 230ba or the region 230bb.
- the bonding region may have a hydrogen concentration equal to or lower than that of the regions 230ba and 230bb and equal to or higher than that of the region 230bc.
- the bonding region may have oxygen vacancies equal to or less than those of the regions 230ba and 230bb and equal to or greater than those of the region 230bc.
- FIG. 2A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b
- the present invention is not limited to this.
- each of the above regions may be formed up to oxide 230a as well as oxide 230b.
- the concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes for each region, and may change continuously within each region. In other words, the closer the region is to the channel formation region, the lower the concentrations of the metal elements and the impurity elements such as hydrogen and nitrogen.
- a metal oxide functioning as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a and the oxide 230b) including a channel formation region.
- the bandgap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more.
- the off-state current of the transistor can be reduced by using a metal oxide with a large bandgap.
- an In-M-Zn oxide containing indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium).
- element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.
- an In--Ga oxide, an In--Zn oxide, or an indium oxide may be used.
- the oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions.
- the atomic ratio of the element M to the main component metal element is the same as the atomic ratio of the element M to the main component metal element in the metal oxide used for the oxide 230b. Larger is preferable.
- the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. With this structure, diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b can be suppressed.
- the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
- the transistor 200 can have high on-state current and high frequency characteristics.
- the oxides 230a and 230b have a common element other than oxygen as a main component, the defect level density at the interface between the oxides 230a and 230b can be reduced. Since the defect level density at the interface between the oxides 230a and 230b can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.
- the neighboring composition includes a range of ⁇ 30% of the desired atomic number ratio.
- the element M it is preferable to use gallium. In the case where a single layer of the oxide 230b is provided as the oxide 230, a metal oxide that can be used for the oxide 230a may be used as the oxide 230b.
- the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, and the atomic ratio of the sputtering target used for the deposition of the metal oxide. may be
- the oxide 230b preferably has crystallinity.
- CAAC-OS c-axis aligned crystal oxide semiconductor
- CAAC-OS is a metal oxide that has a dense structure with high crystallinity and few impurities and defects (eg, oxygen vacancies (V 2 O 3 ) and the like).
- heat treatment is performed at a temperature at which the metal oxide does not become polycrystalline (for example, 400° C. or higher and 600° C. or lower), so that the CAAC-OS has a dense structure with higher crystallinity.
- a temperature at which the metal oxide does not become polycrystalline for example, 400° C. or higher and 600° C. or lower
- the oxide 230b by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Accordingly, extraction of oxygen from the oxide 230b can be reduced even if heat treatment is performed, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
- a crystalline oxide such as CAAC-OS
- a transistor including an oxide semiconductor if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to vary, and reliability may be degraded.
- hydrogen in the vicinity of oxygen vacancies may form defects in which hydrogen enters oxygen vacancies (hereinafter sometimes referred to as V OH ) to generate electrons serving as carriers. Therefore, if oxygen vacancies are included in the region where the channel is formed in the oxide semiconductor, the transistor has normally-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and current flows through the transistor). flow characteristics). Therefore, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in a region where a channel is formed in the oxide semiconductor. In other words, the region in which the channel is formed in the oxide semiconductor preferably has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.
- an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor, and heat treatment is performed so that the oxide semiconductor is converted from the insulator.
- Oxygen can be supplied to reduce oxygen vacancies and VOH.
- the on-state current or the field-effect mobility of the transistor 200 might decrease.
- variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface cause variations in the characteristics of the semiconductor device having transistors.
- the region 230bc functioning as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type.
- Region 230bb has a high carrier concentration and is preferably n-type. In other words, it is preferable to reduce oxygen vacancies and VOH in the region 230bc of the oxide semiconductor, and prevent an excessive amount of oxygen from being supplied to the regions 230ba and 230bb .
- microwave treatment is performed in an atmosphere containing oxygen with the conductors 242a and 242b provided over the oxide 230b, so that oxygen vacancies in the region 230bc and VOH are reduced.
- the microwave treatment refers to treatment using an apparatus having a power supply for generating high-density plasma using microwaves, for example.
- oxygen gas By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmatized using microwaves or high frequencies such as RF (radio frequency), and the oxygen plasma can act. At this time, the region 230bc can also be irradiated with microwaves or high frequencies such as RF.
- RF radio frequency
- V OH in the region 230bc is divided into oxygen vacancies (V 0 ) and hydrogen ( H ), the hydrogen is removed from the region 230bc, and the oxygen vacancies are repaired with oxygen. can be done. Therefore, the hydrogen concentration, oxygen vacancies, and VOH in the region 230bc can be reduced, and the carrier concentration can be lowered.
- the effects of microwaves, high frequencies such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb. .
- the effects of oxygen plasma can be reduced by insulators 271 and 280 provided over oxide 230b and conductor 242. FIG. As a result, V OH is reduced and an excessive amount of oxygen is not supplied in the regions 230ba and 230bb during the microwave treatment, so that a decrease in carrier concentration can be prevented.
- microwave treatment is preferably performed in an oxygen-containing atmosphere.
- an atmosphere containing oxygen By performing microwave treatment in an atmosphere containing oxygen through the insulator 252 or the insulator 250 in this manner, oxygen can be efficiently injected into the region 230bc.
- the insulator 252 so as to be in contact with the side surface of the conductor 242 and the surface of the region 230bc, it is possible to suppress the injection of more than a necessary amount of oxygen into the region 230bc and suppress the oxidation of the side surface of the conductor 242. .
- oxidation of the side surface of the conductor 242 can be suppressed when the insulating film to be the insulator 250 is formed.
- the oxygen injected into the region 230bc has various forms such as oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, atoms or molecules with unpaired electrons, or ions).
- the oxygen injected into the region 230bc may be one or more of the above forms, and oxygen radicals are particularly preferable.
- oxygen radicals are particularly preferable.
- the film quality of the insulator 252 and the insulator 250 can be improved, the reliability of the transistor 200 is improved.
- oxygen vacancies and VOH can be selectively removed from the oxide semiconductor region 230bc to make the region 230bc i-type or substantially i-type. Furthermore, excessive supply of oxygen to the regions 230ba and 230bb functioning as the source region or the drain region can be suppressed, and the state of the n-type region before the microwave treatment can be maintained. As a result, variations in the electrical characteristics of the transistor 200 can be suppressed, and variation in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.
- a semiconductor device with little variation in transistor characteristics can be provided by adopting the configuration described above. Moreover, a highly reliable semiconductor device can be provided. Moreover, a semiconductor device having favorable electrical characteristics can be provided.
- a curved surface may be provided between the side surface of the oxide 230b and the top surface of the oxide 230b in a cross-sectional view of the transistor 200 in the channel width direction. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter also referred to as round shape).
- the radius of curvature of the curved surface is preferably larger than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region without the curved surface.
- the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and more preferably greater than or equal to 2 nm and less than or equal to 10 nm.
- the interface between the oxide 230 and the insulator 252 and its vicinity can be Indium contained in the oxide 230 may be unevenly distributed.
- the vicinity of the surface of the oxide 230 has an atomic ratio close to that of indium oxide or an atomic ratio close to that of In—Zn oxide.
- the defect level density at the interface between the oxide 230a and the oxide 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
- At least one of the insulator 212 , the insulator 214 , the insulator 271 , the insulator 275 , the insulator 282 , the insulator 283 , and the insulator 285 is exposed to impurities such as water and hydrogen from the substrate side or the transistor 200 . It preferably functions as a barrier insulating film that suppresses diffusion from above into the transistor 200 .
- At least one of the insulators 212, 214, 271, 275, 282, 283, and 285 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.) and copper atoms (thus, the above impurities hardly permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (the oxygen hardly permeates).
- an insulating material that has a function of suppressing the diffusion of oxygen eg, at least one of oxygen atoms, oxygen molecules, and the like
- a barrier insulating film refers to an insulating film having barrier properties.
- barrier property refers to the function of suppressing the diffusion of the corresponding substance (also referred to as “low permeability”).
- the corresponding substance has the function of capturing and fixing (also called gettering).
- the insulators 212, 214, 271, 275, 282, 283, and 285 are insulators having a function of suppressing diffusion of water, impurities such as hydrogen, and oxygen. is preferably used, and for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used.
- the insulator 212, the insulator 275, and the insulator 283 are preferably made of silicon nitride or the like, which has a higher hydrogen barrier property.
- the insulator 214, the insulator 271, the insulator 282, and the insulator 285 are preferably made of aluminum oxide, magnesium oxide, or the like, which has high functions of capturing and fixing hydrogen.
- impurities such as water and hydrogen can be prevented from diffusing from the substrate side to the transistor 200 side through the insulators 212 and 214 .
- impurities such as water and hydrogen can be prevented from diffusing toward the transistor 200 from an interlayer insulating film or the like arranged outside the insulator 285 .
- diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulators 212 and 214 can be suppressed.
- oxygen contained in the insulator 280 or the like can be prevented from diffusing above the transistor 200 through the insulator 282 or the like.
- the transistor 200 is formed of the insulators 212, 214, 271, 275, 282, 283, and 283, which have a function of suppressing diffusion of water, impurities such as hydrogen, and oxygen.
- a structure surrounded by an insulator 285 is preferable.
- the insulators 212, 214, 271, 275, 282, 283, and 285 are preferably oxides having an amorphous structure.
- metal oxides such as AlO x (x is any number greater than 0) or MgO y (y is any number greater than 0).
- Oxygen atoms in metal oxides having such an amorphous structure have dangling bonds, and the dangling bonds sometimes have the property of capturing or fixing hydrogen.
- hydrogen contained in the transistor 200 or hydrogen existing around the transistor 200 is captured or fixed. be able to.
- the transistor 200 and the semiconductor device with favorable characteristics and high reliability can be manufactured.
- the insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but part of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 has a polycrystalline structure. may be formed.
- the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 are multilayers in which a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. It may be a structure. For example, a laminated structure in which a layer of polycrystalline structure is formed on a layer of amorphous structure may be used.
- the insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited by sputtering, for example. Since the sputtering method does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentrations of the insulators 212, 214, 271, 275, 282, 283, and 285 are can be reduced.
- the film formation method is not limited to the sputtering method, chemical vapor deposition (CVD) method, molecular beam epitaxy (MBE) method, pulsed laser deposition (PLD) method. ) method, Atomic Layer Deposition (ALD) method, or the like may be used as appropriate.
- insulators 212, 275, and 283 It may also be desirable to reduce the resistivity of insulators 212, 275, and 283.
- the resistivity of the insulator 212, the insulator 275, and the insulator 283 can be approximately 1 ⁇ 10 13 ⁇ cm, the insulator 212, the insulator 275, and the insulator 283 can be processed using plasma or the like in a manufacturing process of a semiconductor device. Insulator 283 can mitigate charge-up in conductor 205, conductor 242, conductor 260, or conductor 246 in some cases.
- Each of the insulator 212, the insulator 275, and the insulator 283 preferably has a resistivity of 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
- the insulator 216, the insulator 274, the insulator 280, and the insulator 285 preferably have a lower dielectric constant than the insulator 214.
- the parasitic capacitance generated between wirings can be reduced.
- the insulator 216, the insulator 274, the insulator 280, and the insulator 285 include silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Silicon oxide having vacancies or the like may be used as appropriate.
- the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260 .
- the conductor 205 is preferably embedded in an opening formed in the insulator 216 . Also, part of the conductor 205 is embedded in the insulator 214 in some cases.
- the conductor 205 has a conductor 205a and a conductor 205b.
- the conductor 205a is provided in contact with the bottom and side walls of the opening.
- the conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a.
- the height of the top surface of the conductor 205b approximately matches the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216 .
- the conductor 205a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N 2 O, NO, NO 2 ), and copper atoms. It is preferable to use a conductive material having a Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.
- the conductor 205a By using a conductive material having a function of reducing diffusion of hydrogen for the conductor 205a, impurities such as hydrogen contained in the conductor 205b are prevented from diffusing into the oxide 230 through the insulator 224 or the like. can be prevented. In addition, by using a conductive material having a function of suppressing diffusion of oxygen for the conductor 205a, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 205b. As the conductive material having a function of suppressing diffusion of oxygen, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example. Therefore, the conductor 205a may be a single layer or a laminate of the above conductive materials. For example, the conductor 205a may be titanium nitride.
- a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 205b.
- tungsten may be used for the conductor 205b.
- the conductor 205 may function as a second gate electrode.
- the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 .
- Vth of the transistor 200 can be increased and off-state current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.
- the electric resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electric resistivity. Also, the thickness of the insulator 216 is almost the same as that of the conductor 205 . Here, it is preferable to reduce the film thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205 . By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced;
- the conductor 205 is preferably provided larger than a region of the oxide 230 that does not overlap with the conductors 242a and 242b, as shown in FIG. 1A.
- the conductor 205 preferably extends also in regions outside the ends of the oxides 230a and 230b in the channel width direction.
- the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the oxide 230 in the channel width direction.
- the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode electrically surround the channel formation region of the oxide 230 .
- a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.
- a transistor with an S-channel structure represents a transistor structure in which a channel formation region is electrically surrounded by electric fields of one and the other of a pair of gate electrodes.
- the S-channel structure disclosed in this specification and the like is different from the Fin type structure and the planar type structure.
- the transistor can have increased resistance to the short channel effect, in other words, a transistor in which the short channel effect is less likely to occur.
- the transistor 200 By setting the transistor 200 to be normally off and having the above S-channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 200 can also be regarded as having a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure.
- GAA Gate All Around
- LGAA Layer Advanced Gate All Around
- a channel formation region formed at or near the interface between the oxide 230 and the gate insulator is the entire bulk of the oxide 230. can be done. Therefore, since the density of the current flowing through the transistor can be increased, it can be expected that the on-state current of the transistor or the field-effect mobility of the transistor can be increased.
- the conductor 205 is extended to function as wiring.
- a structure in which a conductor functioning as a wiring is provided under the conductor 205 may be employed.
- one conductor 205 does not necessarily have to be provided for each transistor.
- the conductor 205 may be shared by a plurality of transistors.
- the conductor 205 has a structure in which the conductor 205a and the conductor 205b are stacked in the transistor 200, the present invention is not limited to this.
- the conductor 205 may be provided as a single layer or a laminated structure of three or more layers.
- the insulator 222 and the insulator 224 function as gate insulators.
- the insulator 222 preferably has a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules). Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like). For example, the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224 does.
- hydrogen for example, at least one of hydrogen atoms and hydrogen molecules
- oxygen eg, at least one of oxygen atoms, oxygen molecules, and the like.
- the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224 does.
- the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
- the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 and the oxide 230 .
- aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator.
- these insulators may be nitrided.
- these insulators may be stacked with silicon oxide, silicon oxynitride, or silicon nitride.
- the insulator 222 may be a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
- high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
- thinning of gate insulators may cause problems such as leakage current.
- the gate potential during transistor operation can be reduced while maintaining the physical film thickness.
- a substance with a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr)TiO 3 (BST) may be used in some cases.
- silicon oxide, silicon oxynitride, or the like may be used as appropriate.
- the heat treatment may be performed at, for example, 100° C. to 600° C., more preferably 350° C. to 550° C.
- the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide 230 to reduce oxygen vacancies.
- the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen after heat treatment in a nitrogen gas or inert gas atmosphere. good.
- heat treatment may be continuously performed in a nitrogen gas or inert gas atmosphere.
- oxygen vacancies in the oxide 230 can be repaired with supplied oxygen. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 230, so that the hydrogen can be removed as H 2 O (dehydrated). This can suppress recombination of hydrogen remaining in the oxide 230 with oxygen vacancies to form VOH.
- the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may be used.
- the insulator 224 may be formed in an island shape so as to overlap with the oxide 230a. In this case, the insulator 275 is in contact with the side surface of the insulator 224 and the top surface of the insulator 222 .
- an island shape means a state in which two or more layers formed in the same process and using the same material are physically separated.
- the conductors 242a and 242b are provided in contact with the top surface of the oxide 230b.
- the conductors 242a and 242b function as the source and drain electrodes of the transistor 200, respectively.
- Examples of the conductor 242 include nitride containing tantalum, nitride containing titanium, nitride containing molybdenum, nitride containing tungsten, nitride containing tantalum and aluminum, and titanium. and a nitride containing aluminum is preferably used.
- nitrides containing tantalum are particularly preferred.
- ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even after absorbing oxygen.
- hydrogen contained in the oxide 230b and the like might diffuse into the conductor 242a or the conductor 242b.
- hydrogen contained in the oxide 230b or the like easily diffuses into the conductor 242a or the conductor 242b, and the diffused hydrogen 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b or the like might be absorbed by the conductor 242a or the conductor 242b.
- the conductor 242 without the curved surface, the cross-sectional area of the conductor 242 in the cross section in the channel width direction as shown in FIG. 1D can be increased. Accordingly, the conductivity of the conductor 242 can be increased, and the on current of the transistor 200 can be increased.
- the sheet resistance of the oxide 230b in a region overlapping with the conductor 242a (the conductor 242b) is reduced.
- the carrier concentration may increase. Therefore, the resistance of the oxide 230b in the region overlapping with the conductor 242a (the conductor 242b) can be reduced in a self-aligning manner.
- the insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b.
- the insulator 271 preferably functions as a barrier insulating film against at least oxygen. Therefore, the insulator 271 preferably has a function of suppressing diffusion of oxygen.
- the insulator 271 preferably has a function of suppressing diffusion of oxygen more than the insulator 280 does.
- an insulator such as aluminum oxide or magnesium oxide may be used.
- the insulator 275 is provided so as to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 271.
- the insulator 275 preferably has a function of trapping hydrogen and fixing hydrogen.
- the insulator 275 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide.
- the insulator 275 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.
- the conductor 242 can be wrapped with an insulator having a barrier property against oxygen. That is, oxygen contained in the insulators 224 and 280 can be prevented from diffusing into the conductor 242 . Accordingly, oxygen contained in the insulator 224 and the insulator 280 can suppress the direct oxidation of the conductor 242 to increase the resistivity and reduce the on-current.
- the insulator 252 functions as part of the gate insulator.
- a barrier insulating film against oxygen is preferably used.
- any of the insulators that can be used for the insulator 282 may be used.
- an insulator containing oxides of one or both of aluminum and hafnium is preferably used.
- aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used.
- aluminum oxide is used as the insulator 252 .
- the insulator 252 is an insulator containing at least oxygen and aluminum.
- the insulator 252 is provided in contact with the top and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222, as shown in FIG. 1C. That is, regions of the oxides 230a and 230b, and the insulator 224 overlapping with the conductor 260 are covered with the insulator 252 in the cross section in the channel width direction.
- the insulator 252 having a barrier property against oxygen can block oxygen from being released from the oxides 230a and 230b when heat treatment or the like is performed. Therefore, formation of oxygen vacancies in the oxides 230a and 230b can be reduced. Thereby, oxygen vacancies and VOH formed in the region 230bc can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be improved.
- the insulator 280, the insulator 250, and the like contain an excessive amount of oxygen, excessive supply of the oxygen to the oxides 230a and 230b can be suppressed. Therefore, it is possible to suppress excessive oxidation of the regions 230ba and 230bb through the region 230bc, resulting in a decrease in the on current of the transistor 200 or a decrease in the field effect mobility.
- the insulator 252 is provided in contact with the side surfaces of the conductor 242, the insulator 271, the insulator 275, and the insulator 280, respectively. Therefore, the side surfaces of the conductor 242 are oxidized and formation of an oxide film on the side surfaces can be reduced. Accordingly, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.
- the thickness of the insulator 252 is preferably thin.
- the insulator 252 has a thickness of 0.1 nm to 5.0 nm, preferably 0.5 nm to 3.0 nm, more preferably 1.0 nm to 3.0 nm. In this case, at least part of the insulator 252 may have a region with the thickness as described above. Further, the thickness of the insulator 252 is preferably thinner than the thickness of the insulator 250 . In this case, at least part of the insulator 252 may have a region thinner than the insulator 250 .
- the ALD method includes a thermal ALD (thermal ALD) method in which a precursor and a reactant react with only thermal energy, a PEALD (plasma enhanced ALD) method using a plasma-excited reactant, and the like.
- thermal ALD thermal ALD
- PEALD plasma enhanced ALD
- film formation can be performed at a lower temperature by using plasma, which is preferable in some cases.
- the ALD method utilizes the self-limiting nature of atoms and can deposit atoms one layer at a time. There are effects such as the ability to form a small amount of film, the ability to form a film with excellent coverage, and the ability to form a film at a low temperature. Therefore, the insulator 252 can be formed with a thin film thickness as described above with good coverage on the side surfaces of the opening formed in the insulator 280 or the like.
- a film formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods.
- quantification of impurities secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), or Auger electron spectroscopy (AES: Auger Electron Spectroscopy) can be performed using
- the region can be reduced. Oxygen vacancies and VOH formed in 230bc may be reduced, and excessive oxidation of the regions 230ba and 230bb may be suppressed. In such a case, the structure without the insulator 252 can simplify the manufacturing process of the semiconductor device and improve productivity.
- the insulator 250 functions as part of the gate insulator. Insulator 250 is preferably placed in contact with the top surface of insulator 252 .
- the insulator 250 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 250 is an insulator containing at least oxygen and silicon.
- the insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen.
- the thickness of the insulator 250 is preferably from 1 nm to 20 nm, more preferably from 0.5 nm to 15.0 nm. In this case, the insulator 250 may have at least a portion of the region with the film thickness as described above.
- the insulator 250 may have a two-layer laminated structure of an insulator 250a and an insulator 250b on the insulator 250a.
- the lower insulator 250a is formed using an insulator through which oxygen easily permeates
- the upper insulator 250b is formed using an insulator through which oxygen diffuses.
- the insulator 250a is preferably formed using the material that can be used for the insulator 250
- the insulator 250b is preferably an insulator containing an oxide of one or both of aluminum and hafnium.
- the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used.
- hafnium oxide is used for the insulator 250b.
- the insulator 250b is an insulator containing at least oxygen and hafnium.
- the thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and 3.0 nm or less. In this case, at least a part of the insulator 250b may have a region with the thickness as described above.
- an insulating material that is a high-k material with a high dielectric constant may be used for the insulator 250b.
- the gate insulator has a stacked structure of the insulators 250a and 250b, the stacked structure can be stable against heat and have a high relative dielectric constant. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical film thickness of the gate insulator. Also, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced. Therefore, the withstand voltage of the insulator 250 can be increased.
- EOT equivalent oxide thickness
- the insulator 254 functions as part of the gate insulator.
- a barrier insulating film against hydrogen is preferably used as the insulator 254 . Accordingly, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the insulator 250 and the oxide 230b.
- an insulator that can be used for the insulator 283 described above may be used.
- silicon nitride deposited by a PEALD method may be used as the insulator 254 .
- the insulator 254 is an insulator containing at least nitrogen and silicon.
- the insulator 254 may further have a barrier property against oxygen. Accordingly, diffusion of oxygen contained in the insulator 250 to the conductor 260 can be suppressed.
- the thickness of the insulator 254 is preferably thin.
- the insulator 254 has a thickness of 0.1 nm to 5.0 nm, preferably 0.5 nm to 3.0 nm, more preferably 1.0 nm to 3.0 nm. In this case, at least part of the insulator 254 may have a region with the thickness as described above. Further, the thickness of the insulator 254 is preferably thinner than the thickness of the insulator 250 . In this case, at least part of the insulator 254 may have a region thinner than the insulator 250 .
- the insulator 250 has a two-layer structure as illustrated in FIG. 2B
- an insulator such as hafnium oxide which has a function of suppressing permeation of impurities such as hydrogen and oxygen, such as hafnium oxide
- the insulator 250b can also have the function of the insulator 254 .
- the structure without the insulator 254 can simplify the manufacturing process of the semiconductor device and improve productivity.
- a conductor 260 functions as a first gate electrode of the transistor 200 .
- the conductor 260 preferably has a conductor 260a and a conductor 260b disposed over the conductor 260a.
- conductor 260a is preferably arranged to wrap the bottom and side surfaces of conductor 260b.
- the top surface of conductor 260 is substantially aligned with the top surface of insulator 250 .
- the conductor 260 has a two-layer structure of conductors 260a and 260b, but may have a single-layer structure or a laminated structure of three or more layers.
- the conductor 260a preferably uses a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms.
- a conductive material having a function of suppressing diffusion of oxygen eg, at least one of oxygen atoms and oxygen molecules is preferably used.
- the conductor 260a has a function of suppressing the diffusion of oxygen
- oxygen contained in the insulator 250 can suppress oxidation of the conductor 260b and a decrease in conductivity.
- the conductive material having a function of suppressing diffusion of oxygen titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example.
- the conductor 260 since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity.
- the conductor 260b can use a conductive material whose main component is tungsten, copper, or aluminum. Further, the conductor 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials.
- the conductor 260 is formed in self-alignment so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductors 242a and 242b without being aligned.
- the height of the bottom surface of the region of the conductor 260 where the conductor 260 and the oxide 230b do not overlap with each other is based on the bottom surface of the insulator 222 in the channel width direction of the transistor 200.
- the height is preferably less than the height of the bottom surface of oxide 230b.
- the conductor 260 functioning as a gate electrode covers the side surface and top surface of the channel formation region of the oxide 230b with the insulator 250 or the like interposed therebetween. Easier to work on the whole. Therefore, the on current of the transistor 200 can be increased and the frequency characteristics can be improved.
- the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.
- the insulator 280 is provided on the insulator 275, and openings are formed in regions where the insulator 252, the insulator 250, the insulator 254, and the conductor 260 are provided. Also, the upper surface of the insulator 280 may be flattened.
- the insulator 280 functioning as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.
- the insulator 280 is preferably provided using a material similar to that of the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Alternatively, a material such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies is particularly preferable because a region containing oxygen that is released by heating can be easily formed.
- the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
- an oxide containing silicon such as silicon oxide or silicon oxynitride may be used as appropriate for the insulator 280 .
- the insulator 282 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 282 preferably functions as a barrier insulating film that suppresses permeation of oxygen.
- an insulator such as a metal oxide having an amorphous structure such as aluminum oxide may be used. In this case, the insulator 282 is an insulator containing at least oxygen and aluminum.
- the insulator 282 having a function of trapping impurities such as hydrogen in contact with the insulator 280 in a region sandwiched between the insulator 212 and the insulator 283, hydrogen and the like contained in the insulator 280 and the like are provided. of impurities can be captured, and the amount of hydrogen in the region can be made constant.
- the insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen into the insulator 280 from above. Insulator 283 is placed over insulator 282 .
- a nitride containing silicon such as silicon nitride or silicon nitride oxide is preferably used.
- silicon nitride deposited by a sputtering method may be used as the insulator 283 .
- a silicon nitride film with high density can be formed.
- silicon nitride deposited by a PEALD method or a CVD method may be stacked over silicon nitride deposited by a sputtering method.
- the conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. Further, the conductor 240a and the conductor 240b may have a laminated structure.
- the first conductor provided near the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271 includes:
- a conductive material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used.
- the conductive material having a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or stacked layers.
- impurities such as water and hydrogen contained in a layer above the insulator 283 can be prevented from entering the oxide 230 through the conductors 240a and 240b.
- a barrier insulating film that can be used for the insulator 275 or the like may be used as the insulator 241a and the insulator 241b.
- an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used for the insulators 241a and 241b.
- the insulators 241a and 241b are provided in contact with the insulators 283, 282, and 271; can be suppressed from being mixed into the oxide 230 through the
- silicon nitride is suitable because it has a high blocking property against hydrogen.
- oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.
- the insulator 241a and the insulator 241b have a laminated structure as shown in FIG. It is preferable to use a combination of a barrier insulating film and a barrier insulating film against hydrogen.
- aluminum oxide deposited by the ALD method may be used as the first insulator, and silicon nitride deposited by the PEALD method may be used as the second insulator.
- the oxidation of the conductor 240 can be suppressed, and the entry of hydrogen into the conductor 240 can be reduced.
- conductors 246 (conductors 246a and 246b) functioning as wirings may be arranged in contact with the top surface of the conductor 240a and the top surface of the conductor 240b.
- a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 246 .
- the conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.
- an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example.
- insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), and resin substrates.
- Semiconductor substrates include, for example, semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.
- SOI Silicon On Insulator
- Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include a capacitor element, a resistance element, a switch element, a light emitting element, a memory element, and the like.
- Insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. oxynitrides with silicon, or nitrides with silicon and hafnium.
- Insulators with a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and an empty silicon oxide. There are silicon oxide with pores, resin, and the like.
- insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in stacks.
- insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen
- Metal oxides such as tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
- An insulator that functions as a gate insulator preferably has a region containing oxygen that is released by heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
- Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from among the above, an alloy containing the above-described metal elements as a component, or an alloy or the like in which the above-described metal elements are combined.
- tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like are used. is preferred. Also, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
- a conductive material or a material that maintains conductivity even after absorbing oxygen.
- a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
- a plurality of conductive layers formed of the above materials may be laminated and used.
- a laminated structure in which the material containing the metal element described above and the conductive material containing oxygen are combined may be used.
- a laminated structure may be employed in which the material containing the metal element described above and the conductive material containing nitrogen are combined.
- a laminated structure may be employed in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined.
- a stacked-layer structure in which the above-described material containing the metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode.
- a conductive material containing oxygen is preferably provided on the channel formation region side.
- a conductor functioning as a gate electrode it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed.
- a conductive material containing the metal element and nitrogen described above may be used.
- a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
- indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
- Indium tin oxide may also be used.
- indium gallium zinc oxide containing nitrogen may be used.
- a metal oxide (oxide semiconductor) that functions as a semiconductor is preferably used as the oxide 230 .
- Metal oxides applicable to the oxide 230 according to the present invention are described below.
- the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, and the like are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.
- the metal oxide is an In-M-Zn oxide having indium, the element M and zinc.
- the element M is aluminum, gallium, yttrium, or tin.
- Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.
- the element M there are cases where a plurality of the above elements may be combined.
- the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.
- an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used for a semiconductor layer of a transistor.
- an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used for the semiconductor layer of the transistor.
- an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO) may be used for the semiconductor layer of the transistor.
- nitrogen-containing metal oxides may also be collectively referred to as metal oxides.
- a metal oxide containing nitrogen may also be referred to as a metal oxynitride.
- oxides containing indium (In), gallium (Ga), and zinc (Zn) will be described as examples of metal oxides. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) is sometimes called an In--Ga--Zn oxide.
- Crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal. (poly crystal) and the like.
- the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum.
- XRD X-ray diffraction
- it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement.
- GIXD Gram-Incidence XRD
- the GIXD method is also called a thin film method or a Seemann-Bohlin method.
- the XRD spectrum obtained by the GIXD measurement may be simply referred to as the XRD spectrum.
- the shape of the peak of the XRD spectrum is almost bilaterally symmetrical.
- the shape of the peak of the XRD spectrum is left-right asymmetric.
- the asymmetric shape of the peaks in the XRD spectra demonstrates the presence of crystals in the film or substrate. In other words, the film or substrate cannot be said to be in an amorphous state unless the shape of the peaks in the XRD spectrum is symmetrical.
- the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nano beam electron diffraction pattern) observed by nano beam electron diffraction (NBED).
- a diffraction pattern also referred to as a nano beam electron diffraction pattern
- NBED nano beam electron diffraction
- a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state.
- a spot-like pattern is observed instead of a halo. Therefore, it cannot be concluded that the In--Ga--Zn oxide film formed at room temperature is in an intermediate state, neither single crystal nor polycrystal, nor amorphous state, and is in an amorphous state. Presumed.
- oxide semiconductors may be classified differently from the above when their structures are focused. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
- CAAC-OS is an oxide semiconductor that includes a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the formation surface of the CAAC-OS film, or the normal direction to the surface of the CAAC-OS film.
- a crystalline region is a region having periodicity in atomic arrangement. If the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement.
- CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have strain.
- the strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and has no obvious orientation in the ab plane direction.
- each of the plurality of crystal regions is composed of one or more microcrystals (crystals having a maximum diameter of less than 10 nm).
- the maximum diameter of the crystalline region is less than 10 nm.
- the maximum diameter of the crystal region may be about several tens of nanometers.
- the CAAC-OS includes a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (
- In layer a layer containing indium (In) and oxygen
- Ga gallium
- Zn zinc
- oxygen oxygen
- it tends to have a layered crystal structure (also referred to as a layered structure) in which (Ga, Zn) layers are laminated.
- the (Ga, Zn) layer may contain indium.
- the In layer may contain gallium.
- the In layer may contain zinc.
- the layered structure is observed as a lattice image in, for example, a high-resolution TEM (Transmission Electron Microscope) image.
- a plurality of bright points are observed in the electron beam diffraction pattern of the CAAC-OS film.
- a certain spot and another spot are observed at point-symmetrical positions with respect to the spot of the incident electron beam that has passed through the sample (also referred to as a direct spot) as the center of symmetry.
- the lattice arrangement in the crystal region is basically a hexagonal lattice, but the unit cell is not always a regular hexagon and may be a non-regular hexagon. Moreover, the distortion may have a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, no clear crystal grain boundary can be observed even near the strain. That is, it can be seen that the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal atoms. it is conceivable that.
- a crystal structure in which clear grain boundaries are confirmed is called a polycrystal.
- a grain boundary becomes a recombination center, traps carriers, and is highly likely to cause a decrease in on-current of a transistor, a decrease in field-effect mobility, and the like. Therefore, a CAAC-OS in which no clear grain boundaries are observed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor.
- a structure containing Zn is preferable for forming a CAAC-OS.
- In--Zn oxide and In--Ga--Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.
- CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is less likely to occur in CAAC-OS.
- CAAC-OS since the crystallinity of an oxide semiconductor may be deteriorated due to contamination of impurities, generation of defects, or the like, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS is resistant to heat and has high reliability.
- CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for a transistor including a metal oxide in a channel formation region (sometimes referred to as an OS transistor), the degree of freedom in the manufacturing process can be increased.
- nc-OS has periodic atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
- the nc-OS has minute crystals.
- the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also called a nanocrystal.
- nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
- an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.
- an nc-OS film is subjected to structural analysis using an XRD apparatus, out-of-plane XRD measurement using ⁇ /2 ⁇ scanning does not detect a peak indicating crystallinity.
- an nc-OS film is subjected to electron beam diffraction (also referred to as selected area electron beam diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is obtained. Observed.
- an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than the nanocrystal size (for example, 1 nm or more and 30 nm or less)
- electron diffraction also referred to as nanobeam electron diffraction
- an electron beam with a probe diameter close to or smaller than the nanocrystal size for example, 1 nm or more and 30 nm or less
- An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor.
- An a-like OS has void or low density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. In addition, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
- CAC-OS relates to material composition.
- CAC-OS is, for example, one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
- the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
- the mixed state is also called mosaic or patch.
- CAC-OS is a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). is called). That is, CAC-OS is a composite metal oxide in which the first region and the second region are mixed.
- the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In--Ga--Zn oxide are denoted by [In], [Ga], and [Zn], respectively.
- the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
- the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film.
- the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
- the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
- the first region is a region whose main component is indium oxide, indium zinc oxide, or the like.
- the second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. That is, the first region can be rephrased as a region containing In as a main component. Also, the second region can be rephrased as a region containing Ga as a main component.
- a clear boundary between the first region and the second region may not be observed.
- the CAC-OS in the In—Ga—Zn oxide means a region containing Ga as a main component and a region containing In as a main component in a material structure containing In, Ga, Zn, and O. Each region is a mosaic, and refers to a configuration in which these regions exist randomly. Therefore, CAC-OS is presumed to have a structure in which metal elements are unevenly distributed.
- the CAC-OS can be formed, for example, by sputtering under the condition that the substrate is not heated.
- a sputtering method one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas is used as the film formation gas. good.
- the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas during film formation is preferably as low as possible.
- the flow ratio of the oxygen gas to the total flow rate of the film forming gas during film formation is 0% or more and less than 30%, preferably 0% or more and 10% or less.
- an EDX mapping obtained using energy dispersive X-ray spectroscopy shows that a region containing In as a main component It can be confirmed that the (first region) and the region (second region) containing Ga as the main component are unevenly distributed and have a mixed structure.
- the first region is a region with higher conductivity than the second region. That is, when carriers flow through the first region, conductivity as a metal oxide is developed. Therefore, by distributing the first region in the form of a cloud in the metal oxide, a high field effect mobility ( ⁇ ) can be realized.
- the second region is a region with higher insulation than the first region.
- the leakage current can be suppressed by distributing the second region in the metal oxide.
- CAC-OS when used for a transistor, the conductivity caused by the first region and the insulation caused by the second region act complementarily to provide a switching function (on/off). functions) can be given to the CAC-OS.
- a part of the material has a conductive function
- a part of the material has an insulating function
- the whole material has a semiconductor function.
- CAC-OS is most suitable for various semiconductor devices including display devices.
- Oxide semiconductors have a variety of structures, each with different characteristics.
- An oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS. may
- an oxide semiconductor with low carrier concentration is preferably used for a transistor.
- the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm ⁇ 3 or less, preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less. 3 or less, more preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
- the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
- a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
- an oxide semiconductor with a low carrier concentration is sometimes referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
- the trap level density may also be low.
- the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor whose channel formation region is formed in an oxide semiconductor with a high trap level density might have unstable electrical characteristics.
- Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.
- the impurities in the oxide semiconductor refer to, for example, substances other than the main components of the oxide semiconductor. For example, an element whose concentration is less than 0.1 atomic percent can be said to be an impurity.
- the concentration of silicon or carbon in the oxide semiconductor is 2 ⁇ 10 atoms/cm or less, preferably 2 ⁇ 10 17 atoms/cm 3 or less.
- the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
- the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms/cm 3 , preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less. , more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
- the oxide semiconductor reacts with oxygen that bonds to a metal atom to form water, which may cause oxygen vacancies.
- oxygen vacancies When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated.
- part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, hydrogen in the oxide semiconductor is preferably reduced as much as possible.
- the hydrogen concentration in the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
- Semiconductor materials that can be used for oxide 230 are not limited to the metal oxides described above.
- a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used as the oxide 230 .
- a layered substance that functions as a semiconductor as the semiconductor material it is preferable to use a layered substance that functions as a semiconductor as the semiconductor material.
- a layered substance is a general term for a group of materials having a layered crystal structure.
- a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds such as van der Waals forces that are weaker than covalent or ionic bonds.
- a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
- Layered substances include graphene, silicene, and chalcogenides.
- Chalcogenides are compounds that contain chalcogens.
- Chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
- Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
- the oxide 230 it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor.
- a transition metal chalcogenide that functions as a semiconductor.
- Specific examples of transition metal chalcogenides applicable as the oxide 230 include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ).
- tungsten sulfide typically WS 2
- tungsten selenide typically WSe 2
- tungsten tellurium typically WTe 2
- hafnium sulfide typically HfS 2
- hafnium selenide typically HfSe 2
- zirconium sulfide typically ZrS 2
- zirconium selenide typically ZrSe 2
- a in each figure shows a top view.
- B in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in A in each figure, and is also a cross-sectional view of the transistor 200 in the channel length direction.
- C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in A in each figure, and is also a cross-sectional view of the transistor 200 in the channel width direction.
- D in each figure is a cross-sectional view of a portion indicated by a dashed line A5-A6 in A in each figure.
- some elements are omitted for clarity of the drawing.
- an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. etc. can be used as appropriate for film formation.
- Sputtering methods include an RF sputtering method using a high-frequency power source as a power source for sputtering, a DC sputtering method using a DC power source, and a pulse DC sputtering method in which the voltage applied to the electrodes is changed in pulses.
- the RF sputtering method is mainly used for forming an insulating film
- the DC sputtering method is mainly used for forming a metal conductive film.
- the pulse DC sputtering method is mainly used when forming a film of a compound such as an oxide, a nitride, or a carbide by a reactive sputtering method.
- the CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. Furthermore, it can be divided into a metal CVD (MCVD) method and an organic metal CVD (MOCVD) method depending on the raw material gas used.
- PECVD plasma CVD
- TCVD thermal CVD
- Photo CVD photo CVD
- MCVD metal CVD
- MOCVD organic metal CVD
- the plasma CVD method can obtain high-quality films at relatively low temperatures.
- the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed.
- wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, and the like included in the semiconductor device.
- a thermal CVD method that does not use plasma does not cause such plasma damage, so that the yield of semiconductor devices can be increased.
- the thermal CVD method does not cause plasma damage during film formation, a film with few defects can be obtained.
- the ALD method a thermal ALD method in which the precursor and the reactant react with only thermal energy, a PEALD method using a plasma-excited reactant, or the like can be used.
- the CVD method and ALD method are different from the sputtering method, in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage.
- the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
- the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method, such as the CVD method, which has a high film formation rate.
- a film of any composition can be deposited depending on the flow rate ratio of the raw material gases.
- the CVD method it is possible to form a film whose composition is continuously changed by changing the flow rate ratio of the source gas while forming the film.
- the time required for film formation is reduced compared to the case where film is formed using multiple film formation chambers, because the time required for transportation or pressure adjustment is not required. can do. Therefore, productivity of semiconductor devices can be improved in some cases.
- a film of any composition can be formed by simultaneously introducing different types of precursors.
- a film of any composition can be formed by controlling the number of cycles for each precursor.
- a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 6A to 6D).
- the insulator 212 is preferably deposited by a sputtering method.
- the hydrogen concentration in the insulator 212 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
- the film formation of the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
- silicon nitride is deposited as the insulator 212 by a pulse DC sputtering method using a silicon target in an atmosphere containing nitrogen gas.
- a pulse DC sputtering method it is possible to suppress the generation of particles due to arcing on the target surface, so that the film thickness distribution can be made more uniform.
- the rise and fall of the discharge can be steeper than the high-frequency voltage. As a result, power can be supplied to the electrodes more efficiently, and the sputtering rate and film quality can be improved.
- an insulator such as silicon nitride
- impurities such as water and hydrogen
- diffusion of impurities such as water and hydrogen contained in a layer below the insulator 212 can be suppressed.
- an insulator such as silicon nitride through which copper is difficult to permeate as the insulator 212, even if a metal such as copper that is easily diffused is used as a conductor in a layer (not shown) below the insulator 212, the metal does not easily pass through. The upward diffusion through the insulator 212 can be suppressed.
- an insulator 214 is formed over the insulator 212 (see FIGS. 6A to 6D).
- the insulator 214 is preferably deposited by a sputtering method.
- the hydrogen concentration in the insulator 214 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
- the film formation of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
- aluminum oxide is deposited as the insulator 214 by a pulse DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas.
- the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
- RF power may now be applied to the substrate.
- the amount of oxygen injected into layers below the insulator 214 can be controlled by the amount of RF power applied to the substrate.
- the RF power is 0 W/cm 2 or more and 1.86 W/cm 2 or less.
- the amount of oxygen suitable for the characteristics of the transistor can be changed and implanted according to the RF power when the insulator 214 is formed. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be implanted.
- the RF frequency is preferably 10 MHz or higher. It is typically 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate.
- the insulator 214 it is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of trapping and fixing hydrogen. Accordingly, hydrogen contained in the insulator 216 or the like can be captured or fixed, and diffusion of the hydrogen to the oxide 230 can be prevented.
- a metal oxide having an amorphous structure such as aluminum oxide
- aluminum oxide having an amorphous structure aluminum oxide having an amorphous structure as the insulator 214 because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor 200 and the semiconductor device with favorable characteristics and high reliability can be manufactured.
- an insulator 216 is deposited on the insulator 214 .
- the insulator 216 is preferably deposited by a sputtering method.
- the hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
- the film formation of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
- a silicon oxide film is formed as the insulator 216 by a pulse DC sputtering method using a silicon target in an atmosphere containing oxygen gas.
- the pulse DC sputtering method the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
- the insulators 212, 214, and 216 are preferably formed continuously without being exposed to the atmosphere.
- a multi-chamber film deposition apparatus may be used. Accordingly, the insulator 212, the insulator 214, and the insulator 216 can be formed by reducing hydrogen in the films, and furthermore, entry of hydrogen into the films between film formation steps can be reduced.
- Openings include, for example, grooves and slits. Also, an area in which an opening is formed may be referred to as an opening. Wet etching may be used to form the openings, but dry etching is preferable for fine processing.
- the insulator 214 it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 forming the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator 214 .
- a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as a dry etching device.
- a capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency voltage to one electrode of the parallel plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel plate electrodes. Alternatively, a high-frequency voltage having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, high-frequency voltages having different frequencies may be applied to parallel plate electrodes.
- a dry etching apparatus having a high density plasma source can be used.
- a dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus.
- ICP inductively coupled plasma
- the conductive film preferably contains a conductor having a function of suppressing permeation of oxygen.
- a conductor having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
- a stacked film of a conductor having a function of suppressing permeation of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used.
- the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a titanium nitride film is formed as a conductive film to be the conductor 205a.
- a metal nitride as a lower layer of the conductor 205b, oxidation of the conductor 205b by the insulator 216 or the like can be suppressed.
- diffusion of the metal to the outside from the conductor 205a can be prevented.
- a conductive film to be the conductor 205b is formed.
- the conductive film tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used.
- the conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, tungsten is deposited as the conductive film.
- a CMP (Chemical Mechanical Polishing) process is performed to remove part of the conductive film that will become the conductor 205a and the conductive film that will become the conductor 205b, thereby exposing the insulator 216 (see FIGS. 6A to 6D). ). As a result, conductors 205a and 205b remain only in the openings. Note that part of the insulator 216 is removed by the CMP treatment in some cases.
- an insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 7A to 7D).
- an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited.
- the insulator containing oxides of one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- hafnium-zirconium oxide is preferably used.
- Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has barrier properties against hydrogen and water, diffusion of hydrogen and water contained in structures provided around the transistor 200 into the transistor 200 through the insulator 222 is suppressed. , the generation of oxygen vacancies in the oxide 230 can be suppressed.
- the film formation of the insulator 222 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulator 222 is formed using hafnium oxide by an ALD method.
- the heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.
- the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- oxygen gas may be about 20%.
- heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen.
- the gas used in the heat treatment is preferably highly purified.
- the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less.
- the heat treatment after the insulator 222 is formed, treatment is performed at a temperature of 400° C. for 1 hour at a flow ratio of nitrogen gas to oxygen gas of 4:1. Impurities such as water and hydrogen contained in the insulator 222 can be removed by the heat treatment. In the case where an oxide containing hafnium is used as the insulator 222, the insulator 222 may be partly crystallized by the heat treatment. Further, the heat treatment can be performed at a timing such as after the insulator 224 is formed.
- an insulating film 224A is formed over the insulator 222 (see FIGS. 7A to 7D).
- the insulating film 224A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a silicon oxide film is formed as the insulating film 224A by a sputtering method.
- the hydrogen concentration in the insulating film 224A can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Since the insulating film 224A is in contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this manner.
- an oxide film 230A and an oxide film 230B are formed in order on the insulating film 224A (see FIGS. 7A to 7D).
- the oxide films 230A and 230B are preferably formed continuously without being exposed to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230A and 230B. can be kept clean.
- the oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the oxide film 230A and the oxide film 230B are preferably formed by the ALD method because films with uniform thickness can be formed even in trenches or openings with a large aspect ratio.
- using the PEALD method is preferable because the oxide films 230A and 230B can be formed at a lower temperature than the thermal ALD method.
- the sputtering method is used to form the oxide films 230A and 230B.
- the oxide film 230A and the oxide film 230B are formed by sputtering
- oxygen or a mixed gas of oxygen and rare gas is used as the sputtering gas.
- excess oxygen in the formed oxide film can be increased.
- the above oxide film is formed by a sputtering method, the above In-M-Zn oxide target or the like can be used.
- the percentage of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.
- the oxide film 230B is formed by a sputtering method, if the percentage of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, oxygen-excess oxidation occurs. A material semiconductor is formed. A transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region has relatively high reliability. However, one embodiment of the present invention is not limited to this.
- an oxygen-deficient oxide semiconductor is formed by setting the oxygen content in the sputtering gas to 1% to 30%, preferably 5% to 20%. be.
- a transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region has relatively high field-effect mobility.
- the crystallinity of the oxide film can be improved by forming the film while heating the substrate.
- the insulating film 224A, the oxide film 230A, and the oxide film 230B are preferably formed by a sputtering method without being exposed to the atmosphere.
- a multi-chamber film deposition apparatus may be used.
- the insulating film 224A, the oxide film 230A, and the oxide film 230B can be prevented from being mixed with hydrogen between the film formation steps.
- the heat treatment may be performed within a temperature range in which the oxide films 230A and 230B are not polycrystallized, and may be performed at 250° C. to 650° C., preferably 400° C. to 600° C.
- the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- oxygen gas may be about 20%.
- heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen.
- the gas used in the heat treatment is preferably highly purified.
- the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less.
- the heat treatment is performed at a temperature of 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
- Impurities such as carbon, water, and hydrogen in the oxide films 230A and 230B can be reduced by such heat treatment including oxygen gas.
- the crystallinity of the oxide film 230B can be improved, and a denser structure can be obtained.
- the crystal regions in the oxide films 230A and 230B can be increased, and the in-plane variations in the crystal regions in the oxide films 230A and 230B can be reduced. Therefore, in-plane variations in electrical characteristics of the transistor 200 can be reduced.
- hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B moves to the insulator 222 and is absorbed into the insulator 222.
- hydrogen in insulator 216 , insulating film 224 A, oxide film 230 A, and oxide film 230 B diffuses into insulator 222 . Therefore, although the hydrogen concentration in the insulator 222 increases, the hydrogen concentrations in the insulator 216, the insulating film 224A, the oxide films 230A, and the oxide films 230B decrease.
- the insulating film 224A functions as a gate insulator of the transistor 200, and the oxide films 230A and 230B function as channel formation regions of the transistor 200. Therefore, the transistor 200 including the insulating film 224A, the oxide films 230A, and the oxide films 230B with reduced hydrogen concentration is preferable because it has high reliability.
- a conductive film 242A is formed on the oxide film 230B (see FIGS. 7A to 7D).
- the conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the conductive film 242A may be formed using tantalum nitride by a sputtering method.
- heat treatment may be performed before the conductive film 242A is formed. The heat treatment may be performed under reduced pressure to continuously form the conductive film 242A without exposure to the air.
- the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment mode, the temperature of the heat treatment is set to 200.degree.
- an insulating film 271A is formed on the conductive film 242A (see FIGS. 7A to 7D).
- the insulating film 271A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film 271A is preferably an insulating film having a function of suppressing permeation of oxygen.
- aluminum oxide or silicon nitride may be deposited by a sputtering method.
- the conductive film 242A and the insulating film 271A are preferably formed by a sputtering method without being exposed to the atmosphere.
- a multi-chamber film deposition apparatus may be used. Accordingly, the conductive film 242A and the insulating film 271A can be formed by reducing hydrogen in the films, and furthermore, the entry of hydrogen into the films between film formation steps can be reduced. Further, in the case of providing a hard mask over the insulating film 271A, a film to be the hard mask may be formed continuously without being exposed to the air.
- the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A are processed into an island shape by a lithography method, so that the insulator 224, the oxide 230a, the oxide 230b, and the conductive film 224A are formed.
- a layer 242B and an insulating layer 271B are formed (see FIGS. 8A-8D).
- the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B are formed so as to overlap with the conductor 205 at least partially.
- a dry etching method or a wet etching method can be used for the above processing. Processing by the dry etching method is suitable for fine processing.
- the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A may be processed under different
- the resist is first exposed through a mask.
- the exposed regions are then removed or left behind using a developer to form a resist mask.
- a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching treatment through the resist mask.
- a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
- a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
- an electron beam or an ion beam may be used instead of the light described above.
- the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.
- a hard mask made of an insulator or conductor may be used under the resist mask.
- an insulating film or a conductive film that serves as a hard mask material is formed over the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do.
- the etching of the conductive film 242A or the like may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching.
- the hard mask may be removed by etching after etching the conductive film 242A or the like.
- the insulating layer 271B is used as a hard mask.
- the conductive layer 242B does not have curved surfaces between the side surfaces and the top surface, as shown in FIGS. 8B to 8D.
- the conductors 242a and 242b shown in FIGS. 1B and 1D have angular ends where the side surface and the top surface intersect. Since the end portion where the side surface and the top surface of the conductor 242 intersect is angular, the cross-sectional area of the conductor 242 is larger than when the end portion has a curved surface. Accordingly, the resistance of the conductor 242 is reduced, so that the on current of the transistor 200 can be increased.
- side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be tapered.
- a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface.
- the angle formed by the inclined side surface and the substrate surface (hereinafter sometimes referred to as taper angle) is preferably less than 90°.
- the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may have a taper angle of, for example, 60° or more and less than 90°. By tapering the side surface in this manner, the coverage of the insulator 275 or the like is improved in subsequent steps, and defects such as voids can be reduced.
- the structure is not limited to the above, and the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be substantially perpendicular to the top surface of the insulator 222.
- the area can be reduced and the density can be increased.
- a byproduct generated in the etching step is formed in layers on side surfaces of the insulator 224, the oxides 230a and 230b, the conductive layer 242B, and the insulating layer 271B.
- the layered byproduct is formed between the insulator 224 , the oxide 230 a , the oxide 230 b , the conductive layer 242 B, the insulating layer 271 B, and the insulator 275 . Therefore, the layered byproduct formed in contact with the top surface of the insulator 222 is preferably removed.
- an insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 9A to 9D).
- insulator 275 is preferably in close contact with the top surface of insulator 222 and the side surface of insulator 224 .
- the insulator 275 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- An insulating film having a function of suppressing permeation of oxygen is preferably used as the insulator 275 .
- the insulator 275 aluminum oxide is deposited by a sputtering method, and silicon nitride is deposited thereover by a PEALD method.
- the function of suppressing diffusion of water, impurities such as hydrogen, and oxygen may be improved.
- the oxides 230a, 230b, and the conductive layer 242B can be covered with the insulator 275 and the insulating layer 271B, which have a function of suppressing diffusion of oxygen. Accordingly, direct diffusion of oxygen from the insulator 280 or the like to the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B in a later step can be reduced.
- an insulating film to be the insulator 280 is formed on the insulator 275 .
- the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a silicon oxide film may be formed by a sputtering method.
- the insulator 280 containing excess oxygen can be formed.
- the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Note that heat treatment may be performed before the insulating film is formed.
- the heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the air.
- moisture and hydrogen adsorbed to the surface of the insulator 275 or the like can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b and the insulator 224 can be reduced.
- the heat treatment conditions described above can be used for the heat treatment.
- the insulating film to be the insulator 280 is subjected to CMP treatment to form the insulator 280 with a flat upper surface (see FIGS. 9A to 9D).
- CMP treatment to form the insulator 280 with a flat upper surface.
- a silicon nitride film may be formed over the insulator 280 by a sputtering method, for example, and CMP treatment may be performed until the silicon nitride reaches the insulator 280 .
- part of the insulator 280, part of the insulator 275, part of the insulating layer 271B, and part of the conductive layer 242B are processed to form an opening reaching the oxide 230b.
- the opening is preferably formed so as to overlap with the conductor 205 .
- an insulator 271a, an insulator 271b, a conductor 242a, and a conductor 242b are formed (see FIGS. 10A to 10D).
- the side surfaces of the insulator 280, the insulator 275, the insulator 271, and the conductor 242 may be tapered.
- the taper angle of insulator 280 may be greater than the taper angle of conductor 242 .
- the upper portion of oxide 230b may be removed when forming the opening.
- a dry etching method or a wet etching method can be used for processing part of the insulator 280, part of the insulator 275, part of the insulating layer 271B, and part of the conductive layer 242B. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions. For example, part of the insulator 280 is processed by a dry etching method, part of the insulator 275 and part of the insulating layer 271B are processed by a wet etching method, and part of the conductive layer 242B is processed by a dry etching method. You may
- the impurity adheres to the side surface of the oxide 230a, the top surface and side surface of the oxide 230b, the side surface of the conductor 242, the side surface of the insulator 280, or the like, or diffuses into these.
- a step of removing such impurities may be performed.
- the dry etching may form a damaged region on the surface of the oxide 230b. Such damaged areas may be removed.
- the impurities include components contained in the insulator 280, the insulator 275, part of the insulating layer 271B, and the conductive layer 242B, components contained in a member used in an apparatus used for forming the opening, It may be caused by components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.
- impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, impurities such as aluminum and silicon are preferably removed from the surface of oxide 230b and its vicinity. Further, it is preferable that the concentration of the impurity is reduced.
- the concentration of aluminum atoms on the surface of the oxide 230b and its vicinity may be 5.0 atomic percent or less, preferably 2.0 atomic percent or less, more preferably 1.5 atomic percent or less. 0 atomic % or less is more preferable, and less than 0.3 atomic % is even more preferable.
- the regions with low crystallinity of the oxide 230b are preferably reduced or removed.
- the oxide 230b have a layered CAAC structure.
- the conductor 242a or the conductor 242b and its vicinity function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this manner, even at the drain end portion, which significantly affects the drain breakdown voltage, the region with low crystallinity of the oxide 230b is removed and the CAAC structure is provided. can. In addition, reliability of the transistor 200 can be improved.
- a cleaning process is performed to remove impurities adhered to the surface of the oxide 230b in the etching process.
- a cleaning method there are wet cleaning using a cleaning solution (which can also be referred to as wet etching treatment), plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate. Note that the cleaning process may deepen the groove.
- Wet cleaning may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc. with carbonated water or pure water, pure water, carbonated water, or the like.
- ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
- these washings may be appropriately combined.
- an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid
- an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water.
- concentration, temperature, and the like of the aqueous solution may be adjusted as appropriate depending on impurities to be removed, the configuration of the semiconductor device to be cleaned, and the like.
- the ammonia concentration of the diluted ammonia water should be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less.
- the concentration of hydrogen fluoride in the diluted hydrofluoric acid should be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.
- a frequency of 200 kHz or higher is preferable, and a frequency of 900 kHz or higher is more preferable.
- a frequency of 900 kHz or higher is more preferable.
- the cleaning treatment may be performed multiple times, and the cleaning liquid may be changed for each cleaning treatment.
- a treatment using diluted hydrofluoric acid or diluted ammonia water may be performed as the first cleaning treatment
- a treatment using pure water or carbonated water may be performed as the second cleaning treatment.
- wet cleaning is performed using diluted ammonia water.
- impurities attached to the surfaces of the oxides 230a and 230b or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.
- a heat treatment may be performed after the above etching or after the above cleaning.
- the heat treatment may be performed at 100° C. or higher and 450° C. or lower, preferably 350° C. or higher and 400° C. or lower.
- the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxides 230a and 230b, and oxygen vacancies can be reduced. Further, by performing such heat treatment, the crystallinity of the oxide 230b can be improved.
- after heat treatment in an oxygen atmosphere heat treatment may be continuously performed in a nitrogen atmosphere without exposure to the air.
- an insulating film 252A is formed (see FIGS. 11A to 11D).
- the insulating film 252A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film 252A is preferably formed using the ALD method.
- the insulating film 252A is preferably formed with a thin film thickness, and it is necessary to reduce variations in film thickness.
- the ALD method is a method of forming a film by alternately introducing a precursor and a reactant (for example, an oxidizing agent). Film thickness can be adjusted.
- a precursor and a reactant for example, an oxidizing agent
- the insulating film 252A needs to be formed with good coverage on the bottom and side surfaces of the opening formed in the insulator 280 and the like. In particular, it is preferable to form films with good coverage on the top surface and side surfaces of the oxide 230 and the side surfaces of the conductor 242 . Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 252A can be formed with good coverage over the opening.
- ozone (O 3 ), oxygen (O 2 ), water (H 2 O), or the like can be used as an oxidizing agent.
- oxygen (O 2 ), or the like that does not contain hydrogen can be used as an oxidizing agent.
- the insulating film 252A is formed by thermal ALD using aluminum oxide.
- microwave treatment refers to treatment using an apparatus having a power supply for generating high-density plasma using microwaves, for example.
- microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
- Dotted lines shown in FIGS. 11B to 11D indicate microwaves, high frequencies such as RF, oxygen plasma, or oxygen radicals.
- a microwave treatment apparatus having a power supply for generating high-density plasma using microwaves, for example.
- the frequency of the microwave processing device may be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz.
- High-density oxygen radicals can be generated by using high-density plasma.
- the power of the power source for applying microwaves in the microwave processing apparatus may be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less.
- the microwave processing apparatus may have a power supply for applying RF to the substrate side. Further, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.
- the above microwave treatment is preferably performed under reduced pressure, and the pressure should be 10 Pa or more and 1000 Pa or less, preferably 300 Pa or more and 700 Pa or less.
- the treatment temperature may be 750°C or lower, preferably 500°C or lower, for example, about 400°C.
- heat treatment may be continuously performed without exposure to the outside air. For example, heat treatment may be performed at 100° C. or higher and 750° C. or lower, preferably 300° C. or higher and 500° C. or lower.
- the microwave treatment may be performed using oxygen gas and argon gas.
- the oxygen flow rate ratio (O 2 /(O 2 +Ar)) should be greater than 0% and 100% or less.
- the oxygen flow ratio (O 2 /(O 2 +Ar)) should be greater than 0% and 50% or less.
- the oxygen flow ratio (O 2 /(O 2 +Ar)) should be 10% or more and 40% or less.
- the oxygen flow ratio (O 2 /(O 2 +Ar)) should be 10% or more and 30% or less.
- microwave treatment is performed in an oxygen-containing atmosphere so that oxygen gas is plasmatized using microwaves or high frequencies such as RF, and the oxygen plasma is turned into a conductor of the oxide 230b. It can act on the region between 242a and conductor 242b.
- the region 230bc can also be irradiated with microwaves or high frequencies such as RF. That is, microwaves, high frequencies such as RF, oxygen plasma, or the like can be applied to the region 230bc shown in FIG. 2A.
- the VOH in region 230bc can be disrupted and hydrogen can be removed from region 230bc.
- VOH contained in the region 230bc can be reduced. Therefore, oxygen vacancies and VOH in the region 230bc can be reduced, and the carrier concentration can be lowered.
- oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 are supplied to the oxygen vacancies formed in the region 230bc, thereby further reducing the oxygen vacancies in the region 230bc and increasing the carrier concentration. can be lowered.
- conductors 242a and 242b are provided on the regions 230ba and 230bb shown in FIG. 2A.
- the conductor 242 preferably functions as a shielding film against the action of microwaves, high frequencies such as RF, oxygen plasma, and the like when microwave treatment is performed in an oxygen-containing atmosphere. Therefore, the conductor 242 preferably has a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.
- the conductors 242a and 242b block the effects of microwaves, high frequencies such as RF, oxygen plasma, and the like, so that these effects do not reach the regions 230ba and 230bb. do not have.
- reduction of V OH and supply of an excessive amount of oxygen do not occur in the regions 230ba and 230bb due to the microwave treatment, so that a decrease in carrier concentration can be prevented.
- An insulator 252 having a barrier property against oxygen is provided in contact with side surfaces of the conductors 242a and 242b. Accordingly, formation of an oxide film on the side surfaces of the conductors 242a and 242b due to microwave treatment can be suppressed.
- the film quality of the insulator 252 can be improved, the reliability of the transistor 200 is improved.
- oxygen vacancies and V OH can be selectively removed from the oxide semiconductor region 230bc to make the region 230bc i-type or substantially i-type. Furthermore, excessive supply of oxygen to the regions 230ba and 230bb functioning as the source region or the drain region can be suppressed, and the state of the n-type region before the microwave treatment can be maintained. As a result, variations in the electrical characteristics of the transistor 200 can be suppressed, and variation in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.
- heat energy may be directly transmitted to the oxide 230b due to the electromagnetic interaction between the microwave and the molecules in the oxide 230b. This thermal energy may heat the oxide 230b.
- Such heat treatment is sometimes called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing may be obtained. Further, when hydrogen is contained in the oxide 230b, it is conceivable that this thermal energy is transmitted to hydrogen in the oxide 230b and thus activated hydrogen is released from the oxide 230b.
- an insulating film 250A is formed (see FIGS. 12A to 12D).
- Heat treatment may be performed before the insulating film 250A is formed, or the heat treatment may be performed under reduced pressure and the insulating film 250A may be formed continuously without exposure to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such treatment, moisture and hydrogen adsorbed to the surface of the insulating film 252A or the like can be removed, and the moisture concentration and hydrogen concentration in the oxides 230a and 230b can be reduced.
- the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.
- the insulating film 250A can be formed using a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes the insulator 250 facing the oxide 230b through the thin insulator 252 in a later step, it is preferable that the hydrogen concentration is reduced in this way.
- silicon oxynitride is deposited by PECVD as the insulating film 250A.
- an insulating film to be the insulator 250b may be formed after the insulating film 250A is formed.
- the insulating film to be the insulator 250b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film to be the insulator 250b is preferably formed using an insulator having a function of suppressing diffusion of oxygen. With such a structure, diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. That is, reduction in the amount of oxygen supplied to the oxide 230 can be suppressed.
- An insulating film to be the insulator 250 b can be provided using a material similar to that of the insulator 222 .
- hafnium oxide may be deposited by thermal ALD as an insulating film to be the insulator 250b.
- a microwave treatment may be performed after the insulating film 250A is formed (see FIGS. 12A to 12D).
- the microwave treatment conditions for the microwave treatment performed after the insulating film 252A is formed may be used.
- the microwave treatment may be performed after the insulating film 250A is formed without performing the microwave treatment after the insulating film 252A is formed.
- microwave treatment may be performed after the insulating film to be the insulator 250b is formed.
- conditions for the microwave treatment performed after the insulating film 252A is formed may be used.
- the microwave treatment may be performed after the insulating film to be the insulator 250b is formed without performing the microwave treatment after the insulating film 252A or the insulating film 250A is formed.
- heat treatment may be performed while maintaining the reduced pressure.
- hydrogen in the insulating film 252A, the insulating film 250A, the insulating film to be the insulator 250b, the oxide 230b, and the oxide 230a can be efficiently removed.
- part of the hydrogen may be gettered by the conductors 242 (the conductors 242a and 242b).
- the step of performing the heat treatment may be repeated a plurality of times while the reduced pressure state is maintained.
- the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.
- microwave treatment that is, microwave annealing may serve as the heat treatment. When the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.
- the diffusion of hydrogen, water, impurities, and the like can be suppressed by modifying the film quality of the insulating film 252A, the insulating film 250A, and the insulating film to be the insulator 250b by microwave treatment. Therefore, in a post-process such as formation of a conductive film to be the conductor 260 or a post-treatment such as heat treatment, hydrogen, water, impurities, or the like diffuse through the insulator 252 into the oxides 230b, 230a, and the like. can be suppressed.
- an insulating film 254A is formed (see FIGS. 13A to 13D).
- the insulating film 254A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulating film 254A is preferably formed using the ALD method similarly to the insulating film 252A.
- the insulating film 254A can be formed with a thin film thickness and good coverage.
- silicon nitride is deposited by the PEALD method as the insulating film 254A.
- a conductive film to be the conductor 260a and a conductive film to be the conductor 260b are formed in this order.
- the conductive film to be the conductor 260a and the conductive film to be the conductor 260b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- titanium nitride is deposited as a conductive film to be the conductor 260a by an ALD method
- tungsten is deposited as a conductive film to be the conductor 260b by a CVD method.
- the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive film to be the conductor 260a, and the conductive film to be the conductor 260b are polished by CMP treatment until the insulator 280 is exposed.
- 252, insulator 250, insulator 254, and conductors 260 (conductors 260a and 260b) are formed (see FIGS. 14A-14D). Insulator 252 is thereby placed to cover the opening to oxide 230b.
- the conductor 260 is arranged to fill the opening with the insulator 252, the insulator 250, and the insulator 254 interposed therebetween.
- heat treatment may be performed under the same conditions as the above heat treatment.
- the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere.
- the heat treatment can reduce the moisture concentration and the hydrogen concentration in the insulators 250 and 280 .
- the insulator 282 may be formed continuously without exposure to the air.
- an insulator 282 is formed over the insulator 252, the insulator 250, the insulator 254, the conductor 260, and the insulator 280 (see FIGS. 14A to 14D).
- the insulator 282 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulator 282 is preferably deposited by a sputtering method.
- the concentration of hydrogen in the insulator 282 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
- aluminum oxide is deposited as the insulator 282 by a pulse DC sputtering method using an aluminum target in an atmosphere containing oxygen gas.
- the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
- the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 while the insulator 280 is being formed.
- the insulator 280 can contain excess oxygen.
- the insulator 282 is preferably formed while heating the substrate.
- an etching mask is formed over the insulator 282 by a lithography method, and the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216 are etched. is processed until the top surface of the insulator 214 is exposed (see FIGS. 15A to 15D).
- wet etching may be used for the processing, use of dry etching is preferable for fine processing.
- heat treatment may be performed.
- the heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 350° C. or higher and 600° C. or lower. Further, the heat treatment is preferably performed at a temperature lower than the heat treatment temperature performed after forming the oxide film 230B. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing the heat treatment, part of the oxygen added to the insulator 280 diffuses into the oxide 230 through the insulator 250 and the like.
- the insulator 282 the insulator 280, the insulator 275, the insulator 222, and the insulator 216 are processed, so that the insulator 280 can be included in the insulator 280 from the side surface thereof. Oxygen and hydrogen bound to the oxygen can be released to the outside. Hydrogen combined with oxygen is released as water. Therefore, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced.
- an insulator 252 is provided in contact with the top surface and side surfaces of the oxide 230 in a region of the oxide 230 that overlaps with the conductor 260 .
- the insulator 252 has a barrier property against oxygen, so that diffusion of an excessive amount of oxygen into the oxide 230 can be reduced. Oxygen can thereby be supplied to the region 230bc and its vicinity so that an excessive amount of oxygen is not supplied. Accordingly, oxygen vacancies and VOH formed in the region 230bc can be reduced while suppressing oxidation of the side surfaces of the conductor 242 due to excess oxygen. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be improved.
- the volume of the insulator 280 for one transistor 200 may become excessively small.
- the amount of oxygen that diffuses into the oxide 230 is significantly reduced in the heat treatment. If the oxide 230 is heated in contact with an oxide insulator (eg, the insulator 250 or the like) that does not contain enough oxygen, oxygen in the oxide 230 might be released.
- the insulator 252 is provided in contact with the top surface and side surfaces of the oxide 230 in a region of the oxide 230 overlapping with the conductor 260 . Since the insulator 252 has a barrier property against oxygen, elimination of oxygen from the oxide 230 can be reduced even in the above heat treatment. Thereby, oxygen vacancies and VOH formed in the region 230bc can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be improved.
- a transistor having favorable electrical characteristics and favorable reliability can be formed regardless of whether the amount of oxygen supplied from the insulator 280 is large or small. can be done. Therefore, it is possible to provide a semiconductor device that suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.
- an insulator 283 is formed over the insulator 282 (see FIGS. 16A to 16D).
- the insulator 283 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulator 283 is preferably deposited by a sputtering method.
- the concentration of hydrogen in the insulator 283 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
- the insulator 283 may be multi-layered.
- a silicon nitride film may be formed using a sputtering method, and a silicon nitride film may be formed over the silicon nitride film using an ALD method.
- an insulator 274 is formed on the insulator 283 .
- the insulator 274 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- silicon oxide is deposited as the insulator 274 by a CVD method.
- the insulator 274 is polished by CMP treatment until the insulator 283 is exposed, thereby planarizing the top surface of the insulator 274 (see FIGS. 16A to 16D). Part of the top surface of the insulator 283 may be removed by the CMP treatment.
- an insulator 285 is formed over the insulator 274 and the insulator 283 (see FIGS. 17A to 17D).
- the insulator 285 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the insulator 285 is preferably deposited by a sputtering method.
- the concentration of hydrogen in the insulator 285 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
- silicon oxide is deposited as the insulator 285 by a sputtering method.
- openings reaching the conductors 242 are formed in the insulators 271, 275, 280, 282, 283, and 285 (see FIGS. 17A and 17B).
- the formation of the opening may be performed using a lithography method.
- the shape of the opening is circular when viewed from above, but the shape is not limited to this.
- the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners when viewed from above.
- an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 17B).
- the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an insulating film having a function of suppressing permeation of oxygen is preferably used.
- the anisotropic etching of the insulating film that becomes the insulator 241 for example, a dry etching method or the like may be used.
- a dry etching method or the like By providing the insulator 241 on the side wall portion of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed next can be prevented.
- impurities such as water and hydrogen contained in the insulator 280 and the like can be prevented from diffusing into the conductors 240a and 240b.
- the conductive film preferably has a stacked-layer structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen.
- a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. can be used.
- the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- CMP treatment is performed to remove part of the conductive film to be the conductors 240a and 240b, and the upper surface of the insulator 285 is exposed.
- the conductive film remains only in the openings, so that the conductors 240a and 240b with flat top surfaces can be formed (see FIGS. 17A to 17D). Note that part of the top surface of the insulator 285 is removed by the CMP treatment in some cases.
- the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the conductive film to be the conductor 246 is processed by a lithography method to form a conductor 246a in contact with the top surface of the conductor 240a and a conductor 246b in contact with the top surface of the conductor 240b.
- part of the insulator 285 in a region where the conductors 246a and 246b do not overlap with the insulator 285 may be removed.
- a semiconductor device including the transistor 200 illustrated in FIGS. 1A to 1D can be manufactured.
- the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device described in this embodiment.
- ⁇ Microwave processing device> A microwave processing apparatus that can be used in the above method for manufacturing a semiconductor device is described below.
- FIG. 18 the configuration of a manufacturing apparatus in which impurities are less mixed when manufacturing a semiconductor device or the like will be described with reference to FIGS. 18 to 21.
- FIG. 18 the configuration of a manufacturing apparatus in which impurities are less mixed when manufacturing a semiconductor device or the like will be described with reference to FIGS. 18 to 21.
- FIG. 18 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700.
- the manufacturing apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 having a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning substrates, and an atmosphere-side substrate transfer chamber for transferring substrates from the atmosphere-side substrate supply chamber 2701 .
- a chamber 2702 for loading a substrate and switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, and a substrate unloading chamber for carrying out the substrate and changing the pressure in the chamber from reduced pressure to atmospheric pressure, or It has an unload lock chamber 2703b for switching from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in vacuum, chambers 2706a, 2706b, 2706c, and 2706d.
- the atmospheric side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the chamber 2706a. , chamber 2706b, chamber 2706c and chamber 2706d.
- a gate valve GV is provided at the connecting portion of each chamber, and each chamber can be independently held in a vacuum state except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702 .
- the atmosphere-side substrate transfer chamber 2702 is provided with a transfer robot 2763a
- the transfer chamber 2704 is provided with a transfer robot 2763b. The substrate can be transported within the manufacturing apparatus 2700 by the transport robot 2763a and the transport robot 2763b.
- the back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1 ⁇ 10 ⁇ 4 Pa or less, preferably 3 ⁇ 10 ⁇ 5 Pa or less, more preferably 1 ⁇ 10 ⁇ 5 Pa or less.
- the partial pressure of gas molecules (atoms) having a mass-to-charge ratio (m/z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less. and more preferably 3 ⁇ 10 ⁇ 6 Pa or less.
- the partial pressure of gas molecules (atoms) having an m/z of 28 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less, more preferably 3 ⁇ 10 ⁇ 5 Pa or less. ⁇ 10 ⁇ 6 Pa or less.
- the partial pressure of gas molecules (atoms) with m/z of 44 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less, more preferably 3 ⁇ 10 ⁇ 5 Pa or less. ⁇ 10 ⁇ 6 Pa or less.
- the total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using an ionization vacuum gauge, a mass spectrometer, or the like.
- the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage.
- the leak rate of the transfer chamber 2704 is 1 ⁇ 10 0 Pa/min or less, preferably 5 ⁇ 10 ⁇ 1 Pa/min or less.
- the leak rate of each chamber is 1 ⁇ 10 ⁇ 1 Pa/min or less, preferably 5 ⁇ 10 ⁇ 2 Pa/min or less.
- the leak rate can be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, mass spectrometer, or the like. For example, it may be derived from the total pressure 10 minutes after the start of vacuuming with a vacuum pump such as a turbo-molecular pump and the total pressure 10 minutes after the valve is closed.
- the total pressure after 10 minutes from the start of the evacuation may be an average value obtained by measuring the total pressure a plurality of times.
- the leak rate depends on external and internal leaks.
- An external leak is an inflow of gas from outside the vacuum system due to a minute hole, poor seal, or the like.
- Internal leaks result from leaks from partitions such as valves in the vacuum system or from released gas from internal components. In order to keep the leak rate below the above numerical value, it is necessary to take measures against both external and internal leaks.
- the transfer chamber 2704 and the opening/closing parts of each chamber may be sealed with metal gaskets.
- Metal gaskets are preferably made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leaks.
- passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like it is possible to suppress released gas containing impurities released from the metal gasket, thereby reducing internal leaks.
- aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits less gas containing impurities is used as a member constituting the manufacturing apparatus 2700 .
- an alloy containing iron, chromium, nickel, or the like may be coated with the aforementioned metal containing impurities and emitting less gas. Alloys containing iron, chromium, nickel, and the like are rigid, heat resistant, and workable.
- the surface unevenness of the member is reduced by polishing or the like in order to reduce the surface area, the emitted gas can be reduced.
- the members of the manufacturing apparatus 2700 described above may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.
- the members of the manufacturing apparatus 2700 are made of only metal as much as possible. It is advisable to thinly coat with chromium or the like.
- the adsorbate present in the transfer chamber 2704 and each chamber does not affect the pressure of the transfer chamber 2704 and each chamber because it adheres to the inner wall or the like, but it is a cause of gas release when the transfer chamber 2704 and each chamber is evacuated. becomes. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with a high evacuation capacity to desorb as much as possible the adsorbate existing in the transfer chamber 2704 and each chamber and to evacuate them in advance.
- the transfer chamber 2704 and each chamber may be baked in order to facilitate the desorption of the adsorbate. By baking, the desorption speed of the adsorbate can be increased by about ten times. Baking may be performed at 100° C.
- the desorption speed of water and the like which is difficult to desorb only by exhausting, can be further increased.
- the desorption speed of the adsorbate can be further increased.
- an inert gas such as a heated rare gas, oxygen, or the like to increase the pressure in the transfer chamber 2704 and each chamber, and then evacuate the transfer chamber 2704 and each chamber again after a certain period of time.
- an inert gas or oxygen having a temperature of 40° C. or more and 400° C. or less, preferably 50° C. or more and 200° C.
- the pressure is preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less.
- the transfer chamber 2704 and each chamber are evacuated for a period of 5 to 300 minutes, preferably 10 to 120 minutes.
- the chamber 2706b and the chamber 2706c are, for example, chambers capable of subjecting an object to be processed to microwave processing. Note that the chamber 2706b and the chamber 2706c are different only in the atmosphere when the microwave treatment is performed. Since other configurations are common, they will be collectively described below.
- the chamber 2706b and the chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812 and an exhaust port 2819. Further, outside the chambers 2706b and 2706c, etc., there are a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, and a waveguide 2807. , a matching box 2815 , a high frequency power supply 2816 , a vacuum pump 2817 and a valve 2818 are provided.
- a high frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804 .
- Mode converter 2805 is connected to slot antenna plate 2808 via waveguide 2807 .
- Slot antenna plate 2808 is placed in contact with dielectric plate 2809 .
- gas supply source 2801 is connected to mode converter 2805 via valve 2802 .
- Gas is sent to chambers 2706b and 2706c by gas pipe 2806 passing through mode converter 2805, waveguide 2807 and dielectric plate 2809.
- the vacuum pump 2817 has a function of exhausting gas and the like from the chambers 2706b and 2706c through the valve 2818 and the exhaust port 2819 .
- the high-frequency power supply 2816 is connected to the substrate holder 2812 through the matching box 2815 .
- the substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically chucking or mechanically chucking the substrate 2811 . It also functions as an electrode to which power is supplied from the high frequency power supply 2816 . It also has a heating mechanism 2813 inside and has a function of heating the substrate 2811 .
- the vacuum pump 2817 for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, a turbomolecular pump, or the like can be used. Also, in addition to the vacuum pump 2817, a cryotrap may be used. The use of a cryopump and a cryotrap is particularly preferable because water can be discharged efficiently.
- the heating mechanism 2813 for example, a heating mechanism that heats using a resistance heating element or the like may be used.
- a heating mechanism that heats by heat conduction or heat radiation from a medium such as heated gas may be used.
- RTA Rapid Thermal Annealing
- GRTA Gas Rapid Thermal Annealing
- LRTA Low Rapid Thermal Annealing
- GRTA performs heat treatment using high temperature gas.
- An inert gas is used as the gas.
- the gas supply source 2801 may be connected to the refiner via a mass flow controller. It is preferable to use a gas having a dew point of ⁇ 80° C. or lower, preferably ⁇ 100° C. or lower.
- a gas having a dew point of ⁇ 80° C. or lower preferably ⁇ 100° C. or lower.
- oxygen gas, nitrogen gas, and rare gas such as argon gas may be used.
- dielectric plate 2809 for example, silicon oxide (quartz), aluminum oxide (alumina), yttrium oxide (yttria), or the like may be used. Further, another protective layer may be formed on the surface of dielectric plate 2809 . As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, or the like may be used. Since the dielectric plate 2809 will be exposed to a particularly high-density region of the high-density plasma 2810, which will be described later, damage can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.
- the high-frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz.
- a microwave generated by the high frequency generator 2803 is transmitted to the mode converter 2805 via the waveguide 2804 .
- the microwave transmitted as TE mode is converted into TEM mode.
- the microwave is transmitted to slot antenna plate 2808 via waveguide 2807 .
- Slot antenna plate 2808 is provided with a plurality of slot holes, and microwaves pass through the slot holes and dielectric plate 2809 .
- an electric field can be generated below the dielectric plate 2809 to generate high density plasma 2810 .
- Ions and radicals according to the gas species supplied from the gas supply source 2801 are present in the high-density plasma 2810 . For example, there are oxygen radicals.
- the ions and radicals generated by the high-density plasma 2810 can modify the film on the substrate 2811 .
- the high-frequency power supply 2816 for example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz and 27.12 MHz may be used.
- RF Radio Frequency
- oxygen radical treatment using high-density plasma 2810 can be performed.
- the chamber 2706a and the chamber 2706d are, for example, chambers capable of irradiating an object to be processed with electromagnetic waves.
- the only difference between the chamber 2706a and the chamber 2706d is the type of electromagnetic wave. Since there are many common parts in other configurations, they will be collectively described below.
- the chambers 2706 a and 2706 d have one or more lamps 2820 , substrate holders 2825 , gas inlets 2823 and exhaust ports 2830 . Further, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chambers 2706a and 2706d.
- a gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822 .
- Vacuum pump 2828 is connected to exhaust port 2830 through valve 2829 .
- the lamp 2820 is arranged facing the substrate holder 2825 .
- the substrate holder 2825 has the function of holding the substrate 2824 . Further, the substrate holder 2825 has a heating mechanism 2826 inside and has a function of heating the substrate 2824 .
- a light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light
- a light source having a function of emitting an electromagnetic wave having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.
- a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp may be used.
- the electromagnetic waves radiated from the lamp 2820 can be partially or wholly absorbed by the substrate 2824 to modify the film or the like on the substrate 2824 .
- defects can be created or reduced, or impurities can be removed. Note that by heating the substrate 2824, defects can be efficiently generated or reduced, impurities can be removed, or the like.
- electromagnetic waves radiated from the lamps 2820 may cause the substrate holder 2825 to generate heat to heat the substrate 2824 .
- the heating mechanism 2826 may not be provided inside the substrate holder 2825 .
- the vacuum pump 2828 refers to the description of the vacuum pump 2817.
- the heating mechanism 2826 the description of the heating mechanism 2813 is referred to.
- the gas supply source 2821 the description of the gas supply source 2801 is referred to.
- the microwave processing device that can be used in this embodiment is not limited to the above.
- a microwave processing apparatus 2900 shown in FIG. 21 can be used.
- Microwave processing apparatus 2900 has quartz tube 2901 , exhaust port 2819 , gas supply source 2801 , valve 2802 , high frequency generator 2803 , waveguide 2804 , gas pipe 2806 , vacuum pump 2817 and valve 2818 .
- the microwave processing apparatus 2900 also has a substrate holder 2902 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more) inside the quartz tube 2901 . Further, the microwave processing apparatus 2900 may have heating means 2903 outside the quartz tube 2901 .
- the microwave generated by the high-frequency generator 2803 is applied to the substrate provided inside the quartz tube 2901 via the waveguide 2804 .
- a vacuum pump 2817 is connected to an exhaust port 2819 via a valve 2818 and can adjust the pressure inside the quartz tube 2901 .
- a gas supply source 2801 is also connected to a gas pipe 2806 via a valve 2802 so that a desired gas can be introduced into the quartz pipe 2901 .
- the heating means 2903 can heat the substrate 2811 in the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801 .
- the microwave treatment apparatus 2900 heat treatment and microwave treatment can be performed on the substrate 2811 at the same time. Further, microwave treatment can be performed after the substrate 2811 is heated. Further, heat treatment can be performed after microwave treatment is performed on the substrate 2811 .
- All of the substrates 2811_1 to 2811_n may be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates.
- the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n ⁇ 1 may be processing substrates.
- the substrates 2811_1, 2811_2, 2811_n ⁇ 1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n ⁇ 2 may be processing substrates.
- the use of a dummy substrate is preferable because a plurality of substrates to be processed can be uniformly processed during microwave treatment or heat treatment, and variations among the substrates to be processed can be reduced.
- placing a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804 is preferable because direct exposure of the processing substrate to microwaves can be suppressed.
- Each figure A shows a top view of a semiconductor device.
- Each drawing B is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in each drawing A.
- each drawing C is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in each drawing A.
- Each drawing D is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in each drawing A, respectively.
- some elements are omitted for clarity of illustration.
- the semiconductor device shown in FIGS. 3A to 3D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
- the semiconductor devices shown in FIGS. 3A to 3D are different from the semiconductor devices shown in FIGS. 1A to 1D in that the insulator 282 is not provided. Therefore, in the semiconductor device shown in FIGS. touch the top.
- oxide 230 For example, if sufficient oxygen can be supplied to oxide 230, such as by the microwave treatment shown in FIG. can be of type i. In such a case, a structure in which the insulator 282 is not provided as shown in FIGS. 3A to 3D is employed, so that manufacturing steps of a semiconductor device can be simplified and productivity can be improved.
- the semiconductor device shown in FIGS. 4A to 4D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
- the semiconductor devices illustrated in FIGS. 4A to 4D are different from the semiconductor devices illustrated in FIGS. 1A to 1D in that oxides 243 (oxides 243a and 243b) are provided.
- the oxide 243a is provided between the oxide 230b and the conductor 242a
- the oxide 243b is provided between the oxide 230b and the conductor 242b.
- oxide 243a preferably contacts the top surface of oxide 230b and the bottom surface of conductor 242a.
- oxide 243b preferably contacts the top surface of oxide 230b and the bottom surface of conductor 242b.
- the oxide 243 preferably has a function of suppressing permeation of oxygen.
- the oxide 243 having a function of suppressing permeation of oxygen between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, an electric current between the conductor 242 and the oxide 230b is reduced. This is preferable because resistance is reduced. With such a structure, electrical characteristics, field-effect mobility, and reliability of the transistor 200 can be improved in some cases.
- a metal oxide containing the element M may also be used as the oxide 243 .
- the element M is preferably aluminum, gallium, yttrium, or tin.
- the oxide 243 preferably has a higher concentration of the element M than the oxide 230b.
- gallium oxide may be used as the oxide 243 .
- a metal oxide such as an In-M-Zn oxide may be used as the oxide 243 .
- the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
- the thickness of the oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and still more preferably 1 nm to 2 nm. Further, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, release of oxygen from the oxide 230 can be suppressed favorably. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal structure, release of oxygen from the oxide 230 can be suppressed in some cases.
- the semiconductor device shown in FIGS. 5A to 5D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
- the semiconductor devices shown in FIGS. 5A to 5D are different from the semiconductor devices shown in FIGS. 1A to 1D in that the insulator 283 is in contact with part of the top surface of the insulator 212 .
- Transistor 200 is thus located within the area encapsulated by insulator 283 and insulator 212 . With the above structure, hydrogen contained outside the sealed region can be prevented from entering the sealed region. Further, although the transistor 200 illustrated in FIGS.
- each of the insulator 212 and the insulator 283 may have a laminated structure of two or more layers.
- an OS transistor such as the transistor 200 has little change in electrical characteristics due to radiation irradiation, that is, it has high resistance to radiation, so it can be suitably used in an environment where radiation may be incident.
- an OS transistor can be suitably used when used in outer space.
- the OS transistor can be used as a transistor included in a semiconductor device provided in a space shuttle, an artificial satellite, a space probe, or the like.
- Radiation includes, for example, X-rays, neutron beams, and the like.
- outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may include the thermosphere, the mesosphere, and the stratosphere.
- the OS transistor can be used as a transistor that constitutes a semiconductor device provided in a nuclear power plant, a radioactive waste disposal site, or a working robot in a disposal site.
- it can be suitably used for a transistor that constitutes a semiconductor device provided in a remote-controlled robot that is remotely controlled for dismantling a nuclear reactor facility, retrieving nuclear fuel or fuel debris, and conducting a field survey of a space with a large amount of radioactive materials.
- the OS transistor can be suitably used as a transistor included in a semiconductor device provided in electronic equipment used in radiology.
- electronic equipment is an X-ray detection panel in radiography.
- FIG. 22A shows a top view of the semiconductor device 500.
- FIG. The x-axis shown in FIG. 22A is parallel to the channel length direction of the transistor 200, and the y-axis is perpendicular to the x-axis.
- 22B is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in FIG. 22A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
- FIG. 22C is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in FIG. 22A, and is also a cross-sectional view of the opening region 400 and its vicinity. Note that some elements are omitted in the top view of FIG. 22A for clarity of illustration.
- a semiconductor device 500 shown in FIGS. 22A to 22C is a modification of the semiconductor device shown in FIGS. 1A to 1D.
- a semiconductor device 500 shown in FIGS. 22A to 22C differs from the semiconductor device shown in FIGS. 1A to 1D in that a sealing portion 265 is formed so as to surround a plurality of transistors 200.
- FIG. 22A to 22C differs from the semiconductor device shown in FIGS. 1A to 1D in that a sealing portion 265 is formed so as to surround a plurality of transistors 200.
- a semiconductor device 500 has a plurality of transistors 200 and a plurality of opening regions 400 arranged in a matrix.
- a plurality of conductors 260 that function as gate electrodes of the transistor 200 are provided extending in the y-axis direction.
- Open region 400 is formed in a region that does not overlap oxide 230 and conductor 260 .
- a sealing portion 265 is formed to surround the plurality of transistors 200 , the plurality of conductors 260 and the plurality of opening regions 400 .
- the number, arrangement, and size of transistors 200, conductors 260, and opening regions 400 are not limited to the structure shown in FIG.
- the sealing portion 265 is provided so as to surround the plurality of transistors 200, the insulators 216, the insulators 222, the insulators 275, the insulators 280, and the insulators 282.
- insulator 283 is provided to cover insulator 216 , insulator 222 , insulator 275 , insulator 280 , and insulator 282 .
- the insulator 283 is in contact with the upper surface of the insulator 214 .
- An insulator 274 is provided between the insulator 283 and the insulator 285 over the sealing portion 265 .
- the top surface of the insulator 274 is approximately level with the top surface of the insulator 283 .
- an insulator similar to the insulator 280 can be used.
- the plurality of transistors 200 can be wrapped with the insulators 283 , 214 and 212 .
- one or more of the insulator 283, the insulator 214, and the insulator 212 preferably function as barrier insulating films against hydrogen. This can prevent hydrogen contained outside the region of the sealing portion 265 from entering the region of the sealing portion 265 .
- the insulator 282 has openings in the opening regions 400 .
- the insulator 280 may have a groove overlapping the opening of the insulator 282.
- the depth of the groove of the insulator 280 should be at least as deep as the upper surface of the insulator 275 is exposed, and for example, it may be about 1/4 or more and 1/2 or less of the maximum film thickness of the insulator 280 .
- the insulator 283 is in contact with the side surfaces of the insulator 282 , the side surfaces of the insulator 280 , and the top surface of the insulator 280 inside the opening region 400 .
- the insulator 274 is partially formed so as to fill the recess formed in the insulator 283 within the opening region 400 .
- the upper surface of the insulator 274 formed in the opening region 400 and the height of the uppermost surface of the insulator 283 may approximately match.
- Heat treatment is performed in a state where the opening region 400 is formed and the insulator 280 is exposed from the opening of the insulator 282 , whereby oxygen contained in the insulator 280 is removed while oxygen is supplied to the oxide 230 . can be diffused out of the open area 400 .
- sufficient oxygen and an excessive amount of oxygen are supplied from the insulator 280 containing oxygen, which is released by heating, to the region functioning as a channel formation region in the oxide semiconductor and the vicinity thereof. You can prevent it from happening.
- hydrogen contained in the insulator 280 can be combined with oxygen and released to the outside through the opening region 400 . Hydrogen combined with oxygen is released as water. Therefore, hydrogen contained in the insulator 280 can be reduced, and entry of hydrogen contained in the insulator 280 into the oxide 230 can be reduced.
- the shape of the opening region 400 in top view is substantially rectangular, but the present invention is not limited to this.
- the top view shape of the open area 400 may be a rectangle, an ellipse, a circle, a rhombus, or a combination thereof.
- the area and arrangement intervals of the opening regions 400 can be appropriately set according to the design of the semiconductor device including the transistor 200 . For example, in a region where the density of the transistors 200 is low, the area of the opening regions 400 may be widened or the arrangement interval of the opening regions 400 may be narrowed. Further, for example, in a region where the density of the transistors 200 is high, the area of the opening regions 400 may be narrowed or the arrangement interval of the opening regions 400 may be widened.
- a novel transistor can be provided according to one embodiment of the present invention.
- a semiconductor device with little variation in transistor characteristics can be provided.
- a semiconductor device with favorable electrical characteristics can be provided.
- a highly reliable semiconductor device can be provided.
- a semiconductor device with high on-state current can be provided.
- a semiconductor device with high field-effect mobility can be provided.
- a semiconductor device with favorable frequency characteristics can be provided.
- a semiconductor device that can be miniaturized or highly integrated can be provided.
- a semiconductor device with low power consumption can be provided.
- Example 1 In this example, one mode of a semiconductor device will be described with reference to FIGS.
- the semiconductor device described in this embodiment mode is an evaluation element (also referred to as a TEG) capable of multipoint measurement.
- FIG. 23 is a circuit diagram of a TEG 900 as an example of a semiconductor device according to one embodiment of the present invention.
- the TEG 900 has a transistor group TRA and a peripheral circuit PC.
- the transistor group TRA has m ⁇ n (m and n are each independently integers of 1 or more) transistors (transistors Tr[1,1] to Tr[m,n] shown in FIG. 23).
- the peripheral circuit PC includes two multiplexers (multiplexer MUXX and multiplexer MUXY), m analog switches (analog switch ASX[1] to analog switch ASX[m]), and n analog switches (analog switch ASY[1 ] to analog switches ASY[n]).
- an analog switch is an electronic component that switches an analog signal between on and off in accordance with an input control signal.
- the control signal indicates a digital potential (binary voltage condition)
- the analog signal indicates an analog potential (binary or higher voltage condition).
- Analog switches are also called transmission gates.
- the TEG 900 is also electrically connected to the wiring WX, the wiring WY, the wiring DL, the wiring TGL, the wiring BGL, and the wiring SL.
- the wiring WX is electrically connected to the multiplexer MUXX. Also, the wiring WY is electrically connected to the multiplexer MUXY.
- the wiring BGL is electrically connected to the second gates of the transistors Tr[1,1] to Tr[m,n].
- the wiring SL is electrically connected to one of the source and the drain of each of the transistors Tr[1,1] to Tr[m,n].
- the TEG 900 does not have the wiring BGL.
- the transistors Tr[1,1] to Tr[m,n] are single-gate transistors, that is, transistors without a second gate, the TEG 900 does not need to have the wiring BGL. .
- a control signal used in the multiplexer MUXX is supplied to the wiring WX.
- a control signal used in the multiplexer MUXY is supplied to the wiring WY.
- a first terminal of each of the analog switches ASX[1] to ASX[m] is electrically connected to the multiplexer MUXX.
- a second terminal of each of the analog switches ASX[1] to ASX[m] is electrically connected to the wiring DL.
- the third terminal of the analog switch ASX[i] (i is an integer of 1 or more and m or less) is electrically connected to the other of the source and drain of each of the transistors Tr[i,1] to Tr[i,n]. properly connected.
- the multiplexer MUXX has a function of controlling on/off of each of the analog switches ASX[1] to ASX[m]. Specifically, the multiplexer MUXX has a function of turning on any one of the m analog switches ASX or turning off all the analog switches ASX based on the control signal received from the wiring WX. have. For example, when the potential of the signal supplied from the multiplexer MUXX is high level, the analog switch ASX is turned off, and when the potential of the signal supplied from the multiplexer MUXX is low level, the analog switch ASX is turned on.
- a first terminal of each of the analog switches ASY[1] to ASY[n] is electrically connected to the multiplexer MUXY.
- a second terminal of each of the analog switches ASY[1] to ASY[n] is electrically connected to the wiring TGL.
- the third terminal of the analog switch ASY[j] (j is an integer of 1 or more and n or less) is electrically connected to the first gates of the transistors Tr[j,1] to Tr[j,n]. It is connected to the.
- the multiplexer MUXY has a function of controlling on/off of each of the analog switches ASY[1] to ASY[n]. Specifically, the multiplexer MUXY has a function of turning on any one of the n analog switches ASY or turning off all the analog switches ASY based on the control signal received from the wiring WY. have. For example, when the potential of the signal supplied from the multiplexer MUXY is at high level, the analog switch ASY is turned on, and when the potential of the signal supplied from the multiplexer MUXY is at low level, the analog switch ASY is turned off.
- the analog switch ASY when the potential of the signal supplied from the multiplexer MUXY is at high level, the analog switch ASY is turned off, and when the potential of the signal supplied from the multiplexer MUXY is at low level, the analog switch ASY is turned on.
- the analog switch ASY[j] When the analog switch ASY[j] is on, the wiring TGL and the first gates of the transistors Tr[1,j] to Tr[m,j] are brought into conduction. At this time, the potential of the wiring DL is supplied to the first gates of the transistors Tr[1,j] to Tr[n,j].
- the TEG 900 shown in FIG. 23 it is possible to select the transistor to be measured from among the m ⁇ n transistors and measure the electrical characteristics.
- the TEG 900 can be said to be a TEG capable of multi-point measurement.
- the multiplexer MUXX, the multiplexer MUXY, the analog switch ASX, and the analog switch ASY are each preferably independently composed of a CMOS (Complementary Metal Oxide Semiconductor) circuit or a unipolar circuit. and the analog switch ASY are more preferably composed of a CMOS circuit or a unipolar circuit.
- CMOS Complementary Metal Oxide Semiconductor
- the layer including the peripheral circuit PC and the layer including the transistor group TRA are laminated.
- FIG. 24A A perspective view of the TEG 900 is shown in FIG. 24A.
- TEG 900 has layers 910 and 920 .
- FIG. 24B is a perspective view for explaining the configuration of the TEG 900, showing layers 910 and 920 separately.
- a layer 910 has a peripheral circuit PC.
- layer 910 has multiplexers MUXX, multiplexers MUXY, analog switches ASX, and analog switches ASY.
- Layer 920 also includes transistor group TRA.
- the layer 910 may be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like alone or in combination.
- silicon, germanium, or the like can be used as the semiconductor material.
- Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.
- a transistor including silicon in a channel formation region is sometimes called a Si transistor.
- gallium arsenide aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, etc., which are applicable to HEMTs (High Electron Mobility Transistors) may be used.
- HEMTs High Electron Mobility Transistors
- the layer 920 may be provided using a semiconductor material capable of forming a thin film, such as an oxide semiconductor or silicon.
- a semiconductor material capable of forming a thin film such as an oxide semiconductor or silicon.
- the layer 920 may be formed over another substrate and attached to the layer 910 .
- the peripheral circuit PC is configured with a CMOS circuit
- the transistor group TRA is configured with the transistor 200 described in the first embodiment.
- the peripheral circuit PC is composed of Si transistors
- the transistor group TRA is composed of OS transistors. Since the layer containing the Si transistor and the layer containing the OS transistor can be monolithically formed, this configuration can shorten the wiring that connects the peripheral circuit and the OS transistor, and the electrical characteristics of the plurality of OS transistors can be shortened. (Turn Around Time). In addition, the pitch width between the OS transistors can be narrowed.
- the peripheral circuit PC and the transistor group TRA are configured with the transistor 200 described in the first embodiment.
- the peripheral circuit PC and the transistor group TRA are composed of OS transistors. Note that layers including an OS transistor can be stacked. Therefore, by stacking a layer including an OS transistor used in the peripheral circuit PC and a layer including an OS transistor used in the transistor group TRA, the wiring connecting the peripheral circuit and the OS transistor can be shortened, and a plurality of OS transistors can be formed. The electrical characteristics of the transistor can be measured with a short TAT. In addition, the pitch width between the OS transistors can be narrowed.
- the peripheral circuit PC and the transistor group TRA may be divided into three or more layers.
- some of the plurality of transistors included in the peripheral circuit PC may be composed of Si transistors, all other of the plurality of transistors included in the peripheral circuit PC may be composed of OS transistors, and the transistor group TRA may be composed of OS transistors.
- the TEG 900 may have a layer including a Si transistor, a first layer including an OS transistor on the layer, and a second layer including an OS transistor on the first layer.
- the OS transistors included in the first layer are preferably used as all of the plurality of transistors included in the peripheral circuit PC, and the OS transistors included in the second layer are preferably used as the transistor group TRA. With this configuration, the area occupied by the TEG 900 can be further reduced.
- peripheral circuit PC and the transistor group TRA may be formed in the same layer.
- FIG. 25A is also a diagram explaining the layout of the transistor group TRA shown in FIG.
- FIG. 25A shows transistor Tr[i,j], transistor Tr[i,j+1], transistor Tr[i+1,j], and transistor Tr[i+1,j+1] of the transistor group TRA shown in FIG. ing. Note that some elements are omitted in the top view of FIG. 25A for clarity of illustration.
- the oxide OS is a metal oxide including a channel formation region. Note that in FIG. 25A, the oxide OS included in the transistor is separated from the oxide OS included in the transistor adjacent to the transistor in the channel length direction. In addition, the oxide OS included in the transistor is separated from the oxide OS included in the transistor adjacent to the transistor in the channel width direction.
- the conductor VIA functions as a wiring or plug.
- Conductor VIA is electrically connected to the source or drain of the transistor and conductor WIR1 or conductor WIR2.
- the conductor VIA connected to one of the source and drain of transistor Tr[i,j] is connected to conductor WIR1[i], and the source and drain of transistor Tr[i,j] are connected. is connected to the conductor WIR2[i].
- the conductor TGE functions as the first gate of the transistor.
- the conductor TGE[j] has a region that overlaps with the oxide OS included in each of the transistor Tr[i,j] and the transistor Tr[i+1,j].
- the conductor TGE[j+1] has a region that overlaps with the oxide OS included in each of the transistor Tr[i, j+1] and the transistor Tr[i+1, j+1].
- the conductor BGE functions as the second gate of the transistor.
- the conductor BGE[j] has a region that overlaps with the oxide OS included in each of the transistor Tr[i,j] and the transistor Tr[i+1,j].
- the conductor BGE[j+1] has a region that overlaps with the oxide OS included in each of the transistor Tr[i,j+1] and the transistor Tr[i+1,j+1].
- the conductor BGE[j] has a region overlapping with the conductor TGE[j] with the oxide OS included in each of the transistors Tr[i,j] and Tr[i+1,j] interposed therebetween.
- the conductor BGE[j+1] has a region overlapping with the conductor TGE[j+1] with the oxide OS included in each of the transistors Tr[i, j+1] and Tr[i+1, j+1] interposed therebetween.
- conductor WIR1 functions as wiring.
- conductor WIR1[i] is electrically connected to one of the source and drain of each of transistor Tr[i,j] and transistor Tr[i,j+1] through conductor VIA.
- conductor WIR1[i+1] is electrically connected to one of the source and drain of transistor Tr[i+1,j] and transistor Tr[i+1,j+1] through conductor VIA.
- conductor WIR2 functions as wiring.
- conductor WIR2[i] is electrically connected to the other of the source and drain of transistor Tr[i,j] and transistor Tr[i,j+1] through conductor VIA.
- conductor WIR2[i+1] is electrically connected to the other of the source and drain of transistor Tr[i+1,j] and transistor Tr[i+1,j+1] through conductor VIA.
- the transistor 200 described in Embodiment 1 can be applied as the transistor Tr.
- the oxide OS corresponds to the oxide 230 described in Embodiment 1
- the conductor TGE corresponds to the conductor 260 described in Embodiment 1
- the conductor BGE corresponds to corresponds to the conductor 205 described in
- the conductor VIA corresponds to the conductor 240 described in the first embodiment.
- the conductor WIR1 corresponds to one of the conductors 246a and 246b described in Embodiment 1
- the conductor WIR2 corresponds to the other of the conductors 246a and 246b described in Embodiment 1. corresponds to
- the conductor WIR2[i] corresponds to the wiring electrically connected to the analog switch ASX[i]
- the conductor WIR1[i] corresponds to the wiring SL or the wiring electrically connected to the wiring SL. .
- the configuration example of the transistor group TRA included in the TEG 900 is not limited to the above. Another example of the transistor group TRA included in the TEG 900 will be described with reference to FIGS. 25B, 26A, 26B, 27A, 27B, 28A, and 28B. In addition, in each figure, some elements are omitted for clarity of the figure.
- FIG. 25B is another example of a top view of part of the transistor group TRA of the TEG 900.
- FIG. FIG. 25B is also a diagram for explaining the layout of the transistor group TRA shown in FIG.
- FIG. 25B shows transistors Tr[i,j] to Tr[i,j+2] and transistors Tr[i+1,j] to Tr[i+1,j+2] of the transistor group TRA shown in FIG. showing.
- the transistor group TRA shown in FIG. 25B differs from the transistor group TRA shown in FIG. 25A in the configuration or shape of the oxide OS.
- the oxide OS extends in the channel length direction of the transistor. Therefore, part or all of the plurality of transistors arranged in the channel length direction of the transistors share one oxide OS. For example, channels of the transistors Tr[i, j] to Tr[i, j+2] are formed in one oxide OS. Similarly, for example, channels of the transistors Tr[i+1,j] to Tr[i+1,j+2] are formed in one oxide OS different from the oxide OS.
- the source or drain of a transistor also serves as the source or drain of a transistor adjacent to the transistor in the channel length direction.
- one of the source and drain of the transistor Tr[i, j+1] serves as one of the source and drain of the transistor Tr[i, j].
- the other of the source and drain of the transistor Tr[i, j+1] also serves as the other of the source and drain of the transistor Tr[i, j+2].
- a conductor VIA connected to the source or drain of a transistor is also connected to the source or drain of a transistor adjacent to the transistor in the channel length direction.
- a conductor VIA connected to one of the source and drain of transistor Tr[i,j+1] is connected to one of the source and drain of transistor Tr[i,j] and conductor WIR1[i].
- a conductor VIA connected to the other of the source and drain of the transistor Tr[i, j+1] is connected to the other of the source and drain of the transistor Tr[i, j+2] and the conductor WIR2[i].
- the conductor TGE[j+2] has a region overlapping with the oxide OS included in each of the transistor Tr[i, j+2] and the transistor Tr[i+1, j+2].
- the conductor BGE[j+2] has a region that overlaps with the oxide OS included in each of the transistor Tr[i, j+2] and the transistor Tr[i+1, j+2].
- the density of transistors in the transistor group TRA can be increased. Therefore, high integration of the semiconductor device can be achieved.
- FIG. 26A is another example of a top view of part of the transistor group TRA of the TEG 900.
- FIG. FIG. 26A is also a diagram explaining the layout of the transistor group TRA shown in FIG.
- FIG. 26A shows transistor Tr[i,j], transistor Tr[i,j+1], transistor Tr[i+1,j], and transistor Tr[i+1,j+1] of the transistor group TRA shown in FIG. ing.
- the transistor group TRA shown in FIG. 26A differs from the transistor group TRA shown in FIG. 25A in having an oxide OSD.
- an oxide OSD is arranged between two oxide OSs adjacent in the channel width direction of the transistor.
- Oxide OSD is not electrically connected to conductor WIR1 and conductor WIR2.
- the oxide OS and oxide OSD are formed from the same oxide film. Therefore, the oxide OS and the oxide OSD are formed using the same material. In other words, the element forming the oxide OS and the element forming the oxide OSD are the same.
- the oxide OSD shown in FIG. 26A has the same shape as the oxide OS shown in FIG. 26A, it is not limited to this.
- the oxide OSD may have a rectangular, elliptical, circular, rhombic, or substantially rectangular shape, or may have a shape extending in the channel length direction of the transistor like the oxide OS shown in FIG. 25B. , or a combination thereof.
- the oxide OSD By arranging the oxide OSD, it is possible to adjust the pattern density of the oxide formed by processing the oxide film. By adjusting the pattern density, it is possible to suppress the loading effect that changes the etching rate and etching shape.
- the pattern density is defined as the area ratio of formed structures in an arbitrary region. For example, if an oxide film is formed on the entire surface of an arbitrary region, the pattern density will be 100%. On the other hand, when part of the oxide film is removed to form a plurality of oxides, the pattern density of the oxide can be obtained by dividing the area of the remaining oxides by the area of any region.
- part of oxygen added to the oxide OS in manufacturing the transistor is added to the oxide OSD. That is, the amount of oxygen added to the oxide OS can be controlled by adjusting the size of the oxide OSD, the number of the oxide OSDs, and the like. Accordingly, oxygen vacancies and VOH in the channel formation region of the oxide OS can be reduced, and excessive oxidation of the source and drain can be suppressed. Therefore, electrical characteristics of the transistor can be improved and reliability can be improved.
- the oxide OSD has a region overlapping with the conductor WIR1 and a region overlapping with the conductor WIR2. With such a structure, high integration of the semiconductor device can be achieved. Note that the oxide OSD does not have to overlap with the conductor WIR1 or the conductor WIR2.
- FIG. 26B is another example of a top view of part of the transistor group TRA of the TEG 900.
- FIG. FIG. 26B is also a diagram for explaining the layout of the transistor group TRA shown in FIG.
- FIG. 26B shows transistors Tr[i,j] to Tr[i,j+2] and transistors Tr[i+1,j] to Tr[i+1,j+2] of the transistor group TRA shown in FIG. showing.
- the transistor group TRA shown in FIG. 26B differs from the transistor group TRA shown in FIG. 25B in that it has an oxide OSD. Further, the transistor group TRA shown in FIG. 26B is different from the transistor group TRA shown in FIG. 26A in the configuration or shape of the oxide OS and the oxide OSD.
- oxide OSD shown in FIG. 26B has the same shape as the oxide OS shown in FIG. 26B, it is not limited to this.
- the oxide OSD may be rectangular, elliptical, circular, diamond-shaped, substantially rectangular, or a combination of these shapes.
- FIG. 27A is another example of a top view of part of the transistor group TRA of the TEG 900.
- FIG. FIG. 27A is also a diagram for explaining the layout of the transistor group TRA shown in FIG. 27A shows transistor Tr[i,j], transistor Tr[i,j+1], transistor Tr[i+1,j], transistor Tr[i+1,j+1], and transistor Tr[in the transistor group TRA shown in FIG. i+2,j] and transistor Tr[i+2,j+1].
- the transistor group TRA shown in FIG. 27A differs from the transistor group TRA shown in FIG. 25A in the configuration or shape of the conductor WIR2.
- the conductor WIR2[i] is the other of the source and drain of the transistor Tr[i,j] and the transistor Tr[i,j+1], as well as the transistor Tr[i+1,j] and the transistor Tr[i,j+1].
- the other of the source and drain of each Tr[i+1,j+1] is also electrically connected. That is, the conductor WIR2[i] also serves as the conductor WIR2[i+1].
- the interval between transistors adjacent to each other in the channel width direction of the transistors can be narrowed. Therefore, high integration of the semiconductor device can be achieved.
- FIG. 27B is another example of a top view of part of the transistor group TRA of the TEG 900.
- FIG. FIG. 27B is also a diagram for explaining the layout of the transistor group TRA shown in FIG. 27B shows transistors Tr[i, j] to Tr[i, j+2], transistors Tr[i+1, j] to Tr[i+1, j+2], and transistors Tr[i+2,j] through transistor Tr[i+2,j+2] are shown.
- the transistor group TRA shown in FIG. 27B differs from the transistor group TRA shown in FIG. 25B in the configuration or shape of the conductor WIR2. Further, the transistor group TRA shown in FIG. 27B is different from the transistor group TRA shown in FIG. 27A in the configuration or shape of the oxide OS.
- FIG. 28A is another example of a top view of part of the transistor group TRA of the TEG 900.
- FIG. FIG. 28A is also a diagram for explaining the layout of the transistor group TRA shown in FIG. 28A shows transistor Tr[i,j], transistor Tr[i,j+1], transistor Tr[i+1,j], transistor Tr[i+1,j+1], and transistor Tr[in the transistor group TRA shown in FIG. i+2,j] and transistor Tr[i+2,j+1].
- the transistor group TRA shown in FIG. 28A differs from the transistor group TRA shown in FIG. 27A in having an oxide OSD.
- FIG. 28B is another example of a top view of part of the transistor group TRA of the TEG 900.
- FIG. FIG. 28B is also a diagram for explaining the layout of the transistor group TRA shown in FIG.
- FIG. 28B shows transistors Tr[i,j] to Tr[i,j+2], transistors Tr[i+1,j] to Tr[i+1,j+2], and transistors Tr[i+2,j] through transistor Tr[i+2,j+2] are shown.
- the transistor group TRA shown in FIG. 28B differs from the transistor group TRA shown in FIG. 27B in having an oxide OSD. Further, the transistor group TRA shown in FIG. 28B is different from the transistor group TRA shown in FIG. 28A in the configuration or shape of the oxide OS and the oxide OSD.
- FIG. 26B For the details of the structure or shape of the oxide OS and the oxide OSD included in the transistor group TRA illustrated in FIG. 28B, the description using FIG. 26B can be referred to.
- FIG. 1 An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.
- the transistor 200 is provided above the transistor 300 and the capacitor 100 is provided above the transistors 300 and 200 .
- the transistor 200 described in the above embodiment can be used as the transistor 200 .
- a transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.
- a wiring 1001 is electrically connected to the source of the transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300.
- a wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
- the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. .
- the memory device shown in FIG. 29 can form a memory cell array by being arranged in a matrix.
- Transistor 300 is provided on substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 consisting of part of substrate 311, and a low region functioning as a source or drain region. It has a resistance region 314a and a low resistance region 314b. Transistor 300 can be either p-channel or n-channel.
- the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
- a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween.
- the conductor 316 may be made of a material that adjusts the work function.
- Such a transistor 300 is also called a FIN transistor because it utilizes the projections of the semiconductor substrate.
- an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion.
- a semiconductor film having a convex shape may be formed by processing an SOI substrate.
- transistor 300 illustrated in FIG. 29 is only an example, and the structure is not limited, and an appropriate transistor may be used depending on the circuit configuration or driving method.
- the capacitor 100 is provided above the transistor 200 .
- the capacitor 100 has a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.
- an insulator that can be used as the insulator 283 described in the above embodiment is preferably used.
- the conductor 112 provided over the conductor 240 and the conductor 110 can be formed at the same time.
- the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100 , the transistor 200 , or the transistor 300 .
- the conductor 112 and the conductor 110 have a single-layer structure in FIG. 29, they are not limited to this structure, and may have a laminated structure of two or more layers. For example, between a conductor with a barrier property and a conductor with high conductivity, a conductor with a barrier property and a conductor with high adhesion to the conductor with high conductivity may be formed.
- the insulator 130 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. etc., and can be provided as a laminate or a single layer.
- the insulator 130 preferably has a laminated structure of a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material.
- the capacitive element 100 includes an insulator with a high dielectric constant (high-k), so that a sufficient capacitance can be secured, and an insulator with a high dielectric strength improves the dielectric strength and increases the capacitance. Electrostatic breakdown of the element 100 can be suppressed.
- high dielectric constant (high-k) materials examples include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, silicon and There are oxides with hafnium, oxynitrides with silicon and hafnium, or nitrides with silicon and hafnium.
- materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and nitrogen. There are added silicon oxide, silicon oxide with holes, resin, and the like.
- a wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures.
- the wiring layer can be provided in a plurality of layers depending on the design.
- a plurality of structures may be grouped together and given the same reference numerals.
- the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as a wiring and a part of the conductor functions as a plug.
- an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300 as interlayer films.
- conductors 328, 330, and the like electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326, respectively. Note that the conductors 328 and 330 function as plugs or wirings.
- the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape thereunder.
- the top surface of the insulator 322 may be planarized by a chemical mechanical polishing (CMP) method or the like to improve planarity.
- CMP chemical mechanical polishing
- a wiring layer may be provided over the insulator 326 and the conductor 330 .
- an insulator 350, an insulator 352, and an insulator 354 are stacked in this order.
- a conductor 356 is formed over the insulators 350 , 352 , and 354 .
- Conductor 356 functions as a plug or wiring.
- the insulator 210 , the insulator 212 , the insulator 214 , and the insulator 216 are embedded with conductors 218 , conductors forming the transistor 200 (conductors 205 ), and the like. Note that the conductor 218 functions as a plug or wiring that is electrically connected to the capacitor 100 or the transistor 300 . Further, an insulator 150 is provided over the conductor 120 and the insulator 130 .
- an insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug.
- the insulator 217 is provided in contact with inner walls of openings formed in the insulators 210 , 212 , 214 , and 216 . That is, the insulator 217 is provided between the conductor 218 and the insulators 210 , 212 , 214 , and 216 . Note that since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 is formed in contact with the side surface of the conductor 205 in some cases.
- an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride may be used. Since the insulator 217 is provided in contact with the insulator 210 , the insulator 212 , the insulator 214 , and the insulator 222 , impurities such as water or hydrogen from the insulator 210 or the insulator 216 are oxidized through the conductor 218 . It is possible to suppress mixing into the object 230 .
- silicon nitride is suitable because it has a high blocking property against hydrogen.
- oxygen contained in the insulator 210 or the insulator 216 can be prevented from being absorbed by the conductor 218 .
- the insulator 217 can be formed by a method similar to that of the insulator 241 .
- a PEALD method may be used to form a silicon nitride film, and anisotropic etching may be used to form an opening reaching the conductor 356 .
- Insulators that can be used as interlayer films include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.
- the material should be selected according to the function of the insulator.
- the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like preferably have an insulator with a low dielectric constant.
- the insulator preferably contains silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, resin, or the like.
- the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. and resin.
- silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained.
- resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
- an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used for the insulators 214, 212, 350, and the like.
- Examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or stacks.
- an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
- a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
- Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium. , ruthenium and the like can be used.
- a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
- the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like are metal materials, alloy materials, metal nitride materials, metal oxide materials, or the like formed of any of the above materials.
- conductive materials can be used in a single layer or in lamination. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.
- an insulator having an excess oxygen region is provided near the oxide semiconductor in some cases.
- an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
- the insulator 241 may be provided between the insulator 280 containing excess oxygen and the conductor 240 .
- the transistor 200 can be sealed with an insulator having a barrier property.
- the provision of the insulator 241 can suppress excess oxygen in the insulator 280 from being absorbed by the conductor 240 .
- the presence of the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240 .
- an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used as the insulator 241 .
- silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like is preferably used.
- silicon nitride is preferable because it has a high blocking property against hydrogen.
- metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can also be used.
- the transistor 200 may be sealed with the insulator 212, the insulator 214, the insulator 282, and the insulator 283 as described in the above embodiment. With such a structure, entry of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like can be reduced.
- the conductor 240 penetrates through the insulators 283 and 282, and the conductor 218 penetrates through the insulators 214 and 212.
- the insulator 241 is in contact with the conductor 240.
- An insulator 217 is provided in contact with the conductor 218 . Accordingly, hydrogen entering inside the insulators 212 , 214 , 282 , and 283 through the conductors 240 and 218 can be reduced.
- the transistor 200 is sealed with the insulator 212, the insulator 214, the insulator 282, the insulator 283, the insulator 241, and the insulator 217, and impurities such as hydrogen contained in the insulator 274 and the like are removed from the outside. It is possible to reduce contamination from
- dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) provided when taking out a plurality of semiconductor devices in the form of chips by dividing a large-area substrate into individual semiconductor elements will be described.
- a dividing method for example, grooves (dicing lines) for dividing the semiconductor elements are first formed in the substrate, and then cut along the dicing lines to divide (divide) into a plurality of semiconductor devices.
- the region where the insulator 283 and the insulator 214 are in contact overlaps the dicing line. That is, openings are provided in the insulator 282 , the insulator 280 , the insulator 275 , the insulator 222 , and the insulator 216 in the vicinity of the dicing line region provided at the outer edge of the memory cell having the plurality of transistors 200 .
- the insulator 214 and the insulator 283 are in contact with each other in the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216.
- openings may be provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214.
- the insulator 212 and the insulator 283 are in contact with each other in the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214.
- the insulator 212 and the insulator 283 may be formed using the same material and the same method. By providing the insulator 212 and the insulator 283 using the same material and the same method, adhesion can be improved. For example, it is preferable to use silicon nitride.
- the insulator 212 , the insulator 214 , the insulator 282 , and the insulator 283 can wrap the transistor 200 .
- At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water; therefore, the semiconductor element described in this embodiment is formed.
- this structure can prevent excess oxygen in the insulators 280 and 224 from diffusing to the outside.
- excess oxygen in insulator 280 and insulator 224 is effectively supplied to the oxide in which the channel in transistor 200 is formed.
- Oxygen vacancies in the oxide in which a channel is formed in the transistor 200 can be reduced by the oxygen.
- the oxide in which the channel of the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, it is possible to suppress variations in the electrical characteristics of the transistor 200 and improve its reliability.
- the shape of the capacitive element 100 is a planar type, but the storage device shown in this embodiment is not limited to this.
- the shape of capacitive element 100 may be cylindrical. Note that the configuration of the memory device shown in FIG. 30 below the insulator 150 is similar to that of the semiconductor device shown in FIG.
- Capacitor element 100 shown in FIG. an insulator 145 over the conductor 115 and the insulator 142 , a conductor 125 over the insulator 145 , and an insulator 152 over the conductor 125 and the insulator 145 .
- conductor 115 , insulator 145 , and conductor 125 are placed in openings formed in insulator 150 and insulator 142 .
- the conductor 115 functions as the lower electrode of the capacitor 100
- the conductor 125 functions as the upper electrode of the capacitor 100
- the insulator 145 functions as the dielectric of the capacitor 100 .
- the capacitive element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched therebetween not only on the bottom surface but also on the side surfaces in the openings of the insulator 150 and the insulator 142. Capacity can be increased. Therefore, the capacitance of the capacitive element 100 can be increased as the depth of the opening is increased. By increasing the capacitance per unit area of the capacitive element 100 in this manner, miniaturization or high integration of the semiconductor device can be promoted.
- An insulator that can be used for the insulator 280 may be used for the insulator 152 .
- the insulator 142 preferably functions as an etching stopper when the opening of the insulator 150 is formed, and an insulator that can be used for the insulator 214 may be used.
- the shape of the openings formed in the insulators 150 and 142 when viewed from above may be a quadrangle, a polygonal shape other than a quadrangle, or a polygonal shape with curved corners. , or a circular shape including an ellipse.
- the conductor 115 is arranged in contact with openings formed in the insulator 142 and the insulator 150 .
- the top surface of the conductor 115 substantially coincides with the top surface of the insulator 142 .
- the lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130 .
- the conductor 115 is preferably formed by an ALD method, a CVD method, or the like.
- a conductor that can be used for the conductor 205 may be used.
- the insulator 145 is arranged to cover the conductor 115 and the insulator 142 .
- the insulator 145 is preferably formed by an ALD method, a CVD method, or the like.
- the insulator 145 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, nitridation. Hafnium or the like may be used, and a stacked layer or a single layer can be provided.
- an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used.
- a material with high dielectric strength such as silicon oxynitride or a high dielectric constant (high-k) material for the insulator 145 .
- a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.
- high dielectric constant (high-k) materials examples include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, silicon and There are oxides with hafnium, oxynitrides with silicon and hafnium, nitrides with silicon and hafnium, and the like.
- high-k materials gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, silicon and There are oxides with hafnium, oxynitrides with silicon and hafnium, nitrides with silicon and hafnium, and the like.
- materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. silicon oxide, resin, etc.
- silicon nitride (SiN x ) deposited using the PEALD method silicon oxide (SiO x ) deposited using the PEALD method, and silicon nitride (SiN x ) deposited using the PEALD method are stacked in this order. can be used.
- an insulating film in which zirconium oxide, silicon oxide deposited by an ALD method, and zirconium oxide are stacked in this order can be used.
- an insulator with high dielectric strength dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.
- the conductor 125 is arranged so as to fill the openings formed in the insulator 142 and the insulator 150 .
- the conductor 125 is electrically connected to the wiring 1005 through the conductors 140 and 153 .
- the conductor 125 is preferably formed by an ALD method, a CVD method, or the like.
- a conductor that can be used for the conductor 205 may be used.
- the conductor 153 is provided on the insulator 154 and covered with the insulator 156 .
- a conductor that can be used for the conductor 112 may be used for the conductor 153
- an insulator that can be used for the insulator 152 may be used for the insulator 156 .
- the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100 , the transistor 200 , or the transistor 300 .
- FIG. 2 An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.
- FIG. 31 is a cross-sectional view of a semiconductor device having a memory device 290.
- the memory device 290 shown in FIG. 31 has a capacitive device 292 in addition to the transistor 200 shown in FIGS. 1A-1D.
- FIG. 31 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.
- the capacitor device 292 includes a conductor 242b, an insulator 271b provided over the conductor 242b, and an insulator 275 provided in contact with the top surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b. , and a conductor 294 on insulator 275 . That is, the capacitive device 292 constitutes an MIM (Metal-Insulator-Metal) capacity. Note that one of the pair of electrodes included in the capacitor device 292, that is, the conductor 242b can also serve as the source electrode of the transistor.
- MIM Metal-Insulator-Metal
- the dielectric layer included in the capacitive device 292 can also serve as protective layers provided for the transistor, that is, the insulator 271 and the insulator 275 . Therefore, part of the manufacturing process of the transistor can be shared in the manufacturing process of the capacitor device 292, so that the semiconductor device can be manufactured with high productivity. In addition, since one of the pair of electrodes of the capacitor device 292, that is, the conductor 242b also serves as the source electrode of the transistor, the area where the transistor and the capacitor device are arranged can be reduced.
- conductor 294 for example, a material that can be used for the conductor 242 may be used.
- ⁇ Modified example of memory device> 32A, 32B, and 33 a semiconductor including a transistor 200 and a capacitor device 292 according to one embodiment of the present invention, which is different from that described in ⁇ Structure example of memory device>
- An example of the device will be described. Note that in the semiconductor devices shown in FIGS. 32A, 32B, and 33, a structure having the same function as the structure constituting the semiconductor device (see FIG. 31) shown in the previous embodiment and ⁇ Structure Example of Memory Device> is used. are marked with the same reference numerals. Note that in this item, the materials described in detail in the above embodiments and ⁇ Structure Example of Memory Device> can be used as materials for forming the transistor 200 and the capacitor device 292 . Also, in FIGS. 32A, 32B, 33, etc., the memory device shown in FIG. 31 is used as the memory device, but it is not limited to this.
- FIG. 32A is a cross-sectional view along the channel length of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitive device 292a, and a capacitive device 292b.
- the capacitive device 292a includes the conductor 242a, the insulator 271a on the conductor 242a, the insulator 275 in contact with the top surface of the insulator 271a, the side surface of the insulator 271a, and the side surface of the conductor 242a, and the insulator 271a.
- the capacitive device 292b includes a conductor 242b, an insulator 271b on the conductor 242b, an insulator 275 in contact with the top surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and the insulator 275b. and an upper conductor 294b.
- the semiconductor device 600 has a symmetrical configuration with the dashed-dotted line A3-A4 as the axis of symmetry.
- the conductor 242c serves also as one of the source electrode and the drain electrode of the transistor 200a and one of the source electrode and the drain electrode of the transistor 200b.
- an insulator 271c is provided over the conductor 242c.
- the conductor 240 functioning as a plug also serves as connection between the conductor 246 functioning as a wiring and the transistor 200a and connection between the conductor 246 functioning as a wiring and the transistor 200b. In this way, by configuring the two transistors, the two capacitive devices, and the connection between the wiring and the plug as described above, it is possible to provide a semiconductor device that can be miniaturized or highly integrated.
- the configuration example of the semiconductor device illustrated in FIG. 31 can be referred to for the configuration and effect of each of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b.
- the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b are given as examples of the structure of the semiconductor device above, the semiconductor device described in this embodiment is not limited thereto.
- a semiconductor device 600 and a semiconductor device having a configuration similar to that of the semiconductor device 600 may be connected via a capacitor.
- a semiconductor device having transistor 200a, transistor 200b, capacitive device 292a, and capacitive device 292b is referred to herein as a cell.
- the above description of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b can be referred to.
- FIG. 32B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitive device 292a, and a capacitive device 292b, and a cell having a configuration similar to that of the semiconductor device 600 are connected via a capacitive portion.
- a conductor 294b functioning as one electrode of a capacitive device 292b included in the semiconductor device 600 also serves as one electrode of a capacitive device included in a semiconductor device 601 having the same configuration as the semiconductor device 600. It has become. Also, although not shown, the conductor 294a functioning as one electrode of the capacitive device 292a of the semiconductor device 600 is located on the left side of the semiconductor device 600, that is, in FIG. Also serves as an electrode. The right side of the semiconductor device 601, that is, the cells in the A2 direction in FIG. 32B have the same configuration. That is, a cell array (also called a memory device layer) can be constructed.
- the interval between adjacent cells can be reduced, so that the projected area of the cell array can be reduced and high integration can be achieved.
- a matrix cell array By arranging the cell array shown in FIG. 32B in a matrix, a matrix cell array can be formed.
- the cell area can be reduced and a semiconductor device having a cell array can be miniaturized or sophisticated. Integration can be achieved.
- FIG. 33 shows a sectional view of a configuration in which n layers of cell arrays 610 are stacked. As shown in FIG. 33, by stacking a plurality of cell arrays (cell arrays 610_1 to 610_n), cells can be integrated and arranged without increasing the area occupied by the cell arrays. That is, a 3D cell array can be configured.
- FIGS. 34A, 34B, and 35A to 35H are used to describe a transistor using an oxide as a semiconductor (hereinafter also referred to as an OS transistor) according to one embodiment of the present invention, and A memory device to which a capacitor is applied (hereinafter sometimes referred to as an OS memory device) will be described.
- An OS memory device is a memory device that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.
- FIG. 34A shows an example of the configuration of the OS memory device.
- a memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470 .
- Peripheral circuitry 1411 includes row circuitry 1420 , column circuitry 1430 , output circuitry 1440 and control logic circuitry 1460 .
- the column circuit 1430 has, for example, a column decoder, precharge circuit, sense amplifier, write circuit, and the like.
- the precharge circuit has a function of precharging the wiring.
- a sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wirings are wirings connected to memory cells included in the memory cell array 1470, and will be described later in detail.
- the amplified data signal is output to the outside of memory device 1400 via output circuit 1440 as data signal RDATA.
- the row circuit 1420 has, for example, a row decoder, a word line driver circuit, etc., and can select a row to be accessed.
- the storage device 1400 is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as power supply voltages.
- Control signals (CE, WE, RES), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
- the address signal ADDR is input to the row and column decoders, and the data signal WDATA is input to the write circuit.
- the control logic circuit 1460 processes externally input control signals (CE, WE, RES) to generate control signals for the row decoder and column decoder.
- Control signal CE is a chip enable signal
- control signal WE is a write enable signal
- control signal RES is a read enable signal.
- the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
- the memory cell array 1470 has a plurality of memory cells MC arranged in rows and columns and a plurality of wirings.
- the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, and the like.
- the number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.
- FIG. 34A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this.
- a memory cell array 1470 may be provided so as to overlap with part of the peripheral circuit 1411 .
- a structure in which a sense amplifier is provided under the memory cell array 1470 may be employed.
- FIGS. 35A to 35H A configuration example of a memory cell that can be applied to the memory cell MC described above will be described with reference to FIGS. 35A to 35H.
- [DOSRAM] 35A to 35C show circuit configuration examples of memory cells of a DRAM.
- a DRAM using a 1-OS-transistor-1-capacitor-type memory cell is sometimes referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
- a memory cell 1471 illustrated in FIG. 35A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a top gate) and a back gate.
- the transistor M1 has a first terminal connected to the first terminal of the capacitor CA, a second terminal connected to the wiring BIL, a gate connected to the wiring WOL, and a back gate of the transistor M1. are connected to the wiring BGL.
- a second terminal of the capacitive element CA is connected to the wiring LL.
- the wiring BIL functions as a bit line
- the wiring WOL functions as a word line.
- the wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA.
- the wiring LL may be at a ground potential or a low-level potential when writing and reading data.
- the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
- the memory cell 1471 shown in FIG. 35A corresponds to the memory device shown in FIG. That is, the transistor M1 corresponds to the transistor 200 and the capacitive element CA corresponds to the capacitive device 292.
- FIG. 35A corresponds to the memory device shown in FIG. That is, the transistor M1 corresponds to the transistor 200 and the capacitive element CA corresponds to the capacitive device 292.
- the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
- the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, like the memory cell 1472 shown in FIG. 35B.
- the memory cell MC may be a memory cell configured with a single-gate transistor, that is, a transistor M1 that does not have a back gate, like the memory cell 1473 shown in FIG. 35C.
- the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA.
- an OS transistor as the transistor M1
- leakage current of the transistor M1 can be significantly reduced.
- the frequency of refreshing the memory cell can be reduced.
- the refresh operation of the memory cells can be made unnecessary.
- leakage current is very small, multilevel data or analog data can be held in the memory cells 1471, 1472, and 1473.
- the bit line can be shortened. As a result, the bit line capacity is reduced, and the storage capacity of the memory cell can be reduced.
- [NOSRAM] 35D to 35G show a circuit configuration example of a gain cell type memory cell with two transistors and one capacitive element.
- a memory cell 1474 illustrated in FIG. 35D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate.
- NOSRAM Nonvolatile Oxide Semiconductor RAM
- the transistor M2 has a first terminal connected to the first terminal of the capacitor CB, a second terminal connected to the wiring WBL, a gate connected to the wiring WOL, and a back gate of the transistor M2. are connected to the wiring BGL.
- a second terminal of the capacitive element CB is connected to the wiring CAL.
- a first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitor CB.
- the wiring WBL functions as a write bit line
- the wiring RBL functions as a read bit line
- the wiring WOL functions as a word line.
- the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB.
- a high-level potential is preferably applied to the wiring CAL when data is written and when data is read. Further, it is preferable to apply a low-level potential to the wiring CAL while data is being held.
- the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
- the memory cell 1474 shown in FIG. 35D corresponds to the memory device shown in FIGS. That is, the transistor M2 is connected to the transistor 200, the capacitor CB is connected to the capacitor 100, the transistor M3 is connected to the transistor 300, the wiring WBL is connected to the wiring 1003, the wiring WOL is connected to the wiring 1004, the wiring BGL is connected to the wiring 1006, and the wiring CAL is connected to the wiring. 1005 , the wiring RBL corresponds to the wiring 1002 , and the wiring SL corresponds to the wiring 1001 .
- the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate.
- the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, like the memory cell 1475 shown in FIG. 35E.
- the memory cell MC may be a memory cell configured with a single-gate transistor, that is, a transistor M2 that does not have a back gate, like the memory cell 1476 shown in FIG. 35F.
- the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into one wiring BIL, like the memory cell 1477 shown in FIG. 35G.
- the transistor 200 can be used as the transistor M2
- the transistor 300 can be used as the transistor M3
- the capacitor 100 can be used as the capacitor CB.
- an OS transistor as the transistor M2
- leakage current of the transistor M2 can be significantly reduced.
- written data can be held for a long time by the transistor M2, so that the refresh frequency of the memory cell can be reduced.
- the refresh operation of the memory cells can be made unnecessary.
- leakage current is very small, multilevel data or analog data can be held in the memory cell 1474 . The same applies to memory cells 1475 to 1477 .
- the transistor M3 may be a transistor including silicon in a channel formation region (hereinafter sometimes referred to as a Si transistor).
- the conductivity type of the Si transistor may be n-channel type or p-channel type.
- a Si transistor may have higher field effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a read transistor.
- the transistor M2 can be stacked over the transistor M3, so that the area occupied by the memory cell can be reduced and the memory device can be highly integrated.
- the transistor M3 may be an OS transistor.
- OS transistors are used for the transistors M2 and M3, the circuit of the memory cell array 1470 can be formed using only n-channel transistors.
- FIG. 35H shows an example of a gain cell type memory cell with 3 transistors and 1 capacitive element.
- a memory cell 1478 illustrated in FIG. 35H includes transistors M4 to M6 and a capacitor CC. Capacitive element CC is provided as appropriate.
- a memory cell 1478 is electrically connected to a wiring BIL, a wiring RWL, a wiring WWL, a wiring BGL, and a wiring GNDL.
- a wiring GNDL is a wiring for applying a low-level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
- the transistor M4 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. Note that the back gate and gate of the transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a backgate.
- the transistor M5 and the transistor M6 may each be an n-channel Si transistor or a p-channel Si transistor.
- the transistors M4 to M6 may be OS transistors.
- memory cell array 1470 can be configured using only n-type transistors.
- the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitor 100 can be used as the capacitor CC.
- the transistor M4 By using an OS transistor as the transistor M4, leakage current of the transistor M4 can be significantly reduced.
- peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to those described above. Arrangements or functions of these circuits and wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
- FIGS. 36A and 36B An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to FIGS. 36A and 36B.
- a plurality of circuits (systems) are mounted on the chip 1200 .
- SoC System on Chip
- the chip 1200 has a CPU 1211, a GPU 1212, one or more analog computation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
- the chip 1200 is provided with bumps (not shown) to connect with the first surface of the package substrate 1201 as shown in FIG. 36B.
- a plurality of bumps 1202 are provided on the rear surface of the first surface of the package substrate 1201 and connected to the motherboard 1203 .
- the mother board 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222 .
- storage devices such as a DRAM 1221 and a flash memory 1222 .
- the DOSRAM shown in the previous embodiment can be used for the DRAM 1221 .
- the NOSRAM described in the above embodiment can be used for the flash memory 1222 .
- the CPU 1211 preferably has multiple CPU cores.
- the GPU 1212 preferably has multiple GPU cores.
- the CPU 1211 and GPU 1212 may each have a memory for temporarily storing data.
- a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200 .
- the above-mentioned NOSRAM or DOSRAM can be used for the memory.
- the GPU 1212 is suitable for parallel computation of a large amount of data, and can be used for image processing or sum-of-products operations. By providing the image processing circuit or the product-sum operation circuit using the oxide semiconductor of the present invention in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.
- the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened. And, after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.
- the analog computation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation unit 1213 may be provided with the sum-of-products calculation circuit.
- the memory controller 1214 has a circuit functioning as a controller for the DRAM 1221 and a circuit functioning as an interface for the flash memory 1222 .
- the interface 1215 has an interface circuit with externally connected devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, game controllers, and the like. USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used as such an interface.
- USB Universal Serial Bus
- HDMI registered trademark
- the network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.
- LAN Local Area Network
- the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.
- a package substrate 1201 provided with a chip 1200 having a GPU 1212 , a motherboard 1203 provided with a DRAM 1221 and a flash memory 1222 can be called a GPU module 1204 .
- the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
- a product-sum operation circuit using the GPU 1212 enables a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network ( DBN), the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
- DNN deep neural network
- CNN convolutional neural network
- RNN recurrent neural network
- DBM deep Boltzmann machine
- DBN deep belief network
- the semiconductor device described in this embodiment is a semiconductor device that functions as a CPU that can operate with extremely low power consumption.
- FIG. 37 shows a configuration example of the CPU 3310.
- the CPU 3310 includes a CPU core (CPU Core) 3311, an L1 (level 1) cache memory device (L1 Cache) 3371, an L2 cache memory device (L2 Cache) 3372, a bus interface (Bus I/F) 3373, a power switch 3315 to It has a power switch 3317 and a level shifter (LS) 3318 .
- the CPU core 3311 has a flip-flop 3314 .
- the CPU core 3311, the L1 cache memory device 3371, and the L2 cache memory device 3372 are interconnected by the bus interface unit 3373.
- the PMU 3313 generates a clock signal GCLK1 and various PG (power gating) control signals (PG control signals) in response to externally input interrupt signals (Interrupts) and signals such as the signal SLEEP1 issued by the CPU 3310.
- a clock signal GCLK1 and a PG control signal are input to the CPU 3310 .
- the PG control signal controls power switches 3315 to 3317 and flip-flop 3314 .
- a power switch 3315 and a power switch 3316 control the supply of the voltage VDDD and the voltage VDD1 to the virtual power supply line V_VDD (hereinafter referred to as V_VDD line), respectively.
- Power switch 3317 controls supply of voltage VDDH to level shifter (LS) 3318 .
- a voltage VSSS is input to the CPU 3310 and the PMU 3313 without passing through the power switch.
- a voltage VDDD is input to the PMU 3313 without passing through the power switch.
- the voltage VDDD and the voltage VDD1 are drive voltages for the CMOS circuit.
- Voltage VDD1 is lower than voltage VDDD and is a drive voltage in the sleep state.
- Voltage VDDH is a drive voltage for the OS transistor and is higher than voltage VDDD.
- Each of the L1 cache memory device 3371, L2 cache memory device 3372, and bus interface unit 3373 has at least one power domain capable of power gating.
- a power domain capable of power gating is provided with one or more power switches. These power switches are controlled by PG control signals.
- a flip-flop 3314 is used as a register.
- the flip-flop 3314 is provided with a backup circuit.
- the flip-flop 3314 will be described below.
- FIG. 38A A circuit configuration example of the flip-flop 3314 is shown in FIG. 38A.
- the flip-flop 3314 has a scan flip-flop 3319 and a backup circuit 3312 .
- the scan flip-flop 3319 has a node D1, a node Q1, a node SD, a node SE, a node RT, a node CK, and a clock buffer circuit 3319A.
- a node D1 is a data input node
- a node Q1 is a data output node
- a node SD is a scan test data input node.
- Node SE is the input node for signal SCE.
- a node CK is an input node for the clock signal GCLK1.
- the clock signal GCLK1 is input to the clock buffer circuit 3319A.
- the analog switch of the scan flip-flop 3319 is connected to the nodes CK1 and CKB1 of the clock buffer circuit 3319A.
- a node RT is an input node for a reset signal.
- a signal SCE is a scan enable signal and is generated by the PMU 3313.
- PMU 3313 generates signal BK and signal RC.
- a level shifter 3318 level-shifts the signal BK and the signal RC to generate the signal BKH and the signal RCH.
- Signal BK is a backup signal
- signal RC is a recovery signal.
- the circuit configuration of the scan flip-flop 3319 is not limited to that of FIG. 38A.
- a flip-flop prepared in a standard circuit library can be applied.
- the backup circuit 3312 has a node SD_IN, a node SN11, transistors M11 to M13, and a capacitive element C11.
- a node SD_IN is a scan test data input node and is connected to the node Q1 of the scan flip-flop 3319 .
- Node SN11 is a holding node of backup circuit 3312 .
- Capacitive element C11 is a holding capacitor for holding the voltage of node SN11.
- the transistor M11 controls the conduction state between the node Q1 and the node SN11.
- Transistor M12 controls conduction between node SN11 and node SD.
- Transistor M13 controls conduction between node SD_IN and node SD.
- the on/off state of the transistor M11 and the transistor M13 is controlled by the signal BKH, and the on/off state of the transistor M12 is controlled by the signal RCH.
- the transistors M11 to M13 are OS transistors. A configuration in which the transistors M11 to M13 have back gates is illustrated. Back gates of the transistors M11 to M13 are connected to a power supply line that supplies the voltage VBG1.
- At least the transistor M11 and the transistor M12 are preferably OS transistors. Since the OS transistor has an extremely low off-state current, a voltage drop at the node SN11 can be suppressed and almost no power is consumed to hold data; therefore, the backup circuit 3312 has nonvolatile characteristics. Since data is rewritten by charging/discharging the capacitive element C11, the backup circuit 3312 has no restriction on the number of rewritings in principle, and can write and read data with low energy.
- a backup circuit 3312 can be stacked on a scan flip-flop 3319 composed of silicon CMOS circuits.
- the backup circuit 3312 Since the backup circuit 3312 has a very small number of elements compared to the scan flip-flop 3319, there is no need to change the circuit configuration and layout of the scan flip-flop 3319 in order to stack the backup circuit 3312. That is, the backup circuit 3312 is a highly versatile backup circuit. In addition, since the backup circuit 3312 can be provided in the region where the scan flip-flop 3319 is formed, even if the backup circuit 3312 is incorporated, the area overhead of the flip-flop 3314 can be made zero. Therefore, power gating of the CPU core 3311 becomes possible by providing the backup circuit 3312 in the flip-flop 3314 . Since the energy required for power gating is small, it is possible to power-gate the CPU core 3311 with high efficiency.
- the backup circuit 3312 By providing the backup circuit 3312, the parasitic capacitance due to the transistor M11 is added to the node Q1. No effect. In other words, provision of the backup circuit 3312 does not substantially degrade the performance of the flip-flop 3314 .
- a clock gating state for example, a clock gating state, a power gating state, and a sleep state can be set.
- the PMU 3313 selects the low power consumption mode of the CPU core 3311 based on the interrupt signal, signal SLEEP1, and the like. For example, when transitioning from the normal operating state to the clock gating state, the PMU 3313 stops generating the clock signal GCLK1.
- the PMU 3313 when transitioning from a normal operating state to a hibernate state, the PMU 3313 performs voltage and/or frequency scaling. For example, when performing voltage scaling, the PMU 3313 turns off the power switch 3315 and turns on the power switch 3316 in order to input the voltage VDD1 to the CPU core 3311 .
- the voltage VDD1 is a voltage that does not cause the data of the scan flip-flop 3319 to disappear.
- PMU 3313 reduces the frequency of clock signal GCLK1.
- FIG. 39 An example of the power gating sequence of the CPU core 3311 is shown in FIG. In FIG. 39, t1 to t7 represent times.
- Signals PSE0 through PSE2 are control signals for power switches 3315 through 3317 and are generated by PMU 3313 . When the signal PSE0 is "H"/"L", the power switch 3315 is on/off. The same applies to the signal PSE1 and the signal PSE2.
- the PMU 3313 stops the clock signal GCLK1 and changes the signal PSE2 and signal BK to "H".
- Level shifter 3318 becomes active and outputs signal BKH of “H” to backup circuit 3312 .
- the transistor M11 of the backup circuit 3312 is turned on, and the data of the node Q1 of the scan flip-flop 3319 is written to the node SN11 of the backup circuit 3312. If the node Q1 of the scan flip-flop 3319 is "L”, the node SN11 remains “L”, and if the node Q1 is "H”, the node SN11 becomes "H”.
- the PMU 3313 sets the signal PSE2 and the signal BK to "L” at time t2, and sets the signal PSE0 to "L” at time t3. At time t3, the state of the CPU core 3311 shifts to the power gating state. Note that the signal PSE0 may fall at the same timing as the signal BK falls.
- the PMU 3313 changes the signal PSE0 to "H", thereby shifting from the power gating state to the recovery state.
- the PMU 3313 changes the signal PSE2, the signal RC, and the signal SCE to "H".
- the transistor M12 is turned on, and the charge of the capacitive element C11 is distributed between the node SN11 and the node SD. If the node SN11 is "H”, the voltage of the node SD rises. Since the node SE is at "H”, the data of the node SD is written to the input-side latch circuit of the scan flip-flop 3319.
- clock signal GCLK1 is input to node CK at time t6, data in the input-side latch circuit is written to node Q1. That is, the data of node SN11 is written to node Q1.
- the PMU 3313 sets the signal PSE2, signal SCE, and signal RC to "L", and the recovery operation ends.
- the backup circuit 3312 using an OS transistor has both low dynamic and static low power consumption, so it is very suitable for normally-off computing.
- the CPU 3310 including the CPU core 3311 having the backup circuit 3312 using the OS transistor can be called NoffCPU (registered trademark).
- the NoffCPU has a backup circuit with nonvolatile characteristics, and can stop power supply when no operation is required. Even if the flip-flop 3314 is mounted, the performance degradation of the CPU core 3311 and the dynamic power increase can be prevented from occurring.
- the CPU core 3311 may have a plurality of power domains capable of power gating. A plurality of power domains are provided with one or more power switches for controlling voltage input. Also, the CPU core 3311 may have one or more power domains in which power gating is not performed. For example, a power gating control circuit for controlling the flip-flop 3314 and power switches 3315 to 3317 may be provided in a power domain where power gating is not performed.
- the application of the flip-flop 3314 is not limited to the CPU 3310.
- a flip-flop 3314 can be applied to a register provided in a power domain capable of power gating.
- an OS transistor has small changes in electrical characteristics due to irradiation of radiation, that is, has high resistance to radiation. Therefore, it can be said that a NoffCPU including a CPU core having a backup circuit using an OS transistor has high resistance to radiation.
- the NoffCPU which has high resistance to radiation and can operate with extremely low power consumption, can be suitably used, for example, in outer space.
- the NoffCPU can be used in a semiconductor device provided in a nuclear power plant, a radioactive waste disposal site, or a working robot in a disposal site.
- it can be suitably used for a semiconductor device installed in a remote-controlled robot that is remotely controlled for dismantling nuclear reactor facilities, retrieving nuclear fuel or fuel debris, and conducting field surveys in spaces with a large amount of radioactive materials.
- This embodiment mode shows an example of an electronic component and an electronic device in which the storage device or the like described in the above embodiment mode is incorporated.
- FIG. 40A shows a perspective view of an electronic component 700 and a board (mounting board 704) on which the electronic component 700 is mounted.
- Electronic component 700 shown in FIG. 40A has storage device 720 in mold 711 .
- FIG. 40A is partially omitted to show the inside of electronic component 700 .
- Electronic component 700 has lands 712 outside mold 711 . Land 712 is electrically connected to electrode pad 713 , and electrode pad 713 is electrically connected to storage device 720 by wire 714 .
- the electronic component 700 is mounted on a printed circuit board 702, for example.
- a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed board 702 .
- the memory device 720 has a drive circuit layer 721 and a memory circuit layer 722 .
- FIG. 40B A perspective view of the electronic component 730 is shown in FIG. 40B.
- Electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module).
- An electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 provided on the interposer 731 .
- the electronic component 730 shows an example of using the storage device 720 as a high bandwidth memory (HBM).
- HBM high bandwidth memory
- an integrated circuit semiconductor device
- a CPU, GPU, or FPGA can be used.
- a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 732 .
- a silicon interposer, a resin interposer, or the like can be used as the interposer 731 .
- the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. A plurality of wirings are provided in a single layer or multiple layers.
- the interposer 731 also has a function of electrically connecting the integrated circuit provided over the interposer 731 to electrodes provided over the package substrate 732 . For these reasons, the interposer is sometimes called a "rewiring board" or an "intermediate board".
- through electrodes are provided in the interposer 731 and the integrated circuit and the package substrate 732 are electrically connected using the through electrodes.
- a TSV Through Silicon Via
- a silicon interposer is preferably used as the interposer 731 . Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.
- HBM In HBM, it is necessary to connect many wires in order to achieve a wide memory bandwidth. Therefore, an interposer for mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts the HBM.
- the reliability is less likely to deteriorate due to the difference in expansion coefficient between the integrated circuit and the interposer.
- the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur.
- a 2.5D package 2.5-dimensional packaging in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
- a heat sink may be provided overlapping the electronic component 730 .
- a heat sink it is preferable that the heights of the integrated circuits provided over the interposer 731 be uniform.
- the memory device 720 and the semiconductor device 735 have the same height.
- An electrode 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate.
- FIG. 40B shows an example in which the electrodes 733 are formed from solder balls.
- BGA All Grid Array
- the electrodes 733 may be formed of conductive pins.
- PGA Peripheral Component Interconnect
- the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA.
- a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) be able to.
- the semiconductor devices described in the above embodiments are, for example, storage devices of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/reproducing devices, navigation systems, etc.).
- the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
- the semiconductor devices described in the above embodiments are applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives).
- 41A to 41E schematically show some configuration examples of the removable storage device.
- the semiconductor devices described in the previous embodiments are processed into packaged memory chips and used for various storage devices and removable memories.
- FIG. 41A is a schematic diagram of a USB memory.
- USB memory 1100 has housing 1101 , cap 1102 , USB connector 1103 and substrate 1104 .
- a substrate 1104 is housed in a housing 1101 .
- a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104 .
- the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 or the like.
- FIG. 41B is a schematic diagram of the appearance of the SD card
- FIG. 41C is a schematic diagram of the internal structure of the SD card.
- SD card 1110 has housing 1111 , connector 1112 and substrate 1113 .
- a substrate 1113 is housed in a housing 1111 .
- a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113 .
- a wireless chip having a wireless communication function may be provided on the substrate 1113 .
- data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110 .
- the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 or the like.
- FIG. 41D is a schematic diagram of the appearance of the SSD
- FIG. 41E is a schematic diagram of the internal structure of the SSD.
- SSD 1150 has housing 1151 , connector 1152 and substrate 1153 .
- a substrate 1153 is housed in a housing 1151 .
- substrate 1153 has memory chip 1154 , memory chip 1155 and controller chip 1156 attached thereto.
- a memory chip 1155 is a work memory for the controller chip 1156, and may be a DOSRAM chip, for example.
- the capacity of the SSD 1150 can be increased.
- the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 or the like.
- a semiconductor device can be used for a processor such as a CPU or a GPU, or a chip.
- 42A to 42H illustrate specific examples of electronic devices including processors such as CPUs and GPUs, or chips according to one embodiment of the present invention.
- a GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
- electronic devices include relatively large screens such as televisions, monitors for desktop or notebook information terminals, digital signage (digital signage), large game machines such as pachinko machines, etc. , digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproducing devices, and the like.
- the electronic device can be equipped with artificial intelligence.
- the electronic device of one embodiment of the present invention may have an antenna.
- An image, information, or the like can be displayed on the display portion by receiving a signal with the antenna.
- the antenna may be used for contactless power transmission.
- the electronic device of one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared).
- An electronic device of one embodiment of the present invention can have various functions. For example, functions to display various information (still images, moving images, text images, etc.) on the display, touch panel functions, functions to display calendars, dates or times, functions to execute various software (programs), wireless communication function, a function of reading a program or data recorded on a recording medium, and the like.
- 42A to 42H show examples of electronic devices.
- FIG. 42A shows a mobile phone (smartphone), which is a type of information terminal.
- the information terminal 5100 has a housing 5101 and a display unit 5102.
- the display unit 5102 is provided with a touch panel
- the housing 5101 is provided with buttons.
- the information terminal 5100 can execute an application using artificial intelligence.
- Applications using artificial intelligence include, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5102.
- An application displayed on the display portion 5102, an application for performing biometric authentication such as a fingerprint or a voiceprint, and the like can be given.
- a notebook information terminal 5200 is illustrated in FIG. 42B.
- the notebook information terminal 5200 has an information terminal main body 5201 , a display section 5202 , and a keyboard 5203 .
- the notebook information terminal 5200 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
- applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Also, by using the notebook information terminal 5200, it is possible to develop new artificial intelligence.
- a smartphone and a notebook information terminal are shown as examples of electronic devices in FIGS. 42A and 42B, respectively, but information terminals other than smartphones and notebook information terminals can be applied.
- Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.
- FIG. 42C shows a portable game machine 5300, which is an example of a game machine.
- a portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like.
- Housing 5302 and housing 5303 can be removed from housing 5301 .
- the connection portion 5305 provided in the housing 5301 to another housing (not shown)
- the video output to the display portion 5304 can be output to another video device (not shown). can.
- the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play the game at the same time.
- the chips described in the above embodiments can be incorporated into the chips or the like provided in the substrates of the housings 5301, 5302, and 5303.
- FIG. 42D shows a stationary game machine 5400, which is an example of a game machine.
- a controller 5402 is wirelessly or wiredly connected to the stationary game machine 5400 .
- a low power consumption game machine By applying the GPU or chip of one embodiment of the present invention to a game machine such as the portable game machine 5300 and the stationary game machine 5400, a low power consumption game machine can be realized.
- the low power consumption can reduce the heat generated from the circuit, thereby reducing the influence of the heat on the circuit itself, the peripheral circuits, and the module.
- the portable game machine 5300 having artificial intelligence can be realized.
- the progress of the game, the speech and behavior of creatures appearing in the game, and the expressions that occur in the game are determined by the program of the game. , which enables expressions not limited to game programs. For example, it is possible to express changes in the content of questions asked by the player, the progress of the game, the time, and the speech and behavior of characters appearing in the game.
- the game players can be anthropomorphically configured by artificial intelligence. can play games.
- FIGS. 42C and 42D illustrate a portable game machine and a stationary game machine as examples of game machines
- game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these.
- Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in amusement facilities (game arcades, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like. are mentioned.
- a GPU or chip of one aspect of the present invention can be applied to large-scale computers.
- FIG. 42E is a diagram showing a supercomputer 5500, which is an example of a large computer.
- FIG. 42F is a diagram showing a rack-mounted computer 5502 that the supercomputer 5500 has.
- a supercomputer 5500 has a rack 5501 and a plurality of rack-mount computers 5502 .
- a plurality of computers 5502 are stored in the rack 5501 .
- the computer 5502 is provided with a plurality of substrates 5504, and the GPUs or chips described in the above embodiments can be mounted over the substrates.
- the supercomputer 5500 is a large computer mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous amounts of computation, resulting in high power consumption and high chip heat generation.
- a low power consumption supercomputer can be realized.
- the low power consumption can reduce heat generation from the circuit, so that the influence of the heat generation on the circuit itself, the peripheral circuits, and the module can be reduced.
- FIGS. 42E and 42F illustrate a supercomputer as an example of a large computer, but the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
- Large computers to which the GPU or chip of one aspect of the present invention is applied include, for example, computers that provide services (servers), large general-purpose computers (mainframes), and the like.
- a GPU or chip of one embodiment of the present invention can be applied to automobiles, which are mobile objects, and to the vicinity of the driver's seat of automobiles.
- FIG. 42G is a diagram showing the vicinity of the windshield in the interior of an automobile, which is an example of a mobile object.
- FIG. 42G shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to the pillar.
- the display panels 5701 to 5703 can provide various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, and the like. In addition, the display items and layout displayed on the display panel can be appropriately changed according to user's preference, and the design can be improved.
- the display panels 5701 to 5703 can also be used as lighting devices.
- the display panel 5704 can complement the field of view (blind spot) blocked by the pillars by displaying an image from an imaging device (not shown) provided in the automobile. That is, by displaying an image from an imaging device provided outside the automobile, blind spots can be compensated for and safety can be enhanced. In addition, by projecting an image that supplements the invisible part, safety confirmation can be performed more naturally and without discomfort.
- the display panel 5704 can also be used as a lighting device.
- the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
- the chip can be used, for example, in an automatic driving system for automobiles.
- the chip can be used in a system for road guidance, danger prediction, and the like.
- the display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.
- moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like, and the chip of one embodiment of the present invention can be applied to these moving objects. It is possible to give a system using artificial intelligence.
- FIG. 42H shows an electric refrigerator-freezer 5800, which is an example of an appliance.
- the electric freezer-refrigerator 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
- the electric refrigerator-freezer 5800 having artificial intelligence can be realized.
- the electric freezer-refrigerator 5800 has a function of automatically generating a menu based on the ingredients stored in the electric freezer-refrigerator 5800, the expiration date of the ingredients, etc. It can have a function of automatically adjusting the temperature according to the temperature.
- Electric refrigerators and freezers have been described as an example of electrical appliances, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
- the electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, the effects thereof, and the like described in the present embodiment can be appropriately combined with the descriptions of other electronic devices.
- the sheet resistance in the depth direction of the oxide was measured in a laminate in which a conductor was provided on the oxide.
- Sample A used for measurement will be described.
- heat treatment was performed at 400° C. for 1 hour in a nitrogen atmosphere, followed by heat treatment at 400° C. for 1 hour in an oxygen atmosphere.
- a 20 nm-thickness tantalum nitride film was formed on the oxide by sputtering.
- the tantalum nitride film was formed at room temperature in an atmosphere containing argon and nitrogen using a target containing Ta.
- Sample A was divided into four samples A1 to A4. Samples A2 to A4 were subjected to heat treatment in a nitrogen atmosphere for 1 hour. Note that sample A2 was heat-treated at a temperature of 250°C in a nitrogen atmosphere, sample A3 was heat-treated at a temperature of 300°C in a nitrogen atmosphere, and sample A4 was heat-treated in a nitrogen atmosphere at a temperature of 400°C. Sample A1 was not subjected to heat treatment in a nitrogen atmosphere.
- the tantalum nitride film was removed from the samples A1 to A4 using a dry etching method.
- the step of measuring the sheet resistance of the oxide step 1 was performed.
- a step of etching part of the oxide step 2) was performed.
- a step (step 3) of measuring the residual film thickness of the oxide was performed. Thereafter, steps 1 to 3 were repeated until the sheet resistance reached 6 ⁇ 10 6 ⁇ /square, which is an overrange. It should be noted that the sheet resistance of samples A3 and A4 did not exceed the range even when the film thickness of the etched oxide was around 450 nm.
- FIG. 43 is a diagram explaining the correlation between the heat treatment temperature and the sheet resistance of the oxide.
- the horizontal axis is the depth from the surface of the oxide (Depth) [nm]
- the vertical axis is the sheet resistance of the oxide (Sheet Resistance of IGZO) [ ⁇ /square].
- This embodiment can be used in appropriate combination with the configurations, structures, methods, and the like shown in other embodiments and other embodiments.
- Example 2 the transistor described in this embodiment mode was manufactured as a prototype, and electrical characteristics of the transistor were measured. Note that the design values of the prototyped transistor were a channel length of 60 nm and a channel width of 60 nm.
- the transistor includes an In--Ga--Zn oxide (CAAC-IGZO) having a CAAC structure in a channel formation region.
- CAAC-IGZO In--Ga--Zn oxide
- 44A and 44B show the top gate voltage (indicated by “Vg” in the figure)-drain current (indicated by “Id” in the figure) characteristics of the prototyped transistor.
- the top gate voltage-drain current characteristic shown in FIG. 44A shows that when the drain voltage to the source is 0.1 V and the temperature of the measurement environment is 27° C., the back gate voltage to the source (denoted as “Vb” in the figure) varies from +6 V to ⁇ 6 V. It is the result of measuring every 2 V until
- the top gate voltage-drain current characteristic shown in FIG. 44B is the result of measuring the drain voltage to the source at 2.5 V, the temperature of the measurement environment at 27° C., and the back gate voltage to the source from +6 V to ⁇ 6 V at intervals of 2 V. be.
- 45A1, 45B1, 45C1, and 45D1 are diagrams for explaining capacitance.
- 45A1, 45B1, 45C1, and 45D1 G is the first gate (also called top gate), S is the source, D is the drain, and BG is the second gate (back gate). Also called).
- 45A2 and 45B2 are diagrams showing the top gate voltage (denoted as “Vg” in the figure)-capacitance characteristics of the prototyped transistor.
- 45C2 and 45D2 are diagrams showing the back gate voltage (denoted as "Vbg” in the figure)-capacitance characteristics of the prototyped transistor.
- the capacitance shown in FIGS. 45A1 and 45A2 (denoted as “Cgsd (Cgc)” in the figure) is a combined capacitance of the top gate-source capacitance and the top gate-drain capacitance.
- Capacitances shown in FIGS. 45B1 and 45B2 (denoted as “Cgb” in the drawings) are capacitances between the top gate and the back gate.
- the drain voltage to the source is 0.0 V
- the measurement frequency is 100 kHz
- the temperature of the measurement environment is 27° C.
- the back gate voltage to the source is from +6 V to ⁇ 6 V. It is the result of changing and measuring.
- the capacitance shown in FIGS. 45C1 and 45C2 (denoted as “Cbsd (Cbc)” in the figures) is the combined capacitance of the backgate-source capacitance and the backgate-drain capacitance.
- Capacitances shown in FIGS. 45D1 and 45D2 (denoted as “Cbg” in the drawings) are back gate-top gate capacitances.
- the back gate voltage-capacitance characteristics shown in FIGS. 45C2 and 45D2 are obtained by changing the top gate voltage to the source from +2.5 V to ⁇ This is the result of measurement by changing the voltage up to 2.5V.
- FIG. 46 shows the temperature-off current (denoted as "Ioff” in the figure) characteristics of the prototype transistor in the measurement environment.
- the temperature-off current characteristics of the measurement environment shown in FIG. This is the result of measurement at 125°C. 20,000 transistors connected in parallel were measured.
- FIG. 46 shows that the off-state current value of the transistor prototyped in this example is 3 zA/FET (3 ⁇ 10 ⁇ 21 A/FET) at 85° C., which is small.
- a TEG capable of multi-point measurement described in Embodiment 2 was manufactured, and variations in electrical characteristics of transistors were evaluated.
- the multiplexer MUXX, the multiplexer MUXY, the analog switch ASX, and the analog switch ASY are each composed of a CMOS circuit. That is, a peripheral circuit including a multiplexer MUXX, a multiplexer MUXY, an analog switch ASX, and an analog switch ASY is formed of Si transistors.
- the transistor 200 described in Embodiment 1 is manufactured as the transistors Tr[1,1] to Tr[m,n]. That is, the transistors Tr[1,1] to Tr[m,n] have metal oxide in their channel formation regions.
- the first gate of the transistor Tr corresponds to the conductor 260 described in Embodiment 1
- the second gate of the transistor Tr corresponds to the conductor 205 described in Embodiment 1.
- the source or drain of the transistor Tr corresponds to the conductor 242a or the conductor 242b or the region 230ba or the region 230bb described in the first embodiment.
- m and n are each set to 128. Further, the design values of each transistor were set to a channel length of 60 nm and a channel width of 60 nm.
- FIG. 47 shows an enlarged cross-sectional TEM photograph of a part of the TEG900 produced in this example.
- the TEG 900 has layers M1 through M9. Note that the layers M1 to M9 are layers containing conductors such as wirings or electrodes. It can be seen from FIG. 47 that an OS transistor (CAAC-IGZO FET) and a capacitor (MIM) having a MIM (Metal-Insulator-Metal) structure are provided above the Si transistor (Bulk Si FET).
- CAAC-IGZO FET an OS transistor
- MIM capacitor
- FIG. 48 shows the arrangement of 12 TEGs 900 (TEG900[1] to TEG900[12]). Note that hereinafter, variations in electrical characteristics of transistors in each of TEG900[1] to TEG900[12] are referred to as local variations.
- the Id-Vg characteristics of the transistor Tr were measured, and the threshold voltage (Vth) and the field effect mobility ( ⁇ ) were calculated from the measured Id-Vg characteristics. Note that in the measurement of the Id-Vg characteristics, the potential applied to the source electrode of the transistor Tr was 0 V, the potential applied to the drain electrode of the transistor Tr was 0.1 V, and the potential applied to the second gate electrode of the transistor Tr. was set to 0V.
- FIGS. 49A to 50F are diagrams for explaining variations in threshold voltage (Vth) of transistors calculated by TEG900[1] to TEG900[12], respectively.
- 49A to 49F are histograms of threshold voltages calculated for 1024 transistors Tr included in TEG900[1] to TEG900[6], respectively.
- 50A to 50F are histograms of threshold voltages calculated for 1024 transistors Tr included in TEG900[7] to TEG900[12], respectively.
- the horizontal axis is threshold voltage (Vth) [V] and the vertical axis is frequency (count).
- FIGS. 49A to 50F show threshold voltages (Vth) calculated by the root Id method.
- the root Id method refers to an Id-Vg curve plotted with the gate voltage Vg [V] on the horizontal axis and the square root of the drain current Id 1/2 [A] on the vertical axis.
- the median threshold voltage was 1.32V and the deviation ( ⁇ ) was 0.16V. From this, it was found that the OS transistors manufactured in this example have small variations in threshold voltage.
- 51A to 52F are diagrams for explaining variations in the field-effect mobility ( ⁇ ) of transistors calculated by TEG900[1] to TEG900[12], respectively.
- 51A to 51F are field effect mobility histograms calculated for 1024 transistors Tr included in TEG900[1] to TEG900[6], respectively.
- 52A to 52F are field effect mobility histograms calculated for 1024 transistors Tr included in TEG900[7] to TEG900[12], respectively.
- the horizontal axis is the field effect mobility (cm 2 /(V ⁇ s)) and the vertical axis is the frequency (count).
- FIGS. 51A to 52F show the field-effect mobility calculated using the equation of the linear region of the gradual channel approximation.
- FIGS. 53A and 53B are diagrams for explaining a method of arranging the transistors Tr[1,1] to Tr[m,n].
- the transistors Tr[1,1] to Tr[m,n] having the arrangement shown in FIG. 53A are referred to as a transistor group TRAa.
- the transistors Tr[1,1] to Tr[m,n] having the arrangement shown in FIG. 53B are referred to as a transistor group TRAb.
- the oxide OS is a metal oxide including a channel formation region and corresponds to the oxide 230 described in Embodiment 1.
- a conductor TGE is a first gate and corresponds to the conductor 260 described in the first embodiment.
- a conductor BGE is a second gate and corresponds to the conductor 205 described in the first embodiment.
- a conductor VIA is a conductor connected to a source electrode or a drain electrode and corresponds to the conductor 240 described in Embodiment 1.
- a transistor group TRAa shown in FIG. 53A has a configuration in which the source electrode or drain electrode of a transistor also serves as the source electrode or drain electrode of a transistor adjacent to the transistor in the channel length direction.
- the transistor group TRAb shown in FIG. 53B has a configuration in which the source electrode or drain electrode of the transistor is separated from the source electrode or drain electrode of the transistor adjacent to the transistor in the channel length direction.
- the variations in the electrical characteristics of the transistors were evaluated for the TEG900 having the transistor group TRAa and the TEG900 having the transistor group TRAb. Specifically, the Id-Vg characteristics were measured for 1024 transistors Tr included in the transistor group TRAa and 1024 transistors Tr included in the transistor group TRAb. Note that in the measurement of the Id-Vg characteristics, the potential applied to the source electrode of the transistor Tr was 0 V, the potential applied to the drain electrode of the transistor Tr was 0.1 V, and the potential applied to the second gate electrode of the transistor Tr. was set to 0V.
- FIG. 54A and 54B show the Id-Vg characteristics of the transistor.
- FIG. 54A shows the Id-Vg characteristics of 192 transistors out of 1024 transistors Tr measured for the transistor group TRAa.
- FIG. 54B shows Id-Vg characteristics of 192 transistors out of 1024 transistors Tr measured for the transistor group TRAb.
- the horizontal axis is the gate potential (Vg) [V] and the vertical axis is the drain current (Id) [A].
- FIGS. 55A to 55C are diagrams for explaining variations in threshold voltage (Vth) of transistors included in each of the transistor group TRAa and the transistor group TRAb. Note that FIGS. 55A to 55C show threshold voltages (Vth) calculated by the constant current method.
- the constant current method is a method in which Vg when a constant current (here, 1 nA) flows is used as the threshold voltage (Vth) from the results of the Id-Vg characteristics.
- FIG. 55A is a histogram of threshold voltages calculated for 1024 transistors Tr included in the transistor group TRAa.
- FIG. 55B is a histogram of threshold voltages calculated for 1024 transistors Tr included in the transistor group TRAb.
- the horizontal axis is threshold voltage (Vth) [V] and the vertical axis is frequency.
- the transistors included in the transistor group TRAa have a smaller median threshold voltage and a smaller threshold voltage variation than the transistor group TRAb.
- the median value of the threshold voltage was 0.37 V and the standard deviation of the threshold voltage was 43 mV.
- FIG. 55C is a normal quantile plot of the threshold voltages shown in FIGS. 55A and 55B.
- the horizontal axis is the threshold voltage (Vth) [V]
- the vertical axis is the normal distribution (Normal distribution) [ ⁇ ].
- Example 2 In this example, the semiconductor devices shown in FIGS. 56A to 56D were manufactured, the reliability of the transistor 200 was evaluated, and the stress time dependency was investigated.
- FIG. 56A shows a top view of a semiconductor device.
- FIG. 56B is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in FIG. 56A.
- FIG. 56C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. 56A.
- FIG. 56D is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in FIG. 56A.
- the top view of FIG. 56A omits some elements for clarity of illustration.
- the semiconductor device shown in FIGS. 56A to 56D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
- the semiconductor devices shown in FIGS. 56A to 56D are different from the semiconductor devices shown in FIGS. 1A to 1D in that the insulators 252 and 254 are not provided.
- Another difference is that the insulators 250 and 283 each have a stacked-layer structure, and the insulator 241 has a single-layer structure.
- Tantalum nitride was formed as the conductor 242 .
- Silicon oxynitride was formed as the insulator 250a.
- hafnium oxide was formed by ALD.
- Titanium nitride was formed as the conductor 260a.
- Tungsten was formed as the conductor 260b. Note that the film to be the conductor 260a and the film to be the conductor 260b were formed by continuous deposition.
- the transistor 200 manufactured in this example was subjected to heat treatment at 400° C. for 8 hours in a nitrogen atmosphere before reliability evaluation.
- the design values of the transistor 200 manufactured in this example are a channel length of 60 nm and a channel width of 60 nm.
- Reliability was evaluated by a +GBT (Gate Bias Temperature) stress test at a stress temperature of 150°C.
- the set temperature was set to 150° C.
- the drain potential Vd, the source potential Vs, and the bottom gate potential Vbg were set to 0V
- the top gate potential Vg was set to +3.63V.
- ⁇ Vsh is the amount of change in the shift voltage (Vsh).
- FIG. 57 is a graph showing stress time dependence of ⁇ Vsh.
- the horizontal axis indicates stress time (Time) [hr]
- the vertical axis indicates ⁇ Vsh [mV].
- ⁇ Vsh remained within the range of ⁇ 100 mV or more and +100 mV or less after the stress had elapsed for 5390 hours. In the period from 5390 hours to 6400 hours, the ⁇ Vsh of the transistor 200 manufactured in this example remained in the range of ⁇ 110 mV to +100 mV. From the above results, it was confirmed that the transistor 200 which is one embodiment of the present invention has high reliability.
- Example 2 the OS transistor described in Embodiment 1 with reference to FIG. 1 was prototyped, and an X-ray irradiation test was performed on the OS transistor. Note that the design values of the prototype OS transistor were a channel length of 200 nm and a channel width of 60 nm.
- OS transistor OSTr1 two OS transistors were manufactured.
- OS transistor OSTr2 the OS transistor OSTr2
- OS transistor OSTr1 and the OS transistor OSTr2 may be collectively referred to as an OS transistor.
- Fig. 74 shows the evaluation environment for the X-ray irradiation test used in this example.
- a lift table was provided in the chamber irradiated with the X-ray 8000, and the probe and the stage 8001 were set on the lift table.
- a diaphragm plate 8003 is arranged between the X-ray source 8002 and the stage 8001 .
- the aperture plate 8003 By arranging the aperture plate 8003, the recoil X-rays can be shielded.
- X-ray irradiation to the coaxial arm of the probe can be reduced, and abnormal current flowing through the probe can be suppressed.
- the irradiation dose rate was measured using an Accu-Dose radiation measurement system Model 2186 manufactured by Radcal.
- 4156C manufactured by Keysight Technologies was used to evaluate the electrical characteristics of the OS transistor.
- MX-160Labo manufactured by Mediex Tech was used as the X-ray irradiation device used for the X-ray irradiation test.
- the X-ray source is tungsten
- the tube voltage range is 30 kV or more and 160 kV or less
- the tube current range is 0.3 mA or more and 3.0 mA or less.
- the substrate was placed in the X-ray irradiation device, and static elimination was performed for 5 minutes using an ionizer.
- the Id-Vg measurement was performed on the OS transistor before X-ray irradiation.
- the substrate temperature is room temperature
- the drain voltage Vd is 0.1 V or 1.2 V
- the source voltage Vs and the back gate voltage Vbg are 0 V
- the gate voltage Vg is swept from ⁇ 4 V to +4 V. This was done by measuring the drain current Id at the time of
- the OS transistor was irradiated with X-rays for about 25 hours. All terminals (source, drain, gate, and back gate) of the OS transistor were grounded during X-ray irradiation. Further, the total dose of X-rays irradiated to the OS transistor was equivalent to 1000 Gy.
- Id-Vg was measured in the OS transistor after X-ray irradiation.
- the conditions for the Id-Vg measurement were the same as those for the Id-Vg measurement of the OS transistor before X-ray irradiation.
- the Id-Vg measurement of the OS transistor was also performed at the timing when the total dose of X-rays irradiated to the OS transistor was equivalent to 100 Gy or 200 Gy. In addition, it can be said that the total dose of X-rays is 0 Gy before X-ray irradiation.
- the Id-Vg measurement of the OS transistor after X-ray irradiation was performed multiple times at time intervals.
- the OS transistor was controlled at room temperature during the period when the Id-Vg measurement was not performed. Room temperature annealing can be investigated by performing multiple Id-Vg measurements at time intervals.
- the threshold voltage (Vth) of the OS transistor was calculated using the constant current method.
- the constant current method is a method in which the gate voltage Vg when a constant current (here, 1 pA) flows is used as the threshold voltage (Vth) from the results of the Id-Vg characteristics.
- FIG. 58 is a diagram explaining the time dependence of Vth of the OS transistor after X-ray irradiation.
- the horizontal axis represents elapsed time [hr] from the end of X-ray irradiation
- the vertical axis represents Vth [V].
- a graph indicated by black circles and a solid line in FIG. 58 shows variations in Vth of the OS transistor OSTr1 over time.
- a dashed line in FIG. 58 indicates Vth of the OS transistor OSTr1 before X-ray irradiation.
- a dotted line shown in FIG. 58 indicates Vth of the OS transistor OSTr1 immediately after the end of X-ray irradiation.
- a graph indicated by white triangles and a dashed line in FIG. 58 shows variations in Vth of the OS transistor OSTr2 over time.
- a two-dot chain line shown in FIG. 58 is Vth of the OS transistor OSTr2 before X-ray irradiation.
- a dashed-dotted line in FIG. 58 indicates Vth of the OS transistor OSTr2 immediately after the end of the X-ray irradiation.
- Vth before X-ray irradiation was 0.51 V
- Vth immediately after X-ray irradiation was finished was 0.16 V
- Vth of both the OS transistor OSTr1 and the OS transistor OSTr2 was negatively shifted by X-ray irradiation. Note that the difference between Vth before X-ray irradiation and Vth immediately after X-ray irradiation was 0.35 V for the OS transistor OSTr1 and 0.38 V for the OS transistor OSTr2. In addition, it was found that Vth of both the OS transistor OSTr1 and the OS transistor OSTr2 is positively shifted over time after X-ray irradiation.
- the subthreshold swing value (S value) of the OS transistor was calculated from the Id-Vg characteristics of the OS transistor measured before and after X-ray irradiation.
- the S value refers to the amount of change in gate voltage that causes the drain current in the subthreshold region to change by one digit with the drain voltage constant.
- FIG. 59 is a diagram explaining the time dependence of the S value of the OS transistor after 1000 Gy of X-ray irradiation.
- the horizontal axis represents elapsed time [hr] from the end of X-ray irradiation
- the vertical axis represents S value [mV/dec]. Note that a graph indicated by black circles and a solid line in FIG. 59 shows variations in the S value of the OS transistor OSTr1 over time. A graph indicated by white triangles and a dashed line in FIG. 59 shows variations in the S value of the OS transistor OSTr2 over time.
- FIG. 60A is a diagram explaining the dependence of the Vth of the OS transistor on the total dose of X-rays.
- the horizontal axis is the total X-ray dose [Gy]
- the vertical axis is ⁇ Vth [V].
- ⁇ Vth indicates the amount of change in Vth, and is a value obtained by subtracting Vth before X-ray irradiation from Vth after X-ray irradiation.
- Vth tended to decrease as the total dose increased.
- ⁇ Vth was approximately ⁇ 0.2 V during X-ray irradiation with a total dose of 1000 Gy.
- FIG. 60B is a diagram for explaining the dependence of the S value of the OS transistor on the total dose of X-rays.
- the horizontal axis is the total X-ray dose [Gy]
- the vertical axis is the ⁇ S value [mV/dec].
- the ⁇ S value indicates the amount of change in the S value, and is a value obtained by subtracting the S value before X-ray irradiation from the S value after X-ray irradiation.
- defects that occur in the gate insulator or at the interface between the channel formation region and the gate insulator are considered to be one of the factors that cause the threshold voltage to fluctuate due to radiation.
- a physical process from irradiation of a silicon oxide (SiO 2 ) film to generation of defects in a Si transistor is described below.
- Electron-hole pairs are generated by irradiating the SiO 2 film with radiation. Most of the generated electron-hole pairs disappear due to recombination. In addition, among electron-hole pairs that do not recombine, electrons having higher mobility than holes are emitted into the gate electrode or Si by a slight bias. In addition, in electron-hole pairs that do not recombine, some holes move to the vicinity of the interface between Si and SiO 2 due to shallow defect levels and are trapped in deep defect levels in the SiO 2 film. Alternatively, in some electron-hole pairs that do not recombine, some other holes move to the interface between Si and SiO2 via hydrogen to form interface states.
- FIGS. 61A to 61C The structure of the OS transistor used for calculation is shown in FIGS. 61A to 61C.
- FIG. 61A is a cross-sectional view of the OS transistor in the channel length direction.
- FIG. 61B is a cross-sectional view in the channel width direction including the source region or drain region of the OS transistor.
- FIG. 61C is a cross-sectional view in the channel width direction including the channel formation region of the OS transistor.
- the OS transistors used in the calculations are a conductor 805, an insulator 822 over the conductor 805, an insulator 824 over the insulator 822, and an oxide over the insulator 824.
- the oxide 830a and the oxide 830b may be collectively referred to as the oxide 830.
- a conductor 860 functions as a first gate electrode and corresponds to the conductor 260 described in Embodiment Mode 1.
- a conductor 805 functions as a second gate electrode and corresponds to the conductor 205 described in Embodiment Mode 1.
- FIG. Insulators 852, 850, and 854 function as first gate insulators and correspond to the insulators 252, 250, and 254 described in Embodiment 1, respectively.
- Insulators 822 and 824 function as second gate insulators and correspond to the insulators 222 and 224 described in Embodiment 1, respectively.
- the conductor 842a functions as either a source electrode or a drain electrode and corresponds to the conductor 242a described in Embodiment 1.
- the conductor 842b functions as the other of a source electrode and a drain electrode and corresponds to the conductor 242b described in Embodiment 1. At least part of the region of the oxide 830 overlapping with the conductor 860 functions as a channel formation region.
- the oxide 830a corresponds to the oxide 230a described in Embodiment 1
- the oxide 830b corresponds to the oxide 230b described in Embodiment 1.
- the interface between the metal oxide including the channel formation region of the OS transistor and the gate insulator corresponds to the interface between the oxide 230 b and the insulator 252 .
- the channel formation region may be simply referred to as a channel.
- L (SD) shown in Table 1 is the distance between the side surface of the conductor 842a and the side surface of the conductor 842b that face each other with the conductor 860 interposed therebetween.
- L (gate) in Table 1 is the distance between the conductor 842a and the conductor 842b in the region where the oxide 830b and the conductor 860 overlap with each other in the top view of the OS transistor.
- L (gate) in Table 1 is the width of the conductor 860 in the cross-sectional view of the OS transistor in the channel length direction.
- H in Table 1 is the distance from the top surface of the insulator 824 to the top surface of the insulator 822 in a region that does not overlap with the oxide 830 in the cross-sectional view of the OS transistor in the channel width direction (FIGS. 61B and 61B). 61C).
- the OS transistor used for calculation has an L length of 200 nm and a W length of 60 nm.
- FIG. 60C is a diagram for explaining the hole concentration dependence of ⁇ Vth of the OS transistor.
- the horizontal axis is the hole concentration [cm ⁇ 2 ] at the interface between the oxide 830b and the insulator 852, and the vertical axis is ⁇ Vth [V].
- FIG. 60D is a diagram for explaining the hole concentration dependence of the ⁇ S value of the OS transistor.
- the horizontal axis is the hole concentration [cm ⁇ 2 ] at the interface between the oxide 830b and the insulator 852, and the vertical axis is the ⁇ S value [mV/dec].
- ⁇ Vth was approximately ⁇ 0.2 V during X-ray irradiation with a total dose of 1000 Gy. This corresponds to ⁇ Vth when the hole concentration at the interface between the oxide 830b and the insulator 852 is approximately 1 ⁇ 10 12 cm ⁇ 2 . Therefore, it is estimated that the hole concentration at the interface between the oxide 830b and the insulator 852 increases by about 1 ⁇ 10 12 cm ⁇ 2 when the OS transistor is irradiated with X-rays of 1000 Gy.
- Fig. 62 shows an optical microscope photograph of the prototype chip.
- the chip has a NoffCPU, data memory, program memory, power generation circuit, A/D converter (ADC), clock generation oscillator (OSC), back gate holding circuit (VBG), and the like.
- the power generation circuit has a bandgap reference circuit, a Low Drop-Out regulator (LDO), and the like.
- An 8 KByte NOSRAM is mounted as a data memory
- a 32 KByte NOSRAM is mounted as a program memory.
- the NoffCPU has a first logic circuit and a second logic circuit.
- the transistors included in the first logic circuit are composed of Si transistors.
- the second logic circuit has a flip-flop (hereinafter, OSFF) including an OS transistor.
- OSFF flip-flop
- FIG. 63 shows a circuit diagram of the OSFF. As shown in FIG. 63, three OS transistors and one capacitor are added to the scan flip-flop (SCAN_FF). Signal BK is a backup signal and signal RC is a recovery signal. The OSFF is backed up and recovered by signals BK and RE sent from the PMU (not shown in FIG. 63).
- SCAN_FF scan flip-flop
- the scan flip-flop is composed of Si transistors. That is, the OSFF is composed of a Si transistor and an OS transistor.
- the X-ray resistance was evaluated by a tester before and after X-ray irradiation of the entire prototype chip.
- MX-160Labo manufactured by Medix Tech was used as an X-ray irradiation device.
- the total dose of X-rays is 1000 Gy, and the X-ray tube voltage is 160 kV.
- Tester evaluation refers to evaluation using a tester device to see if the chip is executing the input instructions and performing the desired operation.
- T2000 manufactured by Advantest Corporation was used as a tester.
- X-ray resistance was evaluated by inputting a Noff command to the chip before and after X-ray irradiation.
- the Noff command means that a pulse signal (a signal given in order of "L”, “H”, “L”) is given to the signal BK, and the chip is stopped for a certain period of time (a state in which no signal is given after the signal BK for a certain period of time). hold) and then give a pulse signal to the signal RE to end the operation.
- a pulse signal (a signal given in order of "L”, "H”, "L) is given to the signal BK, and the chip is stopped for a certain period of time (a state in which no signal is given after the signal BK for a certain period of time). hold) and then give a pulse signal to the signal RE to end the operation.
- the X-ray resistance of the Si transistor and the OS transistor can be evaluated.
- Si transistors and OS transistors are known to undergo a negative shift in Vth after X-ray irradiation.
- data in OSFF may be converted.
- the X-ray resistance of the Si transistor and the OS transistor can be evaluated depending on the presence or absence of this data conversion.
- Table 3 shows the results of NoffCPU tester evaluation. The circles shown in Table 3 indicate that the output from the logic circuit was normal.
- Example 2 the OS transistor described in Embodiment 1 with reference to FIG. 1 was prototyped, and an X-ray irradiation test was performed on the OS transistor. Note that the design values of the prototype OS transistor were a channel length of 200 nm and a channel width of 60 nm.
- the evaluation environment for the X-ray irradiation test described using FIG. 74 was used.
- MX-160Labo manufactured by MEDIEX TECH was used as an X-ray irradiation apparatus used for the X-ray irradiation test.
- the X-ray source is tungsten
- the tube voltage range is 30 kV to 160 kV
- the tube current range is 0.3 mA to 3.0 mA.
- the substrate was placed in the X-ray irradiation device, and static elimination was performed for 5 minutes using an ionizer.
- the Id-Vg measurement of the OS transistor was performed before X-ray irradiation.
- the Id-Vg measurement was performed by setting the drain voltage Vd to 0.1V, setting the source voltage Vs and the back gate voltage Vbg to 0V, and measuring the drain current Id when the gate voltage Vg was swept from -4V to +4V. Subsequently, the drain current Id was measured when the drain voltage Vd was set to 1.2V, the source voltage Vs and the back gate voltage Vbg were set to 0V, and the gate voltage Vg was swept from -4V to +4V.
- the measurement at the drain voltage Vd of 0.1 V and the measurement at 1.2 V were alternately repeated, and a total of 5 sets of measurements were performed (5 measurements at the drain voltage Vd of 0.1 V; 5 measurements at 2V). Note that the substrate temperature during the Id-Vg measurement was all room temperature.
- the OS transistor was irradiated with X-rays. All terminals (source, drain, gate, and back gate) of the OS transistor were grounded during X-ray irradiation.
- the irradiation dose of X-rays was set to 100 Gy.
- the dose rate of X-rays was changed for each sample, and the dose rate of the OS transistor OSTr3 was set to 40.0 Gy/hr, and the dose rate of the OS transistor OSTr4 was set to 13.3 Gy/hr.
- the conditions for the Id-Vg measurement were the same as those for the Id-Vg measurement before X-ray irradiation.
- the threshold voltage (Vth) of the OS transistor was calculated from the Id-Vg characteristics using the constant current method.
- the gate voltage Vg at which a current of 1 pA flows is defined as the threshold voltage (Vth).
- the threshold voltage (Vth) of the OS transistor OSTr3 is shown in FIG. 64A.
- FIG. 64B shows the threshold voltage (Vth) of the OS transistor OSTr4.
- 64A and 64B the horizontal axis indicates the total X-ray dose, and the vertical axis indicates the threshold voltage (Vth).
- FIG. 65 shows the variation ( ⁇ Vth) of the threshold voltages of the OS transistor OSTr3 and the OS transistor OSTr4.
- the horizontal axis indicates the total dose of X-rays
- the vertical axis indicates the amount of change in threshold voltage ( ⁇ Vth).
- the amount of change in threshold voltage ( ⁇ Vth) is a value obtained by subtracting the threshold voltage before X-ray irradiation from the threshold voltage after X-ray irradiation.
- 64A, 64B and 65 each show data when the drain voltage Vd is 0.1V.
- ⁇ Evaluation 2> The conditions for Id-Vg measurement and X-ray irradiation were changed from those in ⁇ Evaluation 1> described above, and changes in the electrical characteristics of the OS transistor with respect to X-ray irradiation were evaluated.
- three OS transistors OS transistors OSTr5 to OS transistors OSTr7 are used as samples.
- the description of the part that overlaps with ⁇ evaluation 1> may be omitted.
- the substrate was placed in the X-ray irradiation device, and static elimination was performed for 5 minutes using an ionizer.
- the Id-Vg measurement of the OS transistor was performed before X-ray irradiation.
- the Id-Vg measurement was performed by setting the drain voltage Vd to 0.1V, setting the source voltage Vs and the back gate voltage Vbg to 0V, and measuring the drain current Id when the gate voltage Vg was swept from 0V to +3V. Subsequently, the drain current Id was measured when the drain voltage Vd was set to 1.2V, the source voltage Vs and the back gate voltage Vbg were set to 0V, and the gate voltage Vg was swept from 0V to +3V.
- the measurement at the drain voltage Vd of 0.1 V and the measurement at 1.2 V were alternately repeated, and a total of 5 sets of measurements were performed (5 measurements at the drain voltage Vd of 0.1 V; 5 measurements at 2V). Note that the substrate temperature during the Id-Vg measurement was all room temperature.
- the OS transistor was irradiated with X-rays. All terminals (source, drain, gate, and back gate) of the OS transistor were grounded during X-ray irradiation.
- the X-ray irradiation dose was 100 Gy, and the X-ray dose rate was 35.0 Gy/hr.
- the conditions for the Id-Vg measurement were the same as those for the Id-Vg measurement before X-ray irradiation.
- the OS transistor OSTr5 repeated the aforementioned X-ray irradiation and Id-Vg measurement until the total dose of irradiated X-rays reached 3200 Gy.
- the above-described X-ray irradiation and Id-Vg measurement were repeated until the total dose of irradiated X-rays reached 300 Gy.
- FIG. 66A shows the threshold voltages (Vth) of the OS transistors OSTr5 to OStransistor OSTr7 when the total dose of X-rays is up to 300 Gy.
- the horizontal axis indicates the total X-ray dose
- the vertical axis indicates the threshold voltage (Vth).
- FIG. 66B shows the amount of change ( ⁇ Vth) in the threshold voltages of the OS transistors OSTr5 to OSTr7.
- the horizontal axis indicates the total dose of X-rays
- the vertical axis indicates the amount of change in threshold voltage ( ⁇ Vth).
- FIG. 67 shows the amount of change ( ⁇ Vth) in the threshold voltage of the OS transistor OSTr5 when the total dose of X-rays is up to 3200 Gy.
- the horizontal axis indicates the total dose of X-rays
- the vertical axis indicates the amount of change in threshold voltage ( ⁇ Vth).
- FIG. 67 also shows data of the OS transistor OSTr6 and the OS transistor OSTr7.
- 66A, 66B and 67 each show data when the drain voltage Vd is 1.2V.
- ⁇ Evaluation 3> The conditions for Id-Vg measurement and X-ray irradiation were changed from those in ⁇ Evaluation 1> and ⁇ Evaluation 2> described above, and changes in the electrical characteristics of the OS transistor due to X-ray irradiation were evaluated.
- three OS transistors OS transistors OSTr8 to OStransistor OSTr10 are used as samples. Note that descriptions of portions that overlap with ⁇ evaluation 1> or ⁇ evaluation 2> may be omitted.
- the substrate was placed in the X-ray irradiation apparatus, and static elimination was performed for 5 minutes using an ionizer (step S11 in FIG. 68).
- Id-Vg measurement of the OS transistor was performed before X-ray irradiation (step S12 in FIG. 68).
- the conditions for Id-Vg measurement were changed for each sample.
- the OS transistor OSTr8 and the OS transistor OSTr9 respectively set the drain voltage Vd to 0.1 V, the source voltage Vs and the back gate voltage Vbg to 0 V, and sweep the gate voltage Vg from 0 V to +3 V and then from +3 V to 0 V.
- the drain current Id at the time of the measurement was measured.
- the drain voltage Vd is set to 1.2 V
- the source voltage Vs and the back gate voltage Vbg are set to 0 V
- the gate voltage Vg is swept from 0 V to +3 V
- the drain current Id when swept from +3 V to 0 V is It was measured.
- the measurement at the drain voltage Vd of 0.1 V and the measurement at 1.2 V were alternately repeated, and a total of 5 sets of measurements were performed (5 measurements at the drain voltage Vd of 0.1 V; 5 measurements at 2V). Note that the substrate temperature during the Id-Vg measurement was all room temperature.
- the drain current Id of the OS transistor OSTr10 was measured when the drain voltage Vd was set to 0.1V, the source voltage Vs and the back gate voltage Vbg were set to 0V, and the gate voltage Vg was swept from -4V to +4V. Subsequently, the drain current Id was measured when the drain voltage Vd was set to 1.2V, the source voltage Vs and the back gate voltage Vbg were set to 0V, and the gate voltage Vg was swept from -4V to +4V. The measurement at the drain voltage Vd of 0.1 V and the measurement at 1.2 V were alternately repeated, and a total of 5 sets of measurements were performed (5 measurements at the drain voltage Vd of 0.1 V; 5 measurements at 2V). Note that the substrate temperature during the Id-Vg measurement was all room temperature.
- the OS transistor was irradiated with X-rays (step S13 in FIG. 68). All terminals (source, drain, gate, and back gate) of the OS transistor were grounded during X-ray irradiation.
- the X-ray irradiation dose was 100 Gy, and the X-ray dose rate was 35.0 Gy/hr.
- step S14 in FIG. 68 The conditions for the Id-Vg measurement were the same as those for the Id-Vg measurement before X-ray irradiation (step S12 in FIG. 68).
- Each of the OS transistor OSTr8 and the OS transistor OSTr9 repeated the X-ray irradiation (step S13 in FIG. 68) and the Id-Vg measurement (step S14 in FIG. 68) until the total dose of the irradiated X-rays reached 3000 Gy.
- the OS transistor OSTr10 repeated the above-described X-ray irradiation (step S13 in FIG. 68) and Id-Vg measurement (step S14 in FIG. 68) until the total dose of irradiated X-rays reached 1000 Gy.
- step S15 in FIG. 68 All terminals (source, drain, gate, and back gate) of the OS transistor were grounded when left unattended.
- step S16 in FIG. 68 the Id-Vg measurement of the OS transistor was performed (step S16 in FIG. 68).
- the conditions for the Id-Vg measurement were the same as those for the Id-Vg measurement before X-ray irradiation (step S12 in FIG. 68). Leaving at room temperature (step S15 in FIG. 68) and Id-Vg measurement (step S16 in FIG. 68) were repeated.
- FIGS. 69A and 69B show the Id-Vg characteristics when the total dose of X-rays irradiated in the OS transistor OSTr8 is 1000 Gy.
- the horizontal axis indicates the gate potential (Vg) and the vertical axis indicates the drain current (Id).
- FIG. 69A shows the first to fifth measurement data (1st_F, 2nd_F, 3rd_F, 4th_F and 5th_F) in which the drain voltage Vd is 0.1 V and the gate voltage (Vg) is swept from 0 V to +3 V. .
- FIG. 69B shows measurement data obtained by sweeping the gate voltage (Vg) from 0V to +3V with the drain voltage Vd set to 0.1V, and measurement data obtained by sweeping the gate voltage (Vg) from +3V to 0V.
- Measured data (2nd_F), 2nd measured data swept from +3V to 0V (2nd_R), 5th measured data swept from 0V to +3V (5th_F), 5th measured data swept from +3V to 0V (5th_R) are shown overlaid.
- FIGS. 69A and 69B show the gate potential (Vg) on the horizontal axis in an enlarged range of
- 70A and 70B show the difference ( ⁇ Vth_his) between the threshold voltage when swept from 0 V to +3 V and the threshold voltage when swept from +3 V to 0 V in the OS transistor OSTr8.
- 70A and 70B the horizontal axis indicates the total dose of X-rays, and the vertical axis indicates the threshold voltage difference ( ⁇ Vth_his).
- the threshold voltage difference ( ⁇ Vth_his) indicates the difference between the threshold voltage when sweeping from +3V to 0V and the threshold voltage when sweeping from 0V to +3V.
- FIG. 70A shows data when the drain voltage Vd is 0.1V
- FIG. 70B shows data when the drain voltage Vd is 1.2V.
- the first measurement at a drain voltage Vd of 0.1 V tends to result in large fluctuations in the characteristics.
- the second to fifth measurements at a drain voltage Vd of 0.1 V show better characteristics than the first measurement at a drain voltage Vd of 0.1 V. It was found that the variation tended to be small. It was also found that the measurement at a drain voltage Vd of 1.2V tended to show less variation in characteristics than the first measurement at a drain voltage Vd of 0.1V.
- FIGS. 71A and 71B show changes in the threshold voltage of the OS transistor.
- the horizontal axis indicates time (Time) and the vertical axis indicates threshold voltage (Vth).
- the time (Time) shown in FIGS. 71A and 71B indicates a relative time when the last X-ray irradiation is completed, and a negative value repeats X-ray irradiation and Id-Vg measurement.
- a positive value indicates a period in which standing at room temperature and Id-Vg measurement were repeatedly performed after X-ray irradiation was completed.
- FIG. 71A shows data when the drain voltage Vd is 0.1V
- FIG. 71B shows data when the drain voltage Vd is 1.2V.
- plots in FIGS. 71A and 71B show median values of threshold voltages (Vth) obtained by five Id-Vg measurements, and error bars show maximum and minimum values.
- FIGS. 72A and 73A show the amount of change in the threshold voltage of the OS transistor when the drain voltage Vd is 0.1V.
- the horizontal axis indicates time (Time)
- the vertical axis indicates the amount of change in threshold voltage ( ⁇ Vth).
- FIG. 72A shows an enlarged range from ⁇ 12 hr to 0 hr on the horizontal axis, and shows the variation ( ⁇ Vth) of the threshold voltage during the period in which the X-ray irradiation and the Id-Vg measurement were repeatedly performed.
- FIGS. 72A and 73A each show the first to fifth data in an overlapping fashion.
- FIG. 72B shows a graph in which the horizontal axis of FIG. 72A is converted to the number of Id-Vg measurements.
- FIG. 73B shows a graph in which the horizontal axis of FIG. 73A is converted to the number of Id-Vg measurements.
- the horizontal axis indicates the number of Id-Vg measurements (measurement count)
- the vertical axis indicates the amount of change in threshold voltage ( ⁇ Vth).
- the number of times (measurement count) indicates the relative number of times when the first Id-Vg measurement after the end of X-ray irradiation (the first Id-Vg measurement in step S16 of FIG. 68) is zero.
- FIG. 71A plots the median value of threshold voltages (Vth) obtained from five Id-Vg measurements.
- FIG. 75A shows the superimposed data of the first to fifth times regarding the variation in the threshold voltage of the OS transistor OSTr8.
- the horizontal axis indicates time (Time) [h], and the vertical axis indicates the amount of change in threshold voltage ( ⁇ Vth_recovery) [V].
- the time (Time) shown in FIG. 75A indicates the relative time when the last X-ray irradiation is completed, and the negative value is the period during which X-ray irradiation and Id-Vg measurement are repeated ( A positive value indicates a period (recovery) in which standing at room temperature and Id-Vg measurement were repeatedly performed after the end of X-ray irradiation.
- the vertical axis is adjusted so that ⁇ Vth in the Id-Vg measurement performed when the last X-ray irradiation is completed (when the horizontal axis is zero) is zero.
- FIG. 75B shows the results of the period in which the standing at room temperature and the Id-Vg measurement were repeatedly performed after the X-ray irradiation was completed.
- 76A to 76C show variations in the threshold voltage Vth, subthreshold slope SS, and field effect mobility ⁇ FE of the OS transistor OSTr8.
- FIG. 76A plots the amount of change in threshold voltage ( ⁇ Vth).
- the horizontal axis indicates the total dose of X-rays (Total Dose) [Gy], and the vertical axis indicates ⁇ Vth [V].
- the plot in FIG. 76A shows the median value of ⁇ Vth obtained from five Id-Vg measurements, and the error bars indicate the maximum and minimum values.
- FIG. 76B plots the normalized subthreshold slope SS.
- the horizontal axis indicates the total dose of X-rays (Total Dose) [Gy]
- the vertical axis indicates the normalized SS (Normalized SS).
- the plot in FIG. 76B also shows the median normalized SS values obtained from five Id-Vg measurements, with error bars indicating the maximum and minimum values.
- FIG. 76C plots the normalized field effect mobility ⁇ FE.
- the horizontal axis indicates the total dose (Gy) of X-rays
- the vertical axis indicates the normalized field effect mobility ⁇ FE (Normalized ⁇ FE).
- the plot in FIG. 76C shows the median normalized ⁇ FE obtained from five Id-Vg measurements, with error bars indicating the maximum and minimum values.
- 77A and 77B show the top gate voltage ("Vgs” in the figure)-drain current (“Id” in the figure) characteristics of the OS transistor OSTr8.
- the top gate voltage-drain current characteristics shown in FIG. 77A are such that when the drain voltage to the source is 0.1 V, the source voltage is 0 V, and the temperature of the measurement environment is 27° C., the back gate voltage Vbs to the source is 2 V from +2 V to ⁇ 6 V. These are the results of measurements taken at intervals.
- top gate voltage-drain current characteristics shown in FIG. 77B were measured at a temperature of 125° C., 27° C., or ⁇ 40° C. at a drain voltage of 0.1 V relative to the source and a source voltage and a back gate voltage of 0 V. This is the result.
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Abstract
Description
図2Aおよび図2Bは本発明の一態様である半導体装置の断面図である。
図3Aは本発明の一態様である半導体装置の上面図である。図3B乃至図3Dは本発明の一態様である半導体装置の断面図である。
図4Aは本発明の一態様である半導体装置の上面図である。図4B乃至図4Dは本発明の一態様である半導体装置の断面図である。
図5Aは本発明の一態様である半導体装置の上面図である。図5B乃至図5Dは本発明の一態様である半導体装置の断面図である。
図6Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図6B乃至図6Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図7Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図7B乃至図7Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図8Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図8B乃至図8Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図9Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図9B乃至図9Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図10Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図10B乃至図10Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図11Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図11B乃至図11Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図12Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図12B乃至図12Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図13Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図13B乃至図13Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図14Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図14B乃至図14Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図15Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図15B乃至図15Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図16Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図16B乃至図16Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図17Aは本発明の一態様である半導体装置の作製方法を示す上面図である。図17B乃至図17Dは本発明の一態様である半導体装置の作製方法を示す断面図である。
図18は本発明の一態様に係るマイクロ波処理装置を説明する上面図である。
図19は本発明の一態様に係るマイクロ波処理装置を説明する断面図である。
図20は本発明の一態様に係るマイクロ波処理装置を説明する断面図である。
図21は本発明の一態様に係るマイクロ波処理装置を説明する断面図である。
図22Aは本発明の一態様に係る半導体装置の平面図である。図22Bおよび図22Cは本発明の一態様である半導体装置の断面図である。
図23は、半導体装置の回路図を示す図である。
図24Aは、半導体装置の斜視図である。図24Bは、半導体装置の構成を説明する斜視図である。
図25A及び図25Bは、本発明の一態様の半導体装置が有するトランジスタ群のレイアウトを説明する上面図である。
図26A及び図26Bは、本発明の一態様の半導体装置が有するトランジスタ群のレイアウトを説明する上面図である。
図27A及び図27Bは、本発明の一態様の半導体装置が有するトランジスタ群のレイアウトを説明する上面図である。
図28A及び図28Bは、本発明の一態様の半導体装置が有するトランジスタ群のレイアウトを説明する上面図である。
図29は本発明の一態様に係る記憶装置の構成を示す断面図である。
図30は本発明の一態様に係る記憶装置の構成を示す断面図である。
図31は本発明の一態様に係る半導体装置の断面図である。
図32Aおよび図32Bは本発明の一態様に係る半導体装置の断面図である。
図33は本発明の一態様に係る半導体装置の断面図である。
図34Aは本発明の一態様に係る記憶装置の構成例を示すブロック図である。図34Bは本発明の一態様に係る記憶装置の構成例を示す斜視図である。
図35A乃至図35Hは本発明の一態様に係る記憶装置の構成例を示す回路図である。
図36Aおよび図36Bは本発明の一態様に係る半導体装置の模式図である。
図37は、CPUの構成例を説明する図である。
図38Aおよび図38Bは、CPUの構成例を説明する図である。
図39は、CPUの構成例を示す図である。
図40Aおよび図40Bは電子部品の一例を説明する図である。
図41A乃至図41Eは本発明の一態様に係る記憶装置の模式図である。
図42A乃至図42Hは本発明の一態様に係る電子機器を示す図である。
図43は、加熱処理温度と酸化物のシート抵抗の相関を説明する図である。
図44A及び図44Bは、試作したトランジスタのId−Vg特性を示す図である。
図45A1、図45B1、図45C1、及び図45D1は、容量を説明する図である。図45A2、図45B2、図45C2、及び図45D2は、試作したトランジスタのゲート電圧−容量特性を示す図である。
図46は、試作したトランジスタの測定環境の温度−オフ電流特性を示す図である。
図47は、半導体装置の断面TEM写真である。
図48は、TEGの配置を説明する図である。
図49A乃至図49Fは、トランジスタのしきい値電圧ばらつきを説明する図である。
図50A乃至図50Fは、トランジスタのしきい値電圧ばらつきを説明する図である。
図51A乃至図51Fは、トランジスタの電界効果移動度ばらつきを説明する図である。
図52A乃至図52Fは、トランジスタの電界効果移動度ばらつきを説明する図である。
図53A及び図53Bは、トランジスタの配列方法を説明する図である。
図54A及び図54Bは、トランジスタのId−Vg特性を示す図である。
図55A乃至図55Cは、トランジスタのしきい値電圧ばらつきを説明する図である。
図56Aは本実施例に係る半導体装置の上面図である。図56B乃至図56Dは本実施例に係る半導体装置の断面図である。
図57は、本実施例に係る+GBTストレス試験におけるΔVshのストレス時間依存性を示す図である。
図58は、X線照射後の、OSトランジスタのVthの時間依存性を説明する図である。
図59は、X線照射後の、OSトランジスタのS値の時間依存性を説明する図である。
図60Aは、OSトランジスタのVthのX線の合計線量依存性を説明する図である。図60Bは、OSトランジスタのS値のX線の合計線量依存性を説明する図である。図60C及び図60Dは、計算の結果を示す図である。
図61A乃至図61Cは、計算に用いたトランジスタ構造を説明する図である。
図62は、試作したチップの光学顕微鏡写真である。
図63は、試作したOSフリップフロップの回路図である。
図64A及び図64Bは、OSトランジスタのしきい値電圧のX線の合計線量依存性を示す図である。
図65は、OSトランジスタのしきい値電圧のX線の合計線量依存性を示す図である。
図66A及び図66Bは、OSトランジスタのしきい値電圧のX線の合計線量依存性を示す図である。
図67は、OSトランジスタのしきい値電圧のX線の合計線量依存性を示す図である。
図68は、X線照射試験方法を示すフローチャートである。
図69A及び図69Bは、OSトランジスタのId−Vg特性を示す図である。
図70A及び図70Bは、OSトランジスタのしきい値電圧の差を示す図である。
図71A及び図71Bは、OSトランジスタのしきい値電圧の変動を示す図である。
図72A及び図72Bは、OSトランジスタのしきい値電圧の変動量を示す図である。
図73A及び図73Bは、OSトランジスタのしきい値電圧の変動量を示す図である。
図74は、X線照射試験の評価環境を説明する図である。
図75Aおよび図75Bは、OSトランジスタのしきい値電圧の変動量を示す図である。
図76Aは、OSトランジスタのしきい値電圧の変動量を示す図である。図76Bは、OSトランジスタのSSの変動量を示す図である。図76Cは、OSトランジスタの電界効果移動度の変動量を示す図である。
図77A及び図77Bは、試作したトランジスタのId−Vg特性を示す図である。
本実施の形態では、図1A乃至図22Cを用いて、本発明の一態様に係るトランジスタ200を有する半導体装置の一例、およびその作製方法について説明する。
図1を用いて、トランジスタ200を有する半導体装置の構成を説明する。図1A乃至図1Dは、トランジスタ200を有する半導体装置の上面図および断面図である。図1Aは、当該半導体装置の上面図である。また、図1B乃至図1Dは、当該半導体装置の断面図である。ここで、図1Bは、図1AにA1−A2の一点鎖線で示す部位の断面図であり、トランジスタ200のチャネル長方向の断面図でもある。また、図1Cは、図1AにA3−A4の一点鎖線で示す部位の断面図であり、トランジスタ200のチャネル幅方向の断面図でもある。また、図1Dは、図1AにA5−A6の一点鎖線で示す部位の断面図である。なお、図1Aの上面図では、図の明瞭化のために一部の要素を省いている。
図1A乃至図1Dに示すように、トランジスタ200は、絶縁体214上の絶縁体216と、絶縁体216に埋め込まれるように配置された導電体205(導電体205aおよび導電体205b)と、絶縁体216上、および導電体205上の絶縁体222と、絶縁体222上の絶縁体224と、絶縁体224上の酸化物230aと、酸化物230a上の酸化物230bと、酸化物230b上の導電体242aと、導電体242a上の絶縁体271aと、酸化物230b上の導電体242bと、導電体242b上の絶縁体271bと、酸化物230b上の絶縁体252と、絶縁体252上の絶縁体250と、絶縁体250上の絶縁体254と、絶縁体254上に位置し、酸化物230bの一部と重なる導電体260(導電体260aおよび導電体260b)と、絶縁体222、絶縁体224、酸化物230a、酸化物230b、導電体242a、導電体242b、絶縁体271a、および絶縁体271b上に配置される絶縁体275と、を有する。ここで、図1Bおよび図1Cに示すように、絶縁体252は、絶縁体222の上面、絶縁体224の側面、酸化物230aの側面、酸化物230bの側面および上面、導電体242の側面、絶縁体271の側面、絶縁体275の側面、絶縁体280の側面、および絶縁体250の下面と接する。また、導電体260の上面は、絶縁体254の最上部、絶縁体250の最上部、絶縁体252の最上部、および絶縁体280の上面と高さが概略一致するように配置される。また、絶縁体282は、導電体260、絶縁体252、絶縁体250、絶縁体254、および絶縁体280のそれぞれの上面の少なくとも一部と接する。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムを材料とした半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、SOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いることが好ましい。例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、半導体として機能する金属酸化物(酸化物半導体)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
酸化物半導体の結晶構造としては、アモルファス(completely amorphousを含む)、CAAC(c−axis−aligned crystalline)、nc(nanocrystalline)、CAC(cloud−aligned composite)、単結晶(single crystal)、および多結晶(poly crystal)等が挙げられる。
なお、酸化物半導体は、構造に着目した場合、上記とは異なる分類となる場合がある。例えば、酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、上述のCAAC−OS、及びnc−OSがある。また、非単結晶酸化物半導体には、多結晶酸化物半導体、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)、非晶質酸化物半導体、などが含まれる。
CAAC−OSは、複数の結晶領域を有し、当該複数の結晶領域はc軸が特定の方向に配向している酸化物半導体である。なお、特定の方向とは、CAAC−OS膜の厚さ方向、CAAC−OS膜の被形成面の法線方向、またはCAAC−OS膜の表面の法線方向である。また、結晶領域とは、原子配列に周期性を有する領域である。なお、原子配列を格子配列とみなすと、結晶領域とは、格子配列の揃った領域でもある。さらに、CAAC−OSは、a−b面方向において複数の結晶領域が連結する領域を有し、当該領域は歪みを有する場合がある。なお、歪みとは、複数の結晶領域が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。つまり、CAAC−OSは、c軸配向し、a−b面方向には明らかな配向をしていない酸化物半導体である。
nc−OSは、微小な領域(例えば、1nm以上10nm以下の領域、特に1nm以上3nm以下の領域)において原子配列に周期性を有する。別言すると、nc−OSは、微小な結晶を有する。なお、当該微小な結晶の大きさは、例えば、1nm以上10nm以下、特に1nm以上3nm以下であることから、当該微小な結晶をナノ結晶ともいう。また、nc−OSは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、nc−OSは、分析方法によっては、a−like OSまたは非晶質酸化物半導体と区別が付かない場合がある。例えば、nc−OS膜に対し、XRD装置を用いて構造解析を行うと、θ/2θスキャンを用いたOut−of−plane XRD測定では、結晶性を示すピークが検出されない。また、nc−OS膜に対し、ナノ結晶よりも大きいプローブ径(例えば50nm以上)の電子線を用いる電子線回折(制限視野電子線回折ともいう)を行うと、ハローパターンのような回折パターンが観測される。一方、nc−OS膜に対し、ナノ結晶の大きさと近いかナノ結晶より小さいプローブ径(例えば1nm以上30nm以下)の電子線を用いる電子線回折(ナノビーム電子線回折ともいう)を行うと、ダイレクトスポットを中心とするリング状の領域内に複数のスポットが観測される電子線回折パターンが取得される場合がある。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。a−like OSは、鬆又は低密度領域を有する。即ち、a−like OSは、nc−OS及びCAAC−OSと比べて、結晶性が低い。また、a−like OSは、nc−OS及びCAAC−OSと比べて、膜中の水素濃度が高い。
次に、上述のCAC−OSの詳細について、説明を行う。なお、CAC−OSは材料構成に関する。
CAC−OSとは、例えば、金属酸化物を構成する元素が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つまたは複数の金属元素が偏在し、該金属元素を有する領域が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
酸化物230に用いることができる半導体材料は、上述の金属酸化物に限られない。酸化物230として、バンドギャップを有する半導体材料(ゼロギャップ半導体ではない半導体材料)を用いてもよい。例えば、シリコンなどの単体元素の半導体、ヒ化ガリウムなどの化合物半導体、半導体として機能する層状物質(原子層物質、2次元材料などともいう)などを半導体材料に用いることが好ましい。特に、半導体として機能する層状物質を半導体材料に用いると好適である。
次に、図1A乃至図1Dに示す、本発明の一態様である半導体装置の作製方法を、図6A乃至図17Dを用いて説明する。
以下では、上記半導体装置の作製方法に用いることができる、マイクロ波処理装置について説明する。
以下では、図3A乃至図5Dを用いて、本発明の一態様である半導体装置の一例について説明する。
図3A乃至図3Dに示す半導体装置は、図1A乃至図1Dに示した半導体装置の変形例である。図3A乃至図3Dに示す半導体装置は、図1A乃至図1Dに示した半導体装置とは、絶縁体282が設けられていないことが異なる。従って、図3A乃至図3Dに示す半導体装置では、絶縁体283が、導電体260の上面、絶縁体280の上面、絶縁体254の最上部、絶縁体250の最上部、および絶縁体252の最上部に接する。
図4A乃至図4Dに示す半導体装置は、図1A乃至図1Dに示した半導体装置の変形例である。図4A乃至図4Dに示す半導体装置は、図1A乃至図1Dに示した半導体装置とは、酸化物243(酸化物243a、酸化物243b)が設けられていることが異なる。酸化物243aは、酸化物230bと導電体242aの間に設けられ、酸化物243bは、酸化物230bと導電体242bの間に設けられる。ここで、酸化物243aは、酸化物230bの上面、および導電体242aの下面に接することが好ましい。また、酸化物243bは、酸化物230bの上面、および導電体242bの下面に接することが好ましい。
図5A乃至図5Dに示す半導体装置は、図1A乃至図1Dに示した半導体装置の変形例である。図5A乃至図5Dに示す半導体装置は、図1A乃至図1Dに示した半導体装置とは、絶縁体283が、絶縁体212の上面の一部と接する構造となっているところが異なる。従って、トランジスタ200は、絶縁体283および絶縁体212で封止された領域内に配置される。上記構成にすることで、上記封止された領域外に含まれる水素が、上記封止された領域内に混入することを抑制できる。また、図5A乃至図5Dに示すトランジスタ200では、絶縁体212および絶縁体283を、単層として設ける構成について示しているが、本発明はこれに限られるものではない。例えば、絶縁体212および絶縁体283のそれぞれを2層以上の積層構造として設ける構成にしてもよい。
以下では、図22を用いて、本発明の一態様である半導体装置の一例について説明する。
本実施例では、半導体装置の一形態を、図23及び図24を用いて説明する。本実施の形態で説明する半導体装置は、多点測定が可能な評価用素子(TEGともいう)である。
次に、図23に示すTEG900が有するトランジスタ群TRAのレイアウトについて、図25A乃至図28Bを用いて説明する。
本実施の形態では、半導体装置の一形態を、図29乃至図33を用いて説明する。
本発明の一態様に係る半導体装置(記憶装置)の一例を図29に示す。本発明の一態様の半導体装置では、トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ300、およびトランジスタ200の上方に設けられている。なお、トランジスタ200として、先の実施の形態で説明したトランジスタ200を用いることができる。
トランジスタ300は、基板311上に設けられ、ゲートとして機能する導電体316、ゲート絶縁体として機能する絶縁体315、基板311の一部からなる半導体領域313、およびソース領域またはドレイン領域として機能する低抵抗領域314a、および低抵抗領域314bを有する。トランジスタ300は、pチャネル型、あるいはnチャネル型のいずれでもよい。
容量素子100は、トランジスタ200の上方に設けられる。容量素子100は、第1の電極として機能する導電体110、第2の電極として機能する導電体120、および誘電体として機能する絶縁体130を有する。ここで、絶縁体130は、上記実施の形態に示す絶縁体283として用いることができる絶縁体を用いることが好ましい。
各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線としての機能を有する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。
なお、トランジスタ200に、酸化物半導体を用いる場合、酸化物半導体の近傍に過剰酸素領域を有する絶縁体を設けることがある。その場合、該過剰酸素領域を有する絶縁体と、該過剰酸素領域を有する絶縁体に設ける導電体との間に、バリア性を有する絶縁体を設けることが好ましい。
以下では、大面積基板を半導体素子ごとに分断することによって、複数の半導体装置をチップ状で取り出す場合に設けられるダイシングライン(スクライブライン、分断ライン、又は切断ラインと呼ぶ場合がある)について説明する。分断方法としては、例えば、まず、基板に半導体素子を分断するための溝(ダイシングライン)を形成した後、ダイシングラインにおいて切断し、複数の半導体装置に分断(分割)する場合がある。
本発明の一態様に係る半導体装置(記憶装置)の一例を図31に示す。
図31は、メモリデバイス290を有する半導体装置の断面図である。図31に示すメモリデバイス290は、図1A乃至図1Dに示すトランジスタ200に加えて、容量デバイス292を有する。図31は、トランジスタ200のチャネル長方向の断面図に相当する。
以下では、図32A、図32B、および図33を用いて、先の<メモリデバイスの構成例>で示したものとは異なる、本発明の一態様に係るトランジスタ200、および容量デバイス292を有する半導体装置の一例について説明する。なお図32A、図32B、および図33に示す半導体装置において、先の実施の形態および<メモリデバイスの構成例>に示した半導体装置(図31参照)を構成する構造と同機能を有する構造には、同符号を付記する。なお、本項目において、トランジスタ200、および容量デバイス292の構成材料については、先の実施の形態および<メモリデバイスの構成例>で詳細に説明した材料を用いることができる。また、図32A、図32B、および図33などでは、メモリデバイスとして、図31に示すメモリデバイスを用いているが、これに限られるものではない。
以下では、本発明の一態様に係るトランジスタ200a、トランジスタ200b、容量デバイス292a、および容量デバイス292bを有する半導体装置600の一例について図32Aを用いて説明する。
上記においては、半導体装置の構成例としてトランジスタ200a、トランジスタ200b、容量デバイス292aおよび容量デバイス292bを挙げたが、本実施の形態に示す半導体装置はこれに限られるものではない。例えば、図32Bに示すように半導体装置600と、半導体装置600と同様の構成を有する半導体装置が容量部を介して接続されている構成としてもよい。本明細書では、トランジスタ200a、トランジスタ200b、容量デバイス292a、および容量デバイス292bを有する半導体装置をセルと称する。トランジスタ200a、トランジスタ200b、容量デバイス292aおよび容量デバイス292bの構成については、上述のトランジスタ200a、トランジスタ200b、容量デバイス292aおよび容量デバイス292bに係る記載を参酌できる。
本実施の形態では、図34A、図34Bおよび図35A乃至図35Hを用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ場合がある)、および容量素子が適用されている記憶装置(以下、OSメモリ装置と呼ぶ場合がある)について説明する。OSメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するOSトランジスタを有する記憶装置である。OSトランジスタのオフ電流は極めて小さいため、OSメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。
図34AにOSメモリ装置の構成の一例を示す。記憶装置1400は、周辺回路1411、およびメモリセルアレイ1470を有する。周辺回路1411は、行回路1420、列回路1430、出力回路1440、およびコントロールロジック回路1460を有する。
図35A乃至図35Cに、DRAMのメモリセルの回路構成例を示す。本明細書等において、1OSトランジスタ1容量素子型のメモリセルを用いたDRAMを、DOSRAM(Dynamic Oxide Semiconductor Random Access Memory)と呼ぶ場合がある。図35Aに示す、メモリセル1471は、トランジスタM1と、容量素子CAと、を有する。なお、トランジスタM1は、ゲート(トップゲートと呼ぶ場合がある)、及びバックゲートを有する。
図35D乃至図35Gに、2トランジスタ1容量素子のゲインセル型のメモリセルの回路構成例を示す。図35Dに示す、メモリセル1474は、トランジスタM2と、トランジスタM3と、容量素子CBと、を有する。なお、トランジスタM2は、トップゲート(単にゲートと呼ぶ場合がある)、及びバックゲートを有する。本明細書等において、トランジスタM2にOSトランジスタを用いたゲインセル型のメモリセルを有する記憶装置を、NOSRAM(Nonvolatile Oxide Semiconductor RAM)と呼ぶ場合がある。
本実施の形態では、図36Aおよび図36Bを用いて、本発明の半導体装置が実装されたチップ1200の一例を示す。チップ1200には、複数の回路(システム)が実装されている。このように、複数の回路(システム)を一つのチップに集積する技術を、システムオンチップ(System on Chip:SoC)と呼ぶ場合がある。
本実施の形態では、上記実施の形態で説明したCPUとして機能する半導体装置について説明する。本実施の形態で説明する半導体装置は、極低消費電力での動作が可能なCPUとして機能する半導体装置である。
本実施の形態は、上記実施の形態に示す記憶装置などが組み込まれた電子部品および電子機器の一例を示す。
まず、記憶装置720が組み込まれた電子部品の例を、図40Aおよび図40Bを用いて説明を行う。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータ、ノート型のコンピュータ、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード(例えば、SDカード)、USBメモリ、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用される。図41A乃至図41Eにリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。
本発明の一態様に係る半導体装置は、CPU、GPUなどのプロセッサ、またはチップに用いることができる。図42A乃至図42Hに、本発明の一態様に係るCPU、GPUなどのプロセッサ、またはチップを備えた電子機器の具体例を示す。
本発明の一態様に係るGPUまたはチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型またはノート型の情報端末用などのモニタ、デジタルサイネージ(Digital Signage:電子看板)、パチンコ機などの大型ゲーム機、などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、電子ブックリーダー、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係るGPUまたはチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。
図42Aには、情報端末の一種である携帯電話(スマートフォン)が図示されている。情報端末5100は、筐体5101と、表示部5102と、を有しており、入力用インターフェースとして、タッチパネルが表示部5102に備えられ、ボタンが筐体5101に備えられている。
図42Cは、ゲーム機の一例である携帯ゲーム機5300を示している。携帯ゲーム機5300は、筐体5301、筐体5302、筐体5303、表示部5304、接続部5305、操作キー5306等を有する。筐体5302、および筐体5303は、筐体5301から取り外すことが可能である。筐体5301に設けられている接続部5305を別の筐体(図示せず)に取り付けることで、表示部5304に出力される映像を、別の映像機器(図示せず)に出力することができる。このとき、筐体5302、および筐体5303は、それぞれ操作部として機能することができる。これにより、複数のプレイヤーが同時にゲームを行うことができる。筐体5301、筐体5302、および筐体5303の基板に設けられているチップなどに先の実施の形態に示すチップを組み込むことができる。
本発明の一態様のGPUまたはチップは、大型コンピュータに適用することができる。
本発明の一態様のGPUまたはチップは、移動体である自動車、および自動車の運転席周辺に適用することができる。
図42Hは、電化製品の一例である電気冷凍冷蔵庫5800を示している。電気冷凍冷蔵庫5800は、筐体5801、冷蔵室用扉5802、冷凍室用扉5803等を有する。
ここでは、基板に形成したトランジスタの、電気特性ばらつきの評価を行った結果について説明する。
ここでは、トランジスタTr[1,1]乃至トランジスタTr[m,n]の配列方法による、トランジスタの電気特性のばらつきへの影響について評価した。
本項では、OSトランジスタにX線を照射したときのVth及びS値の変動傾向について、計算を用いて評価した。
試料でX線の線量率を異ならせ、X線照射に対するOSトランジスタの電気特性の変動を評価した。ここでは、試料として、2つのOSトランジスタ(OSトランジスタOSTr3、およびOSトランジスタOSTr4)を用いた。なお、OSトランジスタOSTr3及びOSトランジスタOSTr4をまとめてOSトランジスタと表記する場合がある。
前述の<評価1>とId−Vg測定及びX線照射の条件を異ならせて、X線照射に対するOSトランジスタの電気特性の変動を評価した。ここでは、試料として、3つのOSトランジスタ(OSトランジスタOSTr5乃至OSトランジスタOSTr7)を用いた。なお、<評価1>と重複する部分は説明を省略する場合がある。
前述の<評価1>及び<評価2>とId−Vg測定及びX線照射の条件を異ならせて、X線照射に対するOSトランジスタの電気特性の変動を評価した。ここでは、試料として、3つのOSトランジスタ(OSトランジスタOSTr8乃至OSトランジスタOSTr10)を用いた。なお、<評価1>または<評価2>と重複する部分は説明を省略する場合がある。
Claims (18)
- 第1の層と、前記第1の層上の第2の層と、第1の配線と、第2の配線と、第3の配線と、を有し、
前記第1の層は、第1のマルチプレクサと、第2のマルチプレクサと、第1乃至第4のアナログスイッチと、を有し、
前記第2の層は、第1乃至第4のトランジスタを有し、
前記第1乃至第4のトランジスタのそれぞれは、ソースと、ドレインと、第1のゲートと、を有し、
前記第1の配線は、前記第1乃至第4のトランジスタそれぞれのソース及びドレインの一方と電気的に接続し、
前記第1のアナログスイッチ、及び前記第2のアナログスイッチそれぞれの第1端子は、前記第1のマルチプレクサと電気的に接続し、
前記第1のアナログスイッチ、及び前記第2のアナログスイッチそれぞれの第2端子は、前記第2の配線と電気的に接続し、
前記第1のアナログスイッチの第3端子は、前記第1のトランジスタ、及び前記第2のトランジスタそれぞれのソース及びドレインの他方と電気的に接続し、
前記第2のアナログスイッチの第3端子は、前記第3のトランジスタ、及び前記第4のトランジスタそれぞれのソース及びドレインの他方と電気的に接続し、
前記第3のアナログスイッチ、及び前記第4のアナログスイッチそれぞれの第1端子は、前記第2のマルチプレクサと電気的に接続し、
前記第3のアナログスイッチ、及び前記第4のアナログスイッチそれぞれの第2端子は、前記第3の配線と電気的に接続し、
前記第3のアナログスイッチの第3端子は、前記第1のトランジスタ、及び前記第3のトランジスタそれぞれの第1のゲートと電気的に接続し、
前記第4のアナログスイッチの第3端子は、前記第2のトランジスタ、及び前記第4のトランジスタそれぞれの第1のゲートと電気的に接続している、
半導体装置。 - 請求項1において、
第4の配線をさらに有し、
前記第1乃至第4のトランジスタのそれぞれは、第2のゲートをさらに有し、
前記第4の配線は、前記第1乃至第4のトランジスタそれぞれの第2のゲートと電気的に接続している、
半導体装置。 - 請求項1又は請求項2において、
前記第1乃至第4のトランジスタのそれぞれは、チャネル形成領域に金属酸化物を有する、
半導体装置。 - 請求項3において、
前記金属酸化物は、インジウムと、ガリウムと、亜鉛と、を有する、
半導体装置。 - 請求項1乃至請求項4のいずれか一項において、
前記第1乃至第4のアナログスイッチのそれぞれは、CMOS回路で構成される、
半導体装置。 - 請求項5において、
前記CMOS回路が有するトランジスタは、チャネル形成領域にシリコンを有する、
半導体装置。 - 第1の層と、前記第1の層上の第2の層と、第1の配線と、第2の配線と、第3の配線と、を有し、
前記第1の層は、第1のマルチプレクサと、第2のマルチプレクサと、第1乃至第3のアナログスイッチと、を有し、
前記第2の層は、第1のトランジスタと、第3のトランジスタと、を有し、
前記第1のトランジスタ、及び前記第3のトランジスタのそれぞれは、ソースと、ドレインと、第1のゲートと、を有し、
前記第1の配線は、前記第1のトランジスタ及び前記第3のトランジスタそれぞれのソース及びドレインの一方と電気的に接続し、
前記第1のアナログスイッチ、及び前記第2のアナログスイッチそれぞれの第1端子は、前記第1のマルチプレクサと電気的に接続し、
前記第1のアナログスイッチ、及び前記第2のアナログスイッチそれぞれの第2端子は、前記第2の配線と電気的に接続し、
前記第1のアナログスイッチの第3端子は、前記第1のトランジスタのソース及びドレインの他方と電気的に接続し、
前記第2のアナログスイッチの第3端子は、前記第3のトランジスタのソース及びドレインの他方と電気的に接続し、
前記第3のアナログスイッチの第1端子は、前記第2のマルチプレクサと電気的に接続し、
前記第3のアナログスイッチの第2端子は、前記第3の配線と電気的に接続し、
前記第3のアナログスイッチの第3端子は、前記第1のトランジスタ、及び前記第3のトランジスタそれぞれの第1のゲートと電気的に接続している、
半導体装置。 - 請求項7において、
第4の配線をさらに有し、
前記第1のトランジスタ及び前記第3のトランジスタのそれぞれは、第2のゲートをさらに有し、
前記第4の配線は、前記第1のトランジスタ及び前記第3のトランジスタそれぞれの第2のゲートと電気的に接続している、
半導体装置。 - 請求項7又は請求項8において、
前記第1のトランジスタ及び前記第3のトランジスタのそれぞれは、チャネル形成領域に金属酸化物を有する、
半導体装置。 - 請求項9において、
前記金属酸化物は、インジウムと、ガリウムと、亜鉛と、を有する、
半導体装置。 - 請求項7乃至請求項10のいずれか一項において、
前記第1乃至第3のアナログスイッチのそれぞれは、CMOS回路で構成される、
半導体装置。 - 請求項11において、
前記CMOS回路が有するトランジスタは、チャネル形成領域にシリコンを有する、
半導体装置。 - 第1の層と、前記第1の層上の第2の層と、第1の配線と、第2の配線と、第3の配線と、を有し、
前記第1の層は、第1のマルチプレクサと、第2のマルチプレクサと、第1のアナログスイッチと、第3のアナログスイッチと、第4のアナログスイッチと、を有し、
前記第2の層は、第1のトランジスタと、第2のトランジスタと、を有し、
前記第1のトランジスタ及び前記第2のトランジスタのそれぞれは、ソースと、ドレインと、第1のゲートと、を有し、
前記第1の配線は、前記第1のトランジスタ及び前記第2のトランジスタそれぞれのソース及びドレインの一方と電気的に接続し、
前記第1のアナログスイッチの第1端子は、前記第1のマルチプレクサと電気的に接続し、
前記第1のアナログスイッチの第2端子は、前記第2の配線と電気的に接続し、
前記第1のアナログスイッチの第3端子は、前記第1のトランジスタ、及び前記第2のトランジスタそれぞれのソース及びドレインの他方と電気的に接続し、
前記第3のアナログスイッチ、及び前記第4のアナログスイッチそれぞれの第1端子は、前記第2のマルチプレクサと電気的に接続し、
前記第3のアナログスイッチ、及び前記第4のアナログスイッチそれぞれの第2端子は、前記第3の配線と電気的に接続し、
前記第3のアナログスイッチの第3端子は、前記第1のトランジスタの第1のゲートと電気的に接続し、
前記第4のアナログスイッチの第3端子は、前記第2のトランジスタの第1のゲートと電気的に接続している、
半導体装置。 - 請求項13において、
第4の配線をさらに有し、
前記第1のトランジスタ及び前記第2のトランジスタのそれぞれは、第2のゲートをさらに有し、
前記第4の配線は、前記第1のトランジスタ及び前記第2のトランジスタそれぞれの第2のゲートと電気的に接続している、
半導体装置。 - 請求項13又は請求項14において、
前記第1のトランジスタ及び前記第2のトランジスタのそれぞれは、チャネル形成領域に金属酸化物を有する、
半導体装置。 - 請求項15において、
前記金属酸化物は、インジウムと、ガリウムと、亜鉛と、を有する、
半導体装置。 - 請求項13乃至請求項16のいずれか一項において、
前記第1のアナログスイッチ、前記第3のアナログスイッチ、及び前記第4のアナログスイッチのそれぞれは、CMOS回路で構成される、
半導体装置。 - 請求項17において、
前記CMOS回路が有するトランジスタは、チャネル形成領域にシリコンを有する、
半導体装置。
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CN107947763B (zh) | 2010-08-06 | 2021-12-28 | 株式会社半导体能源研究所 | 半导体集成电路 |
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JP2017085082A (ja) * | 2015-08-31 | 2017-05-18 | 株式会社半導体エネルギー研究所 | 半導体装置および電子機器 |
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