WO2022222297A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2022222297A1
WO2022222297A1 PCT/CN2021/108970 CN2021108970W WO2022222297A1 WO 2022222297 A1 WO2022222297 A1 WO 2022222297A1 CN 2021108970 W CN2021108970 W CN 2021108970W WO 2022222297 A1 WO2022222297 A1 WO 2022222297A1
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Prior art keywords
layer
barrier layer
substrate
conductive layer
semiconductor structure
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English (en)
French (fr)
Inventor
杨蒙蒙
白杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/579,817 priority Critical patent/US11864373B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • Embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure.
  • Metal Oxide Semiconductor Field Effect Transistor referred to as MOSFET
  • Metal oxide field effect transistors generally include P-type transistors (PMOS) and N-type transistors (NMOS) according to different doping types, and high-k dielectrics are usually set in these two types of transistors. layer to increase the breakdown voltage of the transistor.
  • a first barrier layer is usually first formed on a substrate, wherein the substrate includes a core region and a peripheral region disposed outside the core region; the first barrier layer in the peripheral region is removed, and the first barrier layer in the core region is retained.
  • a barrier layer; a dielectric layer and a first conductive layer are formed in sequence on the first barrier layer and the substrate in the peripheral area; the dielectric layer and the first conductive layer in the core area are removed, and the dielectric layer and the first conductive layer in the peripheral area are retained .
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including a core region and a peripheral region located outside the core region and adjacent to the core region, the A predetermined barrier layer is further formed on the substrate, the predetermined barrier layer covers the core region and the peripheral region; at least part of the predetermined barrier layer corresponding to the peripheral region is removed to expose part of the substrate, The remaining preset barrier layer forms a first barrier layer; a stacked dielectric layer and a first conductive layer are sequentially formed on the first barrier layer and the substrate; and part of the first barrier layer is removed A dielectric layer and a part of the first conductive layer, and a part of the dielectric layer and a part of the first conductive layer on the first barrier layer close to the peripheral region are retained.
  • a substrate in the manufacturing method of the semiconductor structure provided by the embodiment of the present application, includes a core region and a peripheral region located outside the core region and adjacent to the core region, and a predetermined barrier layer is also formed on the substrate, and the predetermined barrier layer covers The core area and the peripheral area; at least part of the preset barrier layer corresponding to the peripheral area is removed to expose part of the substrate, and the remaining preset barrier layer forms a first barrier layer; on the first barrier layer and the substrate, a stacked dielectric layer and The first conductive layer; part of the dielectric layer and part of the first conductive layer on the first barrier layer are removed, and part of the dielectric layer and part of the first conductive layer on the first barrier layer close to the peripheral region are retained.
  • part of the substrate covers the first barrier layer, part of the substrate covers the dielectric layer, and the first barrier layer and The dielectric layers are partially overlapped, thereby reducing the exposure of the substrate, reducing the risk of a portion of the substrate being removed, thereby reducing the risk of device exposure or even damage within the substrate.
  • embodiments of the present application provide a semiconductor structure, which includes: a substrate, the substrate includes a core region and a peripheral region located outside the core region and adjacent to the core region, wherein the substrate is further provided an active area; a first barrier layer arranged on the substrate, the first barrier layer covering at least the core area; a dielectric layer arranged on the substrate and part of the first barrier layer; arranged on the the first conductive layer on the dielectric layer.
  • the semiconductor structure provided by the embodiments of the present application includes a substrate, a first barrier layer, a dielectric layer, and a first conductive layer, wherein the substrate includes a core region and a peripheral region located outside the core region and adjacent to the core region, and the substrate is further provided with the source region; the first barrier layer is arranged on the substrate, the first barrier layer covers at least the core region; the medium layer is arranged on the substrate and part of the first barrier layer, and the first conductive layer is arranged on the medium layer.
  • part of the substrate covers the first barrier layer
  • part of the substrate covers the dielectric layer
  • the first barrier layer and the dielectric layer partially overlap, thereby reducing the exposure of the substrate. The risk of removing portions of the substrate is reduced, which in turn reduces the risk of exposure or even damage to devices within the substrate.
  • FIG. 1 is a cross-sectional view of a first cross-section in a core region after forming a first photoresist layer in the related art
  • FIG. 2 is a cross-sectional view of a second cross-section in the core region after the formation of the first photoresist layer in the related art
  • FIG. 3 is a cross-sectional view of the second cross-section in the peripheral region after the formation of the first photoresist layer in the related art
  • FIG. 4 is a cross-sectional view of the first cross-section in the core region after removing the first barrier layer corresponding to the peripheral region in the related art
  • FIG. 5 is a cross-sectional view of a second cross-section in the core region after removing the first barrier layer corresponding to the peripheral region in the related art
  • FIG. 6 is a cross-sectional view of the second cross section in the peripheral area after removing the first barrier layer corresponding to the peripheral area in the related art
  • FIG. 7 is a cross-sectional view of the first cross-section in the core region after forming the dielectric layer and the first conductive layer in the related art
  • FIG. 8 is a cross-sectional view of a second cross-section in the core region after forming a dielectric layer and a first conductive layer in the related art
  • FIG. 9 is a cross-sectional view of the second cross-section in the peripheral region after forming the dielectric layer and the first conductive layer in the related art
  • FIG. 10 is a cross-sectional view of the first cross section in the core region after the formation of the second photoresist layer in the related art
  • FIG. 11 is a cross-sectional view of the second cross section in the core region after forming the second photoresist layer in the related art
  • FIG. 12 is a cross-sectional view of the second cross-section in the peripheral region after forming the second photoresist layer in the related art
  • FIG. 13 is a cross-sectional view of the first cross section in the core region after removing the dielectric layer and the first conductive layer corresponding to the core region in the related art;
  • FIG. 14 is a cross-sectional view of a second cross-section in the core region after removing the dielectric layer and the first conductive layer corresponding to the core region in the related art;
  • 16 is a schematic diagram of a core area and a peripheral area handover area in the related art
  • 17 is a flowchart of a method for fabricating a semiconductor structure in an embodiment of the present application.
  • FIG. 18 is a cross-sectional view of a second cross-section after forming a first photoresist layer in an embodiment of the present application
  • 19 is a top view of the substrate in the embodiment of the application.
  • 20 is a cross-sectional view of the first cross-section in the core region after the first photoresist layer is formed in the embodiment of the present application;
  • 21 is a cross-sectional view of a third cross-section in the core region after the first photoresist layer is formed in an embodiment of the present application;
  • FIG. 22 is a top view after forming a first photoresist layer in an embodiment of the present application.
  • FIG. 23 is a cross-sectional view of a second cross-section after removing part of the first barrier layer in an embodiment of the present application.
  • FIG. 24 is a cross-sectional view of the first cross-section in the core region after removing part of the first barrier layer in the embodiment of the present application;
  • 25 is a cross-sectional view of a third cross-section in the core region after removing part of the first barrier layer in an embodiment of the present application;
  • 26 is a cross-sectional view of a second cross-section after removing the first photoresist layer in an embodiment of the present application
  • 27 is a cross-sectional view of the first cross-section in the core region after removing the first photoresist layer in an embodiment of the present application;
  • 29 is a cross-sectional view of a second cross-section after forming a dielectric layer in an embodiment of the application.
  • FIG. 30 is a cross-sectional view of the first cross-section in the core region after the formation of the dielectric layer in the embodiment of the application;
  • 31 is a cross-sectional view of the third cross-section in the core region after the formation of the dielectric layer in the embodiment of the application;
  • 34 is a cross-sectional view of a third cross-section in the core region after forming the first conductive layer in an embodiment of the present application;
  • 35 is a cross-sectional view of a second cross-section after forming the first photoresist layer in an embodiment of the present application
  • 36 is a cross-sectional view of the first cross section in the core region after forming the first photoresist layer in the embodiment of the application;
  • FIG. 37 is a cross-sectional view of a third cross-section in the core region after the first photoresist layer is formed in an embodiment of the present application;
  • 38 is a cross-sectional view of a second cross-section after removing part of the dielectric layer and the first conductive layer in an embodiment of the application;
  • 39 is a cross-sectional view of the first cross-section in the core region after removing part of the dielectric layer and the first conductive layer in an embodiment of the present application;
  • FIG. 40 is a cross-sectional view of a third cross-section in the core region after removing part of the dielectric layer and the first conductive layer in an embodiment of the present application;
  • 41 is a cross-sectional view of a second cross-section after removing the second photoresist layer in an embodiment of the present application
  • FIG. 43 is a cross-sectional view of the first cross-section in the core region after the second photoresist layer is removed in an embodiment of the present application;
  • 45 is a cross-sectional view of a second cross-section after forming a third conductive layer and a second barrier layer in an embodiment of the application;
  • 46 is a cross-sectional view of the first cross section in the core region after forming the third conductive layer and the second barrier layer in an embodiment of the application;
  • 47 is a cross-sectional view of a second cross-section after planarization in an embodiment of the present application.
  • FIG. 49 is a schematic diagram of an epitaxial layer in an embodiment of the present application.
  • a substrate 100 when fabricating a semiconductor structure, a substrate 100 is usually provided first.
  • the substrate 100 includes a core region and a peripheral region located outside the core region and adjacent to the core region, and a first barrier layer 200 is provided on the substrate 100;
  • a first photoresist layer 710 is formed on the first barrier layer 200 corresponding to the core area, and the first photoresist layer 710 covers the first photoresist layer on the core area shown in FIGS. 1 and 2 .
  • the barrier layer 200, the first barrier layer 200 on the peripheral area shown in FIG. 3 is exposed; as shown in FIGS. 4 to 6, the first barrier layer 200 corresponding to the peripheral area is removed, and the core area shown in FIGS. 4 and 5 is retained.
  • a dielectric layer 300 and a first conductive layer 400 are sequentially deposited on the first barrier layer 200 corresponding to the core region and the substrate 100 corresponding to the peripheral region, and the dielectric layer 300 Covering the first barrier layer 200 on the core region shown in FIG. 7 and FIG. 8, and covering the substrate 100 on the peripheral region shown in FIG. 9, the first conductive layer 400 covers the dielectric layer 300; as shown in FIG. 10 to FIG. 12, A second photoresist layer 720 is formed on the first conductive layer 400 corresponding to the peripheral region, and the first conductive layer 400 in the core region shown in FIGS. 10 and 11 is exposed; as shown in FIGS.
  • the corresponding core region is removed
  • the first conductive layer 400 and the dielectric layer 300 are kept, and the first conductive layer 400 and the dielectric layer 300 covered by the second photoresist layer 720 remain, and the first barrier layer 200 in the core region shown in FIG. 13 and FIG. 14 is exposed.
  • a fracture is likely to occur between the first barrier layer 200 corresponding to the core region and the dielectric layer 300 corresponding to the peripheral region, and the substrate 100 exposed in the fracture will be partially removed, As shown in the dotted line area in FIG. 16 , the devices in the substrate 100 are easily exposed or even damaged, resulting in a low yield of the semiconductor structure.
  • first section in FIGS. 1 to 16 is perpendicular to the second section, the first section is perpendicular to the extension direction of the word line 130 , and the second section is parallel to the extension direction of the word line 130 .
  • the first section is located between two adjacent active regions 110 , and the second section passes through the center of the active region 110 .
  • the embodiments of the present application provide a method for fabricating a semiconductor.
  • a method for fabricating a semiconductor By forming a first barrier layer and retaining part of the dielectric layer and part of the first conductive layer on the first barrier layer, part of the substrate area covers the first barrier layer, and the substrate is partially covered. Part of the area covers the dielectric layer, and the first barrier layer and the dielectric layer are partially overlapped, thereby reducing the exposure of the substrate, reducing the risk of a portion of the substrate being removed, and further reducing the risk of device exposure or even damage in the substrate.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, and the fabrication method includes the following steps:
  • Step S101 providing a substrate, the substrate includes a core area and a peripheral area located outside the core area and adjacent to the core area, a predetermined barrier layer is also formed on the substrate, and the predetermined barrier layer covers the core area and the peripheral area.
  • the substrate 100 includes a core area and a peripheral area, the core area and the peripheral area may be adjacent, the core area is the area A shown in FIGS. 18 to 21 , and the peripheral area is shown in FIGS. 18 to 21 . area B.
  • the peripheral edge of the core area is provided with a peripheral area, that is, the peripheral area surrounds the core area.
  • Active regions 110 are also generally disposed in the substrate 100 . Referring to FIG. 18 , some of the active regions 110 are located in the core region, and some of the active regions 110 are located in the peripheral region. The active regions 110 in the core region have smaller intervals, and the active regions 110 in the peripheral region have larger intervals. Shallow trench isolation structures 120 are disposed between the active regions 110 . The shallow trench isolation structures 120 are usually filled with oxide, such as silicon oxide, to separate the active regions 110 . As shown in FIG. 18 , the active region 110 is also covered with oxide to prevent the active region 110 from being exposed.
  • the shallow trench isolation structure 120 in the peripheral region is also filled with a nitride layer 140 , such as a silicon nitride layer.
  • a first groove is formed in the peripheral region of the substrate 100; a first oxide layer is deposited in the first groove, and the first oxide layer surrounds a second groove; nitrogen is deposited in the second groove.
  • the compound layer 140 and the nitride layer 140 form a third groove; a second oxide layer is deposited in the third groove, and the second oxide layer fills the third groove to form the shallow trench isolation structure 120 .
  • buried word lines 130 are also generally provided in the substrate 100 .
  • the cross-section shown in FIG. 18 is a cross-section parallel to the extending direction of the word line and passes through the center of the active region 110 , that is, the cross-section shown in FIG. 18 is the second cross-section, and the cross-sections shown in FIGS. 20 and 21 are perpendicular to the word line
  • the cross section in the extension direction of the line is located at different positions in the extension direction of the word line.
  • the first section shown in FIG. 20 is parallel to the third section shown in FIG. 21 , the first section shown in FIG. 20 is located at the center of two adjacent active regions 110 , and the third section shown in FIG. at the center of zone 110.
  • a predetermined barrier layer 210 is disposed on the substrate 100 , and the predetermined barrier layer 210 covers the core region and the peripheral region of the substrate 100 .
  • the material of the preset barrier layer 210 may be silicon nitride, and the thickness of the preset barrier layer 210 may be 200 nm-600 nm.
  • the predetermined barrier layer 210 may be formed on the substrate 100 by a deposition process.
  • the predetermined barrier layer 210 is formed by a chemical vapor deposition (Chemical Vapor Deposition, CVD for short) process, a Physical Vapor Deposition (Physical Vapor Deposition, abbreviated as PVD) process or atomic Atomic Layer Deposition (ALD for short) and other processes are formed on the substrate 100 .
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • ALD atomic Atomic Layer Deposition
  • Step S102 removing at least part of the preset barrier layer corresponding to the peripheral region to expose part of the substrate, and the remaining preset barrier layer forms a first barrier layer.
  • a part of the preset barrier layer 210 is removed to form the first barrier layer 200 .
  • the predetermined barrier layer 210 corresponding to the peripheral region is removed, the predetermined barrier layer 210 corresponding to the core region is retained, the first barrier layer 200 is formed on the core region, and the peripheral region is exposed.
  • the preset barrier layer 210 in the peripheral area that is far from the core area is removed, a part of the substrate 100 in the peripheral area is exposed, and the preset barrier layer 210 on the core area and part of the peripheral area close to the core area is retained, that is, the reserved preset
  • the barrier layer 210 is partially on the peripheral region and partially on the core region.
  • the core region is located inside the orthographic projection of the first barrier layer 200 on the substrate 100 , for example, the core region is located in the center region of the orthographic projection.
  • the step of forming the first barrier layer 200 with the remaining preset barrier layer 210 includes:
  • a first photoresist layer 710 is formed on the predetermined barrier layer 210 , and the first photoresist layer 710 at least covers the predetermined barrier layer 210 corresponding to the core region.
  • the first photoresist layer 710 may only cover the core area, or, as shown in FIG. 18 to FIG. 21 , the first photoresist layer 710 may cover the core area and extend to the peripheral area.
  • the predetermined barrier layer 210 is etched using the first photoresist layer 710 as a mask to form the first barrier layer 200 .
  • the predetermined barrier layer 210 covered by the first photoresist layer 710 remains to form the first barrier layer 200 , and the predetermined barrier layer 210 not covered by the first photoresist layer 710 is removed to expose the substrate 100 .
  • the first barrier layer 200 covers at least the core area. Referring to the top view shown in FIG. 22 , the first barrier layer 200 is under the first photoresist layer 710 , and the first barrier layer 200 covers the core area and the peripheral area at the edge of the core area. .
  • the first photoresist layer 710 is removed.
  • the first photoresist layer 710 may be removed by ashing. After the first photoresist layer 710 is removed, the first barrier layer 200 is exposed.
  • Step S103 sequentially forming a stacked dielectric layer and a first conductive layer 4 on the first barrier layer and the substrate.
  • a dielectric layer 300 is deposited on the first barrier layer 200 and the exposed substrate 100 , and the thickness of the dielectric layer 300 may be 50 nm-200 nm.
  • the dielectric layer 300 may have a higher dielectric constant, so that the layer has better insulation properties and improves the breakdown voltage of the device including the layer.
  • a step is formed between the dielectric layer 300 on the first barrier layer 200 and the dielectric layer 300 on the substrate 100.
  • a first conductive layer 400 is deposited on the dielectric layer 300.
  • the thickness of the first conductive layer 400 may be 300nm-600nm.
  • the first conductive layer 400 and the first barrier layer 200 The corresponding part is higher than the other parts.
  • the material of the first conductive layer 400 may be polycrystalline silicon.
  • Step S104 removing part of the dielectric layer and part of the first conductive layer on the first barrier layer, leaving part of the dielectric layer and part of the first conductive layer on the first barrier layer close to the peripheral region.
  • part of the dielectric layer 300 and part of the first conductive layer 400 on the first barrier layer 200 away from the peripheral region are removed.
  • the orthographic projection of the dielectric layer 300 on the substrate 100 partially overlaps with the orthographic projection of the first barrier layer 200 on the substrate 100 , and the width of the overlapping area is 20 nm-100 nm.
  • the dielectric layer 300 and the first barrier layer 200 are partially overlapped. As shown by the dotted line in FIG. 41 , the orthographic projection of the overlapped portion on the substrate 100 is the overlapping area, and the size of the overlapping area in the horizontal direction (X direction) is 20 nm. -100nm.
  • the overlapping area may be annular, and the overlapping area is at H as shown in FIG. 42 .
  • the area enclosed by the inner dashed line is the core area
  • the area between the two solid lines is the orthographic projection of the dielectric layer 300 on the substrate 100
  • the area enclosed by the outer dashed line is An orthographic projection of the first barrier layer 200 on the substrate 100 .
  • the shape of the overlapping area is adapted to the shape of the core area, for example, the shape of the overlapping area is a square ring.
  • the distance between each inner edge of the square ring and the corresponding outer edge may be equal, and the distance is between 20 nm and 100 nm.
  • each inner edge and the corresponding outer edge of the square ring can also be unequal, that is, in the square ring, the distance between part of the inner edge and the corresponding outer edge is greater than the distance between another part of the inner edge and the corresponding outer edge The distance between them is between 20nm and 100nm.
  • the dielectric layer 300 and the first barrier layer 200 are partially overlapped to avoid the exposed and removed parts of the substrate 100 in the core region and/or the peripheral region, that is, when the dielectric layer 300 and the first conductive layer 400 are removed, the substrate 100
  • the first barrier layer 200 is also covered thereon, so as to avoid removing part of the substrate 100 when the dielectric layer 300 and the first conductive layer 400 are removed.
  • part of the dielectric layer 300 and part of the first conductive layer 400 on the first barrier layer 200 are removed, and part of the dielectric layer 300 and part of the first conductive layer 400 on the first barrier layer 200 near the peripheral region are retained
  • the steps include:
  • a second photoresist layer 720 is formed on the first conductive layer 400 , and the orthographic projection of the second photoresist layer 720 on the substrate 100 and the orthographic projection of the first barrier layer 200 on the substrate 100 partially overlapped.
  • the second photoresist layer 720 is deposited on the first conductive layer 400, and the second photoresist layer 720 partially overlaps the first conductive layer 400, so that the second photoresist layer 720 is partially overlapped with the first conductive layer 400.
  • the orthographic projection of 720 on the substrate 100 partially coincides with the orthographic projection of the first barrier layer 200 on the substrate 100 .
  • the size of the overlapping region of the orthographic projection of the second photoresist layer 720 on the substrate 100 and the orthographic projection of the first barrier layer 200 on the substrate 100 may be 20 nm-100 nm.
  • the surface of the second photoresist layer 720 facing away from the substrate 100 may not be flush. As shown in FIG. 35 , the upper surface of the second photoresist layer 720 corresponding to the first barrier layer 200 may be higher than the rest of the area. the upper surface of the second photoresist layer 720.
  • the first conductive layer 400 and the dielectric layer 300 are etched using the second photoresist layer 720 as a mask to expose the first barrier layer 200 .
  • the part of the first conductive layer 400 and the dielectric layer 300 shielded by the second photoresist layer 720 is retained, and the exposed part of the first conductive layer 400 and the dielectric layer 300 is removed. After etching, the first barrier Layer 200 is revealed.
  • the second photoresist layer 720 is removed. As shown in FIGS. 41 to 44 , after the second photoresist layer 720 is removed, the first conductive layer 400 is exposed, the dielectric layer 300 and the first barrier layer 200 are partially overlapped, and the substrate 100 near the junction of the core region and the peripheral region is not exposed. exposed.
  • a substrate 100 is provided, the substrate 100 includes a core region and a peripheral region located outside the core region and adjacent to the core region, and a predetermined barrier layer 210 is also formed on the substrate 100 .
  • the barrier layer 210 is set to cover the core area and the peripheral area; at least part of the predetermined barrier layer 210 corresponding to the peripheral area is removed to expose part of the substrate 100 , and the remaining predetermined barrier layer 210 forms the first barrier layer 200 ; A stacked dielectric layer 300 and a first conductive layer 400 are formed on the substrate 100 in sequence; part of the dielectric layer 300 and part of the first conductive layer 400 on the first barrier layer 200 are removed, and the part of the first barrier layer 200 close to the peripheral region is retained The dielectric layer 300 and part of the first conductive layer 400 .
  • part of the substrate 100 covers the first barrier layer 200 and part of the substrate 100 covers the dielectric layer 300, and the first barrier layer 200 and the dielectric layer 300 are partially overlapped, thereby reducing the exposure of the substrate 100, reducing the risk of a portion of the substrate 100 being removed, thereby reducing the risk of exposure or even damage to the devices in the substrate 100.
  • the active region 110 is further provided in the substrate 100 in the embodiment of the present application, and part of the dielectric layer 300 and part of the first conductive layer 400 on the first barrier layer 200 are removed, and the first conductive layer 400 is retained.
  • the fabrication method of the semiconductor structure further includes the following steps:
  • a bit line contact hole is formed on the first barrier layer 200 and the substrate 100, and the bottom of the bit line contact hole exposes the active region 110 in the core region.
  • the first barrier layer 200 and the substrate 100 are etched, and bit line contact holes are formed in the first barrier layer 200 and the substrate 100 , and the bit line contact holes expose the active region 110 .
  • bit line contact hole is formed on the first barrier layer 200 and the substrate 100 .
  • a second conductive layer 800 is formed in the bit line contact hole, and the second conductive layer 800 is flush with the first barrier layer 200 .
  • a second conductive layer 800 is deposited in the bit line contact hole, so that the second conductive layer 800 fills the bit line contact hole for subsequent formation of the bit line contact.
  • the upper surface of the second conductive layer 800 is flush with the upper surface of the first barrier layer 200 , that is, the surface of the second conductive layer 800 facing away from the substrate 100 is the same as the surface of the first barrier layer 200 facing away from the substrate 100 .
  • the surfaces are of the same height, so as to form other film layers on the second conductive layer 800 and the first barrier layer 200 .
  • the first barrier layer 200 also has an oxide layer (not shown), and the second conductive layer 800 is deposited in the bit line contact hole and deposited on the oxide layer (not shown). shown) on.
  • chemical mechanical polishing is performed on the second conductive layer 800 with the oxide layer (not shown) as a stop layer.
  • the second conductive layer 800 is polished to be flush with the oxide layer (not shown)
  • the second conductive layer 800 is polished Etch back is performed to make the upper surface of the second conductive layer 800 flush with the first barrier layer 200, and then the oxide layer (not shown) is removed.
  • the third conductive layer 500 is formed on the first barrier layer 200 , the second conductive layer 800 and the first conductive layer 400 .
  • the thickness of the third conductive layer 500 may be 50nm-200nm.
  • a titanium nitride layer is deposited on the first barrier layer 200, the second conductive layer 800 and the first conductive layer 400; a tungsten layer is deposited on the titanium nitride layer.
  • the titanium nitride layer and the tungsten layer constitute the third conductive layer 500 .
  • the third conductive layer 500 covers the first barrier layer 200 , the second conductive layer 800 and the first conductive layer 400 .
  • a metal layer such as a cobalt (Co) layer or a titanium (Ti) layer, is further provided between the titanium nitride layer and the first conductive layer 400 , that is, before the titanium nitride layer is formed, the first conductive layer A metal layer is deposited on 400 .
  • annealing is performed to make the first conductive layer 400 react with the metal layer to form an ohmic contact of metal compounds (such as metal silicides), thereby reducing interface resistance and improving the performance of the semiconductor structure.
  • the second barrier layer 600 is formed on the third conductive layer 500 .
  • a second barrier layer 600 is deposited on the third conductive layer 500, and the material of the second barrier layer 600 may be silicon nitride. As shown in FIGS. 45 and 46 , the second barrier layer 600 covers the third conductive layer 500 .
  • the first barrier layer 200 and the first conductive layer 400 have a certain height difference.
  • the second barrier layer 600 faces away from the substrate 100 . The surface is not flush.
  • a planarization process is performed on the surface of the second barrier layer 600 away from the substrate 100 , and the second barrier layer 600 after the planarization process is planarized.
  • the third conductive layer 500 is not exposed.
  • the surface of the second barrier layer 600 facing away from the substrate 100 is planarized by chemical mechanical polishing (Chemical Mechanical Polishing, CMP for short) to obtain a relatively flat surface.
  • CMP Chemical Mechanical Polishing
  • the substrate 100 in the core area is provided with a second conductive layer 800 , and the second conductive layer 800 can subsequently form bit line contacts, and the substrate 100 in the core area is sequentially provided with a third conductive layer 500 and a second barrier Layer 600, the third conductive layer 500 corresponding to the core region can subsequently form bit lines, and the second barrier layer 600 corresponding to the core region can subsequently form the isolation structure of the bit lines.
  • a dielectric layer 300 , a third conductive layer 500 and a second barrier layer 600 are sequentially formed on the substrate 100 in the peripheral region.
  • the dielectric layer 300 , the third conductive layer 500 and the active region 110 in the substrate 100 may be A device, such as a transistor, is subsequently formed, and the second barrier layer 600 corresponding to the peripheral region is subsequently formed to form an isolation structure for the device.
  • the dielectric layer 300 may have a high dielectric constant (high-k).
  • the material of the dielectric layer 300 may include hafnium oxide, silicon-doped hafnium oxide, silicon-doped zirconium oxide, etc., so that the device has a higher breakdown voltage.
  • the method for fabricating the semiconductor structure further includes: epitaxially growing an epitaxial layer 900 on a part of the active region 110 in the peripheral region, and the epitaxial layer 900 contains a predetermined metal.
  • an epitaxial layer 900 is formed on a part of the active region 110 in the peripheral region.
  • an epitaxial layer 900 is formed on the active region 110 by epitaxial growth and other processes.
  • the epitaxial layer 900 contains a predetermined metal.
  • the material of the epitaxial layer 900 may be the same as that of the active region 110 .
  • the material of the active region 110 and the epitaxial layer are both silicon, and the epitaxial layer 900 may contain germanium.
  • the materials of the active region 110 and the epitaxial layer 900 are not limited.
  • the material of the epitaxial layer 900 may be different from that of the active region 110 , and the default metal may be germanium or other metals.
  • the epitaxial layer 900 is not provided on part of the active region 110 , and NMOS is subsequently formed on this part of the active region 110 ; the epitaxial layer 900 is provided on part of the active region 110 , and PMOS is subsequently formed on this part of the active region 110 .
  • an embodiment of the present application provides a semiconductor structure including a substrate 100 , a first barrier layer 200 , a dielectric layer 300 and a first conductive layer 400 .
  • the substrate 100 includes a core area and a peripheral area, and the core area and the peripheral area may be adjacent to each other.
  • the core area is shown as area A in FIG. 46
  • the peripheral area is shown as B area in FIG. 46 .
  • the peripheral edge of the core area is provided with a peripheral area, that is, the peripheral area surrounds the core area.
  • Active regions 110 are also generally disposed in the substrate 100. Referring to FIG. 46, some of the active regions 110 are located in the core region, and some of the active regions 110 are located in the peripheral region. The active regions 110 in the core region have smaller intervals, and the active regions 110 in the peripheral region have larger intervals. Shallow trench isolation structures 120 are disposed between the active regions 110 . The shallow trench isolation structures 120 are usually filled with oxide, such as silicon oxide, to separate the active regions 110 . As shown in FIG. 46 , the active region 110 is also covered with oxide to prevent the active region 110 from being exposed.
  • buried word lines 130 are usually disposed in the substrate 100 .
  • the second cross-section shown in FIG. 46 is a plane parallel to the extending direction of the word lines 130 and passing through the center of the active region 110 .
  • a first barrier layer 200 is further disposed on the substrate 100 , and the first barrier layer 200 covers at least the core region.
  • the first barrier layer 200 may be disposed on the core area of the substrate 100, or the first barrier layer 200 may be disposed on the core area of the substrate 100 and a part of the peripheral area near the core area.
  • the first barrier layer 200 covers the core area and part of the peripheral area, that is, the core area is located in the inner area of the orthographic projection of the first barrier layer 200 on the substrate 100 .
  • the material of the first barrier layer 200 may be silicon nitride, and the thickness of the first barrier layer 200 may be 200nm-600nm.
  • the dielectric layer 300 is disposed on the substrate 100 and part of the first barrier layer 200 , that is, the dielectric layer 300 partially overlaps with the first barrier layer 200 .
  • the thickness of the dielectric layer 300 may be 50 nm-200 nm, the dielectric layer 300 may have a relatively high dielectric constant, and the material of the dielectric layer 300 may be hafnium oxide, silicon-doped hafnium oxide, silicon-doped zirconium oxide, or the like.
  • the dielectric layer 300 covers the substrate 100 in the peripheral region and a portion of the first barrier layer 200 near the peripheral region.
  • the orthographic projection of the dielectric layer 300 on the substrate 100 coincides with the orthographic projection of the first barrier layer 200 on the substrate 100
  • the width of the overlapping region is 20 nm-100 nm.
  • the first conductive layer 400 is disposed on the dielectric layer 300 . As shown in FIG. 46 , the first conductive layer 400 covers the upper surface of the dielectric layer 300 .
  • the material of the first conductive layer 400 may be polysilicon, and the thickness of the first conductive layer 400 may be 300nm-600nm.
  • the semiconductor structure further includes a third conductive layer 500 and a second barrier layer 600, the third conductive layer 500 is disposed on the first barrier layer 200 and the first conductive layer 400, and the second barrier layer 600 is disposed on the third on the conductive layer 500 .
  • the third conductive layer 500 may include a titanium nitride layer close to the substrate 100 and a tungsten layer disposed on the titanium nitride layer, the thickness of the third conductive layer 500 may be 50nm-200nm, and the material of the second barrier layer 600 may be Silicon Nitride.
  • the surface of the second barrier layer 600 facing away from the substrate 100 is flush, and the upper surface of the third conductive layer 500 is not exposed, that is, the second barrier layer 600 covers the upper surface of the third conductive layer 500 .
  • the upper surfaces of the dielectric layer 300 , the first conductive layer 400 and the third conductive layer 500 are formed with steps at the interface area between the first barrier layer 200 and the substrate 100 , and the upper surface of the second barrier layer 600 is flush .
  • a bit line contact hole is formed on the upper surface of the first barrier layer 200, the bit line contact hole extends to the substrate 100, and the bottom of the bit line contact hole exposes the active region 110 in the core region, and the bit line contact hole
  • the second conductive layer 800 is filled therein.
  • the second conductive layer 800 may be flush with the first barrier layer 200 .
  • the third conductive layer 500 is disposed on the first barrier layer 200 and the second conductive layer 800 , and the second conductive layer 800 is electrically connected to the third conductive layer 500 .
  • an epitaxial layer 900 is provided on a part of the active region 110 in the peripheral region, and the epitaxial layer 900 contains a predetermined metal. As shown in FIG. 48 , the epitaxial layer 900 is not provided on part of the active region 110, and NMOS is subsequently formed in this part of the active region 110; as shown in FIG. 110 subsequently forms a PMOS.
  • the material of the active region 110 and the epitaxial layer 900 may be silicon, and the default metal may be germanium.
  • the semiconductor structure provided by the embodiments of the present application includes a substrate 100, a first barrier layer 200, a dielectric layer 300 and a first conductive layer 400, wherein the substrate 100 includes a core region and a peripheral region located outside the core region and adjacent to the core region, An active region 110 is also arranged in the substrate 100; a first barrier layer 200 is arranged on the substrate 100, the first barrier layer 200 covers at least the core region; the dielectric layer 300 is arranged on the substrate 100 and part of the first barrier layer 200, the first conductive layer 200 is Layer 400 is disposed on dielectric layer 300 .
  • part of the substrate 100 covers the first barrier layer 200
  • part of the substrate 100 covers the dielectric layer 300
  • the first barrier layer 200 and the dielectric layer 300 The parts overlap, thereby reducing the exposure of the substrate 100 , reducing the risk of removing parts of the substrate 100 , thereby reducing the risk of exposure or even damage to the devices within the substrate 100 .
  • references to the terms “one embodiment,” “some embodiments,” “illustrative embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments A particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

本申请提供一种半导体结构的制作方法及半导体结构，涉及半导体制造技术领域，用于解决基底内的器件损伤的技术问题，该制作方法包括：提供基底，基底包括核心区和位于核心区外且相邻的外围区，基底上形成有预设阻挡层，预设阻挡层覆盖核心区和外围区；去除外围区对应的至少部分预设阻挡层，以暴露部分基底，保留的预设阻挡层形成第一阻挡层；在第一阻挡层和基底上依次形成层叠的介质层和第一导电层；去除第一阻挡层上的部分介质层和部分第一导电层，保留第一阻挡层上靠近外围区的部分介质层和部分第一导电层。通过第一阻挡层和介质层部分重叠，减少基底暴露，降低基底被去除部分的风险，进而降低了基底内的器件暴露甚至损伤的风险。

Description

半导体结构的制作方法及半导体结构
本申请要求于2021年04月23日提交中国专利局、申请号为202110444445.9、申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体制造技术领域，尤其涉及一种半导体结构的制作方法及半导体结构。
背景技术
半导体结构一般应用在存储器、控制器等电子器件上；半导体结构应用在存储器上时，存储数据的阵列区内通常形成有电容器，阵列区外的边缘区内通常形成有金属氧化物场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，简称MOSFET)。金属氧化物场效应晶体管一般根据掺杂类型的不同，可包括P型晶体管(PMOS)和N型晶体管(NMOS)，这两种类型的晶体管中通常设置高介电常数(high-k)的介质层，以提高晶体管的击穿电压。
相关技术中，制作半导体结构时，通常先在基底上形成第一阻挡层，其中，基底包括核心区和设置在核心区外的外围区；去除外围区的第一阻挡层，保留核心区的第一阻挡层；在第一阻挡层和位于外围区的基底上依次层叠形成介质层和第一导电层；去除核心区的介质层和第一导电层，保留外围区的介质层和第一导电层。
然而，在上述制作半导体结构的过程中，去除核心区的介质层和第一导电层后，易在位于外围区的介质层与位于核心区的第一阻挡层之间出现断口，该断口的存在导致暴露出来的基底被去除，甚至导致基底内的器件损伤。
发明内容
第一方面，本申请实施例提供一种半导体结构的制作方法，其包括：提供基底，所述基底包括核心区和位于所述核心区外且与所述核心区相邻的外围区，所述基底上还形成有预设阻挡层，所述预设阻挡层覆盖所述核心区和所述外围区；去除所述外围区对应的至少部分所述预设阻挡层，以暴露部分所述基底，保留的所述预设阻挡层形成第一阻挡层；在所述第一阻挡层和所述基底上依次形成层叠的介质层和第一导电层；去除所述第一阻挡层上的部分所述介质层和部分所述第一导电层，保留所述第一阻挡层上靠近所述外围区的部分所述介质层和部分所述第一导电层。
本申请实施例提供的半导体结构的制作方法具有如下优点：
本申请实施例提供的半导体结构的制作方法中，提供基底，基底包括核心区和位于核心区外且与核心区相邻的外围区，基底上还形成有预设阻挡层，预设阻挡层覆盖核心区和外围区；去除外围区对应的至少部分预设阻挡层，以暴露部分基底，保留的预设阻挡层形成第一阻挡层；在第一阻挡层和基底上依次形成层叠的介质层和第一导电层；去除第一阻挡层上的部分介质层和部分第一导电层，保留第一阻挡层上靠近外围区的部分介质层和部分第一导电层。通过形成第一阻挡层，并保留第一阻挡层上的部分介质层和部分第一导电层，使得基底的部分区域覆盖第一阻挡层，基底的部分区域覆盖介质层，且第一阻挡层和介质层部分重叠，从而减少基底的暴露，降低基底被去除部分的风险，进而降低了基底内的器件暴露甚至损伤的风险。
第二方面，本申请实施例提供一种半导体结构，其包括：基底，所述基底包括核心区和位于所述核心区外且与所述核心区相邻的外围区，所述基底内还设置有源区；设置在所述基底上的第一阻挡层，所述第一阻挡层至少覆盖所述核心区；设置在所述基底和部分所述第一阻挡层上的介质层；设置在所述介质层上的第一导电层。
本申请实施例提供的半导体结构具有如下优点：
本申请实施例提供的半导体结构包括基底、第一阻挡层、介质层和第一导电层，其中，基底包括核心区和位于核心区外且与核心区相邻的外围区，基底内还设置有源区；第一阻挡层设置在基底上，第一阻挡层至少覆盖核心区；介质层设置在基底和部分第一阻挡层上，第一导电层设置在介质层上。通过在基底和部分第一阻挡层上设置介质层，使得基底的部分区 域覆盖第一阻挡层，基底的部分区域覆盖介质层，且第一阻挡层和介质层部分重叠，从而减少基底的暴露，降低基底被去除部分的风险，进而降低了基底内的器件暴露甚至损伤的风险。
附图说明
图1为相关技术中的形成第一光刻胶层后第一截面在核心区的剖视图；
图2为相关技术中的形成第一光刻胶层后第二截面在核心区的剖视图；
图3为相关技术中的形成第一光刻胶层后第二截面在外围区剖视图；
图4为相关技术中的去除外围区对应的第一阻挡层后第一截面在核心区的剖视图；
图5为相关技术中的去除外围区对应的第一阻挡层后第二截面在核心区的剖视图；
图6为相关技术中的去除外围区对应的第一阻挡层后第二截面在外围区的剖视图；
图7为相关技术中的形成介质层和第一导电层后第一截面在核心区的剖视图；
图8为相关技术中的形成介质层和第一导电层后第二截面在核心区的剖视图；
图9为相关技术中的形成介质层和第一导电层后第二截面在外围区剖视图；
图10为相关技术中的形成第二光刻胶层后第一截面在核心区的剖视图；
图11为相关技术中的形成第二光刻胶层后第二截面在核心区的剖视图；
图12为相关技术中的形成第二光刻胶层后第二截面在外围区的剖视图；
图13为相关技术中的去除核心区对应的介质层和第一导电层后第一截面在核心区的剖视图；
图14为相关技术中的去除核心区对应的介质层和第一导电层后第二截面在核心区的剖视图；
图15为相关技术中的去除核心区对应的介质层和第一导电层后第二截面在外围区剖视图；
图16为相关技术中的核心区和外围区交接区域的示意图；
图17为本申请实施例中的半导体结构的制作方法的流程图；
图18为本申请实施例中的形成第一光刻胶层后第二截面的剖视图；
图19为本申请实施例中的基底的俯视图；
图20为本申请实施例中的形成第一光刻胶层后第一截面在核心区的剖视图；
图21为本申请实施例中的形成第一光刻胶层后第三截面在核心区的剖视图；
图22为本申请实施例中的形成第一光刻胶层后的俯视图；
图23为本申请实施例中的去除部分第一阻挡层后第二截面的剖视图；
图24为本申请实施例中的去除部分第一阻挡层后第一截面在核心区的剖视图；
图25为本申请实施例中的去除部分第一阻挡层后第三截面在核心区的剖视图；
图26为本申请实施例中的去除第一光刻胶层后第二截面的剖视图；
图27为本申请实施例中的去除第一光刻胶层后第一截面在核心区的剖视图；
图28为本申请实施例中的去除第一光刻胶层后第三截面在核心区的剖视图；
图29为本申请实施例中的形成介质层后第二截面的剖视图；
图30为本申请实施例中的形成介质层后第一截面在核心区的剖视图；
图31为本申请实施例中的形成介质层后第三截面在核心区的剖视图；
图32为本申请实施例中的形成第一导电层后第二截面的剖视图；
图33为本申请实施例中的形成第一导电层后第一截面在核心区的剖视图；
图34为本申请实施例中的形成第一导电层后第三截面在核心区的剖视图；
图35为本申请实施例中的形成第一光刻胶层后第二截面的剖视图；
图36为本申请实施例中的形成第一光刻胶层后第一截面在核心区的 剖视图；
图37为本申请实施例中的形成第一光刻胶层后第三截面在核心区的剖视图；
图38为本申请实施例中的去除部分介质层和第一导电层后第二截面的剖视图；
图39为本申请实施例中的去除部分介质层和第一导电层后第一截面在核心区的剖视图；
图40为本申请实施例中的去除部分介质层和第一导电层后第三截面在核心区的剖视图；
图41为本申请实施例中的去除第二光刻胶层后第二截面的剖视图；
图42为本申请实施例中的去除第二光刻胶层后的俯视图；
图43为本申请实施例中的去除第二光刻胶层后第一截面在核心区的剖视图；
图44为本申请实施例中的去除第二光刻胶层后第三截面在核心区的剖视图；
图45为本申请实施例中的形成第三导电层和第二阻挡层后第二截面的剖视图；
图46为本申请实施例中的形成第三导电层和第二阻挡层后第一截面在核心区的剖视图；
图47为本申请实施例中的平坦化处理后第二截面的剖视图；
图48为本申请实施例中的平坦化处理后第一截面在核心区的剖视图；
图49为本申请实施例中的外延层的示意图。
具体实施方式
参照图1至图16，制作半导体结构时，通常先在提供基底100，基底100包括核心区和位于核心区外且与核心区相邻的外围区，基底100上设置有第一阻挡层200；如图1至图3所示，在核心区对应的第一阻挡层200上形成第一光刻胶层710，第一光刻胶层710覆盖图1和图2所示核心区上的第一阻挡层200，图3所示外围区上的第一阻挡层200暴露；如图4至图6所示，去除外围区对应的第一阻挡层200，保留图4和图5所示核心区上的第一阻挡层200；如图7至图9所示，在核心区对应的第一阻挡 层200上和外围区对应的基底100上依次沉积介质层300和第一导电层400，介质层300覆盖图7和图8所示核心区上的第一阻挡层200，且覆盖图9所示外围区上的基底100，第一导电层400覆盖介质层300；如图10至图12所示，在外围区对应的第一导电层400上形成第二光刻胶层720，图10和图11所示核心区的第一导电层400暴露；如图13至图15所示，去除核心区对应的第一导电层400和介质层300，保留被第二光刻胶层720覆盖的第一导电层400和介质层300，图13和图14所示核心区的第一阻挡层200暴露。
然而，参照图16，在上述制作半导体结构的过程中，核心区对应的第一阻挡层200和外围区对应的介质层300之间易出现断口，暴露在断口中的基底100会被去除部分，如图16所示虚线区域，基底100内的器件易暴露甚至损伤，导致半导体结构的良率较低。
需要说明的是，图1至图16中的第一截面与第二截面相垂直，第一截面垂直于字线130的延伸方向，第二截面平行于字线130的延伸方向。其中，第一截面位于相邻两个有源区110之间，第二截面过有源区110的中心。
本申请实施例提供一种半导体的制作方法，通过形成第一阻挡层，并保留第一阻挡层上的部分介质层和部分第一导电层，使得基底的部分区域覆盖第一阻挡层，基底的部分区域覆盖介质层，且第一阻挡层和介质层部分重叠，从而减少基底的暴露，降低基底被去除部分的风险，进而降低了基底内的器件暴露甚至损伤的风险。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参照图17，本申请实施例提供一种半导体结构的制作方法，该制作方法包括以下步骤：
步骤S101、提供基底，基底包括核心区和位于核心区外且与核心区相邻的外围区，基底上还形成有预设阻挡层，预设阻挡层覆盖核心区和外围 区。
参照图18至图21，基底100包括核心区和外围区，核心区和外围区可以相邻，核心区如图18至图21中所示的A区，外围区如图18至图21所示的B区。示例性的，如图19所示，核心区的周向边缘设置外围区，即外围区环绕核心区一周。
基底100内还通常设置有源区110，参照图18，部分有源区110位于核心区，部分有源区110位于外围区。位于核心区内的有源区110间隔较小，位于外围区内的有源区110间隔较大。有源区110之间设置浅槽隔离结构120，浅槽隔离结构120内通常填充氧化物，例如氧化硅，以将各有源区110之间隔开。如图18所示，有源区110上还覆盖氧化物，避免有源区110暴露。
需要说明的是，如图18所示，位于外围区的浅槽隔离结构120内还填充有氮化物层140，例如氮化硅层。示例性的，在基底100的外围区形成第一凹槽；在第一凹槽内沉积第一氧化物层，第一氧化物层围设成第二凹槽；在第二凹槽内沉积氮化物层140，氮化物层140围设成第三凹槽；在第三凹槽内沉积第二氧化物层，第二氧化物层填满第三沟槽，以形成浅槽隔离结构120。
参照图20和图21，基底100内通常还设置有埋入式字线130。图18所示的截面为平行于字线的延伸方向的截面，且过有源区110的中心，即图18所示截面为第二截面，图20和图21所示的截面为垂直于字线的延伸方向的截面，且位于字线的延伸方向上的不同位置。图20所示的第一截面与图21所示的第三截面平行，图20所示的第一截面位于相邻两个有源区110的中心，图21所示的第三截面过有源区110的中心位置处。
继续参照图18至图21，基底100上设置有预设阻挡层210，预设阻挡层210覆盖基底100的核心区和外围区。示例性的，预设阻挡层210的材质可以为氮化硅，预设阻挡层210的厚度可以为200nm-600nm。
预设阻挡层210可以通过沉积工艺形成在基底100上，例如，预设阻挡层210通过化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺、物理气相沉积(Physical Vapor Deposition，简称PVD)工艺或者原子层沉积(Atomic Layer Deposition，简称ALD)等工艺形成在基底100上。
步骤S102、去除外围区对应的至少部分预设阻挡层，以暴露部分基底， 保留的预设阻挡层形成第一阻挡层。
参照图18至图28，去除部分预设阻挡层210，以形成第一阻挡层200。例如，去除外围区对应的预设阻挡层210，保留核心区对应的预设阻挡层210，核心区上形成第一阻挡层200，外围区暴露。
或者，去除外围区中远离核心区的部分预设阻挡层210，暴露外围区的部分基底100，保留核心区上以及靠近核心区的部分外围区上的预设阻挡层210，即保留的预设阻挡层210部分位于外围区上，部分位于核心区上。示例性的，核心区位于第一阻挡层200在基底100上的正投影的内部，例如，核心区位于该正投影的中心区域。
在一种可能的示例中，去除外围区对应的至少部分预设阻挡层210，以暴露部分基底100，保留的预设阻挡层210形成第一阻挡层200的步骤包括：
如图18至图21所示，在预设阻挡层210上形成第一光刻胶层710，第一光刻胶层710至少覆盖核心区对应的预设阻挡层210。其中，第一光刻胶层710可以只覆盖核心区，或者，如图18至图21所示，第一光刻胶层710覆盖核心区且延伸至外围区。
如图22至图25所示，以第一光刻胶层710为掩膜刻蚀预设阻挡层210，以形成第一阻挡层200。第一光刻胶层710覆盖的预设阻挡层210保留，形成第一阻挡层200，第一光刻胶层710未覆盖的预设阻挡层210去除，暴露出基底100。第一阻挡层200至少覆盖核心区，参照图22所示的俯视图，第一光刻胶层710下方即为第一阻挡层200，第一阻挡层200覆盖核心区与位于核心区边缘的外围区。
如图26至图28所示，去除第一光刻胶层710。第一光刻胶层710可以通过灰化(Ashing)去除，去除第一光刻胶层710后，第一阻挡层200显露。
步骤S103、在第一阻挡层和基底上依次形成层叠的介质层和第一导电层4。
参照图29至图31，在第一阻挡层200和暴露的基底100上沉积介质层300，介质层300的厚度可以为50nm-200nm。介质层300可以具有较高的介电常数，以使该层绝缘性较好，提高包含该层的器件的击穿电压。如图29所示，位于第一阻挡层200上的介质层300和位于基底100上的介质 层300之间形成台阶。
参照图32至图34，在介质层300上沉积第一导电层400，第一导电层400的厚度可以为300nm-600nm，如图32所示，第一导电层400中与第一阻挡层200对应的部分高于其他部分。第一导电层400的材质可以为多晶硅(polycrystalline silicon)。
步骤S104、去除第一阻挡层上的部分介质层和部分第一导电层，保留第一阻挡层上靠近外围区的部分介质层和部分第一导电层。
参照图35至图44，去除第一阻挡层200上远离外围区的部分介质层300和部分第一导电层400。参照图41，介质层300在基底100上的正投影与第一阻挡层200在基底100上的正投影部分重合，重合区域的宽度尺寸为20nm-100nm。
可以理解的是，介质层300与第一阻挡层200部分重叠，如图41虚线所示，重叠部分在基底100上的正投影即为重合区域，重合区域水平方向(X方向)的尺寸为20nm-100nm。
在一种可能的示例中，参照图42所示的俯视图，重合区域可以为环状，重合区域如图42所示的H处。如图42所示，内部的虚线所围合的区域为核心区，套设的两实线之间的区域为介质层300在基底100上的正投影，位于外侧的虚线所围合的区域为第一阻挡层200在基底100上的正投影。
重合区域的形状与核心区的形状相适配，例如重合区域的形状为方环形。方形环的各内边与相对应的外边之间的间距可以相等，该间距位于20nm-100nm之间。
当然，方形环的各内边与相对应的外边之间的间距也可以不等，即方形环中，部分内边与相对应的外边之间的间距大于另一部分内边与相对应的外边之间的间距，且各间距均位于20nm-100nm之间。
可以理解的是，介质层300和第一阻挡层200部分重叠，以避免核心区和/或外围区的基底100暴露而被去除部分，即去除介质层300和第一导电层400时，基底100上还覆盖第一阻挡层200，从而避免去除介质层300和第一导电层400时会去除部分基底100。
在一种可能的示例中，去除第一阻挡层200上的部分介质层300和部分第一导电层400，保留第一阻挡层200上靠近外围区的部分介质层300和部分第一导电层400的步骤包括：
参照图35至图37，在第一导电层400上形成第二光刻胶层720，第二光刻胶层720在基底100上的正投影与第一阻挡层200在基底100上的正投影部分重合。
如图35至图37所示，第二光刻胶层720沉积在第一导电层400上，且第二光刻胶层720与第一导电层400部分重叠，以使第二光刻胶层720在基底100上的正投影与第一阻挡层200在基底100上的正投影部分重合。第二光刻胶层720在基底100上的正投影与第一阻挡层200在基底100上的正投影重合区域的尺寸可以为20nm-100nm。
需要说明的是，第二光刻胶层720背离基底100的表面可以不齐平，如图35所示，第一阻挡层200对应的第二光刻胶层720的上表面可以高于其余区域的第二光刻胶层720的上表面。
参照图38至图40，以第二光刻胶层720为掩膜刻蚀第一导电层400和介质层300，以暴露第一阻挡层200。如图38至图40示，保留第二光刻胶层720遮挡的部分第一导电层400和介质层300，去除暴露的部分第一导电层400和介质层300，刻蚀后，第一阻挡层200显露。
参照图41至图44，去除第二光刻胶层720。如图41至图44所示，去除第二光刻胶层720后，第一导电层400显露，介质层300和第一阻挡层200部分重叠，核心区和外围区交界处附近的基底100未暴露。
本申请实施例提供的半导体结构的制作方法中，提供基底100，基底100包括核心区和位于核心区外且与核心区相邻的外围区，基底100上还形成有预设阻挡层210，预设阻挡层210覆盖核心区和外围区；去除外围区对应的至少部分预设阻挡层210，以暴露部分基底100，保留的预设阻挡层210形成第一阻挡层200；在第一阻挡层200和基底100上依次形成层叠的介质层300和第一导电层400；去除第一阻挡层200上的部分介质层300和部分第一导电层400，保留第一阻挡层200上靠近外围区的部分介质层300和部分第一导电层400。通过形成第一阻挡层200，并保留第一阻挡层200上的部分介质层300和部分第一导电层400，使得基底100的部分区域覆盖第一阻挡层200，基底100的部分区域覆盖介质层300，且第一阻挡层200和介质层300部分重叠，从而减少基底100的暴露，降低基底100被去除部分的风险，进而降低了基底100内的器件暴露甚至损伤的风险。
需要说明的是，参照图18至图46，本申请实施例中的基底100内还 设置有源区110，去除第一阻挡层200上的部分介质层300和部分第一导电层400，保留第一阻挡层200上靠近外围区的部分介质层300和部分第一导电层400的步骤之后，半导体结构的制作方法还包括以下步骤：
在第一阻挡层200和基底100上形成位线接触孔，位线接触孔的底部暴露核心区内的有源区110。如图45和图46所示，刻蚀第一阻挡层200和基底100，在第一阻挡层200和基底100内形成位线接触孔，位线接触孔暴露有源区110。
在第一阻挡层200和基底100上形成位线接触孔之后，在位线接触孔内形成第二导电层800，第二导电层800与第一阻挡层200齐平。在位线接触孔内沉积第二导电层800，以使第二导电层800填充满位线接触孔，以用于后续形成位线接触。
如图45和图46所示，第二导电层800的上表面与第一阻挡层200的上表面齐平，即第二导电层800背离基底100的表面与第一阻挡层200背离基底100的表面等高，以便于在第二导电层800和第一阻挡层200上形成其他膜层。
需要说明的是，在形成第二导电层800时，第一阻挡层200上还具有氧化层(未图示)，第二导电层800沉积在位线接触孔内且沉积在氧化层(未图示)上。先以氧化层(未图示)为停止层对第二导电层800进行化学机械研磨，当第二导电层800被研磨至与氧化层(未图示)平齐时，对第二导电层800进行回刻蚀，使第二导电层800的上表面与第一阻挡层200平齐，再去除氧化层(未图示)。
在位线接触孔内形成第二导电层800之后，在第一阻挡层200、第二导电层800和第一导电层400上形成第三导电层500。第三导电层500的厚度可以为50nm-200nm。
示例性的，在第一阻挡层200、第二导电层800和第一导电层400上沉积氮化钛层；在氮化钛层上沉积钨层。氮化钛层和钨层构成第三导电层500。如图45和图46所示，第三导电层500覆盖第一阻挡层200、第二导电层800和第一导电层400。
需要说明的是，氮化钛层与第一导电层400之间还设置有金属层，例如钴(Co)层或者钛(Ti)层，即在形成氮化钛层之前，在第一导电层400上沉积金属层。在氮化钛层上沉积钨层后，进行退火处理，以使第一导电 层400与金属层反应，形成金属化合物(例如金属硅化物)的欧姆接触，降低界面电阻，提高半导体结构的性能。
在第一阻挡层200、第二导电层800和第一导电层400上形成第三导电层500之后，在第三导电层500上形成第二阻挡层600。继续参照图45和图46，在第三导电层500上沉积第二阻挡层600，第二阻挡层600的材质可以为氮化硅。如图45和图46所示，第二阻挡层600覆盖第三导电层500。
需要说明的是，如图45所示，第一阻挡层200与第一导电层400具有一定高度差，沉积第三导电层500和第二阻挡层600后，第二阻挡层600背离基底100的表面不齐平。
参照图47和图48，在第三导电层500上形成第二阻挡层600的步骤之后，对第二阻挡层600背离基底100的表面进行平坦化处理，平坦化处理后的第二阻挡层600未暴露出第三导电层500。
示例性的，通过化学机械研磨(Chemical Mechanical Polishing，简称CMP)对第二阻挡层600背离基底100的表面进行平坦化处理，以获得较为平整的表面。如图47所示，核心区对应的第二阻挡层600与外围区对应的第二阻挡层600齐平，且第二阻挡层600覆盖第三导电层500。
如图47所示，核心区的基底100内设置有第二导电层800，第二导电层800后续可以形成位线接触，核心区的基底100上依次设置有第三导电层500和第二阻挡层600，核心区对应的第三导电层500后续可以形成位线，核心区对应的第二阻挡层600后续形成位线的隔离结构。
如图47所示，外围区的基底100上依次形成有介质层300、第三导电层500和第二阻挡层600，介质层300、第三导电层500与基底100中的有源区110可以后续形成器件，例如晶体管，外围区对应的第二阻挡层600后续形成器件的隔离结构。介质层300可以具有高介电常数(high-k)，例如介质层300的材质可以包括氧化铪、掺硅氧化铪、掺硅氧化锆等，以使器件具有较高的击穿电压。
需要说明的是，参照图49，去除第一阻挡层200上的部分介质层300和部分第一导电层400，保留第一阻挡层200上靠近外围区的部分介质层300和部分第一导电层400的步骤之后，半导体结构的制作方法还包括：在外围区内的部分有源区110上外延生长外延层900，外延层900含有预 设金属。
如图49所示，位于外围区内的部分有源区110上形成外延层900，例如，通过外延生长等工艺在有源区110上形成外延层900，外延层900含有预设金属。
外延层900的材质可以与有源区110的材质相同，例如，有源区110与外延层的材质均为硅，外延层900中可以含有锗。当然，有源区110和外延层900的材质不是限定的，外延层900的材质可以与有源区110的材质不同，预设金属可以为锗，也可以为其他金属。
在一些可能的示例中，部分有源区110上不设置外延层900，该部分有源区110后续形成NMOS；部分有源区110上设置外延层900，该部分有源区110后续形成PMOS。
参照图47，本申请实施例提供一种半导体结构，该半导体结构包括基底100、第一阻挡层200、介质层300和第一导电层400。其中，基底100包括核心区和外围区，核心区和外围区可以相邻接，核心区如图46中所示的A区，外围区如图46所示的B区。示例性的，核心区的周向边缘设置外围区，即外围区环绕核心区一周。
基底100内还通常设置有源区110，参照图46，部分有源区110位于核心区，部分有源区110位于外围区。位于核心区内的有源区110间隔较小，位于外围区内的有源区110间隔较大。有源区110之间设置浅槽隔离结构120，浅槽隔离结构120内通常填充氧化物，例如氧化硅，以将各有源区110之间隔开。如图46所示，有源区110上还覆盖氧化物，避免有源区110暴露。
继续参照图46，基底100内通常还设置有埋入式字线130，图46所示的第二截面为平行于字线130的延伸方向且过有源区110的中心的平面。基底100上还设置有第一阻挡层200，第一阻挡层200至少覆盖核心区。第一阻挡层200可以设置在基底100的核心区上，或者第一阻挡层200可以设置在基底100的核心区以及靠近核心区的部分外围区上。
在一种可能的示例中，如图46所示，第一阻挡层200覆盖核心区和部分外围区，即核心区位于第一阻挡层200在基底100上的正投影的内部区域。第一阻挡层200的材质可以为氮化硅，第一阻挡层200的厚度可以为200nm-600nm。
介质层300设置在基底100和部分第一阻挡层200上，即介质层300与第一阻挡层200部分重叠。介质层300的厚度可以为50nm-200nm，介质层300可以具有较高的介电常数，其材质可以为氧化铪、掺硅氧化铪、掺硅氧化锆等。
如图46所示，介质层300覆盖外围区的基底100以及靠近外围区的部分第一阻挡层200。示例性的，介质层300在基底100上的正投影与第一阻挡层200在基底100上的正投影的重合，重合区域的宽度尺寸为20nm-100nm。
第一导电层400设置在介质层300上，如图46所示，第一导电层400覆盖介质层300的上表面。第一导电层400的材质可以为多晶硅，第一导电层400的厚度可以为300nm-600nm。
继续参照图46，半导体结构还包括第三导电层500和第二阻挡层600，第三导电层500设置在第一阻挡层200和第一导电层400上，第二阻挡层600设置在第三导电层500上。
第三导电层500可以包括靠近基底100的氮化钛层，以及设置在氮化钛层上的钨层，第三导电层500的厚度可以为50nm-200nm，第二阻挡层600的材质可以为氮化硅。
继续参照图46，第二阻挡层600背离基底100的表面齐平，且第三导电层500的上表面未显露，即第二阻挡层600覆盖第三导电层500的上表面。如图46所示，介质层300、第一导电层400和第三导电层500的上表面在第一阻挡层200与基底100的交界区域形成有台阶，第二阻挡层600的上表面齐平。
需要说明的是，第一阻挡层200的上表面形成有位线接触孔，位线接触孔延伸至基底100，且位线接触孔的底部暴露核心区内的有源区110，位线接触孔内填充第二导电层800。第二导电层800可以与第一阻挡层200齐平。可以理解的是，第三导电层500设置在第一阻挡层200和第二导电层800上，且第二导电层800与第三导电层500电连接。
参照图48和图49，位于外围区内的部分有源区110上设置有外延层900，外延层900含有预设金属。如图48所示，部分有源区110上不设置外延层900，该部分有源区110后续形成NMOS；如图49所示，部分有源区110上设置外延层900，该部分有源区110后续形成PMOS。其中，有 源区110和外延层900的材质可以为硅，预设金属可以为锗。
本申请实施例提供的半导体结构包括基底100、第一阻挡层200、介质层300和第一导电层400，其中，基底100包括核心区和位于核心区外且与核心区相邻的外围区，基底100内还设置有源区110；第一阻挡层200设置在基底100上，第一阻挡层200至少覆盖核心区；介质层300设置在基底100和部分第一阻挡层200上，第一导电层400设置在介质层300上。通过在基底100和部分第一阻挡层200上设置介质层300，使得基底100的部分区域覆盖第一阻挡层200，基底100的部分区域覆盖介质层300，且第一阻挡层200和介质层300部分重叠，从而减少基底100的暴露，降低基底100被去除部分的风险，进而降低了基底100内的器件暴露甚至损伤的风险。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种半导体结构的制作方法，其中，包括：
    提供基底，所述基底包括核心区和位于所述核心区外且与所述核心区相邻的外围区，所述基底上还形成有预设阻挡层，所述预设阻挡层覆盖所述核心区和所述外围区；
    去除所述外围区对应的至少部分所述预设阻挡层，以暴露部分所述基底，保留的所述预设阻挡层形成第一阻挡层；
    在所述第一阻挡层和所述基底上依次形成层叠的介质层和第一导电层；
    去除所述第一阻挡层上的部分所述介质层和部分所述第一导电层，保留所述第一阻挡层上靠近所述外围区的部分所述介质层和部分所述第一导电层。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述介质层在所述基底上的正投影与所述第一阻挡层在所述基底上的正投影部分重合，且重合区域的宽度尺寸为20nm-100nm。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，去除所述外围区对应的至少部分所述预设阻挡层，以暴露部分所述基底，保留的所述预设阻挡层形成第一阻挡层的步骤包括：
    在所述预设阻挡层上形成第一光刻胶层，所述第一光刻胶层至少覆盖所述核心区对应的所述预设阻挡层；
    以所述第一光刻胶层为掩膜刻蚀所述预设阻挡层，以形成所述第一阻挡层；
    去除所述第一光刻胶层。
  4. 根据权利要求1所述的半导体结构的制作方法，其中，去除所述第一阻挡层上的部分所述介质层和部分所述第一导电层，保留所述第一阻挡层上靠近所述外围区的部分所述介质层和部分所述第一导电层的步骤包括：
    在所述第一导电层上形成第二光刻胶层，所述第二光刻胶层在所述基底上的正投影与所述第一阻挡层在所述基底上的正投影部分重合；
    以所述第二光刻胶层为掩膜刻蚀所述第一导电层和所述介质层，以暴露所述第一阻挡层；
    去除所述第二光刻胶层。
  5. 根据权利要求1所述的半导体结构的制作方法，其中，所述基底内还设置有源区；
    去除所述第一阻挡层上的部分所述介质层和部分所述第一导电层，保留所述第一阻挡层上靠近所述外围区的部分所述介质层和部分所述第一导电层的步骤之后，所述半导体结构的制作方法还包括：
    在所述第一阻挡层和所述基底上形成位线接触孔，所述位线接触孔的底部暴露所述核心区内的所述有源区；
    在所述位线接触孔内形成第二导电层，所述第二导电层与所述第一阻挡层齐平；
    在所述第一阻挡层、所述第二导电层和所述第一导电层上形成第三导电层；
    在所述第三导电层上形成第二阻挡层。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，在所述第三导电层上形成第二阻挡层的步骤之后，所述半导体结构的制作方法还包括：
    对所述第二阻挡层背离所述基底的表面进行平坦化处理，平坦化处理后的所述第二阻挡层未暴露出所述第三导电层。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，通过化学机械研磨对所述第二阻挡层背离所述基底的表面进行平坦化处理。
  8. 根据权利要求6所述的半导体结构的制作方法，其中，在所述第一阻挡层、所述第二导电层和所述第一导电层上形成第三导电层的步骤包括：
    在所述第一阻挡层、所述第二导电层和所述第一导电层上沉积氮化钛层；
    在所述氮化钛层上沉积钨层。
  9. 根据权利要求5所述的半导体结构的制作方法，其中，去除所述第一阻挡层上的部分所述介质层和部分所述第一导电层，保留所述第一阻挡层上靠近所述外围区的部分所述介质层和部分所述第一导电层的步骤之后，所述半导体结构的制作方法还包括：
    在所述外围区内的部分所述有源区上外延生长外延层，所述外延层含有预设金属。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，所述有源区和所述外延层的材质均为硅，所述预设金属为锗。
  11. 根据权利要求1所述的半导体结构的制作方法，其中，所述核心区的周向边缘设有所述外围区，且所述核心区位于所述第一阻挡层在所述基底上的正投影的内部。
  12. 根据权利要求1所述的半导体结构的制作方法，其中，所述第一阻挡层的材质包括氮化硅，所述第一导电层的材质包括多晶硅。
  13. 一种半导体结构，其中，包括：
    基底，所述基底包括核心区和位于所述核心区外且与所述核心区相邻的外围区，所述基底内还设置有源区；
    设置在所述基底上的第一阻挡层，所述第一阻挡层至少覆盖所述核心区；
    设置在所述基底和部分所述第一阻挡层上的介质层；
    设置在所述介质层上的第一导电层。
  14. 根据权利要求13所述的半导体结构，其中，所述介质层在所述基底上的正投影与所述第一阻挡层在所述基底上的正投影部分重合，且重合区域的宽度尺寸为20nm-100nm。
  15. 根据权利要求13所述的半导体结构，其中，所述半导体结构还包括：设置在所述第一阻挡层和所述第一导电层上的第三导电层，以及设置在所述第三导电层上的第二阻挡层，所述第二阻挡层背离所述基底的表面齐平。
  16. 根据权利要求13所述的半导体结构，其中，所述第一阻挡层形成有位线接触孔，所述位线接触孔延伸至所述基底，且位线接触孔的底部暴露所述核心区内的所述有源区；
    所述位线接触孔内填充有第二导电层，所述第二导电层与所述第一阻挡层齐平。
PCT/CN2021/108970 2021-04-23 2021-07-28 半导体结构的制作方法及半导体结构 Ceased WO2022222297A1 (zh)

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