TW200847340A - Semiconductor devices and methods for forming the same - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device comprises a substrate. At least two deep trench capacitors are formed in the substrate. A recesses gate is in the substrate and between the deep trench capacitors. A plurality of word lines are formed on the substrate and pass the deep trench capacitors and the recesses gate. A doped silicon layer is formed on the substrate and between the word lines, wherein the doped silicon layer is a source/drain region.

Description

200847340 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device and a method of fabricating the same, and in particular to a memory device and a method of fabricating the same. [Prior Art] With the widespread use of integrated circuits, various types of semiconductor devices with higher performance and lower price are produced in succession for different purposes, among which, " Dynamic Random Access Memory (DRAM) is nowadays The information electronics industry has an indispensable position. Most DRAM cells today consist of a transistor and a capacitor. Since the memory capacity of DRAM has reached 256 million bits or even 512 million bits or more, the memory cell and the size of the transistor need to be greatly reduced in order to create a memory in the case where the component accumulation requirement is higher and higher. Higher capacity, faster processing DRAM. However, conventional planar transistor technology requires more wafer surface area and product, and it is difficult to achieve the above-mentioned high memory capacity, high integration, and high fast processing speed. Therefore, the application of embedded gate vertical transistor technology and embedded channel technology to DRAM products to reduce the area of use of transistors and capacitors on semiconductor substrates has improved the above-mentioned shortcomings of conventional planar transistor technology. Embedded gate vertical transistor technology has become an important semiconductor manufacturing technology. 1 is a cross-sectional view of a conventional embedded gate vertical transistor in which embedded gate 129 is surrounded by deep trench capacitor 108 and gate dielectric layer 128 is formed in embedded gate 129. Between the substrate 100 and the substrate 100. Doped region 124 is formed on the substrate adjacent to embedded gate 129

Client's Docket No.: 94144 TTs Docket No: 0548-A50829-TW/final/Claire 5 200847340 100, as the channel area of the embedded gate vertical transistor. The source/drain region 101 of the embedded gate vertical transistor is formed in the substrate 100 on both sides of the embedded gate 129, and the source/drain region 101 can be electrically connected to the deep trench capacitor 108 by the buried strap 111. . The word line 146 is formed on the substrate 100' and spans the back-in gate 129 and the deep trench capacitor 108. Since the source/drain region 101 is adjacent to the embedded gate 129, it is easy to affect the channel of the embedded gate vertical transistor. To solve this problem, the source/drain region 101 is usually isolated by the internal insulating layer 105. Affect the channel f to avoid component failure. However, the fabrication of the internal insulating layer 105 tends to result in an increase in the number of processing steps and an increase in the complexity of the semiconductor device process. Therefore, there is a need for a semiconductor device structure and a manufacturing method that can solve the conventional problems. SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure of an embedded transistor having a source/drain region raised and a source/deuterium region on a substrate, and a method of fabricating the same. The present invention provides a structure of a semiconductor device comprising: a substrate; at least two deep trench capacitors formed in the substrate; an embedded gate 'formed in the substrate' and located between the deep trench capacitors; a buried strap formed in the substrate between the deep trench capacitors and the desired gate, a plurality of word line structures 'on the substrate and across the deep trench capacitors and the embedding a gated layer; a doped twin layer formed on the substrate and located between the word line structures, wherein the doped layer is used as a source/drain region. The invention further provides a structure of a semiconductor device, comprising: a base

Client's Docket No.: 94144 TT's Docket No: 0548-A50829-TW/final/Claire 6 200847340 Bottom; at least two deep trench capacitors formed in the substrate; an embedded gate formed in the substrate and located Between the deep trench capacitors; a buried strap formed in the substrate and located between the deep trench capacitors and the embedded gate; a plurality of word line structures formed in the deep trench capacitors a doped twin layer formed on the substrate between the deep trench capacitor and the diffused gate, wherein the doped twin layer serves as a source/drain a region; and a bit line plug electrically connected to the doped twin layer. The present invention further provides a method of fabricating a semiconductor device, comprising: providing a substrate; forming at least two deep trench capacitors in the substrate; forming an embedded gate in the substrate and between the deep trench capacitors; Forming a buried strap in the substrate, and the buried strap is located between the deep trench capacitor and the embedded gate; forming a plurality of word line structures on the substrate and crossing the deep trench capacitors And the diffused gate forms a doped twin layer on the substrate between the word line structures. The embodiments of the present invention will be described with reference to the drawings, in which like or The demand expands, shrinks or changes. It is to be noted that elements not shown or described in the figures may be in a form known to those skilled in the art, and in addition, when a layer is placed on a substrate or another layer, the layer may be directly on the substrate. Or on another layer, or there may be an intermediation layer in between. 2 to 8 are cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment of the present invention, which are applicable to a memory device such as dynamic random access memory.

Client’s Docket No.: 94144 TT’s Docket No: 0548-A50829-TW/fmal/Claire 7 200847340 fe body (DRAM). Referring to Figure 2, first, a semiconductor substrate 200 is provided which may include an undoped or doped germanium wafer, such as a germanium having a p-type dopant. The substrate 200 includes a memory array region and a peripheral circuit region. For the sake of simplicity of explanation, only the memory array region will be described herein. Next, a plurality of deep trench capacitors 2 〇 8 are formed in the substrate 200. Preferably, the lower half of the bead trench capacitor 208 may comprise an upper electrode 210 composed of polycrystalline slabs, and yttrium oxide-tantalum nitride. A capacitor dielectric layer 212 composed of a stack of yttrium oxide layers and a lower gate 214 formed by doped regions of the substrate 200. The upper half of the trench capacitor 208 may include a collar dielectric layer 216, a conductive layer 218 electrically connected to the upper electrode 210, and a unilateral insulating layer 220 at the top of the trench, wherein the unilateral insulating layer 220 only insulates the trench - the other side of the trench is exposed sideways, and in a subsequent process, one side of the exposure will form a buried strap. After the deep trench capacitor 208 is formed in the substrate 200, the substrate 200 can be self-aligned by an etch process or a patterning process to form the embedded trenches 203 between the deep trench capacitors 208. Referring to FIG. 3, the substrate 200 adjacent to the embedded trench 203 is doped to form a channel region 224 surrounding the embedded trench 203. Then, the gate dielectric layer 228 is formed in the embedded trench in the substrate 200. The side wall of the groove 203. In a consistent embodiment, a thermal process such as thermal oxidation can be used to form the gate dielectric layer 228, which preferably contains germanium oxide. Thereafter, a conductive material, such as polysilicon, tungsten, or tungsten telluride, is embedded in the embedded trench 203 to form the embedded gate 229. The outer diffusion region can be simultaneously formed in the substrate 200 as the buried strap 222 during the thermal process of forming the gate dielectric layer 228 and/or the thermal process occurring in other subsequent processes. At this time, the gate dielectric layer 228 and the embedded gate 229 together form a substrate 200 between the deep trench capacitors 208.

Client’s Docket No.: 94144 TT5s Docket No: 0548-A50829-TW/fmal/Claire 8 200847340 Embedded transistor 230. Referring to FIG. 4, after the gate dielectric layer 228 and the embedded gate 229 are formed, the surface of the substrate 200 may be planarized by a chemical mechanical polishing method (CMP) or an etching back method. Next, one or more layers of conductive material and a layer of dielectric material (not shown) are deposited in a comprehensive manner on the substrate 200. For example, the layer of conductive material may comprise a polycrystalline layer or a metal layer such as tungsten or stellite, and the dielectric material layer may comprise, for example, tantalum nitride or cerium oxide. Thereafter, the conductive material layer and the dielectric material layer are patterned by a lithography and etching process to form a word line conductive layer 23 and a word line cap layer 234. As shown in FIG. 4, in an embodiment, the word line conductive layer may include a polycrystalline layer 231 and a metal layer 232, and the word line conductive layer may be formed by chemical vapor deposition. A polycrystalline germanium layer is deposited by a method (CVD), and a metal silicide is formed on the polycrystalline stone layer to form a metal such as Shi Xihua, Tixi, Titan, Shihua, or Molybdenum. Material material; or, a metal halide layer may be deposited on the polysilicon layer by chemical vapor deposition. At this time, the word line conductive layer 23 232 and the word line cap layer 234 collectively constitute the word line structure 288. Next, an insulating spacer 236 such as hafnium oxide or tantalum carbide is formed on the sidewall of the word line structure 288, and the method includes the method of depositing the insulating spacer material on the substrate 200 in a comprehensive manner, followed by dry etching. Etching the insulating spacer material to leave insulating spacers 236 on the sidewalls of the polysilicon layer 231 and the metal germanium layer 232, and exposing portions of the substrate 200. Referring to FIG. 5, the key steps of the present invention will be followed. First, the dream layer 240' is grown on the substrate 200 between adjacent word line structures 2 8 8 'which may be an epitaxial Si layer. Broken crystal

Client's Docket No.: 94144 TT?s Docket No: 0548-A50829-TW/final/Claire 9 200847340 f The growth thickness of layer 240 is preferably lower than the top of word line structure 288, that is, twin layer 240 The top is preferably below the top of the word line structure 288, and the grown thickness of the twin layer 240 is substantially greater than about one-half the height of the word line structure 288. Then, the twinned layer 240 may be doped by a method such as ion implantation to make the doped twin layer 240 on the substrate 200 on both sides of the channel region 224 as an embedded transistor. Source region S of 230 and non-polar region D. In the embodiment of the present invention, the immersed transistor 230 has a source/depolarization S, D' formed on the surface of the substrate 200, thereby reducing the influence of the source/no-polar s, D on the channel region 224. Preferably, after the formation of the twinned layer 240, a metal telluride material layer 245 for reducing the contact resistance may be formed on the twinned layer 240, which may include cobalt telluride, titanium telluride, tungsten telluride, germanium telluride or germanium. Molybdenum, as shown in Figure 5. The metal telluride material layer 245 can be formed by a self-aligned silicidation (SALICIDE) process, which can include a thermal tempering process. Referring to FIG. 6, a dielectric material layer 25 is formed over the substrate 200. For example, the dielectric material layer 250 may be deposited with a layer of ruthenium (BPSG) and then subjected to a reflow process. In order to flatten the borophosphorus bismuth glass layer. The dielectric material layer 250 may also be other dielectric materials such as tantalum nitride, hafnium oxide, niobium oxynitride; or a low dielectric constant liner such as polyimide, spin glass (SOG) flupe Slope (materials, etc. material). The material output portion I is formed. Referring to FIG. 7, the dielectric layer 250 is patterned by a lithography process and an etching process to form a bit line plug hole 255. The metal telluride material layer 245 on the exposed germanium layer 240. Please refer to Figure 8, followed by the bit line material layer (not shown)

Client's Docket No.: 94144 TT^ Docket No: 0548-A50829-TW/final/Claire 10 200847340 on the first dielectric material layer 250, and filled into the bit line plug hole 255 to form a bit line plug, and then The bit line material layer is patterned to form parallel bit lines 260. In another embodiment (not shown), the bit line and the bit line plug can be selectively formed by a conventional metal double damascene process, and the bit line plug hole 255 is coupled to selectively self-align the reactivity. An ion etch back etch process forms and exposes the metal telluride material layer 245, and the bit line trenches can be formed by applying a simple borophospho-f glass etch through process. Next, deposited gold (f, spring (such as chemical vapor deposition or physical vapor deposition titanium / titanium nitride) and chemical phase deposition tungsten bit line and chemical mechanical polishing to form a bimetallic inlaid bit The wire and the bit line plug. The printing tea photo is shown in Fig. 9, which is a schematic view of the semiconductor device according to the embodiment of the present invention. The deep trench capacitor 208 is arranged in parallel around the embedded gate 229'. A shallow trench isolation structure (ST1) 211 abuts an edge region of the ice trench capacitor 208 and the embedded gate 229, which can be used to isolate the transistor and define the active region 266. The word line structure 288 spans (over deep trenches, capacitors) 2〇8 and embedded gate 299, insulating spacer 236 is formed on the sidewall of the word line structure 288, and the metal telluride material layer 245 and the underlying twin layer (not shown) are formed in adjacent words. The metal telluride material layer 245 formed between the deep line capacitors 2〇8 and the embedded gate 229 and the underlying twin layer 240 are used as the source of the owe pen crystal/> And polar regions. When compared with conventional techniques, the present invention The embedded transistor of the embodiment has a source/german region formed on the substrate, thereby effectively reducing the influence of the source/turn region on the channel of the embedded transistor. With the embodiment of the present invention, the embedded gate is not required An additional inner insulating layer is formed on both sides of the pole, so it can be lowered

Client’s Docket No.: 94144 TT5s Docket No: 0548-A50829-TW/fmal/Claire 11 200847340 The complexity of semiconductor device manufacturing. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

Client's Docket No.: 94144 12 TT5s Docket No:0548-A50829-TW/final/Claire 200847340 [Simple description of the diagram] ^The diagram shows the cross-section of the embedded vertical gate transistor of the knowing body; FIG. 9 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; FIG. 9 is a top view of a semiconductor device according to an embodiment of the present invention;

[Main component symbol description] 1〇〇~substrate; 105~internal insulating layer; 111~embedded tape; 128~gate dielectric layer; 146~word line; 203~post-inlet trench; 210~upper electrode 212~ capacitor dielectric layer; 216~ collar dielectric layer; 220~ unilateral insulating layer; 224~channel region; 229~embedded gate; 231,232~word line conductive layer; 236~insulation spacer 245~ metal bismuth material layer; 255~bit line plug hole; 266~ active area; 101~ source/nothing area; 108~deep trench capacitor; 124~channel area; 129~embedded gate; ~ substrate; 208 ~ deep trench capacitor; 211 ~ shallow trench isolation structure; 214 ~ lower electrode; 218 ~ conductive layer; 222 ~ buried band; 228 ~ gate dielectric layer; 230 ~ into transistor; ~ Word line cover layer; 240 ~ Shi Xijing layer; 250 ~ dielectric material layer; 260 ~ bit line; 288 ~ word line structure.

Client’s Docket No.: 94144 TT5s Docket No:0548-A50829-TW/final/Claire 13

Claims (1)

200847340 X. Patent application scope: 1. The structure of a semiconductor device, comprising: a substrate; at least two deep trench capacitors formed in the substrate; an embedded gate formed in the substrate and located in the deep trenches Between the trench capacitors; a buried strap formed in the substrate between the deep trench capacitors and the embedded gate; f a plurality of word line structures on the substrate and spanning the deep trenches a trench capacitor and the embedded gate; and a doped twin layer formed on the substrate between the word line structures, wherein the doped twin layer acts as a source/drain Area. 2. The structure of the semiconductor device of claim 1, wherein the top of the doped twin layer is lower than the top of the word line structures. 3. The structure of the semiconductor device of claim 1, further comprising: a metal lithium material layer formed on the doped layer. 4. The structure of a semiconductor device according to claim 3, wherein the top of the metal halide material layer is lower than the top of the word line structures. 5. The structure of the semiconductor device of claim 1, wherein the doped twin layer comprises an epitaxial germanium. 6. The structure of the semiconductor device of claim 1, further comprising: a one-dimensional plug electrically connected to the doped twin layer. 7. The structure of the semiconductor device according to claim 1, Client's Docket No.: 94144 TT^ Docket No: 0548-A50829-TW/final/Claire 14 200847340 wherein the substrate adjacent to the embedded gate has a doped region to form a channel region surrounding the embedded gate. 8. The structure of a semiconductor device according to claim 3, wherein the metal halide material layer comprises cobalt telluride, titanium telluride, tungsten telluride, germanium telluride or germanium molybdenum. 9. The structure of the semiconductor device of claim 1, further comprising: an insulating spacer formed on a sidewall of the word line structure, the insulating gap spacer isolating the word lines Structure and the twin layer. The structure of the semiconductor device according to the first aspect of the invention, wherein the bit line structure comprises polycrystalline germanium, cobalt telluride, titanium telluride, germanium, or a group of indium. 11. A semiconductor device structure comprising: a substrate; at least two deep trench capacitors formed in the substrate; an embedded gate formed in the substrate and located between the deep trench capacitors; " a buried strap is formed in the substrate and located between the deep trench capacitors and the embedded gate; a plurality of word line structures are formed on the deep trench capacitors and the embedded gate, a doped germanium layer formed on the substrate between the deep trench capacitor and the embedded gate, wherein the doped twin layer acts as a source / > and a polar region, and a bit line A plug electrically connecting the doped twin layer. 12. The junction of the semiconductor device described in claim 11 of the invention, the client's Docket No.: 94144 TT's Docket No: 0548_A50829-TW/final/Claire 15 200847340, wherein the top of the doped twin layer is lower than the The top of these word line structures. 13. The structure of the semiconductor device of claim 11, further comprising: a layer of a metallization material formed on the doped layer. 14. The structure of a semiconductor device according to claim 13 wherein the top of the metal halide material layer is below the top of the word line structures. 15. The junction structure of a semiconductor device according to claim 11, wherein the doped twin layer comprises an epitaxial germanium. 16. The structure of a semiconductor device according to claim 11, wherein the substrate adjacent to the embedded gate has a doped region to form a channel region surrounding the embedded gate. 17. The structure of a semiconductor device according to claim 13, wherein the metallurgical material layer comprises a Shixihua drill, a Shixi Huaqin, a Shihua tungsten, a bismuth telluride or a molybdenum telluride. 18. A method of fabricating a semiconductor device, comprising: f providing a substrate; forming at least two deep trench capacitors in the substrate; forming an embedded gate in the substrate and between the deep trench capacitors; Forming a buried strap in the substrate, and the buried strap is located between the deep trench capacitors and the embedded gate; forming a plurality of word line structures on the substrate and crossing the deep trench capacitors And the embedded gate; and a substrate forming a doped twin layer between the word line structures. Client's Docket No.: 94144 TT?s Docket No: 0548-A50829-TW/final/Claire 16 200847340 on. 19. The method of fabricating a semiconductor device according to claim 18, wherein the step of forming the doped twin layer comprises: growing a twin layer on the substrate between the word line structures; And performing an ion implantation process to dope the layer. 20. The method of fabricating a semiconductor device according to claim 18, wherein the word line structure comprises polycrystalline germanium, cobalt telluride, titanium telluride, r tungsten germanium, germanium telluride or germanium molybdenum. The method of fabricating a semiconductor device according to claim 18, further comprising: forming a layer of a metallization material on the doped layer. 22. The method of fabricating a semiconductor device according to claim 21, wherein the metal halide material layer is formed by an automatic alignment metal halide process. 23. The method of fabricating a semiconductor device according to claim 18, wherein a top of the doped twin layer is lower than a " top of the word line structures. 24. The method of fabricating a semiconductor device according to claim 21, wherein the top of the metal halide material layer is lower than the top of the word line structures. 25. The method of fabricating a semiconductor device according to claim 18, wherein the doped twin layer comprises an epitaxial germanium. 26. The method of fabricating a semiconductor device according to claim 18, further comprising: a one-dimensional plug electrically connecting the doped twin layer. The method of manufacturing a semiconductor device according to claim 18, further comprising: abutting the embedded gate The substrate is doped to form a channel region surrounding the embedded gate. 28. The method of fabricating a semiconductor device according to claim 21, wherein the metal telluride material layer comprises bismuth telluride, titanium telluride, tungsten telluride, bismuth telluride or bismuth molybdenum. 29. The method of fabricating a semiconductor device according to claim 18, further comprising: forming an insulating spacer on the sidewall of the word line structure, the insulating spacer separating the word line structures And the twin layer. 30. The method of fabricating a semiconductor device according to claim 18, wherein the bit line structure comprises polycrystalline germanium, cobalt telluride, titanium telluride, tungsten telluride, germanium telluride or germanium molybdenum. The method of fabricating a semiconductor device according to claim 18, wherein the doped twin layer is a source/drain region. Client’s Docket No.: 94144 18 TT’s Docket No:0548-A50829-TW/fmal/Claire