WO2022221060A1 - Method of correcting wafer bow using a direct write stress film - Google Patents

Method of correcting wafer bow using a direct write stress film Download PDF

Info

Publication number
WO2022221060A1
WO2022221060A1 PCT/US2022/022529 US2022022529W WO2022221060A1 WO 2022221060 A1 WO2022221060 A1 WO 2022221060A1 US 2022022529 W US2022022529 W US 2022022529W WO 2022221060 A1 WO2022221060 A1 WO 2022221060A1
Authority
WO
WIPO (PCT)
Prior art keywords
bow
stress
modification
stress film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2022/022529
Other languages
English (en)
French (fr)
Inventor
Charlotte Cutler
Michael Murphy
David Conklin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
Original Assignee
Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd, Tokyo Electron US Holdings Inc filed Critical Tokyo Electron Ltd
Priority to KR1020237037722A priority Critical patent/KR20230170006A/ko
Priority to JP2023562960A priority patent/JP2024517612A/ja
Priority to CN202280028480.5A priority patent/CN117321735A/zh
Publication of WO2022221060A1 publication Critical patent/WO2022221060A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90Thermal treatments, e.g. annealing or sintering
    • H10P95/906Thermal treatments, e.g. annealing or sintering for altering the shape of semiconductors, e.g. smoothing the surface
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20Exposure; Apparatus therefor
    • G03F7/2022Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/203Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/038Macromolecular compounds which are rendered insoluble or differentially wettable
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/09Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/095Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
    • H10P14/6342Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68Organic materials, e.g. photoresists
    • H10P14/683Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/08Planarisation of organic insulating materials

Definitions

  • Photolithography also called microlithography
  • Photolithography uses radiation, such as ultraviolet or visible light, to generate fine patterns in a semiconductor device design.
  • semiconductor devices such as diodes, transistors, and integrated circuits, can be constructed using semiconductor fabrication techniques including photolithography, etching, film deposition, surface cleaning, metallization, and so forth.
  • Exposure systems also called tools are used to implement photolithographic techniques.
  • An exposure system typically includes an illumination system, a reticle (also called a photomask) or spatial light modulator (SLM) for creating a circuit pattern, a projection system, and a wafer alignment stage for aligning a photosensitive resist-covered semiconductor wafer.
  • the illumination system illuminates a region of the reticle or SLM with a (preferably) rectangular slot illumination field.
  • the projection system projects an image of the illuminated region of the reticle pattern onto the wafer. For accurate projection, it is important to expose a pattern of light on a wafer that is relatively flat or planar, preferably having less than 10 microns of height deviation. Thus, a method for correcting any wafer bow is desired.
  • the present disclosure relates to a method of processing a substrate, including forming a bow modification stress film on a backside of a wafer, the wafer including a working surface and the backside opposite the working surface, the bow modification stress film including a stress-modification agent, the bow modification stress film being sensitive to a predetermined wavelength of actinic radiation; exposing the bow modification stress film to a pattern of the actinic radiation at the predetermined wavelength, the bow modification stress film configured to release the stress-modification agent at locations along the bow modification stress film exposed to the pattern of the actinic radiation, a concentration of the released stress-modification agent corresponding to the pattern of the actinic radiation; and executing a curing process, the curing process activating the released stress-modification agent and causing a stress change within the bow modification stress film, the stress change modifying a bow of the wafer.
  • the present disclosure additionally relates to a method of processing a substrate, including forming a first bow modification stress film on a backside of a wafer, the wafer including a working surface and the backside opposite the working surface, the first bow modification stress film configured to release a first stress-modification agent in response to actinic radiation having a first predetermined wavelength; forming a second bow modification stress film on the first bow modification stress film, the second bow modification stress film configured to release a second stress-modification agent in response to the actinic radiation having a second predetermined wavelength; exposing the first bow modification stress film and the second bow modification stress film to a first pattern of the actinic radiation at the first predetermined wavelength, the first bow modification stress film configured to release the first stress-modification agent at locations along the first bow modification stress film exposed to the first pattern of the actinic radiation, a concentration of the released first stress-modification agent corresponding to the first pattern of the actinic radiation; exposing the first bow modification stress film and the second bow modification stress film to a second pattern
  • FIG.1A is a perspective-view schematic of layers on a wafer having a defect introduced in one of the layers.
  • FIG.1B is a schematic of various types and severities of resulting wafer bow.
  • FIGs.2A-2C are stress maps for a bow mitigation stress film arranged on a wafer and exposed to actinic radiation, according to an embodiment of the present disclosure.
  • FIG.3 is a cross-sectional substrate segment illustrating structures or devices formed on a surface, according to an embodiment of the present disclosure.
  • FIG.4 is a cross-sectional substrate segment illustrating a bow modification stress film formed on the backside of the wafer, according to an embodiment of the present disclosure.
  • FIG.5 is a cross-sectional substrate segment illustrating exposure of the stress film, according to an embodiment of the present disclosure.
  • FIG.6 is a cross-sectional substrate segment illustrating the stress film after exposure, according to an embodiment of the present disclosure.
  • FIG.7 is a flow chart for a method of fabricating a semiconductor device, according to an embodiment of the present disclosure. DETAILED DESCRIPTION [0018]
  • the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • spatially relative terms such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • the spin-on film can be based on a film that undergoes crosslinking/decrosslinking under external stimulus where direct write is achieved by, but is not limited to, 365 nm exposure and subsequent cure is used to "pattern-in" stress. Moreover, the film need not be limited to a spin-on process, and other deposition methods may be used. A develop step is not required with techniques herein (but can be optional), which provides additional significant benefit. An amount of bow (or internal stress to create or affect a bow signature) can be tuned with exposure dose, bake temperature, bake time and number of bakes.
  • the stress-modification films herein can be organic in nature and have the characteristics or components to crosslink upon exposure to light, or crosslink after light exposure followed by a bake or cure step.
  • FIG.1A is a perspective-view schematic of layers on a wafer having a defect introduced in one of the layers.
  • 128 layers can be used for 3D NAND devices on a 300 mm wafer.
  • a defect in an underlaying, earlier layer can be magnified to cause severe bow with later layers.
  • FIG.1B shows the systematic increase in the number of layers in the front side 3D NAND stack results in further wafer bow and increases the severity of the problem.
  • Some mitigation strategies include depositing silicon nitride films on the backside of the wafer via, for example, chemical vapor deposition (CVD), which can cause a large amount of stress on the wafer and the devices. Then, predetermined portions of the silicon nitride can be imaged, illuminated, or exposed, and subsequently removed, alleviating the stress in certain points on the wafer, hence re-shaping the wafer in a different manner.
  • CVD chemical vapor deposition
  • the problem introduced via the silicon nitride film method is that the method requires different tooling, which can mean a simple track-based process may be incompatible, and thus it can require loading the wafers into an entirely different tool. Furthermore, the method can also be time-consuming to put the desired amount of silicon nitride on the back of the wafers. Additionally, the method is generally a very complex process to image the silicon nitride films or to tune the patterns in the silicon nitride film to alleviate the bow of the water. [0023] Described herein, an organic-based, cross-linkable bow mitigation film can be deposited on the backside of a wafer. The bow mitigation film can allow flexibility in global as well as local bow mitigation.
  • global bow mitigation can be applied to the film.
  • local bow mitigation can be applied via a programmable direct write stress pattern on the film on the backside of the wafer, wherein the direct write stress pattern can be based on a bow modification stress map (herein referred to as “stress map) of the front side.
  • the bow mitigation film is a polymer-based, organic film that is deposited on the backside of the wafer using tools that can allow continuous processing in a track-based process.
  • a predetermined wavelength of actinic radiation can be applied to image, illuminate, or expose the film based on the stress map to embed stress into the film and thereby the wafer that mitigates the undesirable bow on the opposite side or surface.
  • the exposure process which can include an exposure step and a heat or bake step, need not require a develop step.
  • this method can be deemed a direct-write process to produce the bow mitigation film.
  • the bow mitigation film can also be described as a stress film, in that the film can be embedded with stress to mitigate the wafer bow.
  • the tool can handle (i.e., move, transport, and manipulate) wafers but can experience handling issues when wafer bow approaches and exceeds 300 ⁇ m.
  • methods described herein can allow an increase of secondary bow mitigation up to 150 ⁇ m while maintaining 300-400 ⁇ m primary bow mitigation. Although this is a direct-write, a develop step can still be included.
  • the develop step can allow flexibility in higher cure temperatures when unexposed material is present in the areas that have not been exposed to light. If, for example, a photoacid generator decomposition temperature is not high, these areas can also be crosslinked at high temperatures.
  • methods described herein can leverage chemistries including epoxy acrylates, epoxy novolaks, benzene cyclobutadiene (BCB) chemistry where Diels Alder reactions can induce crosslinking, and polyimides.
  • BCB benzene cyclobutadiene
  • Other types of chemistry that can be used include any photo-initiating chemistry that causes crosslinking or bond rearrangement to form some type of stress upon irradiation and subsequent heating, or just exposure.
  • an organic formulation can be deposited on the surface of a wafer through a spin coat process or any deposition process.
  • the film can be baked to remove excess solvent.
  • the film can then be exposed to a pattern of actinic radiation.
  • This pattern of actinic radiation can define a stress modification pattern or can be based on a stress modification pattern.
  • Various lithography tools can be used.
  • a direct-write laser or lithography tool can be used. This can be a digital light processing (DLP) chip, laser galvanometer, etc., that projects a pattern as one image or as a scan.
  • DLP digital light processing
  • a mask-based lithographic exposure using a scanner or stepper tool can be used.
  • direct-write tools have lower resolution than mask-based tools, the resolution needed to fine tune stress can be much lower as compared to patterning transistors.
  • a stress map created with a mask can be static, whereas using a direct-write tool can be dynamic so a stress map can be created or projected and changed on a wafer-by-wafer basis if desired.
  • the wavelength of light i.e., the actinic radiation
  • Wavelength can be dependent on components included in a given organic film.
  • Embodiments herein can also include using multiple films that respond to different wavelengths of light.
  • the film can be heated during a post exposure bake.
  • a develop step is not required and the film can then be cured at a higher temperature, the time and temperature of which can be dependent on the thickness of the film and the amount of stress required.
  • a development step can be executed before curing, but this is optional. Curing temperature should be high enough to induce a more complete crosslinking within the film.
  • FIGs.2A-2C are stress maps for a bow mitigation stress film arranged on a wafer and exposed to actinic radiation, according to an embodiment of the present disclosure.
  • the wafer can include a first surface and a second surface.
  • the first surface of the wafer can be a working surface where the target devices are fabricated and the second surface can be a backside of the wafer.
  • the backside of the wafer can have the bow modification stress film (herein referred to as “stress film”) formed thereon.
  • the stress film can be an organic film, or a polymer-based film.
  • FIGs.2A-2C demonstrate how the organic stress film can affect wafer bow.
  • the stress film can be deposited on the backside of the wafer via, for example, spin-coating.
  • Other deposition processes can be contemplated, such as sputter coating, spray coating, doctor blading, CVD, physical vapor deposition (PVD), and atomic layer deposition (ALD), among others.
  • the stress film can be exposed according to a predetermined pattern or shape, such as a strip of the stress film through a middle of the wafer. As shown in FIGs.2A- 2C, a 100 mm strip of the stress film was exposed down a middle of the wafer and exposed to light having a 365 nm wavelength.
  • the wafer including the exposed stress film can be heated during a post-exposure bake, then cured at higher temperatures.
  • FIGs.2A-2C show process conditions in the table (left) and corresponding stress maps for an epoxy novolak film with resulting saddle pattern images through a center of the wafer.
  • a first cure was performed at 175oC for 10 minutes, which resulted in a wafer bow of approximately 88 ⁇ m for the stress film having a thickness of 17 ⁇ m.
  • a second cure was performed at 200oC for an additional 10 minutes, which resulted in a wafer bow of approximately 214 ⁇ m.
  • a third cure was performed at 200oC for an additional 5 minutes, which resulted in a wafer bow of approximately 260 ⁇ m.
  • the chemistries included in such stress films can include, but are not limited to, epoxy acrylates, epoxy novolaks, BCB chemistry where Diels Alder reactions can induce crosslinking, and polyimides.
  • the wafer bows shown in FIGs. 2A-2C demonstrate that the stress film can indeed cause wafer bow, and as such, can be used on a wafer already bowed due to the devices fabricated thereon in order to mitigate or correct said wafer bow.
  • coater developer systems can be used for spin-on deposition of stress films herein. These tools can include multiple modules for coating wafers, baking wafers, and developing films. Coater-developer tools described herein can also include direct-write exposure modules. The coater developer system can then shuttle wafers between the various spin coating, baking/curing modules, and exposure modules, or to an attached scanner/stepper tool. Moreover, the coater developer tools described herein can also include point-of-dispense mixing. That is, chemicals can be mixed at or proximate to a dispense nozzle, immediately prior to dispensing on the wafer. For example, a solvent can be added to a resist at the nozzle to modulate viscosity or film thickness.
  • FIG.3 is a cross-sectional substrate segment illustrating structures or devices 399 formed on a surface, according to an embodiment of the present disclosure.
  • a wafer 305 includes a first surface 310 and a second surface 315.
  • the first surface 310 of the wafer can be a working surface where the target devices are fabricated and the second surface 315 can be a backside of the wafer.
  • the devices 399 formed on the working surface 310 can be active devices or partially formed active devices such as transistors or memory cells.
  • the wafer 305 can be received in a coating module of a coater-developer tool or other track-based tool.
  • FIG.4 is a cross-sectional substrate segment illustrating a bow modification stress film 325 (herein referred to as “stress film 325”) formed on the backside 315 of the wafer 305, according to an embodiment of the present disclosure.
  • the wafer 305 can be flipped and the stress film 325 can be formed on the backside 315, but the wafer 305 need not be flipped.
  • the tool can include systems for vertically upward directed coating, spraying, or deposition. That is, the wafer 305 can continue on the track and the tool can form the stress film 315 on the backside 315 of the wafer by spray coating.
  • the stress film 325 can be formed on the backside 315, and the stress film 325 can be an organic film configured to release a stress-modification agent in response to actinic radiation. That is, the stress film 325 can include one or more photo acid generators, thermal acid generators, photo initiators, photo destructive bases, or the like.
  • the stress film 325 can include various epoxy materials or resins or other organic materials that will result in stresses (tensile or compressive) within the stress film 325 from curing in the presence of acids, bases, or radicals.
  • a protective fill or protective film can be deposited, or a carrier wafer can be attached, to facilitate handling of the wafer 305.
  • working surface 310 and the backside 315 are used herein to label opposing sides of the wafer 305. In some microfabrication processes, a given wafer can have active devices or power delivery structures formed on both sides. In this case, either the working surface 310 or the backside 315 can receive the stress film 325 depending on fabrication process stage.
  • FIG.5 is a cross-sectional substrate segment illustrating exposure of the stress film 325, according to an embodiment of the present disclosure.
  • the stress film 325 can be exposed to a pattern of actinic radiation that releases the stress-modification agent within the stress film 325.
  • This exposure step can be executed within a direct write module on the coater-developer tool or be transferred to a separate or connected tool for exposure.
  • the actinic radiation can be patterned wherein more or less radiation is received at coordinate locations on the backside 315 of the wafer 305 having the stress film 325. Resolution can be dependent on a particular lithography system selected for executing the exposure.
  • FIG.6 is a cross-sectional substrate segment illustrating the stress film 325 after exposure, according to an embodiment of the present disclosure.
  • one or more curing steps can be executed, such as those described in FIGs.2A-2C.
  • the wafer 305 can be transferred to a bake/curing module of the coater developer tool.
  • the curing process can activate the stress-modification agent in the stress film 325 and cause a modified stress within the stress film 325 sufficient to modify bow of the wafer 305.
  • a photoacid generator (in a non-limiting example) can produce a photoacid which in turn catalyzes an epoxy crosslinking reaction upon bake and cure. It is the crosslinking reaction in the stress film 325 that causes the stress mitigation.
  • the imaging or exposure to the pattern of actinic radiation can directly change the stress film 325 and thereby directly change or modify bow of the wafer 305.
  • the stress can be alleviated with imaging and removing bonding interactions, such as hydrogen bonding interactions, via the patterned exposure. That is, instead of inducing stress, the patterned exposure can relieve the stress through activating, for example, a photoactive compound (PAC) and removing the inhibition effect of the pre-exposed PAC.
  • PAC photoactive compound
  • the modified stress can be caused by crosslinking, modified bonds among species, or other entanglement.
  • the amount of, for example, cross-linking of the stress film 325 via the stress-modification agent can correspond to the concentration of the stress-modification agent released at the given coordinate location based on the pattern of the actinic radiation.
  • the stress can be tensile or compressive internal stress.
  • the resulting stress in the stress film 325 can then, for example, counter-act stresses in the wafer from microfabrication process steps.
  • FIG.6 illustrates the stress film 325 having more or less stress by coordinate location in the stress film 325 based on the projected pattern of light and curing step or steps.
  • a warped wafer can be flattened with the stress film 325 described herein.
  • the direct write programmable pattern essentially activates (or pre-activates) stress through cross-linking or chemical transformation that is activated by a particular wavelength of light or electromagnetic energy that can include longer wavelengths in the infrared (IR) or thermal regions.
  • the IR wavelengths can be used to pattern the stress film 325 through the wafer 305, that is, exposed through the working surface 310.
  • device fabrication on the working surface of the wafer may impair the ability to pattern the stress film 325 through the wafer, particularly at later stages of the device fabrication process.
  • the backside film may be activated using a wafer chuck with spatial temperature control either in the track device or in the device fabrication equipment. Stress activation can be tailored using different wavelengths of light based on additives instead of a polymer in a given organic film.
  • the stress film 325 herein therefore induces a counter stress instead of releasing stress as with etched films, but no etch step is needed.
  • the wafer can be flipped over (such as the wafer of FIG.5) so the electromagnetic energy is being patterned onto the side that is being imaged instead of via the backside 315. [0043] As previously described, a developing process or step can be executed before curing.
  • a mismatch in the height on the backside of the wafer can result.
  • a fill can be deposited or formed over the stress film 325 on the backside.
  • the backfill can then be planarized prior to flipping the wafer 305 back over for continued fabrication and processing, otherwise the mismatch of the film height in specific locations could itself induce mis-shape of the wafer 305.
  • direct write a planar film can be formed, bow can be induced, and the film remains planar.
  • two or more stress films 325 can be deposited.
  • Each given film can be activated by a same or different wavelength.
  • This multi-layer process can be used to create cumulative or differential stress.
  • films herein can be activated simply by targeted or patterned heating without a photo-activated pattern step (i.e., global bow mitigation).
  • a zone-based heating or mask-based heating cure or microwave heating can cause location-specific crosslinking.
  • either a photo acid generator (PAG) or thermal acid generator (TAG) can be used because most PAGs can act as TAGs at sufficiently high temperatures.
  • backside integration of the stress films can lead to tradeoffs that can impact device yield.
  • the stress film 325 can be formed on the working surface 310, such as in areas between devices on the wafer 305, along a periphery of the working surface 310, or even on top of the devices.
  • Techniques herein can affect wafer bow of hundreds of microns, which is sufficient to counteract wafer bow and warpage observed on wafers during semiconductor manufacturing.
  • Resulting bow modification herein can be first order and second order bowing correction, such as a saddle bow. Techniques herein can be used throughout the semiconductor fabrication process.
  • FIG.7 is a flow chart for a method 700 of processing a substrate, according to an embodiment of the present disclosure.
  • the wafer 305 can be received by the tool, the wafer 305 include the first surface 310 (the working surface 310) and the second surface 315 (the backside 315).
  • the stress film 325 can be formed on the backside 315 of the wafer 305.
  • the stress film 325 can include a stress-modification agent, the stress film 325 being sensitive to the predetermined wavelength of the actinic radiation.
  • the stress film 325 can be exposed to the pattern of the actinic radiation at the predetermined wavelength.
  • the stress film 325 can be configured to release the stress- modification agent at locations along the stress film 325 exposed to the pattern of the actinic radiation. A concentration of the released stress-modification agent can correspond to the pattern of the actinic radiation.
  • the curing process can be executed.
  • the curing process can activate the released stress-modification agent and cause a stress change within the stress film 325 to modify a bow of the wafer 305 and bring the wafer 305 closer to planarity.
  • the developing process can optionally be executed before curing.
  • substrate or “target substrate” as used herein generically refers to an object being processed in accordance with the invention.
  • the substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film.
  • substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures.
  • the description may reference particular types of substrates, but this is for illustrative purposes only.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Formation Of Insulating Films (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
PCT/US2022/022529 2021-04-15 2022-03-30 Method of correcting wafer bow using a direct write stress film Ceased WO2022221060A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020237037722A KR20230170006A (ko) 2021-04-15 2022-03-30 다이렉트 라이트 응력막을 사용하여 웨이퍼 휨을 교정하는 방법
JP2023562960A JP2024517612A (ja) 2021-04-15 2022-03-30 直接描画応力膜を用いたウェーハの反り修正方法
CN202280028480.5A CN117321735A (zh) 2021-04-15 2022-03-30 使用直写式应力膜校正晶片弯曲的方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163175123P 2021-04-15 2021-04-15
US63/175,123 2021-04-15
US17/703,072 2022-03-24
US17/703,072 US20220336226A1 (en) 2021-04-15 2022-03-24 Method of correcting wafer bow using a direct write stress film

Publications (1)

Publication Number Publication Date
WO2022221060A1 true WO2022221060A1 (en) 2022-10-20

Family

ID=83602562

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2022/022529 Ceased WO2022221060A1 (en) 2021-04-15 2022-03-30 Method of correcting wafer bow using a direct write stress film

Country Status (6)

Country Link
US (1) US20220336226A1 (https=)
JP (1) JP2024517612A (https=)
KR (1) KR20230170006A (https=)
CN (1) CN117321735A (https=)
TW (1) TW202305956A (https=)
WO (1) WO2022221060A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12455511B2 (en) * 2022-02-04 2025-10-28 Tokyo Electron Limited In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones
CN117275356B (zh) * 2023-11-23 2024-04-12 荣耀终端有限公司 柔性显示屏、电子设备及电子设备组件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130082358A1 (en) * 2010-03-05 2013-04-04 Disco Corporation Single crystal substrate with multilayer film, manufacturing method for single crystal substrate with multilayer film, and element manufacturing method
US20160293556A1 (en) * 2013-12-03 2016-10-06 Invensas Corporation Warpage reduction in structures with electrical circuitry
US20170010540A1 (en) * 2014-03-25 2017-01-12 Carl Zeiss Sms Ltd. Method and apparatus for generating a predetermined three-dimensional contour of an optical component and/or a wafer
US20200091092A1 (en) * 2018-09-14 2020-03-19 Toshiba Memory Corporation Substrate treatment apparatus, method of manufacturing semiconductor device and workpiece substrate
US20200118822A1 (en) * 2018-10-10 2020-04-16 Applied Materials, Inc. Techniques and apparatus for anisotropic stress compensation in substrates using ion implantation

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001230341A (ja) * 2000-02-18 2001-08-24 Hitachi Ltd 半導体装置
JP3929966B2 (ja) * 2003-11-25 2007-06-13 新光電気工業株式会社 半導体装置及びその製造方法
US7282324B2 (en) * 2004-01-05 2007-10-16 Microchem Corp. Photoresist compositions, hardened forms thereof, hardened patterns thereof and metal patterns formed using them
TW200638812A (en) * 2004-11-18 2006-11-01 Matsushita Electric Industrial Co Ltd Wiring board, method for manufacturing same and semiconductor device
JP6047422B2 (ja) * 2013-02-21 2016-12-21 富士フイルム株式会社 感光性組成物、光硬化性組成物、化学増幅型レジスト組成物、レジスト膜、パターン形成方法、及び電子デバイスの製造方法
US10409163B2 (en) * 2014-09-30 2019-09-10 Toray Industries, Inc. Photosensitive resin composition, cured film, element provided with cured film, and method for manufacturing semiconductor device
US10975263B2 (en) * 2016-04-25 2021-04-13 Kaneka Corporation Thermosetting resin composition, cured film and method for producing same, and flexible printed board with cured film and method for producing same
JP7164289B2 (ja) * 2016-09-05 2022-11-01 東京エレクトロン株式会社 半導体プロセッシング中のオーバレイを制御するための湾曲を制御する応力の位置特定チューニング
JP6867522B2 (ja) * 2020-01-21 2021-04-28 デクセリアルズ株式会社 熱硬化性接着シート、及び半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130082358A1 (en) * 2010-03-05 2013-04-04 Disco Corporation Single crystal substrate with multilayer film, manufacturing method for single crystal substrate with multilayer film, and element manufacturing method
US20160293556A1 (en) * 2013-12-03 2016-10-06 Invensas Corporation Warpage reduction in structures with electrical circuitry
US20170010540A1 (en) * 2014-03-25 2017-01-12 Carl Zeiss Sms Ltd. Method and apparatus for generating a predetermined three-dimensional contour of an optical component and/or a wafer
US20200091092A1 (en) * 2018-09-14 2020-03-19 Toshiba Memory Corporation Substrate treatment apparatus, method of manufacturing semiconductor device and workpiece substrate
US20200118822A1 (en) * 2018-10-10 2020-04-16 Applied Materials, Inc. Techniques and apparatus for anisotropic stress compensation in substrates using ion implantation

Also Published As

Publication number Publication date
JP2024517612A (ja) 2024-04-23
CN117321735A (zh) 2023-12-29
KR20230170006A (ko) 2023-12-18
TW202305956A (zh) 2023-02-01
US20220336226A1 (en) 2022-10-20

Similar Documents

Publication Publication Date Title
US10811265B2 (en) Location-specific tuning of stress to control bow to control overlay in semiconductor processing
US11137685B2 (en) Semiconductor method of protecting wafer from bevel contamination
CN101427348B (zh) 用于降低图案中的最小间距的方法
US8043794B2 (en) Method of double patterning, method of processing a plurality of semiconductor wafers and semiconductor device
TWI862635B (zh) 在基板上調整膜應力變遷的方法
US20220336226A1 (en) Method of correcting wafer bow using a direct write stress film
KR102767600B1 (ko) 교정된 조정 선량을 사용하여 임계 치수를 보정하기 위한 방법
CN119270591A (zh) 一种深台面结构侧壁光滑成型的厚胶光刻方法
US12381118B2 (en) 3D multiple location compressing bonded arm for advanced integration
US20250021006A1 (en) Wafer Bow Mitigation
US20240363340A1 (en) Inorganic/hybrid stress films
US8138059B2 (en) Semiconductor device manufacturing method
US20230005737A1 (en) Method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22788643

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202280028480.5

Country of ref document: CN

Ref document number: 2023562960

Country of ref document: JP

ENP Entry into the national phase

Ref document number: 20237037722

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020237037722

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 11202307622W

Country of ref document: SG

122 Ep: pct application non-entry in european phase

Ref document number: 22788643

Country of ref document: EP

Kind code of ref document: A1