WO2022215173A1 - Système de vérification et système de détermination d'une largeur de bit arithmétique à virgule fixe - Google Patents

Système de vérification et système de détermination d'une largeur de bit arithmétique à virgule fixe Download PDF

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WO2022215173A1
WO2022215173A1 PCT/JP2021/014649 JP2021014649W WO2022215173A1 WO 2022215173 A1 WO2022215173 A1 WO 2022215173A1 JP 2021014649 W JP2021014649 W JP 2021014649W WO 2022215173 A1 WO2022215173 A1 WO 2022215173A1
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fixed
bit width
verification
point
calculation
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PCT/JP2021/014649
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English (en)
Japanese (ja)
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伸男 千田
克久 小笠原
治彦 竹山
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三菱電機株式会社
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Priority to PCT/JP2021/014649 priority Critical patent/WO2022215173A1/fr
Priority to JP2022527871A priority patent/JP7235171B2/ja
Publication of WO2022215173A1 publication Critical patent/WO2022215173A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present disclosure relates to a fixed-point arithmetic bit width verification system and determination system.
  • fixed-point arithmetic can reduce circuit scale, reduce power consumption, and improve latency, making it suitable for embedded systems that require space and power savings.
  • Conventional techniques do not propose an efficient fixed-point bit width determination method when the scale of target computation is enormous.
  • no method has been proposed for flexibly determining the fixed-point bit width in fine granularity of operations.
  • the position of the fixed point is collected from the deep learning training data of Patent Document 1, and the bit width of the fixed point is determined.
  • the learning data is enormous, it is difficult to efficiently determine the fixed-point bit width.
  • a fixed-point arithmetic bit width verification system of the present disclosure includes a specification definition unit that determines the number of data in a verification data set using interval estimation by Bernoulli trial based on computation information and defines a generation specification including a target value; A generation unit that generates a verification data set based on the generation specification, a fixed-point calculation unit that generates a calculation result by fixed-point calculation using the verification data set, and a fixed-point calculation based on the calculation result and the generation specification. and a verification unit that verifies whether the conditions are satisfied.
  • the fixed-point arithmetic bit width determination system of the present disclosure uses interval estimation by Bernoulli trials based on arithmetic information in which the importance of arithmetic is defined, and fixed-point bit width and a target value, a generation unit that generates a verification data set based on the generation specification, and a fixed-point calculation unit that generates calculation results by fixed-point calculation using the verification data set. , a verification unit that verifies whether the fixed-point operation satisfies the specifications based on the operation result and the generation specification, and generates a verification result, and an update unit that determines whether the generation specification is updated according to the verification result. ing.
  • FIG. 1 is a block diagram of a fixed-point arithmetic bit width verification system according to Embodiment 1 of the present disclosure
  • FIG. FIG. 4 is a diagram showing an example of calculation information according to Embodiment 1 of the present disclosure
  • FIG. FIG. 10 is a diagram showing an explanation of the Q format
  • FIG. 4 is a flowchart showing the operation of a specification definition unit according to Embodiment 1 of the present disclosure
  • FIG. 10 is a diagram for explaining the probability of being within an assumed bit width
  • FIG. 4 is a diagram illustrating an example of generation specifications according to the first embodiment of the present disclosure
  • FIG. 4 is a flowchart showing operations of a generating unit according to Embodiment 1 of the present disclosure
  • FIG. 4 is a diagram showing an example of a verification data set after conversion into fixed point data according to Embodiments 1 and 2 of the present disclosure
  • 4 is a flow chart showing the operation of a calculation unit according to Embodiments 1 and 2 of the present disclosure
  • FIG. 4 is a diagram showing computation results of the fixed-point computation bit width verification (determination) system according to Embodiments 1 and 2 of the present disclosure
  • 5 is a flowchart illustrating the flow of operations of a verification unit according to Embodiments 1 and 2 of the present disclosure
  • FIG. 10 is a block diagram of a fixed-point arithmetic bit width determination system according to Embodiment 2 of the present disclosure
  • FIG. 13 is a diagram showing an example of calculation information according to Embodiment 2 of the present disclosure
  • FIG. FIG. 10 is a flow chart showing the operation of a specification definition unit according to Embodiment 2 of the present disclosure
  • FIG. FIG. 10 is a diagram showing a probability distribution within the assumed bit width according to Embodiment 2 of the present disclosure
  • FIG. 10 is a diagram showing the importance of the fixed-point operation bit width determination system and the corresponding fixed-point bit widths according to Embodiment 2 of the present disclosure
  • FIG. 10 is a diagram showing generation specifications of a fixed-point arithmetic bit width determination system according to Embodiment 2 of the present disclosure
  • FIG. 1 is a block diagram of a fixed-point arithmetic bit width verification system according to the first embodiment.
  • the fixed-point arithmetic bit width verification system 100 includes a specification definition section 120 , a generation section 140 , an arithmetic section 160 and a verification section 180 .
  • the fixed-point arithmetic bit width verification system 100 may include elements other than these elements.
  • the fixed-point arithmetic bit width verification system 100 is composed of a computer having a processor and memory.
  • the processor may be a central processing unit (CPU) or the like.
  • the memory may be read only memory (ROM), random access memory (RAM), or the like.
  • the specification definition unit 120, generation unit 140, calculation unit 160, and verification unit 180 are configured by a processor executing a program stored in memory. All or part of the specification definition unit 120, the generation unit 140, the calculation unit 160, and the verification unit 180 may be configured by hardware that does not execute programs.
  • the specification definition unit 120 defines the generation specification 130 based on the calculation information 110 input from the outside. Also, the generation unit 140 generates the verification data set 150 based on the generation specification 130 . The calculation unit 160 outputs a calculation result 170 using the calculation information 110 and the verification data set 150 . The verification unit 180 outputs verification results 190 based on the generation specifications 130 and the calculation results 170 .
  • FIG. 2 is a diagram showing an example of the calculation information 110 according to the present embodiment, and the example will be described below.
  • the operation information 110 includes the operation content, which is the content of the operation whose fixed-point bit width is to be verified, the data type used when the variable of the operation content is a floating-point operation, and the bit width of the fixed-point number to be verified.
  • a certain assumed bit width, the minimum guaranteed number of digits (the number of decimal places obtained in the calculation result 170) of the output of the calculation content (calculation result 170), the number of verification data, and the target value are determined. including verification assurance accuracy required for
  • the content of the operation indicates that the operation takes the variables a and b as inputs and the variable out as an output.
  • the data type indicates that the variable a is of float type and the variable out is of float type in the floating-point calculation.
  • the assumed bit width is the bit width in the fixed-point arithmetic of the variable of the operation content, and is 32 bits, and the bit width of each of the integer part and the decimal part within 32 bits is expressed in Q format.
  • FIG. 3 is a diagram explaining the Q format, and shows the bit widths of the integer part and the fractional part in the case of Q15.16. In other words, if Q15.16 is described, it can be understood that the fixed-point data is a total of 32 bits of 1-bit sign, 15-bit integer part, and 16-bit decimal part.
  • the number of guaranteed output digits means that the difference between the floating point calculation and the assumed bit width fixed point calculation is calculated, and the error is 10 -2 . .
  • FIG. 4 is a flow chart showing the operation of the specification definition unit 120.
  • input calculation information 110 is read.
  • step S102 the number of verification data and the target value that is the pass criterion for verification are determined from the verification guaranteed accuracy that has been read.
  • the generation specification 130 is defined by determining the number of data in the verification data set 150 using interval estimation by Bernoulli trials.
  • FIG. 5 is a diagram for explaining the probability of fitting within the assumed bit width, and more specifically, is a graph showing the distribution of the probability of fitting within the assumed bit width in the verification system 100 for the fixed-point arithmetic bit width.
  • X pieces of data are extracted from the population, and the probability of being within the range of the assumed bit width is calculated. It is assumed that the probability distribution within the range of the bit width assumed when this is repeated Y times is given by a normal distribution as shown in FIG. If the interval between 95% and 100% probability of falling within the assumed bit width range is the confidence interval (1- ⁇ ), the probability of falling within the assumed bit width range is (1- ⁇ ) ⁇ 100% probability. will enter the confidence interval.
  • the specification definition unit 120 determines the fixed-point bit width from the assumed bit width of the operation information 110 in step S103.
  • the assumed bit width is 32 (Q15.16)
  • the data width is 32 bits
  • the fixed point data has an integer part of 15 bits and a decimal part of 16 bits.
  • step S104 the allowable error range between the floating-point arithmetic and the fixed-point arithmetic is determined from the guaranteed output digit number of the arithmetic information 110.
  • FIG. When the number of guaranteed output digits is 10 ⁇ 2 , the pass judgment criterion for verification is that the results of the floating-point calculation and the fixed-point calculation match up to the second decimal place.
  • the specification definition unit 120 defines and outputs the generation specification 130 in step S105.
  • FIG. 6 is a diagram illustrating an example of the generation specification 130 defined by the specification definition unit 120. As shown in FIG. The number of data, target value, fixed-point data width (integer part and decimal part), and output precision described in the generation specification 130 are values determined in steps S102 to S104.
  • FIG. 7 is a flow chart showing the operation of the generator 140 according to Embodiment 1 of the present disclosure.
  • the generation unit 140 reads the generation specification 130 in step S121.
  • all verification data sets 150 described in the generation specification 130 are generated by looping from step S122 to step S125.
  • the generation unit 140 randomly generates verification data in the data type described in the generation specification 130 with the number of data described in the generation specification 130 in step S124.
  • the variables a and b are of float type, 4239 pieces of float type data are generated at random.
  • step S125 the data generated in step S124 is converted into a fixed-point number by approximating the assumed bit width described in the generation specification 130 from the floating-point verification data. Once all verification data sets 150 have been generated, they are output at step S126.
  • the generation unit 140 will randomly generate the same number of verification data as the number of data from the calculation information 110, but generating more verification data than this does not have any practical meaning and is regarded as the same number. and be covered by the scope of rights of this application. It should be noted that verification can be performed for various data by random verification.
  • FIG. 8 is a diagram showing an example of the verification data set 150 after conversion to fixed point. It indicates that the data is converted to the assumed bit width of 15 bits for the integer part and 16 bits for the decimal part, which are described in the generation specification 130 .
  • FIG. 9 is a flow chart showing the operation of the calculation unit 160.
  • the calculation unit 160 reads the calculation information 110 in step S141.
  • the verification data set 150 is read in step S142.
  • the required floating-point calculator is generated from the calculation contents described in the calculation information 110.
  • step S144 similarly, the required fixed-point calculator is generated from the calculation contents described in the calculation information 110.
  • step S145 the verification data set 150 is read.
  • the computing unit 160 computes all verification data sets 150 in a loop from steps S146 to S149. Here, since the number of verification data sets 150 is 4239, S146 to S149 are repeated 4239 times.
  • the computation unit 160 performs computation on the floating-point verification data set 150 randomly generated in step S147 using a floating-point computing unit. Subsequently, in step S148, data obtained by converting the randomly generated floating-point verification data set 150 into the fixed-point verification data set 150 is operated by the fixed-point calculator.
  • step S150 the calculation unit 160 defines the value of the variable out calculated in steps S146 to S149 as the calculation result 170 and outputs it.
  • FIG. 10 shows an example of the calculation result 170. As shown in FIG.
  • FIG. 11 shows a flowchart illustrating the flow of operation of the verification unit 180 .
  • the verification unit 180 reads the generation specification 130 in step S161. Subsequently, in step S162, the calculation result 170 is read.
  • the verification unit 180 determines whether or not all calculation results 170 defined by the calculation unit 160 from steps S163 to S167 satisfy the generation specification 130 .
  • step S164 the verification unit 180 compares the results of the floating-point and fixed-point calculations, and determines whether the calculation error is within the guaranteed number of output digits.
  • the value of the variable out is 10.5528 in the result of the floating-point calculation, whereas it is 10.5546 in the result of the fixed-point calculation.
  • the output accuracy of the generation specification 130 is 10 ⁇ 2 , that is, the values match up to the second decimal place, so the process proceeds to step S165, and it is determined that the results of the floating-point and fixed-point operations are within the error range. judge.
  • the process advances to step S166 to determine that the results of the floating-point and fixed-point calculations are outside the error range.
  • step S168 the verification unit 180 counts the number of data for which the calculation result 170 of the floating-point calculation and the fixed-point calculation is within the error range as a result of the determination from steps S163 to S167, and determines the target value described in the generation specification 130. is reached.
  • the process advances to step S169 to determine that the bit width of the fixed-point calculation is within the assumed bit width.
  • step S170 determines that the data does not fall within the assumed bit width.
  • the verification unit 180 outputs a verification result 190 as to whether or not the bit width of the fixed-point arithmetic is within the assumed bit width. As described above, the verification unit 180 verifies whether the fixed-point calculation satisfies the specifications based on the calculation result 170 and the generation specifications 130 . The verification unit 180 determines that the specification is satisfied when the verification result 190 achieves the target value, and determines that the specification is not satisfied when the verification result 190 does not achieve the target value. ing.
  • the fixed-point arithmetic bit width verification system 100 operates as described above. According to the fixed-point arithmetic bit width verification system according to the present embodiment, it is possible to efficiently verify the bit width of fixed-point arithmetic even in fixed-point arithmetic with a huge scale of arithmetic operations.
  • the specification definition part defines the generation specification including the target value by determining the number of data in the validation dataset using the interval estimation by Bernoulli trial based on the calculation information, and the validation dataset based on the generation specification.
  • a fixed-point computation unit that generates computation results by fixed-point computation using the verification data set, and verifies whether the fixed-point computation satisfies the specifications based on the computation results and generation specifications. Since the fixed-point operation bit width verification system includes the verification unit, it is possible to efficiently verify or determine the fixed-point operation bit width even in a huge scale of operation.
  • FIG. 12 is a block diagram of a fixed-point arithmetic bit width determination system 200 according to the second embodiment.
  • the fixed-point operation bit width determination system 200 of the second embodiment shown in FIG. The difference is that if the bit width of the operation does not fit within the assumed bit width, the verification specification is updated and the bit width is re-verified to determine the bit width. It is also different in that it returns to the specification definition section 120.
  • FIG. 13 is a diagram showing an example of operation information 110 to the fixed-point operation bit width determination system 200 according to the second embodiment.
  • the operation information 110 includes the operation content, which is the content of the operation to be verified for the fixed-point bit width, the degree of importance indicating the degree of importance of the operation content in the entire target operation, and the variable of the operation content. It includes the data type used in the operation, the number of guaranteed output digits, which is the minimum guaranteed number of digits for the output of the content of the operation, and the verification guarantee accuracy necessary to determine the number of verification data and the target value. In addition to this there is a division of bit-width search modes.
  • the content of the operation indicates that the operation takes the variables a and b as inputs and the variable out as an output. Furthermore, the importance is described for each operation, from which the hypothetical fixed-point bit width is determined. The importance is set on a scale of 1 to 10, with 1 being the highest and 10 being the lowest. In the example of FIG. 13, the natural numbers in parentheses in the calculation content column are the degrees of importance.
  • the data type indicates that the variable a is a float type and the variable out is a float type in the floating-point calculation.
  • the number of guaranteed output digits is determined by calculating the error between the case of floating-point arithmetic and the case of fixed-point arithmetic with an assumed bit width, and the error should be 10 ⁇ 2 . That's what it means.
  • the bit width search mode is a strategy for searching the bit width during reverification.
  • FIG. 14 is a flow chart showing the operation of the specification definition unit 120.
  • the specification definition unit 120 reads the update information 310 describing whether or not the specification determined from the previous verification result 190 requires updating. Note that the initial setting of the update information 310 is that update is required.
  • step S202 it is determined from the read update information 310 whether it is necessary to verify the bit width again. If reverification of the bit width is required, the process proceeds to step S203, and if reverification is not required, the process proceeds to step S208 and the verification ends.
  • the initial setting of the update information 310 indicates that update is required, so the process proceeds to step S203.
  • the specification definition unit 120 reads the calculation information 110 in step S203.
  • the specification definition unit 120 determines the number of verification data and the target value in step S204. For example, interval estimation by Bernoulli trials can be used to determine the number of data in validation dataset 150 .
  • the number of data and the target value are determined from the verification guarantee accuracy described in the calculation information 110 and the equation (1).
  • the number of data and the target value are updated according to the bit width search mode.
  • the verification guarantee described in the calculation information 110 The precision ⁇ is updated according to equation (2).
  • FIG. 15 is a diagram showing the distribution of probabilities within the assumed bit width.
  • the probability that the bit width fits into the assumed bit width is 95% or more is 99% or more.
  • the number of verification data is 6623 when calculated according to the formula (1).
  • the bit width of the verification data set 150 falls within the assumed bit width with a probability of 97.0% or more, so the target value is 6425.
  • step S205 the fixed-point data width is determined from the importance described in the calculation content of the calculation information 110.
  • FIG. 16 illustrates the correspondence between importance and fixed-point data width (Q format). Fixed-point data width varies according to importance. In the case of the initial verification, the calculation content described in the calculation information 110 indicates that the importance of the output variable a is 3. Therefore, the data width of the variable a is 32 bits in total, including a sign part of 1 bit, an integer part of 15 bits, and a decimal part of 16 bits. At the time of reverification, the fixed-point data width is determined according to the bit width search mode.
  • the specification definition unit 120 determines the assumed bit width based on the degree of importance and the verification result, relaxes the allowable conditions from the specification according to the verification result 190, and determines the number of data and the target value. . Therefore, the target rate can be lowered while the number of verification data is increased, and the specification can be satisfied by re-verification.
  • bit width search mode is B (second bit width search mode)
  • the fixed-point data width is not changed during reverification, and the boundary between the integer part and the decimal part is changed before reverification.
  • the total of 32 bits (1-bit sign part, 15-bit integer part, and 16-bit decimal part) is used at the time of initial verification
  • the total of 32 bits (1-bit sign part, 10-bit integer part, and 21-bit decimal part) may be used at the time of re-verification. This makes it possible to satisfy the specification by re-verification after increasing the ratio of the number of bits in the decimal part even when higher precision of decimal point arithmetic is required.
  • the bit width search mode is C (third bit width search mode)
  • the fixed point bit width is changed without changing the number of data and the target value.
  • the code part may be 1 bit, the integer part 23 bits, and the decimal part 24 bits for 48 bits.
  • step S206 the specification definition unit 120 determines the allowable error range between the floating-point arithmetic and the fixed-point arithmetic from the guaranteed number of output digits of the arithmetic information 110.
  • FIG. When the number of guaranteed output digits is 10 ⁇ 2 , the acceptance criterion for verification is that the results of the floating-point calculation and the fixed-point calculation match up to the second decimal place.
  • the specification definition unit 120 defines the generation specification 130 in subsequent step S207.
  • FIG. 17 is a diagram illustrating an example of the generation specification 130 defined by the specification definition section 120. As shown in FIG. The number of data, the target value, the variable, the fixed-point data width consisting of the bits of the integer part and the bits of the decimal part, and the output precision described in the generation specification 130 are values determined in steps S204 to S207. .
  • FIG. 7 shows a flowchart illustrating the flow of operation of the generator 140 .
  • FIG. 9 shows a flowchart illustrating the operation flow of the calculation unit 160 .
  • a difference from the first embodiment is step S144.
  • Embodiment 1 there was only one fixed-point bit width.
  • the second embodiment different fixed-point bit widths are defined for each operation. Therefore, a fixed-point arithmetic unit is generated for each defined fixed-point bit width also in step S144.
  • FIG. 11 shows a flow chart illustrating the flow of operation of the verification unit 180 .
  • Update unit 300 Although the flow of operation of the updating unit 300 is not shown, based on the verification result 190 output by the verifying unit 180, the updating information 310 including information indicating whether or not reverification is necessary is output.
  • the generation specification including the fixed-point bit width and the target value is defined from the number of data and the importance of the verification data set using the interval estimation by Bernoulli trial.
  • a specification definition unit that generates a verification data set based on the generation specification; a fixed-point calculation unit that generates a calculation result by fixed-point calculation using the verification data set; and a calculation result and a generation specification based on the Since it is a fixed-point operation bit width determination system equipped with a verification unit that verifies whether fixed-point operations satisfy specifications and generates verification results, and an update unit that determines whether to update the generation specifications according to the verification results, It is possible to efficiently determine the bit width of fixed-point arithmetic even on a huge scale of arithmetic.
  • 100 verification system 110 calculation information, 111 Q format, 120 specification definition part, 130 generation specification, 140 generation part, 150 verification data set, 160 calculation part, 170 calculation result, 180 verification part, 190 verification result, 200 determination system, 300 update unit, 310 update information.

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Abstract

Ce système de vérification (100) d'une largeur de bit arithmétique à virgule fixe comprend : une unité de définition de spécification (120) qui détermine le nombre d'éléments de données dans un ensemble de données de vérification en utilisant une estimation d'intervalle par des parties de pile ou face sur la base d'informations arithmétiques (110) et définit une spécification de génération (130) ; une unité de génération (140) qui génère un ensemble de données de vérification ; une unité arithmétique à virgule fixe (160) qui génère un résultat arithmétique par arithmétique à virgule fixe ; et une unité de vérification (180) qui vérifie si l'arithmétique à virgule fixe satisfait ou non la spécification, la largeur de bit arithmétique à virgule fixe pouvant être vérifiée ou déterminée de manière efficace même dans une grande échelle arithmétique.
PCT/JP2021/014649 2021-04-06 2021-04-06 Système de vérification et système de détermination d'une largeur de bit arithmétique à virgule fixe WO2022215173A1 (fr)

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Citations (2)

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JP2018500635A (ja) * 2014-11-03 2018-01-11 エイアールエム リミテッド プログラム可能な有効度データを使用するデータ処理装置および方法

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JP2009099084A (ja) * 2007-10-19 2009-05-07 Kyocera Corp 変換装置
JP6540770B2 (ja) * 2017-10-17 2019-07-10 富士通株式会社 演算処理回路、演算処理回路を含む演算処理装置、演算処理装置を含む情報処理装置、および方法
JP2020098469A (ja) * 2018-12-18 2020-06-25 富士通株式会社 演算処理装置および演算処理装置の制御方法
JP7188237B2 (ja) * 2019-03-29 2022-12-13 富士通株式会社 情報処理装置、情報処理方法、情報処理プログラム

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JP2008033729A (ja) * 2006-07-31 2008-02-14 Fujitsu Ltd 演算プログラム変換装置、演算プログラム変換プログラム、演算プログラム変換方法
JP2018500635A (ja) * 2014-11-03 2018-01-11 エイアールエム リミテッド プログラム可能な有効度データを使用するデータ処理装置および方法

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