WO2022210592A1 - 半導体回路及び電子機器 - Google Patents

半導体回路及び電子機器 Download PDF

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WO2022210592A1
WO2022210592A1 PCT/JP2022/015161 JP2022015161W WO2022210592A1 WO 2022210592 A1 WO2022210592 A1 WO 2022210592A1 JP 2022015161 W JP2022015161 W JP 2022015161W WO 2022210592 A1 WO2022210592 A1 WO 2022210592A1
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signal
phase
selection
phase signal
circuit
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PCT/JP2022/015161
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English (en)
French (fr)
Japanese (ja)
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貴範 佐伯
義則 田中
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022210592A1 publication Critical patent/WO2022210592A1/ja

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Definitions

  • the present disclosure relates to semiconductor circuits and electronic devices.
  • This type of clock generation circuit is required to have higher time resolution, resistance to PVT (process, voltage, temperature) fluctuations, small area, and power saving.
  • PVT process, voltage, temperature
  • an object of the present disclosure is to provide a semiconductor circuit and an electronic device that are highly resistant to PVT fluctuations and capable of outputting a signal with high time resolution.
  • a first phase signal and a second phase signal having different phases are selected from polyphase signals having different phases based on a first selection signal.
  • a selector that outputs and outputs a third phase signal and a fourth phase signal that are out of phase with each other based on the second selection signal;
  • a first interpolator that outputs a fifth phase signal having a phase corresponding to the phase of the first phase signal and the phase of the second phase signal; and
  • a second interpolator outputting a sixth phase signal having a phase corresponding to the phase of the third phase signal and the phase of the fourth phase signal.
  • the first interpolator and the second interpolator may have the same circuit configuration.
  • a phase difference detection circuit may be provided for detecting a phase difference between the fifth phase signal and the sixth phase signal, using the fifth phase signal as a reference phase signal.
  • the first phase signal and the second phase signal have a phase shift of a minimum phase amount;
  • the third phase signal and the fourth phase signal may have a phase shift of a minimum phase amount.
  • a multiphase clock generation circuit that generates the multiphase signal by shifting the phase of a frequency-divided clock signal obtained by dividing an input clock signal;
  • the selector comprises the first phase signal and the second phase signal, which are out of phase with each other by one cycle or half a cycle of the input clock signal, and the first phase signal and the second phase signal out of phase with each other by one cycle or half a cycle of the input clock signal.
  • the third phase signal and the fourth phase signal that are shifted from each other may be output.
  • each of the first interpolator and the second interpolator a third interpolator that outputs a seventh phase signal having a phase corresponding to the phases of the two phase signals having different phases; a fourth interpolator that outputs an eighth phase signal having a phase corresponding to the phases of the two opposite phase signals obtained by inverting the logic of the two phase signals;
  • a set-reset circuit that outputs a ninth phase signal that becomes the first logic when the seventh phase signal is of a predetermined logic and a second logic when the eighth phase signal is the predetermined logic.
  • the two phase signals are the first phase signal and the second phase signal in the first interpolator, and the third phase signal and the fourth phase signal in the second interpolator. is the phase signal
  • the ninth phase signal may be the fifth phase signal in the first interpolator and the sixth phase signal in the second interpolator.
  • the first interpolator outputs the fifth phase signal having a phase according to the third selection signal
  • the second interpolator may output the sixth phase signal having a phase according to the fourth selection signal.
  • the first interpolator may output the fifth phase signal having the earliest phase among the phases selectable by the third selection signal.
  • each of the first interpolator and the second interpolator a third interpolator for generating a seventh phase signal having a phase corresponding to the third selection signal from two phase signals having different phases; a fourth interpolator that generates an eighth phase signal having a phase corresponding to the fourth selection signal from two opposite phase signals obtained by inverting logics of the two phase signals; a set-reset circuit that outputs a ninth phase signal whose logic is inverted when the seventh phase signal is of a predetermined logic and whose logic is inverted when the eighth phase signal is of the predetermined logic; has The two phase signals are the first phase signal and the second phase signal in the first interpolator, and the third phase signal and the fourth phase signal in the second interpolator. is the phase signal, The ninth phase signal may be the fifth phase signal in the first interpolator and the sixth phase signal in the second interpolator.
  • a first two-selection circuit that selects one of the fifth phase signal and the sixth phase signal based on a fifth selection signal
  • a second two-selection circuit that selects the other of the fifth phase signal and the sixth phase signal that the first two-selection circuit did not select, based on the fifth selection signal.
  • the first interpolator is a fifth interpolator for generating a tenth phase signal having a phase corresponding to a sixth selection signal from the first phase signal and the second phase signal; a sixth interpolator that generates an eleventh phase signal having a phase corresponding to a seventh selection signal from the first phase signal and the second phase signal; a seventh interpolator that generates the fifth phase signal having a phase corresponding to an eighth selection signal from the tenth phase signal and the eleventh phase signal;
  • the second interpolator is an eighth interpolator that generates a twelfth phase signal having a phase corresponding to a ninth selection signal from the third phase signal and the fourth phase signal; a ninth interpolator for generating a thirteenth phase signal having a phase corresponding to a tenth selection signal from the third phase signal and the fourth phase signal; and a tenth interpolator that generates the sixth phase signal having a phase corresponding to the eleventh selection signal from the twelfth phase signal and the thirteenth phase signal.
  • the sixth selection signal consisting of the first bit string signal
  • the seventh selection signal consisting of the second bit string signal
  • the ninth selection signal consisting of the third bit string signal
  • the fourth bit string signal A first control circuit that outputs the tenth selection signal consisting of The first control circuit alternately changes part of bit values in the first bit string signal and the second bit string signal, thereby changing the tenth phase signal and the eleventh phase signal.
  • the twelfth phase signal and the thirteenth phase signal are obtained by shifting the phase by the minimum phase and alternately changing part of the bit values in the third bit string signal and the fourth bit string signal. may be shifted by the minimum phase.
  • the first control circuit alternately changes some bit values in the first bit string signal and the second bit string signal from the lower bit side to the upper bit side, and then By alternately changing toward the lower bit side, the phases of the tenth phase signal and the eleventh phase signal are shifted by the minimum phase, and the phases of the third bit string signal and the fourth bit string signal are shifted by the minimum phase.
  • the twelfth phase signal and the first The phases of the 13 phase signals may be shifted by a minimum phase.
  • the eighth selection signal is a fourth bit string signal
  • the eleventh selection signal is a fifth bit string signal
  • the first control circuit shifts the phase of the fifth phase signal by the minimum phase by sequentially changing the bit values of a part of the fourth bit string signal, and shifts the phase of the fifth bit string signal by the minimum phase.
  • the phase of the sixth phase signal may be shifted by the minimum phase by sequentially changing the bit values of some of them.
  • the first selection signal includes a twelfth selection signal and a thirteenth selection signal
  • the second selection signal includes a fourteenth selection signal and a fifteenth selection signal
  • the selector is a first selection circuit that selects one signal from the polyphase signals based on the twelfth selection signal; a second selection circuit that selects one signal from the polyphase signals based on the thirteenth selection signal; a third selection circuit that selects one signal from the polyphase signals based on the fourteenth selection signal; a fourth selection circuit that selects one signal from the polyphase signals based on the fifteenth selection signal; a first synchronization circuit for generating the first phase signal by synchronizing the signal selected by the first selection circuit with an input clock signal; a second synchronization circuit for generating the second phase signal by synchronizing the signal selected by the second selection circuit with the input clock signal; a third synchronization circuit for generating the third phase signal by synchronizing the signal selected by the third selection circuit with the input clock signal; and a fourth synchronization circuit for generating the
  • the first selection signal includes a twelfth selection signal and a thirteenth selection signal
  • the second selection signal includes a fourteenth selection signal and a fifteenth selection signal
  • the selector is a first selection circuit that selects one signal from the polyphase signals based on the twelfth selection signal; a second selection circuit that selects one signal from the polyphase signals based on the thirteenth selection signal; a third selection circuit that selects one signal from the polyphase signals based on the fourteenth selection signal; a fourth selection circuit that selects one signal from the polyphase signals based on the fifteenth selection signal; a first synchronization circuit for generating a fourteenth phase signal by synchronizing the signal selected by the first selection circuit at the timing when the input clock signal transitions from the first logic to the second logic; a second synchronization circuit for generating a fifteenth phase signal by synchronizing the fourteenth phase signal with timing at which the input clock signal transitions from the second logic to the first logic; a third synchronizing circuit for generating a sixteenth phase signal by
  • a second control circuit that outputs the fifteenth selection signal consisting of The second control circuit alternately changes part of the bit values in the sixth bit string signal and the seventh bit string signal so that the first selection circuit and the second selection circuit
  • the third selection circuit alternately changes the phase of the signal to be selected by the minimum phase and alternately changes part of the bit values in the eighth bit string signal and the ninth bit string signal.
  • the phase of the signal selected by the fourth selection circuit may be alternately changed by the minimum phase.
  • the sixteenth selection signal is a tenth bit string signal
  • the seventeenth selection signal is an eleventh bit string signal
  • the second control circuit alternately changes partial bit values in the tenth bit string signal and the eleventh bit string signal to generate the first phase signal, the second phase signal,
  • the phases of the third phase signal and the fourth phase signal may be shifted by a minimum phase.
  • a standard cell in which circuits constituting the selector, the first interpolator, and the second interpolator are arranged may be provided.
  • phase difference control circuit An electronic device comprising a phase difference detection circuit,
  • the phase difference control circuit is Outputting a first phase signal and a second phase signal whose phases are different from each other based on a first selection signal from among the polyphase signals whose phases are different from each other, and outputting a phase signal whose phases are different from each other based on the second selection signal a selector that outputs different third phase signals and fourth phase signals; a first interpolator that outputs a fifth phase signal having a phase corresponding to the phase of the first phase signal and the phase of the second phase signal; a second interpolator that outputs a sixth phase signal having a phase corresponding to the phase of the third phase signal and the phase of the fourth phase signal;
  • the phase difference detection circuit may detect a phase difference between the fifth phase signal and the sixth phase signal, using the fifth phase signal as a reference phase signal.
  • FIG. 1 is a block diagram of a semiconductor circuit according to a first embodiment
  • FIG. 2 is a schematic block diagram of an electronic device including the semiconductor circuit 1 of FIG. 1
  • FIG. FIG. 4 is a diagram showing a specific example of a first interpolator and a second interpolator
  • FIG. 3B is a circuit diagram showing an example of the internal configuration of the clocked inverter in FIG. 3A
  • FIG. 2 is a block diagram showing a schematic configuration of a semiconductor circuit according to a second embodiment
  • FIG. FIG. 5 is a circuit diagram showing an example of the internal configuration of a multiphase clock generation circuit in the multiphase clock generation & selector of FIG. 4
  • FIG. 5 is a circuit diagram showing an example of the internal configuration of a selector within the multiphase clock generation & selector 5 of FIG. 4;
  • FIG. 5 is a block diagram showing internal configurations of a first interpolator and a second interpolator in FIG. 4;
  • FIG. 8 is a circuit diagram showing an example of the internal configuration of the low leak PI of FIG. 7;
  • FIG. 9 is a circuit diagram showing an internal configuration of a low-leakage PI according to a modified example of FIG. 8;
  • FIG. 10 is a timing diagram for the low-leakage PI of FIG. 9;
  • FIG. 11 is a block diagram showing a schematic configuration of a semiconductor circuit according to a third embodiment;
  • FIG. 12 is a circuit diagram showing an internal configuration of a multiphase clock generation circuit in the multiphase clock generation & selector of FIG. 11;
  • FIG. 12 is a circuit diagram showing the internal configuration of a selector in the multiphase clock generation & selector of FIG. 11;
  • FIG. 14 is a block diagram showing the internal configuration of the 11th to 18th interpolators in FIG. 13;
  • FIG. 15 is a circuit diagram showing the internal configuration of the low-leakage DIV2PI of FIG. 14;
  • FIG. 16 is a circuit diagram according to a first modification of the low-leakage DIV2PI of FIG. 15;
  • FIG. 16 is a circuit diagram according to a second modification of the low-leakage DIV2PI of FIG. 15;
  • FIG. 18 is a timing diagram of the low-leakage DIV2PI of FIG. 17;
  • 14A and 14B are diagrams for explaining operations of a first selection circuit and a second selection circuit in the selector 2 of FIG. 13;
  • FIG. FIG. 14 is a diagram for explaining the operation of a third two-selection circuit and a fourth two-selection circuit in the selector of FIG. 13;
  • 12A and 12B are diagrams for explaining the operation of a fifth interpolator and a sixth interpolator in the semiconductor circuit 1 of FIG. 11;
  • FIG. FIG. 12 is a diagram for explaining operations of a seventh interpolator and a tenth interpolator in the semiconductor circuit 1 of FIG. 11;
  • FIG. 11 is a block diagram showing an internal configuration of a modified example of the multiphase clock generation & selector of FIG. 11;
  • FIG. 11 is a block diagram showing a schematic configuration of a semiconductor circuit according to a fourth embodiment;
  • FIG. 25 is a block diagram of a semiconductor circuit 1 including a first fine-tuning interpolator and a second fine-tuning interpolator in addition to the configuration of FIG. 24;
  • FIG. FIG. 11 is a block diagram showing a schematic configuration of an electronic device including a semiconductor circuit according to a fifth embodiment;
  • semiconductor circuits and electronic devices will be described with reference to the drawings.
  • the main components of the semiconductor circuits and electronic devices will be mainly described below, the semiconductor circuits and electronic devices may have components and functions that are not illustrated or described. The following description does not exclude components or features not shown or described.
  • FIG. 1 is a block diagram of a semiconductor circuit 1 according to the first embodiment.
  • the semiconductor circuit 1 of FIG. 1 outputs two phase signals Outa and Outb that are out of phase with each other. Since these two phase signals Outa and Outb are generated by the same semiconductor circuit 1, they have the same PVT variation.
  • PVT variation means that the signal characteristics change due to the influence of at least one of process P, power supply voltage V, and temperature T.
  • FIG. By detecting the phase difference between the two phase signals Outa and Outb having the same PVT fluctuations in a subsequent circuit (not shown in FIG. 1), a phase difference signal in which the PVT fluctuations are canceled out can be obtained. In this manner, the semiconductor circuit 1 of FIG. 1 outputs two phase signals having different phases so that the circuit at the subsequent stage can detect the phase difference signal in which the PVT variation is canceled.
  • the semiconductor circuit 1 in FIG. 1 includes a selector 2, a first interpolator (PI_1) 3a, and a second interpolator (PI_2) 3b.
  • the selector 2 outputs a first phase signal Pna1 and a second phase signal Pna2 having different phases from among the polyphase signals having different phases based on the first selection signal nas, and performs second selection.
  • a third phase signal Pnb1 and a fourth phase signal Pnb2 having phases different from each other are output based on the signal nbs.
  • a polyphase signal is a plurality of signals having different phases.
  • FIG. 1 shows an example in which the polyphase signal has N phases (N is an integer equal to or greater than 2).
  • the multiphase signal can be generated, for example, by shifting the phase of the frequency-divided clock signal obtained by dividing the input clock signal CLK in a plurality of ways with the input clock signal CLK.
  • the phase difference between the first phase signal Pna1 and the second phase signal Pna2 is arbitrary. have deviations.
  • the minimum phase amount is the phase difference between two consecutive clock signals generated by the multiphase clock generation circuit. For example, as will be described later (FIG. 5), in a multiphase signal generated by phase-shifting a frequency-divided clock signal obtained by dividing an input clock signal by N in a shift register, a first phase signal Pna1 and a second phase signal Pna1 are generated. It is one cycle or half cycle of the input clock signal CLK used to generate the phase signal Pna2.
  • the phase difference between the third phase signal Pnb1 and the fourth phase signal Pnb2 is arbitrary, but typically the third phase signal Pnb1 and the fourth phase signal Pnb2 have a minimum phase amount of has a phase shift of .
  • the first interpolator 3a outputs a fifth phase signal Outa having a phase corresponding to the phase of the first phase signal Pna1 and the phase of the second phase signal Pna2.
  • the second interpolator 3b outputs a sixth phase signal Outb having a phase corresponding to the phases of the third phase signal Pnb1 and the fourth phase signal Pnb2.
  • the fifth phase signal Outa is an interpolation ratio selectable by the third selection signal mas from the phase difference between the phase of the first phase signal Pna1 and the phase of the second phase signal Pna2. has a predetermined phase selected by .
  • the sixth phase signal Outb has a predetermined phase selected by an interpolation ratio selectable by the fourth selection signal mbs.
  • the first interpolator 3a and the second interpolator 3b have the same circuit configuration.
  • the fifth phase signal Outa output from the first interpolator 3a and the second interpolator The PVT variation of the sixth phase signal Outb output from 3b can be made the same.
  • the first interpolator 3a outputs a fifth phase signal Outa having a phase corresponding to the third selection signal mas.
  • the second interpolator 3b outputs a sixth phase signal Outb having a phase corresponding to the fourth selection signal mbs.
  • each of the first interpolator 3a and the second interpolator 3b can select an arbitrary phase from the M phases. Therefore, if the selector 2 can select an arbitrary phase signal from N-phase polyphase signals, the semiconductor circuit 1 in FIG.
  • Each of the sixth phase signals Outb can be independently selected and output.
  • the first interpolator 3a may output the fifth phase signal Outa of the earliest phase among the phases selectable by the third selection signal mas.
  • the fifth phase signal Outa can be used as the reference phase signal.
  • the second interpolator 3b may be capable of outputting the sixth phase signal Outb of any phase.
  • the semiconductor circuit 1 in FIG. 1 can be arranged on a semiconductor substrate. As will be described later, the semiconductor circuit 1 of FIG. 1 can be arranged in at least part of a standard cell preliminarily formed on a semiconductor substrate. By designing the semiconductor circuit 1 of FIG. 1 using standard cells, the design man-hours can be reduced, and manufacturing is facilitated. Also, the semiconductor circuit 1 of FIG. 1 can be arranged on the same semiconductor substrate together with another semiconductor circuit that realizes other functions, and can be packaged and made into a chip. As a result, the semiconductor circuit 1 of FIG. 1 can be incorporated into an LSI (Large Scale Integrated chip) or SoC (Silicon on Chip).
  • LSI Large Scale Integrated chip
  • SoC Silicon on Chip
  • FIG. 2 is a schematic block diagram of an electronic device 10 including the semiconductor circuit 1 of FIG.
  • the electronic device 10 in FIG. 2 includes a PLL circuit 11, a multiphase clock generation circuit 12, the semiconductor circuit 1 in FIG. 1, a control circuit 13, and a system circuit .
  • the PLL circuit 11 generates and outputs a reference clock signal.
  • the multiphase clock generation circuit 12 generates a multiphase signal by, for example, shifting a frequency-divided clock signal DCK obtained by frequency-dividing the input clock signal CLK in synchronization with the input clock signal CLK.
  • a frequency-divided clock signal DCK obtained by frequency-dividing the input clock signal CLK in synchronization with the input clock signal CLK.
  • it may be synchronized at the timing of the rising edge (or falling edge) of the input clock signal CLK, or at both the rising edge and the falling edge. may be synchronized at the timing of
  • the control circuit 13 generates the above-described first selection signal nas, second selection signal nbs, third selection signal mas, and fourth selection signal mbs, and inputs them to the semiconductor circuit 1 .
  • the first selection signal nas and the second selection signal nbs are input to the selector 2 in the semiconductor circuit 1 and used to generate polyphase signals.
  • the first phase signal Pna1 and the second phase signal Pna2 are used to generate the fifth phase signal Outa
  • the third phase signal Pnb1 and the fourth phase signal Pnb2 are used to generate the sixth phase signal Outb. used to generate
  • the control circuit 13 generates the first selection signal nas to the fourth selection signal mbs based on the bit string signal of the control code input from the outside.
  • Each of the first selection signal nas to the fourth selection signal mbs is a bit string signal composed of multiple bits.
  • the function and internal configuration of the system circuit 14 are irrelevant.
  • the fifth phase signal Outa and the sixth phase signal Outb output from the semiconductor circuit 1 are input to the system circuit 14 .
  • the system circuit 14 can, for example, detect the phase difference between the fifth phase signal Outa and the sixth phase signal Outb to generate a phase difference signal independent of PVT variations.
  • the system circuit 14 can use the fifth phase signal Outa and the sixth phase signal Outb as sensing signals. More specifically, the object is irradiated with an optical signal synchronized with the fifth phase signal Outa, which is the reference phase signal, and the reflected optical signal from the object is sampled in synchronization with the sixth phase signal Outb. good too. As a result, the distance to the object can be accurately measured in a non-contact manner.
  • FIG. 3A is a diagram showing a specific example of the first interpolator 3a and the second interpolator 3b.
  • FIG. 3A shows an example in which each of the first interpolator 3a and the second interpolator 3b is composed of a plurality of clocked inverters.
  • the first interpolator 3a having the configuration shown in FIG. 3A will be described below.
  • the first interpolator 3a shown in FIG. 3A includes a plurality of clocked inverters 4 connected in parallel between a node to which the input phase signal Pn is input and an output node, and an input phase signal Pn+1. and a plurality of clocked inverters 4 connected in parallel between the output node and the output node.
  • Each clocked inverter 4 has an enable terminal, and it is possible to individually set whether or not each clocked inverter 4 is enabled. Specifically, whether or not to enable each clocked inverter 4 is determined based on the value of each bit of the control signal having the number of bits corresponding to the total number of clocked inverters 4 . As the number of enabled clocked inverters 4 increases, the phase of the signal output from the interpolator advances. Therefore, by adjusting the value of each bit of the control signal, the phases of the signals output from the first interpolator 3a and the second interpolator 3b can be finely adjusted. If the number of bits of the control signal is M, the first interpolator 3a in FIG. 3A can output an M-phase phase signal.
  • FIG. 3B is a circuit diagram showing an example of the internal configuration of the clocked inverter 4 of FIG. 3A.
  • the clocked inverter 4 of FIG. 3B has PMOS transistors Q1, Q2 and NMOS transistors Q3, Q4 cascode-connected between the power supply voltage node and the ground node.
  • An input phase signal IN is input to the gates of the transistors Q2 and Q3, and control signals SB and S are input to the gates of the transistors Q1 and Q4.
  • the transistors Q1 and Q2 may be interchanged, and the transistors Q3 and Q4 may be interchanged.
  • the fifth phase signal Outa is generated by the first interpolator 3a based on the first phase signal Pna1 and the second phase signal Pna2 output from the selector 2.
  • the second interpolator 3b Based on the third phase signal Pnb1 and the fourth phase signal Pnb2 output from the selector 2, the second interpolator 3b generates the sixth phase signal Outb.
  • the phases of the fifth phase signal Outa and the sixth phase signal Outb can be finely adjusted.
  • the phase difference signal between the fifth phase signal Outa and the sixth phase signal Outb can be controlled by the PVT fluctuation.
  • a phase difference signal that can be canceled and that does not depend on PVT variations can be easily generated.
  • first interpolator 3a and the second interpolator 3b can be composed of, for example, a plurality of clocked inverters 4 connected in parallel.
  • the phases of the phase signal Outa and the sixth phase signal Outb can be easily and finely adjusted. Therefore, according to the present embodiment, the phases of the fifth phase signal Outa and the sixth phase signal Outb can be finely adjusted with a simple circuit configuration and control.
  • FIG. 4 is a block diagram showing a schematic configuration of the semiconductor circuit 1 according to the second embodiment.
  • the semiconductor circuit 1 of FIG. 4 includes a multiphase clock generator & selector 5, a first interpolator 3a, a second interpolator 3b, a first two-selection circuit 6, and a second two-selection circuit. 7 and a control circuit 13 .
  • the multiphase clock generation & selector 5 has a multiphase clock generation circuit 12 and a selector 2 . A detailed description of these circuits is given later.
  • the selector 2 in FIG. 4 outputs the first phase signal Pna1 and the second phase signal Pna2 based on the first selection signal nas, and outputs Based on this, a third phase signal Pnb1 and a fourth phase signal Pnb2 are output.
  • the first phase signal Pna1 and the second phase signal Pna2 are signals that are out of phase with each other by the minimum phase amount.
  • the first phase signal Pna1 and the second phase signal Pna2 are input to the first interpolator 3a.
  • the third phase signal Pnb1 and the fourth phase signal Pnb2 are signals that are out of phase with each other by the minimum phase amount.
  • the third phase signal Pnb1 and the fourth phase signal Pnb2 are input to the second interpolator 3b.
  • the first interpolator 3a outputs a fifth phase signal nma from the third phase signal Pnb1 and the fourth phase signal Pnb2 based on the third selection signal mas.
  • the second interpolator 3b outputs a sixth phase signal nmb from the third phase signal Pnb1 and the fourth phase signal Pnb2 based on the fourth selection signal mbs.
  • the first two-selection circuit 6 selects Outa, one of the fifth phase signal nma and the sixth phase signal nmb, based on the fifth selection signal ss.
  • the second two-selection circuit 7 selects the other Outb of the fifth phase signal nma and the sixth phase signal nmb, which the first two-selection circuit 6 did not select, based on the fifth selection signal ss. .
  • the first two-selection circuit 6 and the second two-selection circuit 7 can switch between the fifth phase signal nma and the sixth phase signal nmb and output them according to the control signal ss from the control circuit 13 .
  • the time difference between the propagation delay times of the paths through which the fifth phase signal nma and the sixth phase signal nmb propagate can be measured, and the functions of the fifth phase signal nma and the sixth phase signal nmb can be reversed. , and subsequent processing can be executed.
  • FIG. 5 is a circuit diagram showing an example of the internal configuration of the multiphase clock generation circuit 12 in the multiphase clock generation & selector 5 of FIG.
  • the multiphase clock generation circuit 12 has an N-divider circuit 8 and a plurality (N) of cascaded flip-flops (hereinafter referred to as FFs) 9 .
  • the N-divider circuit 8 divides the frequency of the input clock signal CLK by N and outputs the divided clock signal DCK.
  • the divided clock signal DCK is synchronized at each FF 9, eg, at the rising edge of the input clock signal CLK.
  • the cascaded FFs 9 output a multiphase signal including a plurality of frequency-divided clock signals DCK whose phases are shifted by one cycle of the input clock signal CLK. More specifically, among the plurality of cascaded FFs 9, the 0-phase signal is output from the FF 9 at the first stage, and the (N ⁇ 1)-phase signal is output from the FF 9 at the final stage.
  • FIG. 6 is a circuit diagram showing an example of the internal configuration of the selector 2 in the multiphase clock generator & selector 5 of FIG.
  • the selector 2 of FIG. 6 includes a first selection circuit 21, a second selection circuit 22, a third selection circuit 23, a fourth selection circuit 24, a first synchronization circuit 25, a second , a third synchronizing circuit 27 and a fourth synchronizing circuit 28 .
  • the 12th selection signal na, the 13th selection signal na1, the 14th selection signal nb, and the 15th selection signal nb1 generated by the control circuit 13 in FIG. 4 are input to the selector 2 in FIG. .
  • the twelfth selection signal na and the thirteenth selection signal na1 correspond to the first selection signal nas in the selector 2 of FIG.
  • the fourteenth selection signal nb and the fifteenth selection signal nb1 in the selector 2 in FIG. 6 correspond to the second selection signal nbs in the selector 2 in FIG.
  • the first selection circuit 21 selects one signal from the polyphase signals based on the twelfth selection signal na.
  • the second selection circuit 22 selects one signal from the polyphase signals based on the thirteenth selection signal na1.
  • the third selection circuit 23 selects one signal from the polyphase signals based on the fourteenth selection signal nb.
  • the fourth selection circuit 24 selects one signal from the polyphase signals based on the fifteenth selection signal nb1.
  • the first synchronization circuit 25 generates the first phase signal Pna1 by synchronizing the signal selected by the third selection circuit 23 with the input clock signal CLK.
  • the second synchronization circuit 26 generates a second phase signal Pna2 by synchronizing the signal selected by the fourth selection circuit 24 with the input clock signal CLK.
  • the third synchronization circuit 27 synchronizes the signal selected by the fifth selection circuit with the input clock signal CLK to generate the third phase signal Pnb1.
  • the fourth synchronization circuit 28 synchronizes the signal selected by the sixth selection circuit with the input clock signal CLK to generate a fourth phase signal Pnb2.
  • Each of the first synchronizing circuit 25 to the fourth synchronizing circuit 28 is composed of FF9, for example.
  • the phase difference of the signals selected by the first selection circuit 21 to the fourth selection circuit 24 is synchronized with the input clock signal CLK. It is possible to adjust the phase variations of the signals selected by the first selection circuit 21 to the fourth selection circuit 24 .
  • FIG. 7 is a block diagram showing the internal configuration of the first interpolator 3a and the second interpolator 3b in FIG.
  • the internal configurations of the first interpolator 3a and the second interpolator 3b are the same.
  • the first interpolator 3 a and the second interpolator 3 b are also called phase interpolators 3 .
  • the phase interpolator 3 selects a phase corresponding to each phase of the two input phase signals IN1 and IN2 based on the selection signal mas or mbs, and outputs a phase signal of the selected phase.
  • the phase interpolator 3 of FIG. 7 has two low-leakage phase interpolators (hereinafter also referred to as low-leakage PIs) 31, 32, two inverters 33, 34, and a set-reset circuit 35.
  • a low leak means a circuit configuration in which a through current does not flow between the power supply voltage node and the ground node.
  • the internal configurations of the two low leak PIs 31 and 32 are the same.
  • one low-leakage PI 31 may be called a third interpolator 31 and the other low-leakage PI 32 may be called a fourth interpolator 32 .
  • the third interpolator 31 generates a seventh phase signal having a phase corresponding to the selection signal mas or mbs from the two phase signals IN1 and IN2 having different phases.
  • a fourth interpolator 32 generates an eighth phase signal having a phase corresponding to the selection signal mas or mbs from two opposite phase signals obtained by inverting the logic of the two phase signals IN1 and IN2 by inverters 33 and 34. Generate.
  • the set-reset circuit 35 outputs a ninth phase signal OUT that becomes the first logic when the seventh phase signal has a predetermined logic, and becomes the second logic when the eighth phase signal has a predetermined logic. Output.
  • the set-reset circuit 35 has, for example, two inverters 36, 37, two NAND gates 38, 39, and a buffer 40.
  • the seventh phase signal is input to one NAND gate 38 after being logically inverted by one inverter 36 .
  • the eighth phase signal is input to the other NAND gate 39 after being logically inverted by the other inverter 37 .
  • One NAND gate 38 outputs a NAND signal of the output of the other NAND gate 39 and the logic inversion signal of the seventh phase signal.
  • the other NAND gate 39 outputs a NAND signal of the output of the NAND gate 38 and the logic inversion signal of the eighth phase signal.
  • the output signal of one NAND gate 38 is output via buffer 40 .
  • the set reset circuit 35 When the output signal of the fourth interpolator 32 in FIG. 7 becomes high level, the set reset circuit 35 enters the set state, and the phase interpolator 3 in FIG. 7 outputs a high level signal. Also, when the output signal of the third interpolator 31 becomes high level, the set reset circuit 35 enters a reset state, and the phase interpolator 3 of FIG. 7 outputs a low level signal.
  • the low leak PIs 31 and 32 in FIG. Variation in the duty ratio of the output ninth phase signal can be improved.
  • FIG. 8 is a circuit diagram showing an example of the internal configuration of the low leak PIs 31 and 32 (third interpolator 31 and fourth interpolator 32) of FIG.
  • Two phase signals IN1 and IN2 are input to the low-leakage PIs 31 and 32 in FIG.
  • the two phase signals IN1, IN2 are the first phase signal Pna1 and the second phase signal Pna2 of FIG. 4 or the third phase signal Pnb1 and the fourth phase signal Pnb2 of FIG.
  • the low-leakage PIs 31, 32 of FIG. 8 are composed of an OR gate 41, two buffers 42, 43, a PMOS transistor Q5, an inverter 44, and N pairs of cascode-connected PIs 31, 32 connected between the input node of the inverter 44 and the ground node. It has a first transistor group 45 and N sets of second transistor groups 46 cascode-connected between the input node of the inverter 44 and the ground node. Each transistor group 45, 46 has two NMOS transistors (Q6, Q7) or (Q8, Q9) cascode-connected between the input node of the inverter 44 and the ground node.
  • the phase signal IN1 is input through the buffer 42 to the gate of one NMOS transistor Q6 in the first transistor group 45.
  • the gate of the other NMOS transistor Q7 in the first transistor group 45 receives the inverted signals SB0 to SBN-1 of the corresponding bit in the third selection signal mas or the fourth selection signal mbs in FIG. be.
  • a phase signal IN2 is input via a buffer 43 to the gate of one NMOS transistor Q8 in the second transistor group 46.
  • the corresponding bit signals S0 to SN-1 in the third selection signal mas or the fourth selection signal mbs in FIG. 7 are input to the gate of the other NMOS transistor Q9 in the second transistor group .
  • the low-leakage PIs 31 and 32 in FIG. 8 use the third select signal mas or the third select signal mas or the third 4, the phase of the phase signals output from the low-leakage PIs 31 and 32 can be adjusted.
  • the phase of the phase signals output from the low-leakage PIs 31 and 32 also changes due to the phase difference between the two phase signals IN1 and IN2 that are input to the low-leakage PIs 31 and 32 .
  • the smaller the phase difference between the phase signals IN1 and IN2 the shorter the time interval between the phase signals output from the low-leakage PIs 31 and 32 in proportion to the phase difference.
  • FIG. 9 is a circuit diagram showing the internal configuration of low-leakage PIs 31 and 32 according to a modified example of FIG.
  • the low-leakage PIs 31, 32 of FIG. 9 have two AND gates 47, 48 in addition to the configuration of FIG.
  • the output signal of the OR gate 41 is a
  • the output signal of the AND gate 47 is b
  • the output signal of the AND gate 48 is c.
  • One AND gate 47 outputs a logical product signal of the phase signal IN1 and a phase signal obtained by delaying the phase signal IN1 by the buffer 42 .
  • the output signal b of one AND gate 47 is input to the gate of one NMOS transistor Q6 in the first transistor group 45.
  • FIG. 9 is a circuit diagram showing the internal configuration of low-leakage PIs 31 and 32 according to a modified example of FIG.
  • the low-leakage PIs 31, 32 of FIG. 9 have two AND gates 47, 48 in addition to the configuration of FIG.
  • the output signal of the OR gate 41
  • the other AND gate 48 outputs a logical AND signal of the phase signal IN2 and a phase signal obtained by delaying the phase signal IN2 by the buffer 43 .
  • the output signal c of the other AND gate 48 is input to the gate of one NMOS transistor Q8 in the second transistor group 46.
  • FIG. 10 is a timing diagram of low leak PIs 31 and 32 in FIG. FIG. 10 shows signal waveforms of the two phase signals IN1 and IN2, the output signal a of the OR gate 41, the output signal b of the AND gate 47, and the output signal c of the AND gate 48. ing.
  • Phase signals IN1 and IN2 delayed by buffers 42 and 43 are input to AND gates 47 and 48. Therefore, the timing at which outputs b and c of AND gates 47 and 48 transition from low level to high level is determined by the OR gate. 41 is delayed by td from the timing at which the output a of 41 transitions to high level. Therefore, the cascode-connected PMOS transistor Q5 does not turn on at the same time as the NMOS transistors (Q6, Q7) or (Q8, Q9), and no through current flows from the power supply voltage node to the ground node.
  • the current extracted by the NMOS transistors (Q6, Q7) or (Q8, Q9) within the period of time difference T from when the phase signal IN1 transitions to high level until when the phase signal IN2 transitions to high level is It can be controlled with high accuracy, and thereby the phase of the phase signals output from the low-leakage PIs 31 and 32 in FIG. 9 can be controlled with high accuracy.
  • FIGS. 8 and 9 are only examples of the circuit configuration of the low-leakage PIs 31 and 32, and any specific circuit configuration may be used as long as the timings shown in FIG. 10 can be realized.
  • the PMOS transistor Q5 charges the potential of the input node of the inverter 44
  • the NMOS transistors (Q6, Q7) or (Q8, Q9) transfer the current from the input node of the inverter 44 to the ground node.
  • the circuit configuration may be such that the roles of the NMOS transistors (Q6, Q7) or (Q8, Q9) and the PMOS transistor Q5 are reversed.
  • the fifth phase signal nma and the sixth phase signal nmb output from the first interpolator 3a and the second interpolator 3b can be alternately switched and output.
  • the time difference between the signal propagation time of the fifth phase signal nma and the signal propagation time of the sixth phase signal nmb can be measured.
  • the low-leakage PIs 31 and 32 of FIG. 8 or 9 as the first interpolator 3a and the second interpolator 3b, it is possible to prevent the through current from flowing, and the configuration is simple. A phase signal whose phase is finely and accurately shifted can be generated.
  • the third embodiment is characterized by generating a phase signal whose phase is shifted in finer units than the second embodiment.
  • FIG. 11 is a block diagram showing a schematic configuration of the semiconductor circuit 1 according to the third embodiment.
  • the semiconductor circuit 1 of FIG. 11 includes a multiphase clock generator & selector 5, a fifth interpolator (PI_ea) 51, a sixth interpolator (PI_oa) 52, and a seventh interpolator (PI_2a). 53, an eighth interpolator (PI_eb) 54, a ninth interpolator (PI_ob) 55, a tenth interpolator (PI_2b) 56, a first two-selection circuit 6, a second and a control circuit 13 .
  • the multiphase clock generation & selector 5 has a multiphase clock generation circuit 12 and a selector 2 . A detailed description of these circuits is given later.
  • the multiphase clock generator & selector 5 generates a first phase signal Pnea corresponding to the first phase signal Pna1 in FIG. 1, a second phase signal Pnoa corresponding to the second phase signal Pna2, and a third phase signal Pna2. It outputs a third phase signal Pneb corresponding to the signal Pnb1 and a third phase signal Pnob corresponding to the fourth phase signal Pnb2.
  • a fifth interpolator 51, a sixth interpolator 52, and a seventh interpolator 53 correspond to the first interpolator 3a in FIG. 1 or FIG.
  • the fifth interpolator 51 generates a tenth phase signal nmea having a phase corresponding to the sixth selection signal meas from the first phase signal Pnea and the second phase signal Pnoa.
  • the sixth interpolator 52 generates an eleventh phase signal nmoa having a phase corresponding to the seventh selection signal moas from the first phase signal Pnea and the second phase signal Pnoa.
  • the seventh interpolator 53 generates a fifth phase signal nmka having a phase corresponding to the eighth selection signal kas from the tenth phase signal nmea and the eleventh phase signal nmoa.
  • the eighth interpolator 54, the ninth interpolator 55, and the tenth interpolator 56 correspond to the second interpolator 3b in FIG. 1 or FIG.
  • the eighth interpolator 54 generates a twelfth phase signal nmeb having a phase corresponding to the ninth selection signal mebs from the third phase signal Pneb and the fourth phase signal Pnob.
  • the ninth interpolator 55 generates a thirteenth phase signal nmob having a phase corresponding to the tenth selection signal mobs from the third phase signal Pneb and the fourth phase signal Pnob.
  • a tenth interpolator 56 generates a sixth phase signal nmkb having a phase corresponding to the eleventh selection signal kbs from the twelfth phase signal nmeb and the thirteenth phase signal nmob.
  • the first two-selection circuit 6 and the second two-selection circuit 7 in FIG. 11 can exchange the fifth phase signal nmka and the sixth phase signal nmkb and output them, as in FIG.
  • the control circuit 13 generates an n-phase selection signal and an h-phase selection signal for controlling the selector 2 based on an externally input control code, and also generates a sixth selection signal meas and a seventh selection signal. It generates moas, an eighth selection signal kas, a ninth selection signal mebs, a tenth selection signal mobs, and an eleventh selection signal kbs.
  • the semiconductor circuit 1 of FIG. 11 has a plurality of interpolators connected in multiple stages, and the finally output fifth phase signal nmka and sixth phase signal nmkb are phase-shifted in fine units. can be changed.
  • FIG. 12 is a circuit diagram showing the internal configuration of the multiphase clock generation circuit 12 in the multiphase clock generation & selector 5 of FIG.
  • the multiphase clock generation circuit 12 of FIG. 12 has an inverter 16 in addition to the N-divider circuit 8 and a plurality of cascade-connected FFs 9, as in FIG.
  • This inverter 16 inverts the logic of the input clock signal CLK.
  • the input clock signal CLK and the inverted clock signal inverted by the inverter 16 are alternately input to the cascaded FFs 9 .
  • the plurality of FFs 9 output multiphase signals whose phases are shifted every half cycle of the input clock signal CLK. Therefore, the multiphase clock generation circuit 12 in FIG. 12 can generate a multiphase signal whose phase is shifted by a finer phase amount than the multiphase clock generation circuit 12 in FIG.
  • equivalent polyphase signals can be output even if FF9 is replaced with a latch circuit.
  • FIG. 13 is a circuit diagram showing the internal configuration of the selector 2 within the multiphase clock generator & selector 5 of FIG.
  • the selector 2 of FIG. 13 includes a first selection circuit 21, a second selection circuit 22, a third selection circuit 23, a fourth selection circuit 24, a first synchronization circuit 61, a second synchronization circuit 62, third synchronization circuit 63, fourth synchronization circuit 64, fifth synchronization circuit 65, sixth synchronization circuit 66, and seventh synchronization circuit 67 , an eighth synchronization circuit 68, an eleventh interpolator 69, a twelfth interpolator 70, a thirteenth interpolator 71, a fourteenth interpolator 72, and a third a two-selection circuit 73, a fourth two-selection circuit 74, a fifth two-selection circuit 75, a sixth two-selection circuit 76, a fifteenth interpolator 77, and a sixteenth interpolator 78; , a seventeenth interpol
  • the twelfth selection signal neas and the thirteenth selection signal noas input to the selector 2 in FIG. 13 correspond to the first selection signal nas in the selector 2 in FIG. 1 or FIG. Also, the fourteenth selection signal nebs and the fifteenth selection signal nobs input to the selector 2 in FIG. 13 correspond to the second selection signal nbs in the selector 2 in FIG. 1 or FIG.
  • the first selection circuit 21 selects one signal from the polyphase signals based on the twelfth selection signal neas.
  • the second selection circuit 22 selects one signal from the polyphase signals based on the thirteenth selection signal noas.
  • the third selection circuit 23 selects one signal from the polyphase signals based on the fourteenth selection signal nebs.
  • the fourth selection circuit 24 selects one signal from the polyphase signals based on the fifteenth selection signal nobs.
  • the first synchronization circuit 61 generates a 14th phase signal by synchronizing the signal selected by the first selection circuit 21 with the timing at which the input clock signal CLK transitions from the first logic to the second logic. .
  • the second synchronization circuit 62 generates a fifteenth phase signal by synchronizing the fourteenth phase signal with the timing at which the input clock signal CLK transitions from the second logic to the first logic.
  • the third synchronization circuit 63 synchronizes the signal selected by the second selection circuit 22 with the timing at which the input clock signal CLK transitions from the first logic to the second logic to generate a 16th phase signal. .
  • the fourth synchronization circuit 64 synchronizes the 16th phase signal with the timing at which the input clock signal CLK transitions from the second logic to the first logic to generate a 17th phase signal.
  • the fifth synchronization circuit 65 synchronizes the signal selected by the third selection circuit 23 with the timing at which the input clock signal CLK transitions from the first logic to the second logic to generate the eighteenth phase signal.
  • the sixth synchronization circuit 66 generates a nineteenth phase signal by synchronizing the eighteenth phase signal with the timing at which the input clock signal CLK transitions from the second logic to the first logic.
  • the seventh synchronization circuit 67 synchronizes the signal selected by the fourth selection circuit 24 with the timing at which the input clock signal CLK transitions from the first logic to the second logic to generate a twentieth phase signal.
  • the eighth synchronization circuit 68 generates a twenty-first phase signal by synchronizing the twenty-first phase signal with the timing at which the input clock signal CLK transitions from the second logic to the first logic.
  • the eleventh interpolator 69 generates a twenty-second phase signal nea having a phase corresponding to the phases of the fourteenth phase signal and the fifteenth phase signal.
  • the twelfth interpolator 70 generates a twenty-third phase signal noa having a phase corresponding to the phase of the sixteenth phase signal and the phase of the seventeenth phase signal.
  • the thirteenth interpolator 71 generates a twenty-fourth phase signal neb having a phase corresponding to the phases of the eighteenth phase signal and the nineteenth phase signal.
  • the fourteenth interpolator 72 generates a twenty-fifth phase signal nob having a phase corresponding to the phases of the twenty-first phase signal and the twenty-first phase signal.
  • the third two-selection circuit 73 selects either the 22nd phase signal nea or the 23rd phase signal noa based on the 16th selection signal has.
  • the fourth two-selection circuit 74 selects the phase signal selected by the third two-selection circuit 73 from the twenty-second phase signal nea and the twenty-third phase signal noa based on the sixteenth selection signal has.
  • a fifth two-selection circuit 75 selects either the twenty-fourth phase signal neb or the twenty-fifth phase signal nob based on the seventeenth selection signal hbs.
  • the sixth two-selection circuit 76 selects the phase signal selected by the fifth two-selection circuit 75 from the twenty-fourth phase signal neb and the twenty-fifth phase signal nob based on the seventeenth selection signal hbs.
  • the selector 2 of FIG. 13 includes a seventh two-selection circuit 81, an eighth two-selection circuit 82, a ninth and a tenth two-selection circuit 84 .
  • the twenty-second phase signal nea and the twenty-third phase signal noa are input to the seventh two-selection circuit 81 and the eighth two-selection circuit 82, respectively.
  • the seventh two-selection circuit 81 always selects the twenty-second phase signal nea
  • the eighth two-selection circuit 82 always selects the twenty-third phase signal noa.
  • the 24th phase signal neb and the 25th phase signal nob are input to the ninth two-selection circuit 83 and the tenth two-selection circuit 84, respectively.
  • the ninth two-selection circuit 83 always selects the twenty-fourth phase signal neb
  • the tenth two-selection circuit 84 always selects the twenty-fifth phase signal nob.
  • the seventh two-selection circuit 81 to tenth two-selection circuit 84 do not perform a selection operation, but are used to match the timing with the third two-selection circuit 73 to sixth two-selection circuit 76. is provided in
  • the fifteenth interpolator 77 outputs a first phase signal having a phase corresponding to the phase of the phase signal selected by the third two-selection circuit 73 and the phase of the phase signal selected by the fourth two-selection circuit 74. Generate Pnea.
  • the sixteenth interpolator 78 selects the phase of the twenty-second phase signal nea selected by the seventh two-selection circuit 81 and the phase of the twenty-third phase signal noa selected by the eighth two-selection circuit 82. to generate a second phase signal Pnoa having a phase according to .
  • a seventeenth interpolator 79 outputs a third phase signal having a phase corresponding to the phase of the phase signal selected by the fifth binary selection circuit 75 and the phase of the phase signal selected by the sixth binary selection circuit 76. Generate Pneb.
  • the eighteenth interpolator 80 selects the phase of the twenty-fourth phase signal neb selected by the ninth binary selection circuit 83 and the phase of the twenty-fifth phase signal nob selected by the tenth binary selection circuit 84. to generate a fourth phase signal Pnob having a phase according to .
  • the selector 2 in FIG. 13 can generate polyphase signals whose phases are sequentially shifted by a minimum phase amount corresponding to half the cycle of the input clock signal CLK, using the 12th selection signal neas to the 17th selection signal hbs.
  • FIG. 14 is a block diagram showing the internal configuration of the 11th interpolator 69 to the 18th interpolator 80 in FIG.
  • Each of the eleventh interpolator 69 to the eighteenth interpolator 80 has the same configuration, and outputs phase signals having phases corresponding to the phases of the two input phase signals IN1 and IN2.
  • Each of the 11 interpolators 69 to the 18th interpolator 80 is collectively referred to as DIV2PI.
  • the DIV2PI in FIG. 14 has two inverters 85, 86, two low-leakage DIV2PIs 87, 88, and a set-reset circuit 89.
  • the two low-leakage DIV2PIs 87, 88 have the same configuration.
  • the two low-leakage DIV2PIs 87, 88 may also be referred to as a first low-leakage DIV2PI 87 and a second low-leakage DIV2PI 88 for distinction.
  • the first low-leakage DIV2PI 87 outputs phase signals having phases corresponding to the phases of the two phase signals IN1 and IN2 input to the DIV2PI in FIG.
  • the second low-leakage DIV2PI 88 outputs phase signals having phases corresponding to phases of two phase signals obtained by inverting the two phase signals IN1 and IN2 by inverters 85 and 86 .
  • the set-reset circuit 89 has the same circuit configuration as the set-reset circuit 35 of FIG.
  • the set reset circuit 89 enters a set state when the phase signal output from the first low-leakage DIV2PI 87 becomes high level, and outputs a high level signal. Also, when the phase signal output from the second low-leakage DIV2PI 88 becomes high level, the set reset circuit 89 enters a reset state and outputs a low level signal.
  • FIG. 15 is a circuit diagram showing the internal configuration of the low-leakage DIV2PI (first low-leakage DIV2PI 87 and second low-leakage DIV2PI 88) of FIG.
  • the low leakage DIV2 PI 87,88 of FIG. 98 input nodes and an NMOS transistor Q12 connected between the ground node.
  • the output node of the OR gate 95 is connected to the gate of the PMOS transistor Q10.
  • the phase signal IN1 is input via the buffer 96 to the gate of the NMOS transistor Q11.
  • the phase signal IN2 is input through the buffer 97 to the gate of the NMOS transistor Q12.
  • the PMOS transistor Q10 When both the phase signals IN1 and IN2 are at low level, the PMOS transistor Q10 is turned on and the input node of the inverter 98 is charged to high level. After that, when at least one of the phase signals IN1 and IN2 is turned on, at least one of the NMOS transistors Q11 and Q12 is turned on, current is drawn from the input node of the inverter 98 to the ground node, and the input node of the inverter 98 is pulled out. The potential drops. With two NMOS transistors on than with one NMOS transistor on, the potential at the input node of inverter 98 falls more quickly and the output of low leakage DIV2PI 87, 88 transitions from low to high. faster timing. As a result, the low-leakage DIV2PIs 87 and 88 in FIG. 15 can output phase signals having phases corresponding to the phases of the two phase signals IN1 and IN2.
  • FIG. 16 is a circuit diagram according to a first modification of the low-leakage DIV2PIs 87, 88 of FIG.
  • the low leakage DIV2PI 87,88 of FIG. 16 has two AND gates 99,100 in addition to the configuration of FIG.
  • One AND gate 99 outputs a logical AND signal b of the phase signal IN1 and a phase signal obtained by delaying the phase signal IN1 by the buffer 96.
  • the output signal b of one AND gate 99 is input to the gate of the NMOS transistor Q11.
  • the other AND gate 100 outputs a logical AND signal c of the phase signal IN1 and the phase signal obtained by delaying the phase signal IN1 by the buffer 97 .
  • the output signal c of the other AND gate 100 is input to the gate of the NMOS transistor Q12.
  • the timing at which the outputs of the AND gates 99 and 100 transition to high level can be reliably delayed from the timing at which the output of the OR gate 95 transitions to high level. It is possible to prevent the PMOS transistor Q10 and the NMOS transistor Q11 or Q12 from turning on at the same time, thereby preventing a through current from flowing from the power supply voltage node to the ground node.
  • FIG. 17 is a circuit diagram according to a second modification of the low-leakage DIV2PIs 87, 88 of FIG. 17 has two OR gates 101 and 102, one AND gate 103, two buffers 104 and 105, and a dummy circuit 106 in addition to the configuration of FIG. Buffers 104 and 105 are for delay adjustment, and the number of connection stages is arbitrary. Any logic gates or inverters may be used instead of the OR gates 95, 101 and 102.
  • One OR gate 101 outputs a logical sum signal a of the phase signal IN1 delayed by the buffer 96 and the phase signal IN2.
  • the output signal a of one OR gate 101 is input to the gate of the NMOS transistor Q11.
  • AND gate 103 outputs a logical AND signal of phase signal IN2 and signals obtained by delaying phase signal IN2 by buffers 104 and 105 .
  • the other OR gate 102 outputs the OR signal c of the output signal of the AND gate 103 and the signal obtained by delaying the phase signal IN2 by the buffer 97 . This signal is input to the gate of the NMOS transistor Q12.
  • a dummy circuit 106 is connected to the signal path of the phase signal IN1.
  • the dummy circuit 106 adds a load similar to that of the signal IN2 to the signal path of the signal IN1, and the internal configuration of the dummy circuit 106 does not matter.
  • FIG. 18 is a timing diagram of the low leakage DIV2PI 87, 88 of FIG. FIG. 18 shows timings of the phase signal IN1, the phase signal IN2, the output signal a of the OR gate 95, the output signal b of the OR gate 101, and the output signal c of the OR gate .
  • FIG. 19 is a diagram explaining the operation of the first selection circuit 21 and the second selection circuit 22 in the selector 2 of FIG.
  • FIG. 19 shows a bit string of the control code input to the semiconductor circuit 1 of FIG.
  • a diagram showing the correspondence relationship with the bit string of the thirteenth selection signal noas, the waveform of the signal selected by the first selection circuit 21, and the waveform of the signal selected by the second selection circuit 22 are shown.
  • the third selection circuit 23 and the fourth selection circuit 24 in the selector 2 of FIG. 13 perform selection operations similar to those of the first selection circuit 21 and the second selection circuit 22, although the signals to be selected are different. Therefore, it is omitted in FIG.
  • a control code is, for example, a bit string signal consisting of 13 bits.
  • the three most significant bits of the bit string signal are used for selection by the first selection circuit 21 to the fourth selection circuit 24 .
  • the upper 3 bits of the control code have 8 different values.
  • the 12th selection signal neas and the 13th selection signal noas are also 3-bit bit string signals.
  • the bit value of either the 12th selection signal neas or the 13th selection signal noas changes. More specifically, every time the bit value of the control code changes by one, the bit value of the twelfth selection signal neas or the thirteenth selection signal noas alternately changes by one.
  • the polyphase signals are frequency-divided clock signals DCK having different phases, as shown in FIG.
  • the second selection circuit 22 selects the frequency-divided clock signal DCK having the signal waveform w3, for example.
  • the first selection circuit 21 selects the frequency-divided clock signal DCK having the signal waveform w4. In this manner, each time the control code changes by 1, the first selection circuit 21 and the second selection circuit 22 are alternately selected based on the 12th selection signal neas or the 13th selection signal noas corresponding to the control code. to select the frequency-divided clock signal DCK whose phase is shifted by the minimum phase amount.
  • control circuit (second control circuit) 13 of FIG. A fourteenth selection signal nebs consisting of eight bit string signals and a fifteenth selection signal nobs consisting of a ninth bit string signal are output and input to the selector 2 in FIG. Then, the control circuit 13 alternately changes part of the bit values in the sixth bit string signal and the seventh bit string signal so that the first selection circuit 21 and the second selection circuit 22 select By alternately changing the phase of the signal by the minimum phase and alternately changing some bit values in the eighth bit string signal and the ninth bit string signal, the third selection circuit 23 and the fourth selection The phase of the signal selected by the circuit 24 is alternately changed by the minimum phase.
  • control circuit 13 may output a 16th selection signal has made up of the tenth bit string signal and a seventeenth selection signal hbs made up of the 11th bit string signal. In this case, the control circuit 13 alternately changes some bit values in the tenth bit string signal and the eleventh bit string signal to obtain the first phase signal Pnea, the second phase signal Pnoa, and the third phase signal Pnoa. and the phase of the fourth phase signal Pnob are shifted by the minimum phase.
  • FIG. 20 is a diagram explaining the operation of the third two-selection circuit 73 and the fourth two-selection circuit 74 in the selector 2 of FIG.
  • FIG. 20 shows part of the bit string in the control code input to the semiconductor circuit 1 of FIG. are shown.
  • FIG. 20 shows a signal waveform w11 of the input clock signal CLK, signal waveforms w12 and w14 of the 22nd phase signal nea output from the 11th interpolator 69, and output from the 12th interpolator 70.
  • a signal waveform w13 of the twenty-third phase signal noa is shown.
  • the twenty-second phase signal nea and the twenty-third phase signal noa are signals whose phases are shifted by about half the cycle of the input clock signal CLK.
  • the eleventh interpolator 69 outputs the 22nd phase signal nea having different phases as shown by the signal waveforms w12 and w14 according to the signal selected by the first selection circuit 21 on the preceding stage. Output.
  • the 4th and 5th bits from the most significant are used to select the third two-selection circuit 73 and the fourth two-selection circuit 74.
  • the third two-selection circuit 73 and the fourth two-selection circuit 74 select the twenty-second phase signal nea.
  • the fifteenth interpolator 77 outputs a first phase signal Pnea having a phase corresponding to the phase of the twenty-second phase signal nea, as indicated by a signal waveform w15.
  • the sixteenth interpolator 78 divides the phase of the twenty-second phase signal nea output from the seventh two-select circuit 81 and the eighth two-phase signal nea, as shown in the signal waveform w16.
  • a second phase signal Pnoa having a phase corresponding to the phase of the twenty-third phase signal noa output from the selection circuit 82 is output.
  • the third two-selection circuit 73 and the fourth two-selection circuit 74 both output the twenty-third phase signal noa.
  • the fifteenth interpolator 77 outputs a first phase signal Pnea having a phase corresponding to the phase of the twenty-third phase signal noa, as indicated by a signal waveform w17.
  • the sixteenth interpolator 78 divides the phase of the twenty-second phase signal nea output from the seventh two-selection circuit 81 and the eighth two-selection circuit 81 as shown in the signal waveforms.
  • a second phase signal Pnoa having a phase corresponding to the phase of the twenty-third phase signal noa output from the circuit 82 is output.
  • the selector 2 in FIG. It outputs a phase signal Pnoa.
  • FIG. 21 is a diagram explaining the operation of the fifth interpolator 51 and the sixth interpolator 52 in the semiconductor circuit 1 of FIG.
  • FIG. 21 shows part of the bit string in the control code input to the semiconductor circuit 1 of FIG. 11, the bit string of the sixth selection signal meas for selecting the phase of the fifth interpolator 51, The bit strings of the seventh selection signal moas for phase selection of the 6 interpolators 52 and the phase differences between these bit strings are shown.
  • FIG. 21 shows a signal waveform w21 of the input clock signal CLK, a signal waveform w22 of the first phase signal Pnea output from the multiphase clock generator & selector 5, a signal waveform w23 of the second phase signal Pnoa, A signal waveform w24 of the first phase signal Pnea obtained by shifting the phase of the signal waveform w22 is shown.
  • the first selection signal nas input to the multiphase clock generator & selector 5 can be used to select whether the phase of the first phase signal Pnea should be the signal waveform w22 or the signal waveform w24.
  • the fifth interpolator 51 and the sixth interpolator 52 are set to the 10th phase by the bit values of, for example, the 6th to 9th bits from the most significant bit of the bit string signal of the control code.
  • a signal nmea and an eleventh phase signal nmoa are generated.
  • the control circuit 13 outputs the bit string signal of the sixth selection signal meas for selecting the phase of the fifth interpolator 51 and the bit string signal of the sixth interpolator 51 according to the bit values of the sixth to ninth bits from the most significant bit of the control code. and a bit string signal of a seventh selection signal moas for performing 52 phase selections.
  • the bit string signals of the sixth selection signal meas and the seventh selection signal moas are each 8 bits, for example.
  • the bit string signal of the sixth selection signal meas and the bit string signal of the seventh selection signal moas alternately change their bit values by two bits from the lower side to the higher side. More specifically, when the sixth bit of the control code is 0, the bit string signal of the sixth selection signal meas and the bit string signal of the seventh selection signal moas alternately change from 00 to 11 by two bits.
  • the bit positions of the 2 bits that change are shifted from the low order side to the high order side of each bit string signal.
  • bit string signal of the sixth selection signal meas For this reason, looking at the bit string signal of the sixth selection signal meas, the same bit string signal continues twice, and then the bit string signal that changes to 11 by 2 bits from the lower side continues twice in succession. is repeated.
  • bit string signal of the seventh selection signal moas but the sixth selection signal meas and the seventh selection signal moas have different timings at which 2 bits in the bit string signal change to 11.
  • FIG. Therefore, the magnitude relationship between the bit string signal of the sixth selection signal meas and the bit string signal of the seventh selection signal moas alternately changes.
  • a change in the magnitude relationship of the bit string signals means a change in the phase difference between the bit string signals, and as shown in FIG. 21, lead and lag of the phase appear alternately.
  • the phase of the first phase signal Pnea input to the fifth interpolator 51 changes and changes from the signal waveform w22 to the signal waveform w24.
  • the bit string signal of the sixth selection signal meas and the bit string signal of the seventh selection signal moas change to 00 by two bits from the upper side as the 7th to 9th bits from the most significant bit of the control code change by one bit. Change.
  • the sixth interpolator 52 outputs the first phase signal Pnea indicated by the signal waveform w22 and the first phase signal Pnea indicated by the signal waveform w23. 2 phase signal Pnoa, the eleventh phase signal nmoa shown in the signal waveform w26 is generated.
  • the fifth interpolator 51 When the 6th to 9th bits from the most significant bit of the control code are 0001, the fifth interpolator 51 outputs the first phase signal Pnea indicated by the signal waveform w22 and the second phase signal Pnoa indicated by the signal waveform w23. , to generate a tenth phase signal nmea shown in signal waveform w27.
  • the fifth interpolator 51 and the sixth interpolator 52 alternately generate the minimum phase amount.
  • a shifted tenth phase signal nmea or an eleventh phase signal nmoa is generated.
  • the bit string signal of the sixth selection signal meas for phase selection of the fifth interpolator 51 and the bit string signal of the seventh selection signal moas for phase selection of the sixth interpolator 52 are 2 Alternately bit by bit.
  • the phase of the first phase signal Pnea input to the fifth interpolator 51 and the sixth interpolator 52 changes (signal waveform w24 ).
  • the sixth interpolator 52 outputs the first phase signal Pnea indicated by the signal waveform w24 and the second phase signal indicated by the signal waveform w23. From Pnoa, an eleventh phase signal nmoa shown in signal waveform w34 is generated.
  • the fifth interpolator 51 converts the first phase signal Pnea indicated by the signal waveform w24 and the second phase signal Pnoa indicated by the signal waveform w23 to , to generate the tenth phase signal nmea shown in the signal waveform w35.
  • the bit string signal of the sixth selection signal meas and the bit string signal of the seventh selection signal moas are changed to 00 by two bits from the upper side.
  • the phases of the tenth phase signal nmea and the eleventh phase signal nmoa alternately output from the fifth interpolator 51 and the sixth interpolator 52 change each time the control code changes by one bit. , are sequentially shifted in the same direction by the minimum phase amount.
  • a bit string signal of the ninth selection signal mebs for phase selection of the eighth interpolator 54 and a bit string signal of the tenth selection signal mobs for phase selection of the ninth interpolator 55 each time the signal changes. is changed by 2 bits, and the phases of the 12th phase signal nmeb and the 13th phase signal nmob are alternately changed by the minimum phase amount.
  • the fifth interpolator 51 outputs the 10 phase signal nmea and the eleventh phase signal nmoa output from the sixth interpolator 52 can be shifted by the minimum phase amount.
  • FIG. 22 is a diagram for explaining operations of the seventh interpolator 53 and the tenth interpolator 56 in the semiconductor circuit 1 of FIG.
  • FIG. 22 shows part of the bit string in the control code input to the semiconductor circuit 1 of FIG. 11 and the bit string signal of the eighth selection signal kas for phase selection of the seventh interpolator 53. Illustrated.
  • the tenth interpolator 56 in the semiconductor circuit 1 in FIG. 11 has different selection target signals, it performs the same selection operation as the seventh interpolator 53, so it is omitted in FIG.
  • FIG. 22 shows a signal waveform w51 of the tenth phase signal nmea, a signal waveform w52 of the eleventh phase signal nmoa, and a signal waveform w53 of the tenth phase signal nmea obtained by shifting the phase of the signal waveform w51.
  • It is A first selection signal nas input to the multiphase clock generator & selector 5 , a sixth selection signal meas input to the fifth interpolator 51 , and a sixth selection signal meas input to the sixth interpolator 52 .
  • 7 selection signal moas it is possible to select whether the phase of the tenth phase signal nmea should be the signal waveform w51 or the signal waveform w53.
  • the seventh interpolator 53 generates the fifth phase signal nmka according to the bit values of, for example, the 10th to 13th bits from the most significant bit of the control code. More specifically, the bit string signal of the eighth selection signal kas is generated from the bit values of the 10th to 13th bits from the most significant bit of the control code. As shown in FIG. 22, the bit string signal of the eighth selection signal kas is, for example, 8 bits. The bit string signal of the eighth selection signal kas changes its bit value bit by bit. More specifically, when the 10th bit from the most significant bit of the control code is 0, each bit of the bit string signal of the eighth selection signal kas changes from 0 to 1 in order from the lower side to the higher side. When the 10th bit from the high order of the control code is 1, each bit of the bit string signal of the eighth selection signal kas sequentially changes from 1 to 0 from the high order side to the low order side.
  • the seventh interpolator 53 When the 10th to 13th bits from the most significant bit of the control code are 0000, the seventh interpolator 53 outputs the tenth phase signal nmea indicated by the signal waveform w51 and the eleventh phase signal nmoa indicated by the signal waveform w52. , the fifth phase signal nmka shown in the signal waveform w55 is generated.
  • the seventh interpolator 53 When the 10th to 13th bits from the most significant bit of the control code are 0001, the seventh interpolator 53 outputs the tenth phase signal nmea indicated by the signal waveform w51 and the eleventh phase signal nmoa indicated by the signal waveform w52. , the fifth phase signal nmka shown in the signal waveform w56 is generated.
  • the bit string signal of the eighth selection signal kas for selecting the phase of the seventh interpolator 53 has a bit value of 1 from the lower side to the higher side. and the fifth phase signal nmka is phase-shifted by the minimum phase amount.
  • the phase of the tenth phase signal nmea input to the seventh interpolator 53 changes (signal waveform w53).
  • the seventh interpolator 53 generates the fifth phase signal nmka indicated by the signal waveform w63 from the tenth phase signal nmea indicated by the signal waveform w53 and the eleventh phase signal nmoa indicated by the signal waveform w52. .
  • the bit string signal of the eighth selection signal kas for selecting the phase of the seventh interpolator 53 has a bit value of 0 from the upper side to the lower side. and the fifth phase signal nmka is phase-shifted by the minimum phase amount.
  • the control circuit (first control circuit) 13 of FIG. It outputs a ninth selection signal mebs consisting of three bit string signals and a tenth selection signal mobs consisting of a fourth bit string signal.
  • the control circuit 13 alternately changes part of the bit values in the first bit string signal and the second bit string signal, thereby changing the phases of the tenth phase signal nmea and the eleventh phase signal nmoa by the minimum phase.
  • the phases of the twelfth phase signal nmeb and the thirteenth phase signal nmob are shifted by the minimum phase by shifting and alternately changing partial bit values in the third bit string signal and the fourth bit string signal.
  • control circuit 13 alternately changes a part of the bit values in the first bit string signal and the second bit string signal from the lower bit side to the upper bit side, and then changes the bit values from the upper bit side to the lower bit side.
  • the twelfth phase signal nmeb and the thirteenth phase signal nmob are changed. Shift the phase by the minimum phase.
  • the control circuit 13 sequentially changes a part of the bit values in the eighth selection signal kas, which is the fourth bit string signal, thereby shifting the phase of the fifth phase signal nmka by the minimum phase.
  • the phase of the sixth phase signal nmkb is shifted by the minimum phase.
  • FIG. 23 is a block diagram showing the internal configuration of a modified example of the multiphase clock generator & selector 5 of FIG.
  • the multiphase clock generation & selector 5 of FIG. 23 is obtained by integrating the multiphase clock generation circuit 12 and the selector 2 .
  • the selector 2 in FIG. 13 generates the first phase signal Pnea to the fourth phase signal Pnob using the multiphase signals from the multiphase clock generation circuit 12 in FIG.
  • the generation & selector 5 includes a first multiphase clock generation circuit 121 for generating the first phase signal Pnea based on the twelfth selection signal neas, and a second phase clock generation circuit 121 for generating the first phase signal Pnea based on the thirteenth selection signal noas.
  • a second multiphase clock generation circuit 122 for generating the signal Pnoa; a third multiphase clock generation circuit 123 for generating the third phase signal Pneb based on the fourteenth selection signal nebs; and a fourth multiphase clock generation circuit 124 for generating a fourth phase signal Pnob based on fifteen selection signals nobs.
  • the first multiphase clock generation circuit 121 has a plurality of cascaded FFs 9 and a plurality of two-selection circuits 125 connected to the input nodes of each FF 9 .
  • Each 2-selection circuit 125 inputs the frequency-divided clock signal DCK generated by the N frequency-dividing circuit 8 to the next-stage FF9, or transmits the output signal of the previous-stage FF9 to the next-stage FF9, based on the twelfth selection signal neas. Select whether to input to FF9.
  • the post-stage side of the first to fourth multiphase clock generation circuits 121 to 124 has basically the same circuit configuration as the post-stage side of the first selection circuit 21 to the fourth selection circuit 24 in FIG. , the explanation is omitted.
  • the semiconductor circuit 1 since a plurality of interpolators are connected in multiple stages and multiphase signals are generated using the rising edge and falling edge of the input clock signal CLK, It is possible to reduce the amount of phase shift of each phase signal. Further, in the present embodiment, as shown in FIGS. 19 to 22, for example, an 8-bit bit string signal is generated based on a partial bit string of the control code from the outside, and some bits of the bit string signal are sequentially processed. By shifting, it is possible to generate phase signals whose phases are sequentially shifted by the minimum phase amount.
  • FIG. 24 is a block diagram showing a schematic configuration of the semiconductor circuit 1 according to the fourth embodiment.
  • the semiconductor circuit 1 of FIG. 24 includes a multiphase clock generation circuit 12, a plurality of interpolators (PI) 126, a phase selection circuit 127, a first interpolator 3a, and a second interpolator 3b. It has
  • the multiphase clock generation circuit 12 generates multiphase signals with different phases in synchronization with the input clock signal CLK.
  • the polyphase signal is a signal obtained by shifting the phase of the frequency-divided clock signal DCK obtained by frequency-dividing the input clock signal CLK in a plurality of ways. The number of phases of the polyphase signal does not matter.
  • a plurality of interpolators 126 respectively generate phase signals whose phases correspond to the phases of the two frequency-divided clock signals DCK output from the multiphase clock generation circuit 12 .
  • the number of interpolators 126 is not particularly limited, and the number of interpolators 126 is provided according to the number of phases of the polyphase signal.
  • the phase selection circuit 127 selects the first phase signal Pnea and the second phase signal Pnoa having different phases from among the plurality of phase signals output from the plurality of interpolators 126, and selects the first phase signal Pnea and the second phase signal Pnoa having different phases.
  • a third phase signal Pneb and a fourth phase signal Pnob are selected.
  • a plurality of interpolators 126 and phase selection circuits 127 may be connected in multiple stages as in the semiconductor circuit 1 according to the third embodiment described above.
  • the first interpolator 3a outputs a fifth phase signal Outa having a phase corresponding to the phase of the first phase signal Pnea and the phase of the second phase signal Pnoa.
  • the second interpolator 3b outputs a sixth phase signal Outb having a phase corresponding to the phases of the third phase signal Pneb and the fourth phase signal Pnob.
  • the fifth phase signal Outa output by the first interpolator 3a is a reference phase signal.
  • the phase difference can be detected without depending on PVT (process P, voltage V, temperature T).
  • FIG. 25 is a block diagram of a semiconductor circuit 1 including a first fine interpolator (fine PI) 128 and a second fine interpolator (fine PI) 129 in addition to the configuration of FIG.
  • the fifth phase signal output from the first interpolator 3 a is input to the first fine adjustment interpolator 128 .
  • the first fine interpolator 128 outputs a first fine phase signal Outa obtained by finely adjusting the phase of the fifth phase signal.
  • the second fine adjustment interpolator 129 receives the sixth phase signal output from the second interpolator 3b.
  • the second fine interpolator 128 outputs a second fine phase signal Outb obtained by finely adjusting the phase of the sixth phase signal.
  • the semiconductor circuit 1 in FIGS. 24 and 25 is composed of logic gates and FFs, it can be arranged in at least part of a standard cell formed in advance on a semiconductor substrate. By arranging the semiconductor circuit 1 of FIGS. 24 and 25 on the standard cell, it is possible to reduce the number of design man-hours, and to easily form a chip.
  • FIG. 26 is a block diagram showing a schematic configuration of an electronic device 10 having the semiconductor circuit 1 according to the fifth embodiment.
  • the electronic device 10 of FIG. 26 includes a semiconductor circuit 1, a light projecting section 111, a light receiving section 112, and a phase difference detection circuit 113, which have the same configuration as in FIG.
  • the electronic device 10 of FIG. 26 can be composed of one or more semiconductor chips.
  • the light projecting unit 111 can be configured with a Vertical Cavity Surface Emitting Laser (VCSEL).
  • the light receiving unit 112 can be configured with SPAD (Single Photon Avalanche Diode).
  • the first fine adjustment phase signal Outa output from the first fine adjustment interpolator 128 is used as a light projection timing signal for the light projection section 111 .
  • the object 15 is irradiated with the light projected from the light projecting unit 111 , and the reflected light from the object 15 is received by the light receiving unit 112 .
  • the second fine phase signal output from the second fine interpolator 128 is used to sample the received light signal at the light receiving section 112 . By gradually shifting the phase of the second fine phase signal, it is possible to generate the second fine phase signal having a phase suitable for sampling the received light signal.
  • the phase difference detection circuit 113 detects the phase difference between the phase of the second fine adjustment phase signal suitable for sampling the received light signal and the first fine adjustment phase signal. Thereby, a phase difference independent of process P, voltage V, and temperature T can be detected.
  • this technique can take the following structures. (1) outputting a first phase signal and a second phase signal having different phases based on a first selection signal from among polyphase signals having different phases, and outputting a first phase signal and a second phase signal having different phases based on the second selection signal; a selector that outputs a third phase signal and a fourth phase signal that are out of phase with each other; a first interpolator that outputs a fifth phase signal having a phase corresponding to the phase of the first phase signal and the phase of the second phase signal; and a second interpolator that outputs a sixth phase signal having a phase corresponding to the phase of the third phase signal and the phase of the fourth phase signal.
  • a multiphase clock generation circuit that generates the multiphase signal by shifting the phase of the frequency-divided clock signal obtained by frequency-dividing the input clock signal;
  • the selector comprises the first phase signal and the second phase signal, which are out of phase with each other by one cycle or half a cycle of the input clock signal, and the first phase signal and the second phase signal out of phase with each other by one cycle or half a cycle of the input clock signal.
  • the semiconductor circuit according to (4) which outputs the third phase signal and the fourth phase signal that are shifted from each other.
  • each of the first interpolator and the second interpolator a third interpolator that outputs a seventh phase signal having a phase corresponding to the phases of the two phase signals having different phases; a fourth interpolator that outputs an eighth phase signal having a phase corresponding to the phases of the two opposite phase signals obtained by inverting the logic of the two phase signals;
  • a set-reset circuit that outputs a ninth phase signal that becomes the first logic when the seventh phase signal is of a predetermined logic and a second logic when the eighth phase signal is the predetermined logic. and
  • the two phase signals are the first phase signal and the second phase signal in the first interpolator, and the third phase signal and the fourth phase signal in the second interpolator.
  • phase signal is the phase signal, (7) or (8), wherein the ninth phase signal is the fifth phase signal in the first interpolator and the sixth phase signal in the second interpolator;
  • a semiconductor circuit as described. (10) a first two-selection circuit that selects one of the fifth phase signal and the sixth phase signal based on a fifth selection signal; a second two-selection circuit that selects the other of the fifth phase signal and the sixth phase signal that the first two-selection circuit did not select, based on the fifth selection signal. , (1) to (9).
  • the first interpolator is a fifth interpolator for generating a tenth phase signal having a phase corresponding to a sixth selection signal from the first phase signal and the second phase signal; a sixth interpolator that generates an eleventh phase signal having a phase corresponding to a seventh selection signal from the first phase signal and the second phase signal; a seventh interpolator that generates the fifth phase signal having a phase corresponding to an eighth selection signal from the tenth phase signal and the eleventh phase signal;
  • the second interpolator is an eighth interpolator that generates a twelfth phase signal having a phase corresponding to a ninth selection signal from the third phase signal and the fourth phase signal; a ninth interpolator for generating a thirteenth phase signal having a phase corresponding to a tenth selection signal from the third phase signal and the fourth phase signal; (1) to a tenth interpolator that generates the sixth phase signal having a phase corresponding to an eleventh selection signal from the twelfth phase signal and the thirteenth phase signal;
  • the sixth selection signal consisting of the first bit string signal; the seventh selection signal consisting of the second bit string signal; the ninth selection signal consisting of the third bit string signal; a first control circuit for outputting the tenth selection signal consisting of a bit string signal of The first control circuit alternately changes part of bit values in the first bit string signal and the second bit string signal, thereby changing the tenth phase signal and the eleventh phase signal.
  • the twelfth phase signal and the thirteenth phase signal are obtained by shifting the phase by the minimum phase and alternately changing part of the bit values in the third bit string signal and the fourth bit string signal.
  • the first control circuit alternately changes part of the bit values in the first bit string signal and the second bit string signal from the lower bit side to the upper bit side, By alternately changing from the bit side to the lower bit side, the phases of the tenth phase signal and the eleventh phase signal are shifted by the minimum phase, and the third bit string signal and the fourth bit string signal are shifted by the minimum phase.
  • the twelfth phase signal and the semiconductor circuit according to (12) After alternately changing a part of bit values in the bit string signal from the lower bit side to the upper bit side, by alternately changing from the upper bit side to the lower bit side, the twelfth phase signal and the semiconductor circuit according to (12), wherein the phase of the thirteenth phase signal is shifted by a minimum phase.
  • the eighth selection signal is a fourth bit string signal; the eleventh selection signal is a fifth bit string signal,
  • the first control circuit shifts the phase of the fifth phase signal by the minimum phase by sequentially changing the bit values of a part of the fourth bit string signal, and shifts the phase of the fifth bit string signal by the minimum phase.
  • the first selection signal includes a 12th selection signal and a 13th selection signal; the second selection signal includes a fourteenth selection signal and a fifteenth selection signal;
  • the selector is a first selection circuit that selects one signal from the polyphase signals based on the twelfth selection signal; a second selection circuit that selects one signal from the polyphase signals based on the thirteenth selection signal; a third selection circuit that selects one signal from the polyphase signals based on the fourteenth selection signal; a fourth selection circuit that selects one signal from the polyphase signals based on the fifteenth selection signal; a first synchronization circuit for generating the first phase signal by synchronizing the signal selected by the first selection circuit with an input clock signal; a second synchronization circuit for generating the second phase signal by synchronizing the signal selected by the second selection circuit with the input clock signal; a third synchronization circuit for generating the third phase signal by synchronizing the signal selected by the third selection circuit with the input clock signal; and a fourth synchronization circuit that generates the fourth phase signal
  • the first selection signal includes a 12th selection signal and a 13th selection signal; the second selection signal includes a fourteenth selection signal and a fifteenth selection signal;
  • the selector is a first selection circuit that selects one signal from the polyphase signals based on the twelfth selection signal; a second selection circuit that selects one signal from the polyphase signals based on the thirteenth selection signal; a third selection circuit that selects one signal from the polyphase signals based on the fourteenth selection signal; a fourth selection circuit that selects one signal from the polyphase signals based on the fifteenth selection signal; a first synchronization circuit for generating a fourteenth phase signal by synchronizing the signal selected by the first selection circuit at the timing when the input clock signal transitions from the first logic to the second logic; a second synchronization circuit for generating a fifteenth phase signal by synchronizing the fourteenth phase signal with timing at which the input clock signal transitions from the second logic to the first logic; a third synchronizing circuit for generating a sixteen
  • a second control circuit for outputting the fifteenth selection signal consisting of bit string signals of By alternately changing the values, the phases of the signals selected by the first selection circuit and the second selection circuit are alternately changed by the minimum phase, and the eighth bit string signal and the ninth bit string signal are alternately changed. alternately changing the phases of the signals selected by the third selection circuit and the fourth selection circuit by a minimum phase by alternately changing a part of the bit values in the bit string signal;
  • the sixteenth selection signal is a tenth bit string signal; the seventeenth selection signal is an eleventh bit string signal;
  • the second control circuit alternately changes partial bit values in the tenth bit string signal and the eleventh bit string signal to generate the first phase signal, the second phase signal,
  • phase difference control circuit (20) a phase difference control circuit;
  • An electronic device comprising a phase difference detection circuit, The phase difference control circuit is Outputting a first phase signal and a second phase signal whose phases are different from each other based on a first selection signal from among the polyphase signals whose phases are different from each other, and outputting a phase signal whose phases are different from each other based on the second selection signal a selector that outputs different third phase signals and fourth phase signals; a first interpolator that outputs a fifth phase signal having a phase corresponding to the phase of the first phase signal and the phase of the second phase signal; a second interpolator that outputs a sixth phase signal having a phase corresponding to the phase of the third phase signal and the phase of the fourth phase signal;
  • the phase difference detection circuit uses the fifth phase signal as a reference phase signal and detects a phase difference from the sixth phase signal.

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PCT/JP2022/015161 2021-03-31 2022-03-28 半導体回路及び電子機器 WO2022210592A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001056723A (ja) * 1999-08-19 2001-02-27 Fujitsu Ltd 半導体集積回路
JP2001273048A (ja) * 2000-03-24 2001-10-05 Nec Corp クロック制御回路及びクロック制御方法
JP2002353808A (ja) * 2001-05-24 2002-12-06 Nec Corp クロック制御回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001056723A (ja) * 1999-08-19 2001-02-27 Fujitsu Ltd 半導体集積回路
JP2001273048A (ja) * 2000-03-24 2001-10-05 Nec Corp クロック制御回路及びクロック制御方法
JP2002353808A (ja) * 2001-05-24 2002-12-06 Nec Corp クロック制御回路

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