WO2022206749A1 - Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur - Google Patents

Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur Download PDF

Info

Publication number
WO2022206749A1
WO2022206749A1 PCT/CN2022/083632 CN2022083632W WO2022206749A1 WO 2022206749 A1 WO2022206749 A1 WO 2022206749A1 CN 2022083632 W CN2022083632 W CN 2022083632W WO 2022206749 A1 WO2022206749 A1 WO 2022206749A1
Authority
WO
WIPO (PCT)
Prior art keywords
encapsulation
redistribution
redistribution structure
layer
die
Prior art date
Application number
PCT/CN2022/083632
Other languages
English (en)
Chinese (zh)
Inventor
周辉星
Original Assignee
矽磐微电子(重庆)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽磐微电子(重庆)有限公司 filed Critical 矽磐微电子(重庆)有限公司
Publication of WO2022206749A1 publication Critical patent/WO2022206749A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
  • MCM multi-chip module
  • a first aspect of the embodiments of the present application provides a semiconductor packaging method.
  • the semiconductor packaging method includes:
  • the step of forming the first encapsulation structure includes: mounting a first die on a first carrier, the front side of the first die facing the a first carrier board, a plurality of first bonding pads are arranged on the front side of the first die; a first encapsulation layer is formed; the first carrier board is peeled off; a first redistribution structure electrically connected to the first pad; the step of forming the second encapsulation structure includes: mounting a second bare chip on a second carrier board, the front surface of the second bare chip is provided with a plurality of a second bonding pad, the front side of the second die facing the second carrier; forming a second encapsulation layer; peeling off the second carrier; A second redistribution structure electrically connected to the second pad;
  • first encapsulation structure and the second encapsulation structure are both facing the carrier board;
  • a third encapsulation layer is formed, and the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure;
  • the third encapsulation structure includes the first encapsulation structure a surface and a second surface opposite to the first surface, the first surface facing the third carrier;
  • the third redistribution structure is electrically connected to the fourth redistribution structure through the conductive structure, and the third redistribution structure is electrically connected to the first redistribution structure and the second redistribution structure, respectively;
  • a passive element is disposed on a side of the fourth redistribution structure away from the second surface, and the passive element is electrically connected to the fourth redistribution structure.
  • the semiconductor packaging method further includes: forming a first dielectric layer, the first dielectric layer fully covering the third redistribution structure, the third redistribution structure facing away from the One side of the first surface exposes the first dielectric layer.
  • the semiconductor packaging method further includes:
  • the second dielectric layer wraps the fourth redistribution structure, and the second dielectric layer is exposed on the side of the fourth redistribution structure away from the second surface,
  • the passive member is located on a side of the second dielectric layer away from the second surface.
  • the fourth rewiring structure includes a pre-wiring substrate, and the pre-wiring substrate includes a pre-wiring line, and the pre-wiring line is electrically connected to the conductive structure and the passive component, respectively.
  • the orthographic projection of the first encapsulation structure on the first surface is located outside the orthographic projection of the conductive structure on the first surface; the second encapsulation structure is located on the first surface.
  • the orthographic projection on the first surface is outside the orthographic projection of the conductive structure on the first surface.
  • a fourth redistribution structure is provided on the surface, including:
  • a conductive structure is formed in the through hole, the conductive structure is electrically connected to the third redistribution structure, and the third encapsulation layer is exposed on the side of the conductive structure away from the first surface;
  • a fourth redistribution structure is disposed on the second surface, and the fourth redistribution structure is electrically connected to the conductive structure.
  • a second aspect of the embodiments of the present application provides a semiconductor package structure, the semiconductor package structure includes:
  • the third encapsulation structure includes a first encapsulation structure, a second encapsulation structure and a third encapsulation layer; the first encapsulation structure includes a first encapsulation layer, a first die and a first redistribution structure,
  • the front side of the first bare chip is provided with a plurality of first bonding pads, the first encapsulation layer covers at least the side surface of the first bare chip, and the first redistribution structure is located on the side of the first bare chip.
  • the first redistribution structure is electrically connected to the first pad;
  • the second encapsulation structure includes a second encapsulation layer, a second die and a second redistribution structure, the second die A plurality of second pads are arranged on the front side of the second die, the second encapsulation layer covers at least the side of the second die, the second redistribution structure is located on the front side of the second die, the second The redistribution structure is electrically connected to the second pad;
  • the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure;
  • the third encapsulation structure includes a first surface and a second surface opposite to the first surface, the first redistribution structure and the second redistribution structure respectively face away from the second surface;
  • the third encapsulation structure is provided with a penetrating structure The through hole of the encapsulation structure;
  • a third redistribution structure disposed on the first surface, and electrically connected to the first redistribution structure and the second redistribution structure, respectively;
  • a fourth redistribution structure disposed on the second surface, and the third redistribution structure is electrically connected to the fourth redistribution structure through the conductive structure;
  • a passive component is disposed on the side of the fourth redistribution structure away from the second surface, and is electrically connected to the fourth redistribution structure.
  • the semiconductor package structure further includes a first dielectric layer, the first dielectric layer completely covers the third redistribution structure, and the third redistribution structure faces away from the first The first dielectric layer is exposed on one side of the surface; and/or,
  • the semiconductor package structure further includes a second dielectric layer, the second dielectric layer covers the fourth redistribution structure, and a side of the fourth redistribution structure away from the second surface exposes the A second dielectric layer, and the passive component is located on a side of the second dielectric layer away from the second surface.
  • the fourth rewiring structure includes a pre-wiring substrate, and the pre-wiring substrate includes a pre-wiring line, and the pre-wiring line is electrically connected to the conductive structure and the passive component, respectively.
  • the orthographic projection of the first encapsulation structure on the first surface is located outside the orthographic projection of the conductive structure on the first surface; the second encapsulation structure is located on the first surface.
  • the orthographic projection on the first surface is outside the orthographic projection of the conductive structure on the first surface.
  • the semiconductor packaging structure includes a first die, a second die, and a passive component, and the passive component is implemented with a fourth redistribution structure, a conductive structure, and a third redistribution structure.
  • the electrical connection between the first bare chip and the second bare chip makes the semiconductor packaging structure have more functions; the first bonding pad of the first bare chip and the second bonding pad of the second bare chip are respectively connected with the The third redistribution structure is electrically connected, and the third redistribution structure is electrically connected to the fourth redistribution structure located on the side facing away from the front surface of the first die through the conductive structure, so that the fourth redistribution structure connects the first solder joint of the first die
  • the pad and the second pad of the second die are led out to the side of the semiconductor package structure away from the front side of the first die to realize double-sided wiring of the package structure, and the external structure can be connected to the side of the semiconductor package structure away from the front side of the first die Electrical connection; the first die and the second die are placed horizontally, and the space in the horizontal direction is reasonably utilized, which can make the semiconductor package structure lighter, thinner, smaller in size and compact in structure, so that the semiconductor package structure can be suitable for small and lightweight Electronic equipment; en
  • FIG. 1 is a flowchart of a semiconductor packaging method provided by an exemplary embodiment of the present application
  • FIG. 2 is a flowchart of forming an encapsulation structure provided by an exemplary embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a silicon wafer for preparing a first die provided by an exemplary embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a protective film formed on the active surface of the silicon wafer shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram obtained by cutting the silicon wafer shown in FIG. 5;
  • FIG. 6 is a schematic structural diagram of a first die provided by an exemplary embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • Figure 8 is a top view of the first intermediate structure shown in Figure 7;
  • FIG. 9 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a third intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a fourth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a fifth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a first encapsulation structure provided by an exemplary embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a second encapsulation structure provided by an exemplary embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a sixth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 16 is a top view of the sixth intermediate structure of the second encapsulation structure shown in FIG. 15;
  • FIG. 17 is a schematic structural diagram of a seventh intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a third encapsulation structure provided by an exemplary embodiment of the present application.
  • FIG. 19 is a flowchart of a semiconductor packaging method provided by another exemplary embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of an eighth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • 21 is a schematic structural diagram of a ninth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of a tenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of an eleventh intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • 24 is a schematic structural diagram of a twelfth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • 25 is a schematic structural diagram of a thirteenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 26 is a top view of a pre-wiring substrate provided by an exemplary embodiment of the present application.
  • 27 is a cross-sectional view of a sub-region of a pre-wiring substrate provided by an exemplary embodiment of the present application.
  • FIG. 28 is a schematic structural diagram of a thirteenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 29 is a schematic structural diagram of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • first, second, third, etc. may be used in this application to describe various information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information without departing from the scope of the present application.
  • word "if” as used herein can be interpreted as "at the time of” or "when” or "in response to determining.”
  • Embodiments of the present application provide a semiconductor packaging method.
  • the semiconductor packaging method includes the following steps 110 to 160 .
  • step 110 a first encapsulation structure and a second encapsulation structure are formed.
  • the process of forming the first encapsulation structure may include the following steps 111 to 114 .
  • a first die is mounted on a first carrier, the first die has a front side, the front side of the first die faces the first carrier, the first die A plurality of first solder pads are arranged on the front side of the .
  • the first die can be prepared by the following process:
  • the silicon wafer 14 has an active surface, and the active surface of the silicon wafer 14 is provided with a first insulating layer 12 and a first bonding pad 11 , and the first insulating layer 12 can cover the edge of the first bonding pad 11 .
  • the first insulating layer 12 is provided with an opening, and the opening exposes the first pad 11 .
  • the first pads 11 are used for electrical connection with external components.
  • the first protective layer 13 is formed on the active surface of the silicon wafer 14 .
  • the first protective layer 13 is one or more layers of insulating material, and the material of the first protective layer 13 can be plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic Polymer composites or other materials with similar properties.
  • the first protective layer 13 may be formed on the silicon wafer 14 by lamination, spin coating, printing, molding or other suitable methods. Through this step, the structure shown in FIG. 4 can be obtained.
  • the silicon wafer 14 is diced.
  • the silicon wafer 14 may be diced along the locations of the dotted lines shown in FIG. 4 .
  • the silicon wafer 14 may be cut by mechanical cutting or laser cutting.
  • a grinding device may be used to grind the backside of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer 14 is a specified thickness. Through this step, the structure shown in FIG. 5 can be obtained.
  • the first protective layer 13 of the structure shown in FIG. 5 is etched to form openings 131 to obtain the first bare chip 10 as shown in FIG. 6 , and the first bare chip 10 has a specific function.
  • the openings 131 of the first protective layer 13 expose the first pads 11 of the first die 10 .
  • the first bonding pads 11 of the first die 10 are formed of conductive electrodes drawn from the internal circuit of the die to the surface of the die.
  • the openings 131 can be formed by means of laser; if the material of the first protective layer 13 is a photosensitive material, photolithography with mask exposure can be used The process forms openings 131 .
  • the openings 131 may also be formed on the first protective layer 13 before the silicon wafer 14 is cut.
  • FIG. 7 only illustrates that one first die 10 is mounted on the first carrier board 15 .
  • the number of the first bare chips 10 mounted on the first carrier board 15 is multiple, as shown in FIG. 8 .
  • the shape of the first carrier plate 15 may be circular, rectangular or other shapes.
  • the first carrier 15 may be a wafer substrate with a small size, or a carrier with a larger size, such as a stainless steel substrate, a polymer substrate, or the like.
  • the first die 10 can be mounted on the first carrier 15 through an adhesive layer, and the adhesive layer can be made of an easily peelable material, so that the first carrier 15 and the first die can be subsequently attached 10.
  • the adhesive layer can be made of a heat-separating material that can lose its adhesiveness by heating.
  • mounting equipment may be employed to mount the first die 10 on the first carrier 15 .
  • the process of mounting the first die 10 on the first carrier board 15 may include the following steps:
  • the first carrier 15 is placed on the stage of the placement apparatus.
  • the first carrier board 15 is provided with a plurality of mounting areas, and each mounting area is respectively provided with an alignment mark.
  • the camera device of the placement device takes a picture of the first carrier board 15, and the controller of the placement device determines the position of each placement area according to the position of the alignment mark in the captured picture;
  • the multiple robots of the placement equipment grab the first die 10 respectively, so that the opening 131 of the first die 10 faces the first carrier board 15 ;
  • the camera device of the placement device takes pictures of the plurality of first bare chips 10 grasped by the robot, and the controller of the placement device determines the position of each of the first bare chips 10 according to the positions of the openings 131 in the captured pictures;
  • the controller of the placement device determines whether the two are corresponding according to the position of the first die 10 and the position of the corresponding placement area. If not, the robot of the placement device drives the first die 10 to move. so that the position of the first bare chip 10 after the movement corresponds to the position of the corresponding mounting area;
  • the first die 10 is mounted on the corresponding mounting area of the first carrier board 15 .
  • the opening 131 of the first protective layer 13 is used as an alignment mark, which can make the alignment of the first die 10 and the corresponding mounting area more accurate , improve the precision of mounting, and then improve the precision of packaging; and the opening 131 of the first protective layer 13 is used as an alignment mark, it is not necessary to set the alignment mark pattern on the front of the first die 10, which helps to simplify the first The complexity of the fabrication process of the die 10 .
  • step 112 a first encapsulation layer is formed.
  • the formed first encapsulation layer covers the first carrier board and encapsulates the first die.
  • a second intermediate structure as shown in FIG. 9 can be obtained.
  • the second intermediate structure includes a first carrier board and an encapsulation structure on the first carrier board.
  • the first encapsulation layer 16 is formed on the first die 10 and the exposed first carrier 15 to completely encapsulate the to-be-first die 10 so as to reconstruct a flat plate structure so that the After peeling off the first carrier board 15, rewiring and packaging can continue on the reconfigured flat panel structure.
  • the first protective layer 13 provided on the front side of the first die 10 can protect the front side of the first die 10 and prevent the material of the first encapsulation layer 16 from affecting the first die.
  • the front of the 10 deals damage.
  • the first encapsulation layer 16 before forming the first encapsulation layer 16, some preprocessing steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the first die 10 and the first carrier 15, Therefore, the first encapsulation layer 16 can be connected more closely with the first die 10 and the first carrier 15 without delamination or cracking.
  • some preprocessing steps such as chemical cleaning, plasma cleaning, etc.
  • the first encapsulation layer 16 may be a polymer, a resin, a resin composite, or a polymer composite.
  • the first encapsulation layer 16 may be a resin with fillers, wherein the fillers are inorganic particles.
  • the first encapsulation layer 16 may be formed by laminating epoxy resin films, or may be formed by injection molding, compression molding, or transfer molding of epoxy resin compounds.
  • step 113 the first carrier plate is peeled off.
  • the first carrier 15 may be mechanically peeled directly from the first encapsulation layer 16 and the first die 10 .
  • the first carrier board 15 and the first die 10 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer can also be heated by heating. After being heated, the viscosity decreases, and the first carrier plate 15 is then peeled off. After the first carrier 15 is peeled off, the front surface of the first die 10 is exposed.
  • the first encapsulation layer 16 is exposed on the front side of the first die 10 . In other embodiments, the first encapsulation layer 16 may not be exposed on the front side of the first die 10 .
  • a cavity for accommodating the first die 10 is provided on the first encapsulation layer 16 . The thickness of the first die 10 Less than the depth of the cavity, the front surface of the first die 10 faces the opening of the cavity.
  • step 114 a first redistribution structure electrically connected to the first pad is formed on the front surface of the first die.
  • the fourth intermediate structure shown in FIG. 11 is obtained after the first redistribution structure is formed on the front surface of the first die 10 .
  • the first redistribution structure 17 includes a redistribution layer, and the redistribution layer includes a first conductive trace 171 electrically connected to the first pad and located on the first conductive trace 171 away from the first die 10 .
  • the first encapsulation structure may further include a first conductive portion 18 filled in the opening 231 , and the first conductive trace 171 is electrically connected to the first pad through the first conductive portion 18 .
  • the first redistribution structure 17 includes only one redistribution layer.
  • the first redistribution structure may include two or more redistribution layers, and two adjacent layers are redistributed. Layer electrical connection.
  • the first redistribution structure leads out the first pad of the first die 10, which can improve the reliability of the electrical connection between the first solder pad and the third redistribution structure formed subsequently; and the first redistribution structure is conducive to realizing semiconductor packaging The more complex wiring structure can help improve the performance of the semiconductor package structure.
  • the first conductive portion 18 and the first conductive trace 171 may be formed in the same process step. In this way, the first conductive portion 18 and the first conductive trace 171 can be simultaneously formed in one process step, which is helpful for simplifying the semiconductor packaging process. In other embodiments, the first conductive portion 18 and the first conductive trace 171 may not be formed at the same time, and the first conductive portion 18 may be formed first, and then the first conductive trace 171 may be formed.
  • the first conductive parts 18 , the first conductive traces 171 and the first conductive bumps 172 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like.
  • the materials of the first conductive portion 18 , the first conductive traces 171 and the first conductive bumps 172 may be metal materials, such as metal copper.
  • the step of forming the first encapsulation structure may further include: forming a first dielectric material layer, the first dielectric material layer covering the first redistribution structure, the first dielectric material layer is exposed on the surface of the first conductive bump. After forming the first dielectric material layer, a fifth intermediate structure as shown in FIG. 12 can be obtained.
  • the first dielectric material layer 19 covers the first redistribution structure 17 , and the surface of the first conductive bumps 172 facing away from the first die 10 exposes the first dielectric material layer 19 .
  • the first dielectric material layer 19 can protect the first redistribution structure 17 , and can prevent the first redistribution structure 17 from contacting the conductive structure formed subsequently, which may affect the performance of the semiconductor package structure.
  • the distance from the side of the first dielectric material layer 19 away from the first die 10 to the first die 10 is approximately the same as the distance from the side of the first conductive bump 172 away from the first die 10 to the first die 10 , so that the surface of the first conductive bump 172 just exposes the first dielectric material layer 19 .
  • the first dielectric material layer 19 may be initially formed to cover the surface and sides of the first conductive bumps 172 , and then the first dielectric material layer 19 is thinned processing so as to expose the first conductive bumps 172 away from the surface of the first die 10 .
  • the first dielectric material layer 19 is one or more layers of insulating material, and the material of the first dielectric material layer 19 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other material with similar properties.
  • the first dielectric material layer 19 may be formed by lamination, spin coating, printing, molding, or other suitable means.
  • the fifth intermediate structure shown in FIG. 12 is obtained, the fifth intermediate structure is cut to obtain a plurality of first encapsulation structures 101 as shown in FIG. 13 .
  • Each of the first encapsulation structures 101 may include one first die 10 .
  • the step of forming the second encapsulation structure includes the following processes:
  • a second die is mounted on a second carrier, a plurality of second solder pads are disposed on the front of the second die, and the front of the second die faces the second carrier;
  • a second redistribution structure electrically connected to the second pad is formed on the front surface of the second die.
  • the process of forming the second encapsulation structure is similar to the process of forming the first encapsulation structure, and will not be repeated here.
  • the second encapsulation structure formed may be as shown in FIG. 14 .
  • the second encapsulation structure 201 includes a second die 20 and a second encapsulation layer 21 .
  • the second encapsulation layer 21 covers at least the side portion of the second die 20 .
  • the second encapsulation layer 21 encapsulates the backside and the side surface of the second die 20 .
  • a second protective layer 25 is provided on the front side of the second die 20 , and openings 251 are formed on the second protective layer 25 to expose the second pads of the second die 20 .
  • the second encapsulation structure 201 may further include The second conductive portion 23 is located in the opening 251 .
  • the second redistribution structure 22 is located on the side of the second protective layer 25 away from the second die 20 , and the second redistribution structure 22 is electrically connected to the second pad of the second die 20 through the second conductive portion 23 .
  • the second redistribution structure 22 includes a redistribution layer, and the redistribution layer includes a second conductive trace 221 electrically connected to the second pad and a second conductive bump on the side of the second conductive trace 221 away from the second die 20 Column 222.
  • the second conductive traces 221 are electrically connected to the second pads through the second conductive portions 23 .
  • the second redistribution structure 22 includes only one redistribution layer.
  • the second redistribution structure 22 may include two or more redistribution layers.
  • the wiring layers are electrically connected.
  • the second redistribution structure 22 leads out the second pad of the second die 20, which can improve the reliability of the electrical connection between the second pad and the third redistribution structure formed subsequently; and the second redistribution structure is beneficial to the realization of semiconductor
  • the more complex wiring of the package structure helps to improve the performance of the semiconductor package structure.
  • the second encapsulation structure 201 may further include a second dielectric material layer 24 , the second dielectric material layer 24 covers the second redistribution structure 22 , and the surface of the second conductive bumps 222 facing away from the second die 20 exposes the second dielectric material Electrical material layer 24 .
  • the second dielectric material layer 24 can protect the second redistribution structure 22 , and can prevent the second redistribution structure 22 from contacting the conductive structure formed subsequently, thereby affecting the performance of the semiconductor package structure.
  • step 120 the first encapsulation structure and the second encapsulation structure are mounted on a third carrier board, and both the first redistribution structure and the second redistribution structure face the first Three carrier boards.
  • step 120 the sixth intermediate structure shown in FIG. 15 and FIG. 16 can be obtained.
  • the third carrier is provided with a mounting area for mounting the first encapsulation structure and a mounting area for mounting the second encapsulation structure.
  • the first encapsulation structure and the second encapsulation structure are respectively mounted on the corresponding mounting areas.
  • FIG. 15 only takes the third carrier board 30 with one first encapsulation structure 101 and one second encapsulation structure 201 mounted on it as an example for illustration.
  • the first encapsulation structure 101 and a plurality of second encapsulation structures 201 are shown in FIG. 16 .
  • Each of the first encapsulation structures 101 corresponds to one second encapsulation structure 201
  • the first encapsulation structures 101 and the corresponding second encapsulation structures 201 are disposed adjacent to each other.
  • the first conductive bumps 172 and the second conductive bumps 222 can be used as alignment marks pattern.
  • the first encapsulation structure 101 and the second encapsulation structure 201 can be aligned with the corresponding mounting areas more accurately, and the mounting precision can be improved, thereby improving the packaging precision; and the first encapsulation structure 101 and the second encapsulation structure
  • the encapsulation structure 201 does not need to be provided with an alignment mark pattern, which helps to simplify the complexity of the fabrication process of the first encapsulation structure 101 and the second encapsulation structure 201 .
  • the first encapsulation structure 101 and the second encapsulation structure 201 can be mounted on the third carrier board 30 through an adhesive layer, and the adhesive layer can be made of an easily peelable material, so that the third The carrier plate 30 and the first encapsulation structure 101 are separated from the second encapsulation structure 201 , for example, the adhesive layer can be made of a heat-separating material that can lose its adhesiveness by heating.
  • a third encapsulation layer is formed, and the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure; the third encapsulation
  • the sealing structure includes a first surface and a second surface opposite to the first surface, and the first surface faces the third carrier board.
  • the seventh intermediate structure as shown in FIG. 17 can be obtained.
  • the seventh intermediate structure includes a third carrier 30 and a third encapsulation structure 301 on the third carrier 30 .
  • the third encapsulation layer 33 is formed on the first encapsulation structure 101, the second encapsulation structure 201 and the exposed third carrier board 30, and completely encapsulates the first encapsulation structure 101 and the second encapsulation structure 201,
  • the first surface 311 of the third encapsulation structure 301 is the surface facing the third carrier 30
  • the second surface 312 is the surface of the third encapsulation structure 301 facing away from the third carrier 30 .
  • some preprocessing steps such as chemical cleaning, plasma cleaning, etc., may be performed, so as to combine the first encapsulation structure 101 , the second encapsulation structure 201 with the third encapsulation structure 101 .
  • the impurities on the surface of the carrier board 30 are removed, so that the first encapsulation structure 101 , the second encapsulation structure 201 and the third carrier board 30 can be connected more closely without delamination or cracking.
  • the third encapsulation layer 33 may be a polymer, a resin, a resin composite material, or a polymer composite material.
  • the third encapsulation layer 33 may be resin with fillers, wherein the fillers are inorganic particles.
  • the third encapsulation layer 33 may be formed by laminating epoxy resin films, or may be formed by injection molding, compression molding, or transfer molding of epoxy resin compounds.
  • the third encapsulation structure 301 includes the first encapsulation structure 101 and the second encapsulation structure 201.
  • the third encapsulation layer 33 of the third encapsulation structure 301 can encapsulate three One or more than three encapsulation structures, that is, three or more dies are encapsulated.
  • the thickness of the initially formed third encapsulation layer 33 may be greater than a specified thickness, and after the third encapsulation layer 33 is formed, the semiconductor packaging method further includes: placing the third encapsulation layer away from the third carrier board Thinning is performed on one side of the thinned so that the thickness of the thinned third encapsulation layer is the specified thickness.
  • step 140 the third carrier is peeled off.
  • step 140 the third encapsulation structure shown in FIG. 18 can be obtained.
  • the first conductive bumps 172 of the first encapsulation structure 101 face away from the surface of the first die 10 and the second conductive bumps 222 of the second encapsulation structure 201 face away from the surface of the first die 10 .
  • the surfaces of the two dies 20 are exposed.
  • the third carrier plate 30 can be directly mechanically peeled off from the third encapsulation structure 301 .
  • the third carrier plate 30 and the third encapsulation structure 301 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the bonding can also be made by heating. When the layer is heated, the viscosity decreases, and the third carrier 30 is peeled off.
  • a through hole is formed penetrating the third encapsulation structure and a conductive structure is formed in the through hole, a third redistribution structure is arranged on the first surface, and a third redistribution structure is arranged on the second surface.
  • Four redistribution structures; the third redistribution structure and the fourth redistribution structure are electrically connected through the conductive structure, and the third redistribution structure is electrically connected to the first redistribution structure and the second redistribution structure, respectively .
  • step 150 includes steps 151 to 154 as follows.
  • step 151 a third redistribution structure is provided on the first surface.
  • the semiconductor packaging method further includes: forming a first dielectric layer, the first dielectric layer covering the third redistribution structure, the third redistribution structure facing away from the first One side of a surface exposes the first dielectric layer.
  • the first dielectric layer may protect the third redistribution structure.
  • the external device can be electrically connected to the final semiconductor package structure through the third redistribution structure exposing the surface of the first dielectric layer.
  • the third redistribution structure 40 includes a redistribution layer 41 and a redistribution layer 42 located on the side of the redistribution layer 41 away from the first surface 311 , and the redistribution layer 41 includes a third conductive trace 411 and a third conductive trace 411 .
  • the fourth conductive bumps 422 on the side of the line 421 away from the first surface 311 are exposed to the first dielectric layer 50 on the side of the fourth conductive bumps 422 away from the first surface 311 .
  • the third conductive trace 411 is electrically connected to the first pad and the second pad through the first redistribution structure 17 .
  • the third conductive traces 411 may electrically connect the first redistribution structure 17 with the second redistribution structure 22 .
  • the third redistribution structure 40 includes two redistribution layers, and the first dielectric layer 50 includes a first sub-dielectric layer 51 covering the redistribution layer 41 , and a covering redistribution layer 42 .
  • the surface of the second sub-dielectric layer 52 of the redistribution layer 41 facing away from the first surface 311 exposes the first sub-dielectric layer 51, and the fourth conductive bumps 422 of the redistribution layer 42 are away from the first sub-dielectric layer 51.
  • the surface of the surface 311 exposes the second sub-dielectric layer 52 .
  • the third redistribution structure 40 may include more than two redistribution layers, and each redistribution layer is covered by the first dielectric layer 50 .
  • Forming the third redistribution structure 40 shown in FIG. 20 and forming the first dielectric layer 50 include the following processes:
  • a third conductive trace 411 and a third conductive bump 412 located on the side of the third conductive trace 411 away from the first die 10 are formed on the first surface 311 .
  • the third conductive traces 411 and the third conductive bumps 412 may be formed by means of metal sputtering, electrolytic plating, electroless plating, or the like.
  • the materials of the third conductive traces 411 and the third conductive bumps 412 are conductive materials, such as metal copper.
  • a first sub-dielectric layer 51 is formed, the first sub-dielectric layer 51 covers the third conductive traces 411 and the third conductive bumps 412 , and the third conductive bumps 412 are exposed on the side away from the first surface 311 .
  • a sub-dielectric layer 51 is formed, the first sub-dielectric layer 51 covers the third conductive traces 411 and the third conductive bumps 412 , and the third conductive bumps 412 are exposed on the side away from the first surface 311 .
  • the distance from the side of the first sub-dielectric layer 51 facing away from the first surface 311 to the first surface 311 is approximately the same as the distance from the side of the third conductive bump 412 facing away from the first surface 311 to the first surface 311 , so that the surface of the third conductive bump 412 just exposes the first sub-dielectric layer 51 .
  • the first sub-dielectric layer 51 may be initially formed to cover the surface and side portions of the third conductive bumps 412 , and then the first sub-dielectric layer 51 is thinned processing to expose the surfaces of the third conductive bumps 412 .
  • the first sub-dielectric layer 51 is one or more layers of insulating materials, and the material of the first sub-dielectric layer 51 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties s material.
  • the first sub-dielectric layer 51 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
  • fourth conductive traces 421 and fourth conductive bumps 422 are formed on the side of the first sub-dielectric layer 51 away from the first surface 311 and on the side of the fourth conductive trace 421 away from the first die.
  • the fourth conductive traces 421 and the fourth conductive bumps 422 may be formed by means of metal sputtering, electrolytic plating, electroless plating, or the like.
  • the materials of the fourth conductive traces 421 and the fourth conductive bumps 422 are conductive materials, such as metal copper.
  • a second sub-dielectric layer 52 is formed, the second sub-dielectric layer 52 covers the fourth conductive traces 421 and the fourth conductive bumps 422 , and the fourth conductive bumps 422 are exposed on the side away from the first surface 311 .
  • Two sub-dielectric layers 52 are formed, the second sub-dielectric layer 52 covers the fourth conductive traces 421 and the fourth conductive bumps 422 , and the fourth conductive bumps 422 are exposed on the side away from the first surface 311 .
  • the second sub-dielectric layer 52 can be one or more layers of insulating materials, and the material of the second sub-dielectric layer 52 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar characteristic material.
  • the second sub-dielectric layer 52 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
  • step 152 a through hole penetrating the third encapsulation structure is formed.
  • the number of through holes formed in this step may be plural, and the through holes expose portions of the third conductive traces 411 .
  • step 153 a conductive structure is formed in the through hole, the conductive structure is electrically connected to the third redistribution structure, and the side of the conductive structure facing away from the first surface exposes the third package seal.
  • step 153 the twelfth intermediate structure shown in FIG. 24 can be obtained.
  • the number of the conductive structures 60 is plural.
  • the conductive structure 60 may be formed by filling the via hole with a conductive material.
  • the conductive material is, for example, metallic copper.
  • the conductive structure 60 is electrically connected to the first redistribution structure 40 .
  • the orthographic projection of the first encapsulation structure 101 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311 ;
  • the orthographic projection of the second encapsulation structure 201 on the first surface 311 is located outside the orthographic projection of the conductive structure 60 on the first surface 311 .
  • the conductive structure 60 is located between the first encapsulation structure 101 and the second encapsulation structure 201 of the third encapsulation structure 301 or at the side of the first encapsulation structure 101 and the second encapsulation structure 201 , the conductive structure 60
  • the setting of does not affect the first encapsulation structure 101 and the second encapsulation structure 201 .
  • a fourth redistribution structure is provided on the second surface, and the fourth redistribution structure is electrically connected to the conductive structure.
  • the fourth rewiring structure is a pre-wiring substrate, and the thirteenth intermediate structure shown in FIG. 25 can be obtained through step 154 .
  • the pre-wiring substrate 84 is fixedly disposed on the second surface 312 .
  • the pre-wiring substrate 84 includes pre-wiring lines 841 , and the pre-wiring lines 841 are electrically connected to the conductive structure 60 .
  • the pre-wiring substrate 84 includes pre-wiring lines 841 , and the pre-wiring lines are relatively complex circuits.
  • the pre-wiring substrate By arranging the pre-wiring substrate on the second surface, compared with the scheme of forming the re-wiring layer on the second surface, it helps to reduce the probability of short circuit when forming the re-wiring layer, and can improve the product yield; Compared with the scheme of forming the rewiring layer, the preparation method can reduce the complexity of the semiconductor packaging process, save the time required for forming the rewiring layer, thereby reducing the time required for the semiconductor packaging method; and the pre-wiring substrate can be prepared before packaging.
  • Tests are performed to avoid defects in the pre-wiring substrate; the pre-wiring circuit included in the pre-wiring substrate is relatively complex, and the pre-wiring substrate with complex multi-circuits rewires the intermediate package structure to improve the performance of the entire package structure.
  • the pre-wiring substrate 84 may also include an insulating material 842 in which the pre-wiring lines 841 are formed.
  • the insulating material 842 may include the pre-wiring lines 841, and make the pre-wiring lines 841 have a fixed shape to facilitate the transfer of the pre-wiring lines.
  • the pre-wiring substrate 84 may include at least one sub-region 801 , each sub-region 801 corresponds to one third encapsulation structure 301 , and the pre-wiring line 841 includes sub-lines located in each sub-region 801 .
  • each sub-region 801 corresponds to a third encapsulation structure 301
  • the conductive structures 60 located in the third encapsulation structure 301 are electrically connected to the sub-circuits in the corresponding sub-region 801 .
  • the conductive structure 60 can also be formed first, then the third rewiring structure is set, and finally the fourth rewiring structure is set; or, the conductive structure 60 can also be formed first, then the fourth rewiring structure is set, and finally the fourth rewiring structure is set
  • the third re-wiring structure; alternatively, the fourth re-wiring structure can also be set first, then the conductive structure 60 is formed, and finally the third re-wiring structure is set.
  • step 151 to step 154 which will not be repeated.
  • the semiconductor packaging method further includes:
  • a second dielectric layer is formed, the dielectric layer covers the fourth redistribution structure, and a side of the fourth redistribution structure away from the second surface exposes the second dielectric layer.
  • the fifteenth intermediate structure shown in FIG. 28 can be obtained through this step.
  • the second dielectric layer 70 covers the pre-wiring substrate 84 , and the second dielectric layer 70 can protect the pre-wiring substrate 84 .
  • the second dielectric layer 70 is one or more layers of insulating material, and the material of the second dielectric layer 70 may be plastic film, PI, PBO, organic polymer film, organic polymer composite material or Other materials with similar properties.
  • the second dielectric layer 70 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
  • the distance from the side of the second dielectric layer 70 facing away from the second surface 312 to the second surface 312 is approximately the same as the distance from the side of the pre-wiring substrate 84 facing away from the second surface 312 to the second surface 312, so that the pre-wiring substrate 84 has a
  • the second dielectric layer 70 is just exposed on the surface.
  • the first formed second dielectric layer 70 may cover the surface and side of the pre-wiring substrate 84, and then the second dielectric layer 70 is thinned to make the The surface of the pre-wiring substrate 84 facing away from the second surface 312 is exposed.
  • a passive component is disposed on a side of the fourth redistribution structure away from the second surface, and the passive component is electrically connected to the fourth redistribution structure.
  • a plurality of passive elements 90 may be disposed on the side of the fourth redistribution structure away from the second surface 312 , and the plurality of passive elements 90 may be the same or different.
  • the passive element 90 is located on the side of the second dielectric layer 70 away from the second surface 312 .
  • the passive element 90 is in direct contact with the pre-wiring circuit 841 and is electrically connected.
  • the passive member 90 is located on the side of the pre-wiring substrate 84 facing away from the second surface 312 .
  • the first pad of the first die 10 is electrically connected to the passive component 90 through the first redistribution structure 17 , the third redistribution structure 40 , the conductive structure 60 and the pre-distribution substrate 84 in sequence.
  • the second pads of the second die 20 are electrically connected to the passive component 90 through the second redistribution structure 22 , the third redistribution structure 40 , the conductive structure 60 and the pre-distribution substrate 84 in sequence, respectively.
  • the passive element 90 may be a capacitor, a resistor, an inductor, or the like.
  • the inductance is a device for electromagnetic conversion.
  • the passive component 90 is an inductance
  • the semiconductor packaging structure can have the function of electromagnetic conversion, so that the semiconductor packaging structure has more functions.
  • the step 160 of arranging the passive element on the side of the fourth redistribution structure away from the second surface may include the following process: first, on a side of the fourth redistribution structure away from the second surface A seed layer is formed on the side; then, a metal layer is formed on the side of the seed layer away from the second surface by an electroplating process; finally, the seed layer and the metal layer are patterned to form an inductor.
  • the semiconductor packaging method further includes: cutting the semiconductor packaging structure to obtain a plurality of sub-package structures, each sub-package structure including a The third encapsulation structure.
  • the obtained semiconductor packaging structure includes a first die, a second die, and a passive component, and the passive component realizes the The electrical connection between the bare chip and the second bare chip makes the semiconductor package structure have more functions; the first bonding pad of the first bare chip and the second bonding pad of the second bare chip are respectively connected with the third The redistribution structure is electrically connected, and the third redistribution structure is electrically connected to the fourth redistribution structure located on the side away from the front side of the first die through the conductive structure, so that the fourth redistribution structure connects the first pad of the first die and the fourth redistribution structure.
  • the second pad of the second die is led out to the side of the semiconductor package structure away from the front surface of the first die, so as to realize double-sided wiring of the package structure, and the external structure can be electrically connected to the side of the semiconductor package structure away from the front surface of the first die ;
  • the first bare chip and the second bare chip are placed horizontally, and the space in the horizontal direction is reasonably utilized, which can make the semiconductor packaging structure relatively thin, small, and compact, so that the semiconductor packaging structure can be suitable for small and lightweight electronic equipment. ;
  • the first bare chip and the second bare chip are packaged and then packaged, which can improve the reliability of the packaging of the first bare chip and the second bare chip.
  • Embodiments of the present application also provide a semiconductor packaging structure.
  • the semiconductor package structure includes:
  • the third encapsulation structure 301 includes the first encapsulation structure 101 , the second encapsulation structure 201 and the third encapsulation layer 33 .
  • the first encapsulation structure 101 includes a first encapsulation layer 16 , a first die 10 and a first redistribution structure 17 .
  • a plurality of first pads are disposed on the front surface of the first die 10 .
  • An encapsulation layer 16 covers at least the side surface of the first die 10 , the first redistribution structure 17 is located on the front surface of the first die 10 , and the first redistribution structure 17 is connected to the first solder pad electrical connection.
  • the second encapsulation structure 201 includes a second encapsulation layer 21, a second die 20 and a second redistribution structure 22.
  • a plurality of second pads are disposed on the front surface of the second die 20.
  • the second encapsulation layer 21 covers at least the side surface of the second die 20 , the second redistribution structure 22 is located on the front surface of the second die 20 , and the second redistribution structure 22 is connected to the second solder pad electrical connection.
  • the third encapsulation layer 33 encapsulates the first encapsulation structure 101 and the second encapsulation structure 201 ;
  • the third encapsulation structure 301 includes a first surface 311 and is opposite to the first surface 311
  • the second surface 312 of the first redistribution structure 17 and the redistribution structure 22 respectively face away from the second surface 312 .
  • the third encapsulation structure 301 is provided with a through hole penetrating the third encapsulation structure;
  • the conductive structure 60 is located in the through hole
  • the third redistribution structure 40 is disposed on the first surface 311 and is electrically connected to the first redistribution structure 17 and the second redistribution structure 22 respectively;
  • a fourth redistribution structure disposed on the second surface 312, and the third redistribution structure 40 is electrically connected to the fourth redistribution structure through the conductive structure 60;
  • the passive element 90 is disposed on the side of the fourth redistribution structure away from the second surface 312 , and the passive element 90 is electrically connected to the fourth redistribution structure.
  • the fourth rewiring structure includes a pre-wiring substrate 84
  • the pre-wiring substrate 84 includes a pre-wiring circuit 841
  • the pre-wiring circuit 841 is respectively connected to the conductive structure 60 and the passive component 90 . electrical connection.
  • the semiconductor package structure further includes a first dielectric layer 50 , the first dielectric layer 50 completely covers the third redistribution structure 40 , and the third redistribution structure 40 is away from One side of the first surface 311 exposes the first dielectric layer 50 .
  • the semiconductor package structure further includes a second dielectric layer 70 , the second dielectric layer 70 encapsulates the fourth redistribution structure, and the fourth redistribution structure faces away from the first redistribution structure.
  • One side of the two surfaces 312 exposes the second dielectric layer 70 .
  • the second semiconductor encapsulation structure includes the pre-wiring substrate 84
  • the second dielectric layer 70 covers the pre-wiring substrate 84
  • the side of the pre-wiring circuit 841 of the pre-wiring substrate 84 facing away from the second surface 312 exposes the second dielectric layer 70 .
  • the orthographic projection of the first encapsulation structure 101 on the first surface 311 is located outside the orthographic projection of the conductive structure 60 on the first surface 311 ; the second encapsulation The orthographic projection of the sealing structure 201 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311 .
  • the semiconductor package structure further includes a first dielectric material layer 19 , the first dielectric material layer 19 covers the first redistribution structure 17 , and the first redistribution structure 17 faces away from the surface of the first die 10 The first dielectric material layer 19 is exposed.
  • the semiconductor package structure further includes a second dielectric material layer 24 , the second dielectric material layer 24 covers the second redistribution structure 22 , and the second redistribution structure 22 faces away from the surface of the second die 20 The second dielectric material layer 24 is exposed.
  • the passive element 90 may be a capacitor, a resistor, an inductor, or the like.
  • the apparatus embodiments and the method embodiments may complement each other without conflict.
  • the device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place , or distributed to multiple network elements. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative effort.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention concerne un procédé d'encapsulation de semi-conducteur et une structure d'encapsulation de semi-conducteur. Le procédé d'encapsulation de semi-conducteur consiste à : former une première structure d'encapsulation (101) et une deuxième structure d'encapsulation (201) ; monter la première structure d'encapsulation (101) et la deuxième structure d'encapsulation (201) sur une troisième plaque de support (30) ; former une troisième couche d'encapsulation (33) pour obtenir une troisième structure d'encapsulation (301) ; dénuder la troisième plaque de support (30) ; former un trou traversant pénétrant à travers la troisième structure d'encapsulation (301), former une structure conductrice (60) dans le trou traversant, agencer une troisième structure de recâblage (40) sur une première surface (311) de la troisième structure d'encapsulation (301), et agencer une quatrième structure de recâblage sur une seconde surface (312) de la troisième structure d'encapsulation (301) ; permettre à la troisième structure de recâblage (40) d'être connectée électriquement à la quatrième structure de recâblage au moyen de la structure conductrice (60), et permettre à la troisième structure de recâblage (40) d'être connectée électriquement à une première structure de recâblage (17) de la première structure d'encapsulation (101) et à une seconde structure de recâblage (22) de la seconde structure d'encapsulation (201), respectivement ; et agencer un élément passif (90) sur le côté de la quatrième structure de recâblage tourné à l'opposé de la seconde surface (312).
PCT/CN2022/083632 2021-03-29 2022-03-29 Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur WO2022206749A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110335642.7A CN115148712A (zh) 2021-03-29 2021-03-29 半导体封装方法及半导体封装结构
CN202110335642.7 2021-03-29

Publications (1)

Publication Number Publication Date
WO2022206749A1 true WO2022206749A1 (fr) 2022-10-06

Family

ID=83404204

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/083632 WO2022206749A1 (fr) 2021-03-29 2022-03-29 Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur

Country Status (2)

Country Link
CN (1) CN115148712A (fr)
WO (1) WO2022206749A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1418048A (zh) * 2001-10-18 2003-05-14 松下电器产业株式会社 元件内置模块及其制造方法
CN1437255A (zh) * 2002-02-09 2003-08-20 旺宏电子股份有限公司 半导体构装与其制造方法
TW201415586A (zh) * 2012-10-11 2014-04-16 Taiwan Semiconductor Mfg Co Ltd 封裝裝置及其製造方法
CN107611100A (zh) * 2016-07-12 2018-01-19 台湾积体电路制造股份有限公司 整合扇出型封装及其制造方法
US20180301418A1 (en) * 2017-04-13 2018-10-18 Powertech Technology Inc. Package structure and manufacturing method thereof
CN111599702A (zh) * 2019-04-24 2020-08-28 矽磐微电子(重庆)有限公司 扇出型芯片封装结构的制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1418048A (zh) * 2001-10-18 2003-05-14 松下电器产业株式会社 元件内置模块及其制造方法
CN1437255A (zh) * 2002-02-09 2003-08-20 旺宏电子股份有限公司 半导体构装与其制造方法
TW201415586A (zh) * 2012-10-11 2014-04-16 Taiwan Semiconductor Mfg Co Ltd 封裝裝置及其製造方法
CN107611100A (zh) * 2016-07-12 2018-01-19 台湾积体电路制造股份有限公司 整合扇出型封装及其制造方法
US20180301418A1 (en) * 2017-04-13 2018-10-18 Powertech Technology Inc. Package structure and manufacturing method thereof
CN111599702A (zh) * 2019-04-24 2020-08-28 矽磐微电子(重庆)有限公司 扇出型芯片封装结构的制作方法

Also Published As

Publication number Publication date
CN115148712A (zh) 2022-10-04

Similar Documents

Publication Publication Date Title
US20200294875A1 (en) Sensor package and manufacturing method thereof
US6586822B1 (en) Integrated core microelectronic package
CN111883481B (zh) 3d封装件结构及其形成方法
EP1354351B1 (fr) Couche formee directement sur un boitier a puce encapsule
EP3288077B1 (fr) Boîtier micro-électronique comprenant une couche d'interconnexion stratifiée sans bosses
US9082780B2 (en) Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US20020127769A1 (en) Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
KR20040014432A (ko) 일체식 열 싱크 및 복합 층을 구비한 초소형 전자 패키지
US11121052B2 (en) Integrated fan-out device, 3D-IC system, and method
WO2022012538A1 (fr) Structure d'encapsulation 3d multicouche et son procédé de fabrication
US20100190294A1 (en) Methods for controlling wafer and package warpage during assembly of very thin die
US11842902B2 (en) Semiconductor package with alignment mark and manufacturing method thereof
US20220367211A1 (en) Semiconductor Device and Methods of Manufacture
US9196507B1 (en) Semiconductor device, semiconductor stacked module structure, stacked module structure and method of manufacturing same
WO2022042682A1 (fr) Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur
US20230117746A1 (en) Semiconductor devices and methods of manufacturing semiconductor devices
US7785928B2 (en) Integrated circuit device and method of manufacturing thereof
WO2022206749A1 (fr) Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur
WO2022012511A1 (fr) Procédé de mise sous boîtier de semi-conducteur et structure de mise sous boîtier de semi-conducteur
CN114446918A (zh) Mcm封装结构及其制作方法
US11894357B2 (en) System-level packaging structure and method for LED chip
CN115148711A (zh) 半导体封装方法及半导体封装结构
CN115148684A (zh) 半导体封装方法及半导体封装结构
CN114446796A (zh) 半导体封装方法及半导体封装结构
CN114446799A (zh) 半导体封装方法及半导体封装结构

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22778931

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22778931

Country of ref document: EP

Kind code of ref document: A1