WO2022206733A1 - 信号传输网络、芯片及信号处理装置 - Google Patents

信号传输网络、芯片及信号处理装置 Download PDF

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Publication number
WO2022206733A1
WO2022206733A1 PCT/CN2022/083590 CN2022083590W WO2022206733A1 WO 2022206733 A1 WO2022206733 A1 WO 2022206733A1 CN 2022083590 W CN2022083590 W CN 2022083590W WO 2022206733 A1 WO2022206733 A1 WO 2022206733A1
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signal
network
switch
attenuation
input
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PCT/CN2022/083590
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English (en)
French (fr)
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严波
方超敏
王悦
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普源精电科技股份有限公司
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Publication of WO2022206733A1 publication Critical patent/WO2022206733A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/401—Circuits for selecting or indicating operating mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form

Definitions

  • the present application relates to the technical field of integrated circuits, for example, to a signal transmission network, a chip and a signal processing device.
  • signal processing devices such as desktop oscilloscopes, virtual oscilloscopes and data acquisition cards, can process and analyze the signals they receive.
  • the signal received by the signal processing device is a voltage signal, and a signal transmission path configured to transmit and process the received voltage signal is provided in the signal processing device.
  • the transmission mode of high-frequency signals on chips and printed circuit boards mainly uses active and passive devices, builds networks and buffers, and transmits high-frequency voltage signals to the next through amplitude adjustment. stage circuit.
  • the signal is propagated step by step in the network in the form of voltage, which has high requirements on the bandwidth of each segment of the network.
  • the overall bandwidth of the network depends on the minimum bandwidth of the devices used, while the bandwidth and linearity of the signal buffer composed of active devices.
  • the bandwidth of the signal transmission path cannot be guaranteed, so that the bandwidth of the signal transmission path cannot be further improved; at the same time, the signal transmission network is very sensitive to the wire length, parasitic resistance and parasitic capacitance, and the process deviation will affect the bandwidth of the signal transmission path;
  • additional signal amplitude adjustment is required to match the input amplitude range of the subsequent circuit, which will increase the complexity of the circuit.
  • the present application provides a signal transmission network, a chip and a signal processing device to simplify the circuit structure and further improve the bandwidth of the signal transmission path.
  • the present application provides a signal transmission network, including:
  • the impedance unit includes a signal input end and a plurality of signal output ends, the impedance unit is configured to convert the input signal received by the signal input end into a plurality of different current signals after performing different gain adjustments to the signal input end, the plurality of different current signals. different current signals are respectively provided to the plurality of signal output terminals;
  • the gating switch unit includes a plurality of switch input ends and a switch output end, the plurality of switch input ends and the plurality of signal output ends are connected in one-to-one correspondence, and the gating switch unit is configured to selectively conduct one a switch input terminal and the switch output terminal to output a current signal.
  • the present application also provides a chip, including: the above-mentioned signal transmission network.
  • the present application also provides a signal processing device, comprising: the above-mentioned chip.
  • FIG. 1 is a schematic structural diagram of a signal transmission network provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an impedance unit provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another impedance unit provided by an embodiment of the present application.
  • 4a is a schematic structural diagram of another impedance unit provided by an embodiment of the present application.
  • FIG. 4b is a schematic structural diagram of another impedance unit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a signal attenuation network provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a circuit structure of a signal attenuation network provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another signal transmission network provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another signal transmission network provided by an embodiment of the present application.
  • Embodiments of the present application provide a signal transmission network, which can perform different degrees of gain adjustment on an input signal, and the signal transmission network can be set in a chip, the chip can be integrated in a signal processing device, and the signal processing Devices include, but are not limited to, oscilloscopes.
  • FIG. 1 is a schematic structural diagram of a signal transmission network provided by an embodiment of the present application.
  • the impedance unit 10 of the signal transmission network includes a signal input terminal In10 and a plurality of signal output terminals (Out11, Out12, Out13, . . . , Out1n).
  • the impedance unit 10 processes the input signal Vin received by the signal input terminal In10 After different degrees of gain adjustment, it is converted into multiple different current signals (I1, I2, I3, ..., In), and the multiple different current signals (I1, I2, I3, ..., In) are respectively provided to multiple signals Output terminals (Out11, Out12, Out13, . In22, In23, . ..., or In2n) and the switch output terminal Out20 to output a corresponding current signal (I1, I2, I3, ..., or In).
  • the implementations of the impedance unit 10 and the gating switch unit 20 are related to the functions to be implemented by themselves, and those skilled in the art can set them according to actual conditions, which are not limited here.
  • the input signal Vin received by the signal input terminal In10 of the impedance unit 10 is usually a voltage signal, and the voltage signal Vin is converted into a plurality of current signals after being adjusted by the impedance unit 10 to different degrees of gain, so that the input signal Vin is in the form of a current signal.
  • the impedance unit 10 converts the input signal Vin into a current signal for transmission, which enables the impedance unit 10 to have a larger bandwidth, thereby It is beneficial to improve the bandwidth of the signal transmission network, thereby helping to improve the accuracy of the signal transmitted by the signal transmission network; at the same time, the impedance unit 10 is used to adjust the gain of the input signal Vin to different degrees, and it is not necessary to set the gain adjustment to achieve different degrees.
  • Multiple signal transmission paths can simplify the structure of the signal transmission path, and can solve the problem that when multiple signal transmission paths are set due to different degrees of gain adjustment, there are process deviations between different signal transmission paths and thus affect the overall bandwidth of the signal transmission path. technical problem.
  • FIG. 1 only exemplarily shows that the impedance unit 10 includes one signal input terminal In10 and n signal output terminals (Out11, Out12, Out13, .
  • FIG. 1 only exemplarily shows that the gate switch unit 20 includes n switch input terminals (In21, In22, In23, . . . , In2n) and one switch output terminal Out20, and in this
  • the gating switch unit may also include a plurality of switch output terminals.
  • the number of signal input ends of the impedance unit in the embodiment of the present application may be smaller than the number of signal output ends thereof, and the number of switch input ends of the gating switch unit may be greater than the number of switch output ends thereof.
  • the embodiments of the present application exemplarily take the impedance unit including one signal input end and n signal output ends, and the gating switch unit including n switch input ends and one switch output end as examples.
  • the technical solution is exemplified.
  • the impedance unit 10 can convert the input signal Vin received by the signal input terminal In10 into a plurality of different current signals (I1, I2, I3, .
  • the unit 20 chooses to turn on one of its switch input terminals (In21, In22, In23, ..., or In2n) and the switch output terminal Out20, it can transmit the corresponding current signal (I1, I2, I3, ..., or In) as a signal The output signal Iout of the network.
  • the gating switch unit 20 selects to turn on the switch input terminal In21 and the switch output terminal Out20, so that the current signal I1 is transmitted by the switch Output terminal Out20 output.
  • the realization forms of the impedance unit 10 and the gating switch unit 20 are related to their own functions, and those skilled in the art can set them according to the actual situation.
  • the structures of the impedance unit 10 and the gating switch unit 20 are exemplarily described below for examples only.
  • FIG. 2 is a schematic structural diagram of an impedance unit provided by an embodiment of the present application. 1 and 2, on the basis of the above embodiment, the impedance unit 10 further includes a plurality of signal attenuation networks (111, 112, 113, ..., 11n); a plurality of signal attenuation networks (111, 112, 113) , ..., 11n) is connected between the signal input terminal In10 and multiple signal output terminals (Out11, Out12, Out13, ..., Out1n); multiple signal attenuation networks (111, 112, 113, ..., 11n) are set to be respectively
  • the input signal Vin is converted into a number of different current signals (I1, I2, I3, ..., In) after being adjusted with different degrees of gain, and the multiple different current signals (I1, I2, I3, ..., In) They are respectively provided to multiple signal output terminals (Out11, Out12, Out13, . . . , Out1n).
  • the n signal attenuation networks (111, 112, 113, ..., 11n) can Different degrees of gain adjustment are converted into corresponding current signals (I1, I2, I3, .
  • the current signal I1 converted by the network 111 is output as the output signal Iout.
  • the switch module 20 turns on other switch input terminals (In22, In23, .
  • the converted current signal (I2, I3, . . . , or In) is output as the output signal Iout.
  • the gating switch unit 20 selectively turns on the switch input terminals (In21, In22, In23, . ..., or In) is output as the output signal Iout.
  • each signal attenuation network (111, 112, 113, . )Structure According to the degree to which each signal attenuation network (111, 112, 113, . )Structure.
  • the attenuation degree of the n signal attenuation networks (111, 112, 113, . 111, 112, 113, ..., 11n) can be composed of one or more RC series-parallel circuits, and the number of RC series-parallel circuits set in the signal attenuation network with a small attenuation degree can be smaller than that of a signal with a large attenuation degree.
  • the number of RC series-parallel circuits set up in the network can be composed of one or more RC series-parallel circuits, and the number of RC series-parallel circuits set in the signal attenuation network with a small attenuation degree can be smaller than that of a signal with a large attenuation degree.
  • FIG. 2 is only an exemplary drawing of the embodiment of the present application, and FIG. 2 exemplarily shows that the signal attenuation networks (111, 112, 113, . . . , 11n) with different attenuation degrees are independent of each other;
  • the n signal attenuation networks ( 111 , 112 , 113 , . . . , 11n ) in the impedance unit 10 may also be set in other manners.
  • FIG. 3 is a schematic structural diagram of another impedance unit provided by an embodiment of the present application.
  • n signal attenuation networks ( 111 , 112 , 113 , . . . , 11n ) of the impedance unit 10 are cascaded.
  • the connection relationship of the cascaded set of signal attenuation networks may be: the input terminal of the first-stage signal attenuation network 111 is connected to the signal input terminal In10, from the first-level signal attenuation network 111 to the nth-level signal attenuation network 11n.
  • One end of the other signal attenuation networks (112, 113, ...) in between is connected to the signal attenuation network of the previous stage, and the other end is connected to the signal attenuation network of the next stage.
  • one end of the signal attenuation network 112 is connected to the signal attenuation network 111.
  • the other end of the attenuation network 112 is connected to the signal attenuation network 113; and the n signal attenuation networks (111, 112, 113, ..., 11n) can be one-to-one with the n signal output terminals (Out11, Out12, Out13, ..., Out1n) corresponding connection.
  • the signal attenuation network is composed of an RC series-parallel circuit
  • the attenuation levels of the n signal attenuation networks (111, 112, 113, ..., 11n) from the signal attenuation network 111 to the signal attenuation network 11n are increased or sequentially
  • FIG. 4a is a schematic structural diagram of another impedance unit provided by an embodiment of the present application.
  • the impedance unit 10 may further include at least one filter network 12 on the basis of including multiple signal attenuation networks (111, 112, 113, . . .
  • the attenuation networks (111, 112, 113, ..., 11n) are cascaded and arranged between the signal input terminal In10 and the filter network 12 in turn; the first-level signal attenuation network 111 to the last-level signal attenuation network 11n for each level of signal
  • the attenuation input terminal of the attenuation network (112, 113, ...) is electrically connected to the attenuation cascade terminal of the previous stage signal attenuation network, the attenuation input terminal of the first stage signal attenuation network 111 is connected to the signal input terminal In10, and the last stage signal
  • the attenuation cascade terminal of the attenuation network 11n is connected to the filter network 12; the attenuation output terminals of the n signal attenuation networks (111, 112, 113, ..., 11n) and the n signal output terminals (Out11, Out12, Out13, ..., Out1n) ) are connected in one-to-one correspondence; the filtering
  • the gain adjustment degree of the input signal Vin can be selected according to the voltage of the input signal Vin.
  • the input signal Vin input to the signal input terminal In10 is a signal with a relatively large voltage, it can be attenuated by a multi-stage signal attenuation network and then output, and when the input signal Vin input to the signal input terminal In10 is a signal with a relatively high voltage
  • the signal is small, it can be attenuated by fewer stages of signal attenuation network and then output.
  • the implementation can be as follows: when the voltage of the input signal Vin received by the signal input terminal In10 is in the first voltage range, the gate switch unit 20 can The switch input terminal In21 and the switch output terminal Out20 are selected to be turned on, so that the input signal Vin is attenuated by the first-stage signal attenuation network 111 and converted into the corresponding current signal I1 and then output; when the voltage of the input signal Vin received by the signal input terminal In10 In the second voltage range, the gating switch unit 20 can selectively turn on the switch input terminal In22 and the switch output terminal Out20, so that the input signal Vin is sequentially attenuated through the first-stage signal attenuation network 111 and the second-stage signal attenuation network 112 and then It is converted into a corresponding current signal I2 and then output; when the voltage of the input signal Vin received by the signal input terminal In10 is in the third voltage range, the gating switch unit 20 can selectively turn on the switch input terminal In23 and the switch output terminal Out20, so that the input signal Vin
  • the attenuation network 112 , the third-level signal attenuation network 113 , . . . and the nth-level signal attenuation network 11 n are attenuated and converted into corresponding current signals In and then output.
  • the voltage in the first voltage range is smaller than the voltage in the second voltage range
  • the voltage in the second voltage range is smaller than the voltage in the third voltage range
  • the voltage in the nth voltage range is greater than the other voltages voltage within the voltage range.
  • a filter network 12 is electrically connected to the attenuation cascade end of the n-th signal attenuation network 11n to filter out the signal within the preset frequency range, so as to filter out the noise in the signal transmission path, especially the first-level signal in sequence.
  • the noise in the current signal In converted after attenuation by the attenuation network 111, the second-level signal attenuation network 112, the third-level signal attenuation network 113, . . , Out12, Out13, .
  • n signal attenuation networks ( 111 , 112 , 113 , . . . , 11n ) in the impedance unit 10 are cascaded between the signal input terminal In10 and the filter network 12 , those skilled in the art can convert the n signals according to actual needs.
  • the structure of the decay network is set to be the same or different.
  • each filter circuit can be set at the connection point between the adjacent two-stage signal attenuation networks, and each filter circuit and the subsequent stage can be controlled by a switch The relationship of the signal attenuation network.
  • a filter circuit 12 can be designed for the first-stage signal attenuation network 111, and the filter circuit 12 is arranged between the first-stage signal attenuation network 111 and the second-stage signal attenuation network 112.
  • the filter circuit 12 cannot affect the current transmission between the first-level signal attenuation network 111 and the second-level signal attenuation network 112 .
  • corresponding filter circuits 12 can be designed for other signal attenuation networks (112, 113, . . . , 11(n-1)).
  • FIG. 5 is a schematic structural diagram of a signal attenuation network provided by an embodiment of the present application.
  • each signal attenuation network includes a DC signal attenuation network 1111 and a high-frequency signal attenuation network 1112; the DC signal attenuation network 1111 and the high-frequency signal attenuation network 1112 are connected in series and/or parallel; wherein the DC signal attenuation
  • the network 1111 is set to convert the DC type input signal Vin received by the signal input terminal In10 into a corresponding current signal after gain adjustment;
  • the high frequency signal attenuation network 1112 is set to convert the high frequency type input signal Vin received by the signal input terminal In10 After the gain adjustment is performed, it is converted into the corresponding current signal.
  • the DC signal attenuation network 1111 and the high-frequency signal attenuation network 1112 of the signal attenuation network 111 may be connected in parallel, in series, or in a series-parallel connection.
  • the DC signal attenuation network 1111 and the high-frequency signal attenuation network 1112 may have the same input terminal, which is the same as the signal input terminal.
  • the terminal In10 or the signal attenuation network of the previous stage is connected.
  • the DC signal attenuation network 1111 and the high frequency signal attenuation network 1112 also have the same output terminal, and both are connected to the same signal output terminal Out11.
  • the signal attenuation network 111 can have a fixed impedance from the DC frequency band to the designated high frequency frequency band to ensure that the signal has a corresponding amplitude value in the entire frequency band, so that each signal attenuation network can have good frequency response characteristics.
  • signal attenuation networks may include a DC signal attenuation network 1111 and a high-frequency signal attenuation network 1112 , the technical principle and structure of which are similar to the above-mentioned signal attenuation network 111 .
  • the description of the signal attenuation network 111 will not be repeated here.
  • the following takes the structure of the signal attenuation network 111 as an example to illustrate the implementation of the signal attenuation network.
  • Both the DC signal attenuation network 1111 and the high frequency signal attenuation network 1112 may include active devices and/or passive devices, and the implementation of the DC signal attenuation network 1111 and the high frequency signal attenuation network 1112 is not limited.
  • the active device may be, for example, a device such as a transistor
  • the passive device may be, for example, a device such as a resistor, a capacitor, or the like.
  • FIG. 6 is a schematic diagram of a circuit structure of a signal attenuation network provided by an embodiment of the present application.
  • the DC signal attenuation network 1111 includes a first resistor R1 and a second resistor R2 connected in series;
  • the high-frequency signal attenuation network 1112 includes a third resistor R3, a first capacitor C1, a third resistor R3, a first capacitor C1, a Four resistors R4 and a second capacitor C2; wherein, the first resistor R1 is connected in parallel with the first capacitor C1, and the second resistor R2 is connected in parallel with the second capacitor C2.
  • the current signal I1 of the input signal Vin transmitted to the signal output terminal Out11 after passing through the DC signal attenuation network 1111 is Vin/3R.
  • the frequency response curve of the high-frequency signal attenuation network 1112 is determined by the size of the third resistor R3, the fourth resistor R4, and the first capacitor C1 and the second capacitor C2; can make the third resistor R3 and the fourth resistor R4
  • the resistance value is smaller than the high-frequency impedance of the first capacitor C1 and the second capacitor C2, and the capacitance value of the first capacitor C1 is set to C, and the capacitance value of the second capacitor C2 is set to 2C, so that the input signal Vin is passed through the high-frequency signal attenuation network 1112.
  • the effective value of the current signal I1 then transmitted to the signal output terminal Out11 is approximately Vin*( ⁇ *C)/3; where ⁇ is the angular frequency.
  • FIG. 7 is a schematic structural diagram of another signal transmission network provided by an embodiment of the present application. As shown in FIG. 7 , the structure of each signal attenuation network in the impedance unit 10 is the same, and each signal transmission network (111, 112, 113, . . . , 11n) may include a first resistor R1, a second resistor R2, a first Capacitor C1, third resistor R3, fourth resistor R4 and second capacitor C2.
  • the resistance values of different resistors in the same signal attenuation network can be the same or different, and the capacitance values of different capacitors in the same signal attenuation network can be the same or different; the resistance values of corresponding resistors and/or corresponding capacitors in different signal attenuation networks
  • the capacitance values of the resistors can also be the same or different; in the embodiments of the present application, the resistance values of the resistors and the capacitance values of the capacitors can be set according to actual needs, which are not limited in the embodiments of the present application.
  • the resistance value of the first resistor R1 of each signal attenuation network is 2R
  • the resistance value of the second resistor R2 of each signal attenuation network is R
  • other signal attenuation after the signal attenuation network 113 The resistance value of the resistor that adjusts the frequency response of the DC type signal in the network and the filter network 12 is equivalent to 2R, and the gating switch unit 20 selects and turns on one switch input terminal (In21, In22, In23, . . .
  • switch input terminal In21 and switch output terminal Out20 other switch input terminals are grounded as an example, when the switch input terminal In21 and switch output terminal Out20 are turned on, and the other switch input terminals (In22, In23, ..., In2n) are grounded, the input signal Vin will pass through After the signal attenuation network 111, the current signal I1 output by the switch output terminal Out20 is:
  • the output current signal I2 is:
  • the current signal I3 output by the switch output terminal Out20 is:
  • the current signals output by the multiple signal attenuation networks are attenuated proportionally, so that the input signal can be converted into a current signal, and the amplitude of the current signal can be adjusted to achieve different degrees of gain adjustment.
  • the resistance values of the third resistors R3 of multiple signal attenuation networks are the same and all are R, and the fourth resistor R4 of each signal attenuation network can be adjusted according to the actual circuit frequency response characteristics.
  • the capacitance value of the first capacitor C1 of each signal attenuation network is C
  • the capacitance value of the second capacitor C2 of each signal attenuation network is 2C
  • the angular frequency of the input signal Vin is ⁇ .
  • the switch input terminal When In21 is connected to the switch output terminal Out20, and other switch input terminals (In22, In23, ..., In2n) are grounded, after the input signal Vin passes through the signal attenuation network 111, the current signal I1 output by the switch output terminal Out20 is:
  • the output current signal I2 is:
  • the current signal I3 output by the switch output terminal Out20 is:
  • FIG. 7 is only an exemplary diagram of the embodiment of the present application, and FIG. 7 only exemplarily shows the cascaded configuration of n signal attenuation networks ( 111 , 112 , 113 , . . . , 11n ).
  • the multiple signal attenuation networks can also be set in other manners, and by determining the implementation manner of the multiple signal attenuation networks as required, the input signal can be adjusted to different degrees of gain.
  • FIG. 7 only exemplarily shows that the filter network 12 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5
  • the fifth resistor R5 is connected in series with the third capacitor C3 to form a first RC series circuit
  • the sixth resistor R6 is connected in series with the fourth capacitor C4 to form a second RC series circuit
  • the first RC series circuit and the second RC series circuit are connected with the seventh
  • the resistor R7 is connected in parallel to form a first filter circuit
  • the eighth resistor R8 is connected in parallel with the fifth capacitor C5 to form a second filter circuit
  • the first filter circuit and the second filter circuit are connected in series to the last stage signal attenuation network 11n and ground
  • the first filter circuit and the second filter circuit connected in series can filter out the signal in the corresponding frequency range, so as to improve the accuracy of the signal transmitted by the impedance unit 10 .
  • the gating switch unit 20 further includes a plurality of switch subunits (21, 22, 23, ..., 2n); each switch subunit (21, 22, 23, ..., 2n) ) is electrically connected between the switch input terminals (In21, In22, In23, ..., In2n) and the switch output terminal Out20; the gating switch unit 20 is set to match each switch subunit (21, 22, 23, ..., 2n) conduction state.
  • the impedance unit 10 can convert the input signal Vin into a plurality of different current signals (I1, I2, I3, . . . , In) after performing gain adjustment to different degrees.
  • the gating switch unit 20 can determine the gain adjustment degree corresponding to the input signal Vin according to the voltage of the input signal Vin, and select the corresponding switch subunits (21, 22, 23, ..., or 2n) to be turned on.
  • the signal transmission network 10 includes a plurality of cascaded signal attenuation networks (111, 112, 113, ..., 11n), and a plurality of switch subunits (21, 22, 23, ..., 2n) and a plurality of signal attenuation networks ( 111, 112, 113, . . .
  • the impedance unit 10 can attenuate the input signal Vin to a small extent, and the gate switch unit 20 can control the switch sub-unit 21 to be turned on, while the other switch sub-units ( 22, 23, .
  • the gate switch unit 20 can control the switch subunit 23 to conduct, while the other switch subunits (21, 22, ..., 2n) are in the disconnected state; by analogy, when the voltage of the input signal Vin is in the nth voltage range, the impedance unit 10 can attenuate the input signal Vin to a large extent, and the gating switch unit 20 can control the switch at this time.
  • the subunit 2n is turned on, and the other switch units (21, 22, 23, . . . ) are all turned off. In this way, the impedance unit 10 combined with each switch subunit (21, 22, 23, .
  • each switch subunit (21, 22, 23, ..., 2n) of the gating switch module 20 that is, each switch subunit (21, 22, 23, ..., 2n) can be a single-pole double-throw switch, and when the switch subunits (21, 22, 23, . 111, 112, 113, ..., or 11n) converted current signals (I1, I2, I3, ..., or In) are transmitted to the switch output terminal Out20; ) is in the disconnected state, its contacts S1 and S3 are electrically connected, so that the attenuation output terminal of the corresponding signal attenuation network (111, 112, 113, ..., or 11n) is grounded.
  • the implementation form of the plurality of switch subunits (111, 112, 113, ..., 11n) is not limited to the form shown in FIG. 7, and those skilled in the art can 11n) functions and practical requirements
  • the multiple switch subunits (111, 112, 113, . . . , 11n) are designed into different structures.
  • FIG. 8 is a schematic structural diagram of still another signal transmission network provided by an embodiment of the present application.
  • the signal transmission network further includes a current-voltage conversion unit 30, which is electrically connected to the switch output terminal Out20; the current-voltage conversion unit 30 is configured to convert the current signal Convert it into a voltage signal and output the voltage signal for subsequent analysis and processing.
  • the implementation manner of the current-voltage conversion unit 30 is related to the function to be implemented by itself, and those skilled in the art can set it according to the actual situation, which is not limited here.
  • the current-voltage conversion unit 30 may include an operational amplifier U1, the switch output terminal Out20 of the gating switch unit 20 may be electrically connected to the inverting input terminal In- of the operational amplifier U1 in the current-voltage conversion unit 30, and the The non-inverting input terminal In+ can receive the reference signal Vref; at this time, the corresponding gain adjustment degree can be selected as required, and the gating switch module 20 can be controlled to select the corresponding switch input terminal (In21, In22, In23, ..., or In2n) to be turned on.
  • the corresponding current signal (I1, I2, I3, ..., or In) is transmitted to the inverting input terminal In- of the operational amplifier U1, and the current signal (I1, I2, I3, ..., ... , or In) after inverting amplification processing by the operational amplifier U1, the corresponding voltage signal Vout is output, that is, the operational amplifier U1 can convert the current signal (I1, I2, I3, ..., or In) into the corresponding voltage signal Vout , and at the same time, a corresponding degree of gain adjustment can be performed on the converted voltage signal Vout.
  • the operational amplifier U1 may be a transimpedance amplifier, so that the operational amplifier U1 can switch the current signal (I1, I2, I3, . . . , or In) output by the gating switch module 20 It is converted into a corresponding voltage signal and output after amplitude adjustment; or, when the operational amplifier U1 is any other operational amplifier well known to those in the art, the output end of the operational amplifier U1 is also electrically connected to its inverting input end In-, to A corresponding feedback circuit is formed. At this time, the operational amplifier U1 can also realize the function of converting the current signal into a voltage signal.
  • An embodiment of the present application further provides a chip, and the chip includes the signal transmission network provided by the embodiment of the present application. Therefore, the chip provided by the embodiment of the present application includes the technical features of the signal transmission network provided by the embodiment of the present application, and can achieve the implementation of the present application.
  • the chip provided by the embodiment of the present application includes the technical features of the signal transmission network provided by the embodiment of the present application, and can achieve the implementation of the present application.
  • Embodiments of the present application further provide a signal processing apparatus, where the signal processing apparatus includes but is not limited to an oscilloscope.
  • the signal processing apparatus provided by the embodiment of the present application includes the chip provided by the embodiment of the present application. Therefore, the signal processing apparatus provided by the embodiment of the present application also includes the technical features of the signal transmission network provided by the embodiment of the present application, and can achieve the requirements provided by the embodiment of the present application. For the technical effect of the signal transmission network, the same can be referred to the above description of the signal transmission network provided by the embodiment of the present application, and details are not repeated here.

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Abstract

本文公开了一种信号传输网络、芯片及信号处理装置。该信号传输网络包括：阻抗单元，包括信号输入端和多个信号输出端，阻抗单元设置为将信号输入端接收的输入信号进行不同程度的增益调节后转换为多个不同的电流信号，多个不同的电流信号分别提供至多个信号输出端；选通开关单元，包括多个开关输入端和开关输出端，多个开关输入端和多个信号输出端一一对应连接，选通开关单元设置为选择性地导通一个开关输入端和开关输出端，以输出一个电流信号。

Description

信号传输网络、芯片及信号处理装置
本申请要求在2021年03月29日提交中国专利局、申请号为202110335542.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，例如涉及一种信号传输网络、芯片及信号处理装置。
背景技术
诸如台式示波器、虚拟示波器和数据采集卡等多类信号处理装置，能够对其所接收的信号进行处理分析等。通常信号处理装置所接收的信号为电压信号，且在信号处理装置中设置有设置为传输、处理其所接收的电压信号的信号传输通路。高频信号在芯片和印制电路板(Printed Circuit Board，PCB)上的传输方式主要利用有源和无源器件，搭建网络和缓冲器，将高频电压信号，通过幅度调理，传输到下一级电路中。
但是，信号以电压方式在网络中进行逐级传播，对每一段网络的带宽有较高的要求，网络整体带宽取决于所用器件的最小带宽，而有源器件构成的信号缓冲器的带宽和线性度都无法保证，使得信号传输通路的带宽无法进一步提高；同时，信号传输网络对线长，寄生电阻和寄生电容非常敏感，工艺偏差等原因将会影响信号传输通路的带宽；后级电路在接收大信号输入或者信号链路较长时，需要额外进行信号幅度调理，以匹配后级电路的输入幅度范围，将会增加电路的复杂性。
发明内容
本申请提供一种信号传输网络、芯片及信号处理装置，以简化电路结构，进一步提高信号传输通路的带宽。
本申请提供了一种信号传输网络，包括：
阻抗单元，包括信号输入端和多个信号输出端，所述阻抗单元设置为将所述信号输入端接收的输入信号进行不同程度的增益调节后转换为多个不同的电流信号，所述多个不同的电流信号分别提供至所述多个信号输出端；
选通开关单元，包括多个开关输入端和开关输出端，所述多个开关输入端和所述多个信号输出端一一对应连接，所述选通开关单元设置为选择性地导通 一个开关输入端和所述开关输出端，以输出一个电流信号。
本申请还提供了一种芯片，包括：上述信号传输网络。
本申请还提供了一种信号处理装置，包括：上述芯片。
附图说明
图1是本申请实施例提供的一种信号传输网络的结构示意图；
图2是本申请实施例提供的一种阻抗单元的结构示意图；
图3是本申请实施例提供的又一种阻抗单元的结构示意图；
图4a是本申请实施例提供的又一种阻抗单元的结构示意图；
图4b是本申请实施例提供的又一种阻抗单元的结构示意图；
图5是本申请实施例提供的一种信号衰减网络的结构示意图；
图6是本申请实施例提供的一种信号衰减网络的电路结构示意图；
图7是本申请实施例提供的又一种信号传输网络的结构示意图；
图8是本申请实施例提供的又一种信号传输网络的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的具体实施例仅仅用于解释本申请。为了便于描述，附图中仅示出了与本申请相关的部分。
本申请实施例提供一种信号传输网络，该信号传输网络能够对输入信号进行不同程度的增益调节，且该信号传输网络能够设置于芯片中，该芯片能够集成于信号处理装置中，该信号处理装置包括但不限于示波器。
图1是本申请实施例提供的一种信号传输网络的结构示意图。如图1所示，信号传输网络的阻抗单元10包括信号输入端In10和多个信号输出端(Out11、Out12、Out13、…、Out1n)，阻抗单元10将信号输入端In10接收的输入信号Vin进行不同程度的增益调节后转换为多个不同的电流信号(I1、I2、I3、…、In)，并将多个不同的电流信号(I1、I2、I3、…、In)分别提供至多个信号输出端(Out11、Out12、Out13、…、Out1n)；选通开关单元20包括多个开关输入端(In21、In22、In23、…、In2n)和开关输出端Out20，多个开关输入端(In21、In22、In23、…、In2n)和多个信号输出端(Out11、Out12、Out13、…、Out1n)连接，选通开关单元20设置为选择性的导通一个开关输入端(In21、In22、In23、…、或In2n)和开关输出端Out20，以输出对应的一个电流信号(I1、I2、I3、…、或In)。
阻抗单元10和选通开关单元20的实现方式与其自身所要实现的功能相关，本领域技术人员可根据实际情况进行设置，此处不做限定。阻抗单元10的信号输入端In10接收的输入信号Vin通常为电压信号，该电压信号Vin经由阻抗单元10进行不同程度的增益调节后转换为多个电流信号，使得输入信号Vin以电流信号的形式在信号传输网络所组成的信号传输通路中进行传输，相较于直接传输电压信号的情况，阻抗单元10将输入信号Vin转换为电流信号进行传输，能够使该阻抗单元10具有更大的带宽，从而有利于提高信号传输网络的带宽，从而有利于提高信号传输网络所传输信号的准确性；同时，采用阻抗单元10对输入信号Vin进行不同程度的增益调节，无需为实现不同程度的增益调节而设置多个信号传输通路，能够简化信号传输通路的结构，以及能够解决因进行不同程度的增益调节而设置多个信号传输通路时，不同信号传输通路之间具有工艺偏差进而影响信号传输通路整体带宽的技术问题。
图1中仅示例性的示出了阻抗单元10包括一个信号输入端In10和n个信号输出端(Out11、Out12、Out13、…、Out1n)，而在本申请实施例中阻抗单元还可以包括多个信号输入端；同样的，图1中仅示例性的示出了选通开关单元20包括n个开关输入端(In21、In22、In23、…、In2n)和一个开关输出端Out20，而在本申请实施例中选通开关单元同样可以包括多个开关输出端。本申请实施例的阻抗单元的信号输入端的数量可以小于其信号输出端的数量，而选通开关单元的开关输入端的数量可以大于其开关输出端的数量。为便于描述，本申请实施例示例性的以阻抗单元包括一个信号输入端和n个信号输出端，以及选通开关单元包括n个开关输入端和一个开关输出端为例，对本申请实施例的技术方案进行示例性的说明。
示例性的，由于阻抗单元10能够将信号输入端In10接收的输入信号Vin进行不同程度的增益调节后转换为多个不同的电流信号(I1、I2、I3、…、In)，且选通开关单元20选择导通其一个开关输入端(In21、In22、In23、…、或In2n)和开关输出端Out20时，能够将对应的电流信号(I1、I2、I3、…、或In)作为信号传输网络的输出信号Iout。例如，当需要将阻抗单元10进行增益调节和转换后的电流信号I1作为输出信号Iout输出时，选通开关单元20选择导通开关输入端In21和开关输出端Out20，以使电流信号I1由开关输出端Out20输出。
当需要将阻抗单元10进行增益调节和转换后的其它电流信号(I2、I3、…、或In)输出时，选通开关单元20可以对应选择相应的开关输入端(In22、In23、…、或In2n)与开关输出端Out20导通，其技术原理和控制方式均与上述选择输出电流信号I1时类似，相同之处可参照上述对选择输出电流信号I1时的技术原理和控制方式的描述，在此不再赘述。
阻抗单元10和选通开关单元20的实现形式与其自身的功能相关，本领域技术人员可以根据实际情况进行设置。以下仅针对示例，对阻抗单元10和选通开关单元20的结构进行示例性的说明。
可选的，图2是本申请实施例提供的一种阻抗单元的结构示意图。结合图1和图2所示，在上述实施例的基础上，阻抗单元10还包括多个信号衰减网络(111、112、113、…、11n)；多个信号衰减网络(111、112、113、…、11n)连接于信号输入端In10和多个信号输出端(Out11、Out12、Out13、…、Out1n)之间；多个信号衰减网络(111、112、113、…、11n)设置为分别将输入信号Vin进行不同程度的增益调节后转换为多个不同的电流信号(I1、I2、I3、…、In)，并将多个不同的电流信号(I1、I2、I3、…、In)分别提供至多个信号输出端(Out11、Out12、Out13、…、Out1n)。
示例性的，以阻抗单元10包括n个信号衰减网络(111、112、113、…、11n)为例，n个信号衰减网络(111、112、113、…、11n)能够将输入信号Vin进行不同程度的增益调节后转换为相应的电流信号(I1、I2、I3、…、In)，以在选通开关单元20根据需要导通开关输入端In21和开关输出端Out20时，能够使信号衰减网络111转换的电流信号I1作为输出信号Iout输出。相应的，当选通开关模块20根据需要导通其他开关输入端(In22、In23、…、或In2n)和开关输出端Out20时，同样能够使其他信号衰减网络(112、113、…、或11n)转换的电流信号(I2、I3、…、或In)作为输出信号Iout输出。如此，选通开关单元20根据需要选择导通开关输入端(In21、In22、In23、…、或In2n)和开关输出端Out20，将具有相应程度的增益调节的电流信号(I1、I2、I3、…、或In)作为输出信号Iout输出。
按照每个信号衰减网络(111、112、113、…、11n)对输入信号Vin进行增益调节的程度，本领域技术人员可根据需要设置每个信号衰减网络(111、112、113、…、11n)的结构。示例性的，以从信号衰减网络111到信号衰减网络11n的n个信号衰减网络(111、112、113、…、11n)的衰减程度依次增加或依次减小为例，每个信号衰减网络(111、112、113、…、11n)可以由一个或多个RC串并联电路组成，且衰减程度较小的信号衰减网络中所设置的RC串并联电路的数量可小于衰减程度较大的信号衰减网络中所设置的RC串并联电路的数量。
图2仅为本申请实施例示例性的附图，图2中示例性的示出了具有不同衰减程度的信号衰减网络(111、112、113、…、11n)之间相互独立；而在本申请实施例中为实现不同程度的增益调节，阻抗单元10中n个信号衰减网络(111、112、113、…、11n)还可以为其它的设置方式。
可选的，图3是本申请实施例提供的又一种阻抗单元的结构示意图。如图3 所示，阻抗单元10的n个信号衰减网络(111、112、113、…、11n)级联设置。其中，对于级联设置的信号衰减网络的连接关系可以为：第一级信号衰减网络111的输入端与信号输入端In10连接，从第一级信号衰减网络111至第n级信号衰减网络11n之间的其它信号衰减网络(112、113、…)的一端与其前一级信号衰减网络连接，另一端与其下一级信号衰减网络连接，例如信号衰减网络112的一端与信号衰减网络111连接，信号衰减网络112的另一端与信号衰减网络113连接；且n个信号衰减网络(111、112、113、…、11n)可与n个信号输出端(Out11、Out12、Out13、…、Out1n)一一对应连接。如此，当信号衰减网络由RC串并联电路组成时，在使从信号衰减网络111到信号衰减网络11n的n个信号衰减网络(111、112、113、…、11n)的衰减程度依次增加或依次减小的前提下，有利于减少整个阻抗单元10中所设置的RC串并联电路的数量。
可选的，图4a是本申请实施例提供的又一种阻抗单元的结构示意图。如图4a所示，阻抗单元10在包括多个信号衰减网络(111、112、113、…、11n)的基础上，该阻抗单元10还可以包括至少一个滤波网络12；此时，多个信号衰减网络(111、112、113、…、11n)依次级联设置于信号输入端In10与滤波网络12之间；第一级信号衰减网络111至最后一级信号衰减网络11n之间的每级信号衰减网络(112、113、…)的衰减输入端与其前一级信号衰减网络的衰减级联端电连接，第一级信号衰减网络111的衰减输入端与信号输入端In10连接，最后一级信号衰减网络11n的衰减级联端与滤波网络12连接；n个信号衰减网络(111、112、113、…、11n)的衰减输出端与n个信号输出端(Out11、Out12、Out13、…、Out1n)一一对应连接；滤波网络12设置为滤除预设频率范围内的信号。
结合参考图1和图4a，在实际工作过程中，可根据输入信号Vin的电压，选择该输入信号Vin的增益调节程度。示例性的，当输入至信号输入端In10的输入信号Vin为电压较大的信号时，可经多级信号衰减网络进行衰减后输出，而当输入至信号输入端In10的输入信号Vin为电压较小的信号时，可经较少级的信号衰减网络进行衰减后输出，实现方式例如可以为：当信号输入端In10接收的输入信号Vin的电压在第一电压范围时，选通开关单元20可选择导通开关输入端In21和开关输出端Out20，使得输入信号Vin经第一级信号衰减网络111进行衰减并转换为相应的电流信号I1后输出；当信号输入端In10接收的输入信号Vin的电压在第二电压范围时，选通开关单元20可选择导通开关输入端In22和开关输出端Out20，使得输入信号Vin依次经第一级信号衰减网络111和第二级信号衰减网络112进行衰减并转换为相应的电流信号I2后输出；当信号输入端In10接收的输入信号Vin的电压在第三电压范围时，选通开关单元20可选择导通开关输入端In23和开关输出端Out20，使得输入信号Vin依次经第一级信 号衰减网络111、第二级信号衰减网络112和第三级信号衰减网络113进行衰减并转换为相应的电流信号I3后输出；以此类推，当信号输入端In10接收的输入信号Vin的电压在第n电压范围时，选通开关单元20可选择导通开关输入端In2n和开关输出端Out20，使得输入信号Vin依次经第一级信号衰减网络111、第二级信号衰减网络112、第三级信号衰减网络113、…和第n级信号衰减网络11n进行衰减并转换为相应的电流信号In后输出。其中，位于第一电压范围内的电压小于位于第二电压范围内的电压，位于第二电压范围内的电压小于位于第三电压范围内的电压，…，位于第n电压范围内的电压大于其它电压范围内的电压。
同时，通过在第n级信号衰减网络11n的衰减级联端电连接一滤波网络12滤除预设频率范围内的信号，以滤除信号传输通路中的噪声，尤其是依次经第一级信号衰减网络111、第二级信号衰减网络112、第三级信号衰减网络113、…和第n级信号衰减网络11n进行衰减后转换的电流信号In中的噪声，防止由每个信号输出端(Out11、Out12、Out13、…、Out1n)输出的电流信号失真，从而能够使信号传输网络10具有低噪声、高增益调节精度。
当阻抗单元10中的n个信号衰减网络(111、112、113、…、11n)级联设置于信号输入端In10与滤波网络12之间时，本领域技术人员可以根据实际需要将n个信号衰减网络的结构设置为相同或不同。
一实施例中，当阻抗单元包含多个滤波电路时，可以将每个滤波电路设置在相邻两级信号衰减网络之间的连接点处，并通过开关来控制每个滤波电路和后一级信号衰减网络的关系。参照图4b，可以为第一级信号衰减网络111设计一个滤波电路12，将该滤波电路12设置于第一级信号衰减网络111和第二级信号衰减网络112之间，同时需要确保选择打开第二级信号衰减网络112时，该滤波电路12不能影响电流在第一级信号衰减网络111和第二级信号衰减网络112之间的传输。同理，可以为其他信号衰减网络(112、113、…、11(n-1))均设计对应的滤波电路12。
可选的，图5是本申请实施例提供的一种信号衰减网络的结构示意图。如图5所示，每个信号衰减网络包括直流信号衰减网络1111和高频信号衰减网络1112；该直流信号衰减网络1111与高频信号衰减网络1112串联和/或并联连接；其中，直流信号衰减网络1111设置为将信号输入端In10接收的直流类型的输入信号Vin进行增益调节后转换为对应的电流信号；高频信号衰减网络1112设置为将信号输入端In10接收的高频类型的输入信号Vin进行增益调节后转换为对应的电流信号。
信号衰减网络111的直流信号衰减网络1111与高频信号衰减网络1112可 以为并联连接、串联连接或者串并联的连接方式。示例性的，以直流信号衰减网络1111与高频信号衰减网络1112以串并联的连接方式进行连接为例，直流信号衰减网络1111和高频信号衰减网络1112具有相同的输入端，均与信号输入端In10或前一级的信号衰减网络连接，直流信号衰减网络1111和高频信号衰减网络1112也具有相同的输出端，均与同一个信号输出端Out11连接。如此，信号衰减网络111能够具有从直流频段到指定高频频段的固定阻抗，保证信号在整个频段内具有相应的幅度值，从而能够使每个信号衰减网络具有良好的频响特性。
对于其他的信号衰减网络(112、113、…、11n)均可以包括直流信号衰减网络1111和高频信号衰减网络1112，其技术原理和结构与上述信号衰减网络111类似，相同之处可参照上述对信号衰减网络111的描述，在此不再赘述。为便于描述，以下以信号衰减网络111的结构为例对信号衰减网络的实现方式进行示例性的说明。
直流信号衰减网络1111和高频信号衰减网络1112均可以包括有源器件和/或无源器件，对直流信号衰减网络1111和高频信号衰减网络1112的实现方式不做限定。其中，有源器件例如可以为晶体管等器件，无源器件例如可以为电阻、电容等器件。
可选的，图6是本申请实施例提供的一种信号衰减网络的电路结构示意图。结合图5和图6所示，直流信号衰减网络1111包括串联连接的第一电阻R1和第二电阻R2；高频信号衰减网络1112包括依次串联连接的第三电阻R3、第一电容C1、第四电阻R4和第二电容C2；其中，第一电阻R1与第一电容C1并联连接，第二电阻R2与第二电容C2并联连接。
示例性的，当第一电阻R1的阻值为2R，第二电阻R2的阻值为R时，输入信号Vin经直流信号衰减网络1111后传输至信号输出端Out11的电流信号I1为Vin/3R；同样的，高频信号衰减网络1112的频率响应曲线由第三电阻R3、第四电阻R4以及第一电容C1和第二电容C2的大小决定；可令第三电阻R3和第四电阻R4的阻值小于第一电容C1和第二电容C2的高频阻抗，且令第一电容C1的容值为C，第二电容C2的容值为2C，使得输入信号Vin经高频信号衰减网络1112后传输至信号输出端Out11的电流信号I1的有效值近似为Vin*(ω*C)/3；其中，ω是角频率。
示例性的，以阻抗单元10的多个信号衰减网络级联设置于信号输入端In10和滤波网络12之间为例。图7是本申请实施例提供的又一种信号传输网络的结构示意图。如图7所示，阻抗单元10中每个信号衰减网络的结构相同，且每个信号传输网络(111、112、113、…、11n)可以包括第一电阻R1、第二电阻R2、 第一电容C1、第三电阻R3、第四电阻R4和第二电容C2。
同一信号衰减网络中不同电阻的阻值可以相同或不同，以及同一信号衰减网络中不同电容的容值可以相同或不同；不同信号衰减网络中相对应的电阻的阻值和/或相对应的电容的容值也可以相同或不同；在本申请实施例中电阻的阻值和电容的容值可根据实际需要进行设置，本申请实施例对此均不作限定。
对于直流信号衰减通路，以每个信号衰减网络的第一电阻R1的阻值为2R，以及每个信号衰减网络的第二电阻R2的阻值为R，以及信号衰减网络113之后的其它信号衰减网络及滤波网络12中对直流类型信号的频响进行调节的电阻的阻值等效为2R，且选通开关单元20每次选择导通一个开关输入端(In21、In22、In23、…、或In2n)和开关输出端Out20，其它开关输入端接地为例，当开关输入端In21与开关输出端Out20导通，而其它开关输入端(In22、In23、…、In2n)接地时，输入信号Vin经由信号衰减网络111后，由开关输出端Out20输出的电流信号I1为：
Figure PCTCN2022083590-appb-000001
当开关输入端In22与开关输出端Out20导通，而其它开关输入端(In21、In23、…、In2n)接地时，输入信号Vin经由信号衰减网络111和信号衰减网络112后，由开关输出端Out20输出的电流信号I2为：
Figure PCTCN2022083590-appb-000002
当开关输入端In23与开关输出端Out20导通，而其它开关输入端(In21、In22、…、In2n)接地时，输入信号Vin经由信号衰减网络111、信号衰减网络112以及信号衰减网络113后，由开关输出端Out20输出的电流信号I3为：
Figure PCTCN2022083590-appb-000003
由此可知，多个信号衰减网络输出的电流信号按比例衰减，从而能够将输入信号转换为电流信号，并对电流信号进行幅度调节，实现不同程度的增益调节。
同样的，对于高频信号衰减通路，以多个信号衰减网络的第三电阻R3的阻值相同且均为R，每个信号衰减网络的第四电阻R4可根据实际电路频响特性进行调整，以及，且每个信号衰减网络的第一电容C1的容值为C，每个信号衰减网络的第二电容C2的容值为2C，输入信号Vin的角频率为ω为例，当开关输入端In21与开关输出端Out20导通，而其它开关输入端(In22、In23、…、In2n)接地时，输入信号Vin经由信号衰减网络111后，由开关输出端Out20输出的电 流信号I1为：
Figure PCTCN2022083590-appb-000004
当开关输入端In22与开关输出端Out20导通，而其它开关输入端(In21、In23、…、In2n)接地时，输入信号Vin经由信号衰减网络111和信号衰减网络112后，由开关输出端Out20输出的电流信号I2为：
Figure PCTCN2022083590-appb-000005
当开关输入端In23与开关输出端Out20导通，而其它开关输入端(In21、In22、…、In2n)接地时，输入信号Vin经由信号衰减网络111、信号衰减网络112以及信号衰减网络113后，由开关输出端Out20输出的电流信号I3为：
Figure PCTCN2022083590-appb-000006
由此可知，通过设置第一电容C1和第二电容C2的容值，可在一定信号输入频率范围内，保证高频电流信号和直流电流信号具有一致的幅度调节比例，使得信号传输网络在较大的频带范围内具有保持不变的阻抗特性，能够传输从直流频段到指定高频频段的信号，使信号传输网络具有较宽的带宽。
图7仅为本申请实施例示例性的图，图7中仅示例性的示出了n个信号衰减网络(111、112、113、…、11n)级联设置，而在本申请实施例中多个信号衰减网络还可以为其它设置方式，且通过可以根据需要确定多个信号衰减网络的实现方式，即可使对输入信号进行不同程度的增益调节。
同时，图7中仅示例性的示出了滤波网络12包括第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8、第三电容C3、第四电容C4和第五电容C5；第五电阻R5与第三电容C3串联构成第一RC串联电路，第六电阻R6与第四电容C4串联构成第二RC串联电路；第一RC串联电路、第二RC串联电路均与第七电阻R7并联连接构成第一滤波电路；第八电阻R8与第五电容C5并联连接构成第二滤波电路；其中，第一滤波电路与第二滤波电路串联连接于最后一级信号衰减网络11n与接地端之间，以通过串联连接的第一滤波电路和第二滤波电路滤除相应频率范围内的信号，提高阻抗单元10所传输的信号的准确性。而在本申请实施例中，滤波网络的实现方式不限于此，可根据实际需要进行设置，本申请实施例对此不做限定。
可选的，继续参考图7所示，选通开关单元20还包括多个开关子单元(21、22、23、…、2n)；每个开关子单元(21、22、23、…、2n)电连接于开关输入端(In21、In22、In23、…、In2n)和开关输出端Out20之间；选通开关单元 20设置为根据目标增益，匹配每个开关子单元(21、22、23、…、2n)的导通状态。
阻抗单元10能够将输入信号Vin进行不同程度的增益调节后转换为多个不同的电流信号(I1、I2、I3、…、In)。此时，选通开关单元20可根据输入信号Vin的电压，确定该输入信号Vin所对应的增益调节程度，并选择对应的开关子单元(21、22、23、…、或2n)导通。以信号传输网络10包括多个级联设置信号衰减网络(111、112、113、…、11n)，且多个开关子单元(21、22、23、…、2n)与多个信号衰减网络(111、112、113、…、11n)的衰减输出端一一对应电连接为例。当输入信号Vin的电压在第一电压范围时，阻抗单元10可对输入信号Vin进行较小程度的衰减，此时选通开关单元20可控制开关子单元21导通，而其它开关子单元(22、23、…、2n)均处于断开状态；当输入信号Vin的电压在第二电压范围时，选通开关单元20可控制开关子单元22导通，而其它开关子单元(21、23、…、2n)均处于断开状态；当输入信号Vin的电压在第三电压范围时，选通开关单元20可控制开关子单元23导通，而其它开关子单元(21、22、…、2n)均处于断开状态；以此类推，当输入信号Vin的电压在第n电压范围时，阻抗单元10可对输入信号Vin进行较大程度的衰减，此时选通开关单元20可控制开关子单元2n导通，而其它开关单元(21、22、23、…)均处于断开状态。如此，阻抗单元10结合选通开关单元20中每个开关子单元(21、22、23、…、2n)，能够使具有不同电压的输入信号Vin实现不同程度的增益调节。
图7中仅示例性的示出了选通开关模块20的每个开关子单元(21、22、23、…、2n)的结构，即每个开关子单元(21、22、23、…、2n)可以为一单刀双掷开关，且在开关子单元(21、22、23、…、或2n)处于导通状态时其触点S1与S2电连接，以将与其对应的信号衰减网络(111、112、113、…、或11n)转换的电流信号(I1、I2、I3、…、或In)传输至开关输出端Out20；而当开关子单元(21、22、23、…、或2n)处于断开状态时其触点S1与S3电连接，以使与其对应的信号衰减网络(111、112、113、…、或11n)的衰减输出端接地。但是，多个开关子单元(111、112、113、…、11n)的实现形式不限于图7所示的形式，本领域技术人员可根据多个开关子单元(111、112、113、…、11n)的功能以及实际需求将多个开关子单元(111、112、113、…、11n)设计为不同结构。
可选的，图8是本申请实施例提供的又一种信号传输网络的结构示意图。如图8所示，在上述实施例的基础上，信号传输网络还包括电流电压转换单元30，该电流电压转换单元30与开关输出端Out20电连接；该电流电压转换单元30设置为将电流信号转换为电压信号，并输出该电压信号，以便于后续的分析 处理。电流电压转换单元30实现方式与其自身所要实现的功能相关，本领域技术人员可根据实际情况进行设置，此处不作限定。
示例性的，电流电压转换单元30可以包括运算放大器U1，选通开关单元20的开关输出端Out20可与电流电压转换单元30中运算放大器U1的反相输入端In-电连接，运算放大器U1的同相输入端In+可接收参考信号Vref；此时，可根据需要选择相应的增益调节程度，并控制选通开关模块20选择导通对应的开关输入端(In21、In22、In23、…、或In2n)和开关输出端Out20，以使对应的电流信号(I1、I2、I3、…、或In)传输至运算放大器U1的反相输入端In-，并将该电流信号(I1、I2、I3、…、或In)经运算放大器U1进行反相放大处理后，输出相应的电压信号Vout，即运算放大器U1能够将电流信号器(I1、I2、I3、…、或In)转换为相应的电压信号Vout，同时还能够对所转换的电压信号Vout进行相应程度的增益调节。
当电流电压转换单元30包括运算放大器U1时，该运算放大器U1可以为跨阻放大器，使得该运算放大器U1能够将选通开关模块20输出的电流信号(I1、I2、I3、…、或In)转换为相应的电压信号并进行幅值调节后输出；或者，运算放大器U1为本领域人员所熟知的其它任何运算放大器时，运算放大器U1的输出端还与其反相输入端In-电连接，以形成相应的反馈电路，此时，运算放大器U1同样能够实现将电流信号转换为电压信号的功能。
本申请实施例还提供一种芯片，该芯片包括本申请实施例提供的信号传输网络，因此本申请实施例提供的芯片包括本申请实施例提供的信号传输网络的技术特征，能够达到本申请实施例提供的信号传输网络的技术效果，相同之处可参照上述对本申请实施例提供的信号传输网络的描述，在此不再赘述。
本申请实施例还提供一种信号处理装置，该信号处理装置包括但不限于示波器。本申请实施例提供的信号处理装置包括本申请实施例提供的芯片，因此本申请实施例提供的信号处理装置同样包括本申请实施例提供的信号传输网络的技术特征，能够达到本申请实施例提供的信号传输网络的技术效果，相同之处可参照上述对本申请实施例提供的信号传输网络的描述，在此不再赘述。

Claims (10)

  1. 一种信号传输网络，包括：
    阻抗单元，包括信号输入端和多个信号输出端，所述阻抗单元设置为将所述信号输入端接收的输入信号进行不同程度的增益调节后转换为多个不同的电流信号，所述多个不同的电流信号分别提供至所述多个信号输出端；
    选通开关单元，包括多个开关输入端和开关输出端，所述多个开关输入端和所述多个信号输出端一一对应连接，所述选通开关单元设置为选择性地导通一个开关输入端和所述开关输出端，以输出一个电流信号。
  2. 根据权利要求1所述的信号传输网络，其中，所述阻抗单元还包括多个信号衰减网络；
    所述多个信号衰减网络连接于所述信号输入端和所述多个信号输出端之间；所述多个信号衰减网络设置为分别将所述输入信号进行不同程度的增益调节后转换为所述多个不同的电流信号，并将所述多个不同的电流信号分别提供至所述多个信号输出端。
  3. 根据权利要求2所述的信号传输网络，其中，所述多个信号衰减网络级联设置。
  4. 根据权利要求2所述的信号传输网络，其中，所述阻抗单元还包括至少一个滤波网络；
    所述多个信号衰减网络依次级联设置于所述信号输入端与所述至少一个滤波网络之间；第一级信号衰减网络至最后一级信号衰减网络之间的每级信号衰减网络的衰减输入端与前一级信号衰减网络的衰减级联端连接，所述第一级信号衰减网络的衰减输入端与所述信号输入端电连接，所述最后一级信号衰减网络的衰减级联端与所述至少一个滤波网络连接；所述多个信号衰减网络的衰减输出端与所述多个信号输出端一一对应连接；
    所述至少一个滤波网络设置为滤除预设频率范围内的信号。
  5. 根据权利要求2所述的信号传输网络，其中，每个信号衰减网络包括直流信号衰减网络和高频信号衰减网络；所述直流信号衰减网络与所述高频信号衰减网络以串联和并联中的至少一种方式连接；
    所述直流信号衰减网络设置为将所述信号输入端接收的直流类型的输入信号进行增益调节后转换为所述直流类型的输入信号对应的电流信号；
    所述高频信号衰减网络设置为将所述信号输入端接收的高频类型的输入信号进行增益调节后转换为所述高频类型的输入信号对应的电流信号。
  6. 根据权利要求5所述的信号传输网络，其中，所述直流信号衰减网络包括串联连接的第一电阻和第二电阻；
    所述高频信号衰减网络包括依次串联连接的第三电阻、第一电容、第四电阻和第二电容；
    其中，所述第一电阻与所述第一电容并联连接，所述第二电阻与所述第二电容并联连接。
  7. 根据权利要求1所述的信号传输网络，其中，所述选通开关单元还包括多个开关子单元；每个开关子单元电连接于一个开关输入端和所述开关输出端之间；
    所述选通开关单元设置为根据目标增益，匹配每个开关子单元的导通状态。
  8. 根据权利要求1所述的信号传输网络，还包括：
    电流电压转换单元，与所述开关输出端电连接，所述电流电压转换单元设置为将所述一个电流信号转换为电压信号，并输出所述电压信号。
  9. 一种芯片，包括：权利要求1～8任一项所述的信号传输网络。
  10. 一种信号处理装置，包括：权利要求9所述的芯片。
PCT/CN2022/083590 2021-03-29 2022-03-29 信号传输网络、芯片及信号处理装置 WO2022206733A1 (zh)

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